[PATCH v2] drm/amd/display: add SI support to AMD DC

[PATCH v2] drm/amd/display: add SI support to AMD DC

[Mauro Rossi]

Sending PATCH v2 series rebase on amd-staging-drm-next

dce/dce60/dce60_resources.c and irq/dce60/irq_service_dce60.c
are still using dce_8_0_{d,sh_mask}.h headers

dpm is used for power management, a non fatal message is generated:

[drm:dm_pp_get_static_clocks: [amdgpu]] 
*ERROR* DM_PPLIB: invalid powerlevel state: 0!

VBIOS parsing requires review about severity of generated Warning:

dce110_link_encoder_construct: 
Failed to get encoder_cap_info from VBIOS with error code 4!


[PATCH v2 01/10] drm/amd/display: add asics info for SI parts
[PATCH v2 02/10] drm/amd/display: dc/dce: add DCE6 support (v2)
[PATCH v2 03/10] drm/amd/display: dc/core: add DCE6 support
[PATCH v2 04/10] drm/amd/display: dc/bios: add support for DCE6
[PATCH v2 05/10] drm/amd/display: dc/gpio: add support for DCE6
[PATCH v2 06/10] drm/amd/display: dc/i2caux: add support for DCE6
[PATCH v2 07/10] drm/amd/display: dc/irq: add support for DCE6
[PATCH v2 08/10] drm/amd/display: amdgpu_dm: add SI support (v2)
[PATCH v2 09/10] drm/amdgpu: enable DC support for SI parts (v2)
[PATCH v2 10/10] drm/amd/display: enable SI support in the Kconfig (v2)

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[PATCH v2 01/10] drm/amd/display: add asics info for SI parts

[Mauro Rossi]

Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL

Tree path:
./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h
---
 .../gpu/drm/amd/display/include/dal_asic_id.h | 40 +++++++++++++++++++
 .../gpu/drm/amd/display/include/dal_types.h   |  3 ++
 2 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 4f501ddcfb8d..5b600c9445bd 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -30,6 +30,34 @@
  * ASIC internal revision ID
  */
 
+/* DCE60 (based on si_id.h in GPUOpen-Tools CodeXL) */
+#define SI_TAHITI_P_A0    0x01
+#define SI_TAHITI_P_B0    0x05
+#define SI_TAHITI_P_B1    0x06
+#define SI_PITCAIRN_PM_A0 0x14
+#define SI_PITCAIRN_PM_A1 0x15
+#define SI_CAPEVERDE_M_A0 0x28
+#define SI_CAPEVERDE_M_A1 0x29
+#define SI_OLAND_M_A0     0x3C
+#define SI_HAINAN_V_A0    0x46
+
+#define SI_UNKNOWN        0xFF
+
+#define ASIC_REV_IS_TAHITI_P(rev) \
+	((rev >= SI_TAHITI_P_A0) && (rev < SI_PITCAIRN_PM_A0))
+
+#define ASIC_REV_IS_PITCAIRN_PM(rev) \
+	((rev >= SI_PITCAIRN_PM_A0) && (rev < SI_CAPEVERDE_M_A0))
+
+#define ASIC_REV_IS_CAPEVERDE_M(rev) \
+	((rev >= SI_CAPEVERDE_M_A0) && (rev < SI_OLAND_M_A0))
+
+#define ASIC_REV_IS_OLAND_M(rev) \
+	((rev >= SI_OLAND_M_A0) && (rev < SI_HAINAN_V_A0))
+
+#define ASIC_REV_IS_HAINAN_V(rev) \
+	((rev >= SI_HAINAN_V_A0) && (rev < SI_UNKNOWN))
+
 /* DCE80 (based on ci_id.h in Perforce) */
 #define	CI_BONAIRE_M_A0 0x14
 #define	CI_BONAIRE_M_A1	0x15
@@ -150,12 +178,24 @@
 /*
  * ASIC chip ID
  */
+
+/* DCE60 */
+#define DEVICE_ID_SI_TAHITI_P_6780 0x6780
+#define DEVICE_ID_SI_PITCAIRN_PM_6800 0x6800
+#define DEVICE_ID_SI_PITCAIRN_PM_6808 0x6808
+#define DEVICE_ID_SI_CAPEVERDE_M_6820 0x6820
+#define DEVICE_ID_SI_CAPEVERDE_M_6828 0x6828
+#define DEVICE_ID_SI_OLAND_M_6600 0x6600
+#define DEVICE_ID_SI_OLAND_M_6608 0x6608
+#define DEVICE_ID_SI_HAINAN_V_6660 0x6660
+
 /* DCE80 */
 #define DEVICE_ID_KALINDI_9834 0x9834
 #define DEVICE_ID_TEMASH_9839 0x9839
 #define DEVICE_ID_TEMASH_983D 0x983D
 
 /* Asic Family IDs for different asic family. */
+#define FAMILY_SI 110 /* Southern Islands: Tahiti (P), Pitcairn (PM), Cape Verde (M), Oland (M), Hainan (V) */
 #define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
 #define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
 #define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index 89627133e188..c79f42544aae 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -34,6 +34,9 @@ struct dc_bios;
 
 enum dce_version {
 	DCE_VERSION_UNKNOWN = (-1),
+	DCE_VERSION_6_0,
+	DCE_VERSION_6_1,
+	DCE_VERSION_6_4,
 	DCE_VERSION_8_0,
 	DCE_VERSION_8_1,
 	DCE_VERSION_8_3,
-- 
2.17.1

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[PATCH v2 02/10] drm/amd/display: dc/dce: add DCE6 support (v2)

[Mauro Rossi]

DCE6 targets are added replicating existing DCE8 implementation.

NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
only to build dce60_resource.c due to missing *_DCE60 macros/registers/masks

IMPORTANT: Coding of dce60_resource.c requires review to understand
if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks

(v2) updated dce60_{hw_sequencer,resources}.c as per amd-staging-drm-next
     removed dce_version cases in dc/dce/dce_clock_source.c
---
 drivers/gpu/drm/amd/display/dc/Makefile       |    4 +
 drivers/gpu/drm/amd/display/dc/dce60/Makefile |   34 +
 .../amd/display/dc/dce60/dce60_hw_sequencer.c |   82 +
 .../amd/display/dc/dce60/dce60_hw_sequencer.h |   36 +
 .../drm/amd/display/dc/dce60/dce60_resource.c | 1458 +++++++++++++++++
 .../drm/amd/display/dc/dce60/dce60_resource.h |   47 +
 .../display/dc/dce60/dce60_timing_generator.c |  242 +++
 .../display/dc/dce60/dce60_timing_generator.h |   39 +
 .../include/asic_reg/dce/dce_6_0_sh_mask.h    |    4 +
 9 files changed, 1946 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/Makefile
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h

diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index aed538a4d1ba..d5d5acd57559 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -36,6 +36,10 @@ DC_LIBS += dce110
 DC_LIBS += dce100
 DC_LIBS += dce80
 
+ifdef CONFIG_DRM_AMD_DC_SI
+DC_LIBS += dce60
+endif
+
 AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LIBS)))
 
 include $(AMD_DC)
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/Makefile b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
new file mode 100644
index 000000000000..39afd7c59a7c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
@@ -0,0 +1,34 @@
+#
+# Copyright 2017 Advanced Micro Devices, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+# OTHER DEALINGS IN THE SOFTWARE.
+#
+#
+# Makefile for the 'controller' sub-component of DAL.
+# It provides the control and status of HW CRTC block.
+
+DCE60 = dce60_timing_generator.o dce60_hw_sequencer.o \
+	dce60_resource.o
+
+AMD_DAL_DCE60 = $(addprefix $(AMDDALPATH)/dc/dce60/,$(DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCE60)
+
+
+
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
new file mode 100644
index 000000000000..502172bf6097
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dc.h"
+#include "core_types.h"
+#include "dce60_hw_sequencer.h"
+
+#include "dce/dce_hwseq.h"
+#include "dce110/dce110_hw_sequencer.h"
+#include "dce100/dce100_hw_sequencer.h"
+
+/* include DCE8 register header files */
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+struct dce60_hw_seq_reg_offsets {
+	uint32_t crtc;
+};
+
+static const struct dce60_hw_seq_reg_offsets reg_offsets[] = {
+{
+	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+	.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+	.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+	.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+}
+};
+
+#define HW_REG_CRTC(reg, id)\
+	(reg + reg_offsets[id].crtc)
+
+/*******************************************************************************
+ * Private definitions
+ ******************************************************************************/
+
+/***************************PIPE_CONTROL***********************************/
+
+void dce60_hw_sequencer_construct(struct dc *dc)
+{
+	dce110_hw_sequencer_construct(dc);
+
+	dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
+	dc->hwss.pipe_control_lock = dce_pipe_control_lock;
+	dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
+	dc->hwss.optimize_bandwidth = dce100_prepare_bandwidth;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
new file mode 100644
index 000000000000..e7ce63b1f75a
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
@@ -0,0 +1,36 @@
+/*
+* Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HWSS_DCE60_H__
+#define __DC_HWSS_DCE60_H__
+
+#include "core_types.h"
+
+struct dc;
+
+void dce60_hw_sequencer_construct(struct dc *dc);
+
+#endif /* __DC_HWSS_DCE60_H__ */
+
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
new file mode 100644
index 000000000000..2731f31ce999
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
@@ -0,0 +1,1458 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dce/dce_8_0_d.h"
+#include "dce/dce_8_0_sh_mask.h"
+
+#include "dm_services.h"
+
+#include "link_encoder.h"
+#include "stream_encoder.h"
+
+#include "resource.h"
+#include "include/irq_service_interface.h"
+#include "irq/dce60/irq_service_dce60.h"
+#include "dce110/dce110_timing_generator.h"
+#include "dce110/dce110_resource.h"
+#include "dce60/dce60_timing_generator.h"
+#include "dce/dce_clk_mgr.h"
+#include "dce/dce_mem_input.h"
+#include "dce/dce_link_encoder.h"
+#include "dce/dce_stream_encoder.h"
+#include "dce/dce_mem_input.h"
+#include "dce/dce_ipp.h"
+#include "dce/dce_transform.h"
+#include "dce/dce_opp.h"
+#include "dce/dce_clock_source.h"
+#include "dce/dce_audio.h"
+#include "dce/dce_hwseq.h"
+#include "dce60/dce60_hw_sequencer.h"
+#include "dce100/dce100_resource.h"
+
+#include "reg_helper.h"
+
+#include "dce/dce_dmcu.h"
+#include "dce/dce_aux.h"
+#include "dce/dce_abm.h"
+#include "dce/dce_i2c.h"
+/* TODO remove this include */
+
+#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
+#include "gmc/gmc_6_0_d.h"
+#include "gmc/gmc_6_0_sh_mask.h"
+#endif
+
+#ifndef mmDP_DPHY_INTERNAL_CTRL
+#define mmDP_DPHY_INTERNAL_CTRL                         0x1CDE
+#define mmDP0_DP_DPHY_INTERNAL_CTRL                     0x1CDE
+#define mmDP1_DP_DPHY_INTERNAL_CTRL                     0x1FDE
+#define mmDP2_DP_DPHY_INTERNAL_CTRL                     0x42DE
+#define mmDP3_DP_DPHY_INTERNAL_CTRL                     0x45DE
+#define mmDP4_DP_DPHY_INTERNAL_CTRL                     0x48DE
+#define mmDP5_DP_DPHY_INTERNAL_CTRL                     0x4BDE
+#define mmDP6_DP_DPHY_INTERNAL_CTRL                     0x4EDE
+#endif
+
+
+#ifndef mmBIOS_SCRATCH_2
+	#define mmBIOS_SCRATCH_2 0x05CB
+	#define mmBIOS_SCRATCH_6 0x05CF
+#endif
+
+#ifndef mmDP_DPHY_FAST_TRAINING
+	#define mmDP_DPHY_FAST_TRAINING                         0x1CCE
+	#define mmDP0_DP_DPHY_FAST_TRAINING                     0x1CCE
+	#define mmDP1_DP_DPHY_FAST_TRAINING                     0x1FCE
+	#define mmDP2_DP_DPHY_FAST_TRAINING                     0x42CE
+	#define mmDP3_DP_DPHY_FAST_TRAINING                     0x45CE
+	#define mmDP4_DP_DPHY_FAST_TRAINING                     0x48CE
+	#define mmDP5_DP_DPHY_FAST_TRAINING                     0x4BCE
+	#define mmDP6_DP_DPHY_FAST_TRAINING                     0x4ECE
+#endif
+
+
+#ifndef mmHPD_DC_HPD_CONTROL
+	#define mmHPD_DC_HPD_CONTROL                            0x189A
+	#define mmHPD0_DC_HPD_CONTROL                           0x189A
+	#define mmHPD1_DC_HPD_CONTROL                           0x18A2
+	#define mmHPD2_DC_HPD_CONTROL                           0x18AA
+	#define mmHPD3_DC_HPD_CONTROL                           0x18B2
+	#define mmHPD4_DC_HPD_CONTROL                           0x18BA
+	#define mmHPD5_DC_HPD_CONTROL                           0x18C2
+#endif
+
+#define DCE11_DIG_FE_CNTL 0x4a00
+#define DCE11_DIG_BE_CNTL 0x4a47
+#define DCE11_DP_SEC 0x4ac3
+
+static const struct dce110_timing_generator_offsets dce60_tg_offsets[] = {
+		{
+			.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
+			.dcp =  (mmGRPH_CONTROL - mmGRPH_CONTROL),
+			.dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
+					- mmDPG_WATERMARK_MASK_CONTROL),
+		},
+		{
+			.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
+			.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
+			.dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
+					- mmDPG_WATERMARK_MASK_CONTROL),
+		},
+		{
+			.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
+			.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
+			.dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
+					- mmDPG_WATERMARK_MASK_CONTROL),
+		},
+		{
+			.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
+			.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
+			.dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
+					- mmDPG_WATERMARK_MASK_CONTROL),
+		},
+		{
+			.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
+			.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
+			.dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
+					- mmDPG_WATERMARK_MASK_CONTROL),
+		},
+		{
+			.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
+			.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
+			.dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
+					- mmDPG_WATERMARK_MASK_CONTROL),
+		}
+};
+
+/* set register offset */
+#define SR(reg_name)\
+	.reg_name = mm ## reg_name
+
+/* set register offset with instance */
+#define SRI(reg_name, block, id)\
+	.reg_name = mm ## block ## id ## _ ## reg_name
+
+
+static const struct clk_mgr_registers disp_clk_regs = {
+		CLK_COMMON_REG_LIST_DCE_BASE()
+};
+
+static const struct clk_mgr_shift disp_clk_shift = {
+		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
+};
+
+static const struct clk_mgr_mask disp_clk_mask = {
+		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
+};
+
+#define ipp_regs(id)\
+[id] = {\
+		IPP_COMMON_REG_LIST_DCE_BASE(id)\
+}
+
+static const struct dce_ipp_registers ipp_regs[] = {
+		ipp_regs(0),
+		ipp_regs(1),
+		ipp_regs(2),
+		ipp_regs(3),
+		ipp_regs(4),
+		ipp_regs(5)
+};
+
+static const struct dce_ipp_shift ipp_shift = {
+		IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
+};
+
+static const struct dce_ipp_mask ipp_mask = {
+		IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
+};
+
+#define transform_regs(id)\
+[id] = {\
+		XFM_COMMON_REG_LIST_DCE80(id)\
+}
+
+static const struct dce_transform_registers xfm_regs[] = {
+		transform_regs(0),
+		transform_regs(1),
+		transform_regs(2),
+		transform_regs(3),
+		transform_regs(4),
+		transform_regs(5)
+};
+
+static const struct dce_transform_shift xfm_shift = {
+		XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
+};
+
+static const struct dce_transform_mask xfm_mask = {
+		XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
+};
+
+#define aux_regs(id)\
+[id] = {\
+	AUX_REG_LIST(id)\
+}
+
+static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
+	aux_regs(0),
+	aux_regs(1),
+	aux_regs(2),
+	aux_regs(3),
+	aux_regs(4),
+	aux_regs(5)
+};
+
+#define hpd_regs(id)\
+[id] = {\
+	HPD_REG_LIST(id)\
+}
+
+static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
+		hpd_regs(0),
+		hpd_regs(1),
+		hpd_regs(2),
+		hpd_regs(3),
+		hpd_regs(4),
+		hpd_regs(5)
+};
+
+#define link_regs(id)\
+[id] = {\
+	LE_DCE80_REG_LIST(id)\
+}
+
+static const struct dce110_link_enc_registers link_enc_regs[] = {
+	link_regs(0),
+	link_regs(1),
+	link_regs(2),
+	link_regs(3),
+	link_regs(4),
+	link_regs(5),
+	link_regs(6),
+};
+
+#define stream_enc_regs(id)\
+[id] = {\
+	SE_COMMON_REG_LIST_DCE_BASE(id),\
+	.AFMT_CNTL = 0,\
+}
+
+static const struct dce110_stream_enc_registers stream_enc_regs[] = {
+	stream_enc_regs(0),
+	stream_enc_regs(1),
+	stream_enc_regs(2),
+	stream_enc_regs(3),
+	stream_enc_regs(4),
+	stream_enc_regs(5),
+	stream_enc_regs(6)
+};
+
+static const struct dce_stream_encoder_shift se_shift = {
+		SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
+};
+
+static const struct dce_stream_encoder_mask se_mask = {
+		SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
+};
+
+#define opp_regs(id)\
+[id] = {\
+	OPP_DCE_80_REG_LIST(id),\
+}
+
+static const struct dce_opp_registers opp_regs[] = {
+	opp_regs(0),
+	opp_regs(1),
+	opp_regs(2),
+	opp_regs(3),
+	opp_regs(4),
+	opp_regs(5)
+};
+
+static const struct dce_opp_shift opp_shift = {
+	OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
+};
+
+static const struct dce_opp_mask opp_mask = {
+	OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
+};
+
+#define aux_engine_regs(id)\
+[id] = {\
+	AUX_COMMON_REG_LIST(id), \
+	.AUX_RESET_MASK = 0 \
+}
+
+static const struct dce110_aux_registers aux_engine_regs[] = {
+		aux_engine_regs(0),
+		aux_engine_regs(1),
+		aux_engine_regs(2),
+		aux_engine_regs(3),
+		aux_engine_regs(4),
+		aux_engine_regs(5)
+};
+
+#define audio_regs(id)\
+[id] = {\
+	AUD_COMMON_REG_LIST(id)\
+}
+
+static const struct dce_audio_registers audio_regs[] = {
+	audio_regs(0),
+	audio_regs(1),
+	audio_regs(2),
+	audio_regs(3),
+	audio_regs(4),
+	audio_regs(5),
+	audio_regs(6),
+};
+
+static const struct dce_audio_shift audio_shift = {
+		AUD_COMMON_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_aduio_mask audio_mask = {
+		AUD_COMMON_MASK_SH_LIST(_MASK)
+};
+
+#define clk_src_regs(id)\
+[id] = {\
+	CS_COMMON_REG_LIST_DCE_80(id),\
+}
+
+
+static const struct dce110_clk_src_regs clk_src_regs[] = {
+	clk_src_regs(0),
+	clk_src_regs(1),
+	clk_src_regs(2)
+};
+
+static const struct dce110_clk_src_shift cs_shift = {
+		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
+};
+
+static const struct dce110_clk_src_mask cs_mask = {
+		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
+};
+
+static const struct bios_registers bios_regs = {
+	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
+};
+
+static const struct resource_caps res_cap = {
+		.num_timing_generator = 6,
+		.num_audio = 6,
+		.num_stream_encoder = 6,
+		.num_pll = 2,
+		.num_ddc = 6,
+};
+
+static const struct resource_caps res_cap_61 = {
+		.num_timing_generator = 4,
+		.num_audio = 6,
+		.num_stream_encoder = 6,
+		.num_pll = 2,
+		.num_ddc = 6,
+};
+
+static const struct resource_caps res_cap_64 = {
+		.num_timing_generator = 2,
+		.num_audio = 2,
+		.num_stream_encoder = 2,
+		.num_pll = 2,
+		.num_ddc = 2,
+};
+
+static const struct dce_dmcu_registers dmcu_regs = {
+		DMCU_DCE80_REG_LIST()
+};
+
+static const struct dce_dmcu_shift dmcu_shift = {
+		DMCU_MASK_SH_LIST_DCE80(__SHIFT)
+};
+
+static const struct dce_dmcu_mask dmcu_mask = {
+		DMCU_MASK_SH_LIST_DCE80(_MASK)
+};
+static const struct dce_abm_registers abm_regs = {
+		ABM_DCE110_COMMON_REG_LIST()
+};
+
+static const struct dce_abm_shift abm_shift = {
+		ABM_MASK_SH_LIST_DCE110(__SHIFT)
+};
+
+static const struct dce_abm_mask abm_mask = {
+		ABM_MASK_SH_LIST_DCE110(_MASK)
+};
+
+#define CTX  ctx
+#define REG(reg) mm ## reg
+
+#ifndef mmCC_DC_HDMI_STRAPS
+#define mmCC_DC_HDMI_STRAPS 0x1918
+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
+#endif
+
+static void read_dce_straps(
+	struct dc_context *ctx,
+	struct resource_straps *straps)
+{
+	REG_GET_2(CC_DC_HDMI_STRAPS,
+			HDMI_DISABLE, &straps->hdmi_disable,
+			AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
+
+	REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
+}
+
+static struct audio *create_audio(
+		struct dc_context *ctx, unsigned int inst)
+{
+	return dce_audio_create(ctx, inst,
+			&audio_regs[inst], &audio_shift, &audio_mask);
+}
+
+static struct timing_generator *dce60_timing_generator_create(
+		struct dc_context *ctx,
+		uint32_t instance,
+		const struct dce110_timing_generator_offsets *offsets)
+{
+	struct dce110_timing_generator *tg110 =
+		kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
+
+	if (!tg110)
+		return NULL;
+
+	dce60_timing_generator_construct(tg110, ctx, instance, offsets);
+	return &tg110->base;
+}
+
+static struct output_pixel_processor *dce60_opp_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dce110_opp *opp =
+		kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
+
+	if (!opp)
+		return NULL;
+
+	dce110_opp_construct(opp,
+			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
+	return &opp->base;
+}
+
+struct aux_engine *dce60_aux_engine_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct aux_engine_dce110 *aux_engine =
+		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
+
+	if (!aux_engine)
+		return NULL;
+
+	dce110_aux_engine_construct(aux_engine, ctx, inst,
+				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+				    &aux_engine_regs[inst]);
+
+	return &aux_engine->base;
+}
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
+
+static const struct dce_i2c_registers i2c_hw_regs[] = {
+		i2c_inst_regs(1),
+		i2c_inst_regs(2),
+		i2c_inst_regs(3),
+		i2c_inst_regs(4),
+		i2c_inst_regs(5),
+		i2c_inst_regs(6),
+};
+
+static const struct dce_i2c_shift i2c_shifts = {
+		I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
+};
+
+static const struct dce_i2c_mask i2c_masks = {
+		I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
+};
+
+struct dce_i2c_hw *dce60_i2c_hw_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dce_i2c_hw *dce_i2c_hw =
+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
+
+	if (!dce_i2c_hw)
+		return NULL;
+
+	dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
+				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
+
+	return dce_i2c_hw;
+}
+
+struct dce_i2c_sw *dce60_i2c_sw_create(
+	struct dc_context *ctx)
+{
+	struct dce_i2c_sw *dce_i2c_sw =
+		kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
+
+	if (!dce_i2c_sw)
+		return NULL;
+
+	dce_i2c_sw_construct(dce_i2c_sw, ctx);
+
+	return dce_i2c_sw;
+}
+static struct stream_encoder *dce60_stream_encoder_create(
+	enum engine_id eng_id,
+	struct dc_context *ctx)
+{
+	struct dce110_stream_encoder *enc110 =
+		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
+
+	if (!enc110)
+		return NULL;
+
+	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
+					&stream_enc_regs[eng_id],
+					&se_shift, &se_mask);
+	return &enc110->base;
+}
+
+#define SRII(reg_name, block, id)\
+	.reg_name[id] = mm ## block ## id ## _ ## reg_name
+
+static const struct dce_hwseq_registers hwseq_reg = {
+		HWSEQ_DCE8_REG_LIST()
+};
+
+static const struct dce_hwseq_shift hwseq_shift = {
+		HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+		HWSEQ_DCE8_MASK_SH_LIST(_MASK)
+};
+
+static struct dce_hwseq *dce60_hwseq_create(
+	struct dc_context *ctx)
+{
+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
+
+	if (hws) {
+		hws->ctx = ctx;
+		hws->regs = &hwseq_reg;
+		hws->shifts = &hwseq_shift;
+		hws->masks = &hwseq_mask;
+	}
+	return hws;
+}
+
+static const struct resource_create_funcs res_create_funcs = {
+	.read_dce_straps = read_dce_straps,
+	.create_audio = create_audio,
+	.create_stream_encoder = dce60_stream_encoder_create,
+	.create_hwseq = dce60_hwseq_create,
+};
+
+#define mi_inst_regs(id) { \
+	MI_DCE8_REG_LIST(id), \
+	.MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
+}
+static const struct dce_mem_input_registers mi_regs[] = {
+		mi_inst_regs(0),
+		mi_inst_regs(1),
+		mi_inst_regs(2),
+		mi_inst_regs(3),
+		mi_inst_regs(4),
+		mi_inst_regs(5),
+};
+
+static const struct dce_mem_input_shift mi_shifts = {
+		MI_DCE8_MASK_SH_LIST(__SHIFT),
+		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
+};
+
+static const struct dce_mem_input_mask mi_masks = {
+		MI_DCE8_MASK_SH_LIST(_MASK),
+		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
+};
+
+static struct mem_input *dce60_mem_input_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
+					       GFP_KERNEL);
+
+	if (!dce_mi) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
+	dce_mi->wa.single_head_rdreq_dmif_limit = 2;
+	return &dce_mi->base;
+}
+
+static void dce60_transform_destroy(struct transform **xfm)
+{
+	kfree(TO_DCE_TRANSFORM(*xfm));
+	*xfm = NULL;
+}
+
+static struct transform *dce60_transform_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dce_transform *transform =
+		kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
+
+	if (!transform)
+		return NULL;
+
+	dce_transform_construct(transform, ctx, inst,
+				&xfm_regs[inst], &xfm_shift, &xfm_mask);
+	transform->prescaler_on = false;
+	return &transform->base;
+}
+
+static const struct encoder_feature_support link_enc_feature = {
+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
+		.max_hdmi_pixel_clock = 297000,
+		.flags.bits.IS_HBR2_CAPABLE = true,
+		.flags.bits.IS_TPS3_CAPABLE = true
+};
+
+struct link_encoder *dce60_link_encoder_create(
+	const struct encoder_init_data *enc_init_data)
+{
+	struct dce110_link_encoder *enc110 =
+		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
+
+	if (!enc110)
+		return NULL;
+
+	dce110_link_encoder_construct(enc110,
+				      enc_init_data,
+				      &link_enc_feature,
+				      &link_enc_regs[enc_init_data->transmitter],
+				      &link_enc_aux_regs[enc_init_data->channel - 1],
+				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
+	return &enc110->base;
+}
+
+struct clock_source *dce60_clock_source_create(
+	struct dc_context *ctx,
+	struct dc_bios *bios,
+	enum clock_source_id id,
+	const struct dce110_clk_src_regs *regs,
+	bool dp_clk_src)
+{
+	struct dce110_clk_src *clk_src =
+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
+
+	if (!clk_src)
+		return NULL;
+
+	if (dce110_clk_src_construct(clk_src, ctx, bios, id,
+			regs, &cs_shift, &cs_mask)) {
+		clk_src->base.dp_clk_src = dp_clk_src;
+		return &clk_src->base;
+	}
+
+	BREAK_TO_DEBUGGER();
+	return NULL;
+}
+
+void dce60_clock_source_destroy(struct clock_source **clk_src)
+{
+	kfree(TO_DCE110_CLK_SRC(*clk_src));
+	*clk_src = NULL;
+}
+
+static struct input_pixel_processor *dce60_ipp_create(
+	struct dc_context *ctx, uint32_t inst)
+{
+	struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
+
+	if (!ipp) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dce_ipp_construct(ipp, ctx, inst,
+			&ipp_regs[inst], &ipp_shift, &ipp_mask);
+	return &ipp->base;
+}
+
+static void destruct(struct dce110_resource_pool *pool)
+{
+	unsigned int i;
+
+	for (i = 0; i < pool->base.pipe_count; i++) {
+		if (pool->base.opps[i] != NULL)
+			dce110_opp_destroy(&pool->base.opps[i]);
+
+		if (pool->base.transforms[i] != NULL)
+			dce60_transform_destroy(&pool->base.transforms[i]);
+
+		if (pool->base.ipps[i] != NULL)
+			dce_ipp_destroy(&pool->base.ipps[i]);
+
+		if (pool->base.mis[i] != NULL) {
+			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
+			pool->base.mis[i] = NULL;
+		}
+
+		if (pool->base.timing_generators[i] != NULL)	{
+			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
+			pool->base.timing_generators[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		if (pool->base.engines[i] != NULL)
+			dce110_engine_destroy(&pool->base.engines[i]);
+		if (pool->base.hw_i2cs[i] != NULL) {
+			kfree(pool->base.hw_i2cs[i]);
+			pool->base.hw_i2cs[i] = NULL;
+		}
+		if (pool->base.sw_i2cs[i] != NULL) {
+			kfree(pool->base.sw_i2cs[i]);
+			pool->base.sw_i2cs[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.stream_enc_count; i++) {
+		if (pool->base.stream_enc[i] != NULL)
+			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
+	}
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] != NULL) {
+			dce60_clock_source_destroy(&pool->base.clock_sources[i]);
+		}
+	}
+
+	if (pool->base.abm != NULL)
+			dce_abm_destroy(&pool->base.abm);
+
+	if (pool->base.dmcu != NULL)
+			dce_dmcu_destroy(&pool->base.dmcu);
+
+	if (pool->base.dp_clock_source != NULL)
+		dce60_clock_source_destroy(&pool->base.dp_clock_source);
+
+	for (i = 0; i < pool->base.audio_count; i++)	{
+		if (pool->base.audios[i] != NULL) {
+			dce_aud_destroy(&pool->base.audios[i]);
+		}
+	}
+
+	if (pool->base.clk_mgr != NULL)
+		dce_clk_mgr_destroy(&pool->base.clk_mgr);
+
+	if (pool->base.irqs != NULL) {
+		dal_irq_service_destroy(&pool->base.irqs);
+	}
+}
+
+bool dce60_validate_bandwidth(
+	struct dc *dc,
+	struct dc_state *context)
+{
+	/* TODO implement when needed but for now hardcode max value*/
+	context->bw.dce.dispclk_khz = 681000;
+	context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
+
+	return true;
+}
+
+static bool dce60_validate_surface_sets(
+		struct dc_state *context)
+{
+	int i;
+
+	for (i = 0; i < context->stream_count; i++) {
+		if (context->stream_status[i].plane_count == 0)
+			continue;
+
+		if (context->stream_status[i].plane_count > 1)
+			return false;
+
+		if (context->stream_status[i].plane_states[0]->format
+				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
+			return false;
+	}
+
+	return true;
+}
+
+enum dc_status dce60_validate_global(
+		struct dc *dc,
+		struct dc_state *context)
+{
+	if (!dce60_validate_surface_sets(context))
+		return DC_FAIL_SURFACE_VALIDATE;
+
+	return DC_OK;
+}
+
+static void dce60_destroy_resource_pool(struct resource_pool **pool)
+{
+	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
+
+	destruct(dce110_pool);
+	kfree(dce110_pool);
+	*pool = NULL;
+}
+
+static const struct resource_funcs dce60_res_pool_funcs = {
+	.destroy = dce60_destroy_resource_pool,
+	.link_enc_create = dce60_link_encoder_create,
+	.validate_bandwidth = dce60_validate_bandwidth,
+	.validate_plane = dce100_validate_plane,
+	.add_stream_to_ctx = dce100_add_stream_to_ctx,
+	.validate_global = dce60_validate_global
+};
+
+static bool dce60_construct(
+	uint8_t num_virtual_links,
+	struct dc *dc,
+	struct dce110_resource_pool *pool)
+{
+	unsigned int i;
+	struct dc_context *ctx = dc->ctx;
+	struct dc_firmware_info info;
+	struct dc_bios *bp;
+
+	ctx->dc_bios->regs = &bios_regs;
+
+	pool->base.res_cap = &res_cap;
+	pool->base.funcs = &dce60_res_pool_funcs;
+
+
+	/*************************************************
+	 *  Resource + asic cap harcoding                *
+	 *************************************************/
+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+	pool->base.pipe_count = res_cap.num_timing_generator;
+	pool->base.timing_generator_count = res_cap.num_timing_generator;
+	dc->caps.max_downscale_ratio = 200;
+	dc->caps.i2c_speed_in_khz = 40;
+	dc->caps.max_cursor_size = 128;
+	dc->caps.dual_link_dvi = true;
+
+	/*************************************************
+	 *  Create resources                             *
+	 *************************************************/
+
+	bp = ctx->dc_bios;
+
+	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+		info.external_clock_source_frequency_for_dp != 0) {
+		pool->base.dp_clock_source =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+
+		pool->base.clock_sources[0] =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
+		pool->base.clock_sources[1] =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
+		pool->base.clock_sources[2] =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
+		pool->base.clk_src_count = 3;
+
+	} else {
+		pool->base.dp_clock_source =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
+
+		pool->base.clock_sources[0] =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
+		pool->base.clock_sources[1] =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
+		pool->base.clk_src_count = 2;
+	}
+
+	if (pool->base.dp_clock_source == NULL) {
+		dm_error("DC: failed to create dp clock source!\n");
+		BREAK_TO_DEBUGGER();
+		goto res_create_fail;
+	}
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] == NULL) {
+			dm_error("DC: failed to create clock sources!\n");
+			BREAK_TO_DEBUGGER();
+			goto res_create_fail;
+		}
+	}
+
+	pool->base.clk_mgr = dce_clk_mgr_create(ctx,
+			&disp_clk_regs,
+			&disp_clk_shift,
+			&disp_clk_mask);
+	if (pool->base.clk_mgr == NULL) {
+		dm_error("DC: failed to create display clock!\n");
+		BREAK_TO_DEBUGGER();
+		goto res_create_fail;
+	}
+
+	pool->base.dmcu = dce_dmcu_create(ctx,
+			&dmcu_regs,
+			&dmcu_shift,
+			&dmcu_mask);
+	if (pool->base.dmcu == NULL) {
+		dm_error("DC: failed to create dmcu!\n");
+		BREAK_TO_DEBUGGER();
+		goto res_create_fail;
+	}
+
+	pool->base.abm = dce_abm_create(ctx,
+			&abm_regs,
+			&abm_shift,
+			&abm_mask);
+	if (pool->base.abm == NULL) {
+		dm_error("DC: failed to create abm!\n");
+		BREAK_TO_DEBUGGER();
+		goto res_create_fail;
+	}
+
+	{
+		struct irq_service_init_data init_data;
+		init_data.ctx = dc->ctx;
+		pool->base.irqs = dal_irq_service_dce60_create(&init_data);
+		if (!pool->base.irqs)
+			goto res_create_fail;
+	}
+
+	for (i = 0; i < pool->base.pipe_count; i++) {
+		pool->base.timing_generators[i] = dce60_timing_generator_create(
+				ctx, i, &dce60_tg_offsets[i]);
+		if (pool->base.timing_generators[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create tg!\n");
+			goto res_create_fail;
+		}
+
+		pool->base.mis[i] = dce60_mem_input_create(ctx, i);
+		if (pool->base.mis[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create memory input!\n");
+			goto res_create_fail;
+		}
+
+		pool->base.ipps[i] = dce60_ipp_create(ctx, i);
+		if (pool->base.ipps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create input pixel processor!\n");
+			goto res_create_fail;
+		}
+
+		pool->base.transforms[i] = dce60_transform_create(ctx, i);
+		if (pool->base.transforms[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create transform!\n");
+			goto res_create_fail;
+		}
+
+		pool->base.opps[i] = dce60_opp_create(ctx, i);
+		if (pool->base.opps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create output pixel processor!\n");
+			goto res_create_fail;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
+		if (pool->base.engines[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create aux engine!!\n");
+			goto res_create_fail;
+		}
+		pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
+		if (pool->base.hw_i2cs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create i2c engine!!\n");
+			goto res_create_fail;
+		}
+		pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
+		if (pool->base.sw_i2cs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create sw i2c!!\n");
+			goto res_create_fail;
+		}
+	}
+
+	dc->caps.max_planes =  pool->base.pipe_count;
+	dc->caps.disable_dp_clk_share = true;
+
+	if (!resource_construct(num_virtual_links, dc, &pool->base,
+			&res_create_funcs))
+		goto res_create_fail;
+
+	/* Create hardware sequencer */
+	dce60_hw_sequencer_construct(dc);
+
+	return true;
+
+res_create_fail:
+	destruct(pool);
+	return false;
+}
+
+struct resource_pool *dce60_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc)
+{
+	struct dce110_resource_pool *pool =
+		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
+
+	if (!pool)
+		return NULL;
+
+	if (dce60_construct(num_virtual_links, dc, pool))
+		return &pool->base;
+
+	BREAK_TO_DEBUGGER();
+	return NULL;
+}
+
+static bool dce61_construct(
+	uint8_t num_virtual_links,
+	struct dc *dc,
+	struct dce110_resource_pool *pool)
+{
+	unsigned int i;
+	struct dc_context *ctx = dc->ctx;
+	struct dc_firmware_info info;
+	struct dc_bios *bp;
+
+	ctx->dc_bios->regs = &bios_regs;
+
+	pool->base.res_cap = &res_cap_61;
+	pool->base.funcs = &dce60_res_pool_funcs;
+
+
+	/*************************************************
+	 *  Resource + asic cap harcoding                *
+	 *************************************************/
+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+	pool->base.pipe_count = res_cap_61.num_timing_generator;
+	pool->base.timing_generator_count = res_cap_61.num_timing_generator;
+	dc->caps.max_downscale_ratio = 200;
+	dc->caps.i2c_speed_in_khz = 40;
+	dc->caps.max_cursor_size = 128;
+	dc->caps.is_apu = true;
+
+	/*************************************************
+	 *  Create resources                             *
+	 *************************************************/
+
+	bp = ctx->dc_bios;
+
+	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+		info.external_clock_source_frequency_for_dp != 0) {
+		pool->base.dp_clock_source =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+
+		pool->base.clock_sources[0] =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
+		pool->base.clock_sources[1] =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
+		pool->base.clock_sources[2] =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
+		pool->base.clk_src_count = 3;
+
+	} else {
+		pool->base.dp_clock_source =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
+
+		pool->base.clock_sources[0] =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
+		pool->base.clock_sources[1] =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
+		pool->base.clk_src_count = 2;
+	}
+
+	if (pool->base.dp_clock_source == NULL) {
+		dm_error("DC: failed to create dp clock source!\n");
+		BREAK_TO_DEBUGGER();
+		goto res_create_fail;
+	}
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] == NULL) {
+			dm_error("DC: failed to create clock sources!\n");
+			BREAK_TO_DEBUGGER();
+			goto res_create_fail;
+		}
+	}
+
+	pool->base.clk_mgr = dce_clk_mgr_create(ctx,
+			&disp_clk_regs,
+			&disp_clk_shift,
+			&disp_clk_mask);
+	if (pool->base.clk_mgr == NULL) {
+		dm_error("DC: failed to create display clock!\n");
+		BREAK_TO_DEBUGGER();
+		goto res_create_fail;
+	}
+
+	pool->base.dmcu = dce_dmcu_create(ctx,
+			&dmcu_regs,
+			&dmcu_shift,
+			&dmcu_mask);
+	if (pool->base.dmcu == NULL) {
+		dm_error("DC: failed to create dmcu!\n");
+		BREAK_TO_DEBUGGER();
+		goto res_create_fail;
+	}
+
+	pool->base.abm = dce_abm_create(ctx,
+			&abm_regs,
+			&abm_shift,
+			&abm_mask);
+	if (pool->base.abm == NULL) {
+		dm_error("DC: failed to create abm!\n");
+		BREAK_TO_DEBUGGER();
+		goto res_create_fail;
+	}
+
+	{
+		struct irq_service_init_data init_data;
+		init_data.ctx = dc->ctx;
+		pool->base.irqs = dal_irq_service_dce60_create(&init_data);
+		if (!pool->base.irqs)
+			goto res_create_fail;
+	}
+
+	for (i = 0; i < pool->base.pipe_count; i++) {
+		pool->base.timing_generators[i] = dce60_timing_generator_create(
+				ctx, i, &dce60_tg_offsets[i]);
+		if (pool->base.timing_generators[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create tg!\n");
+			goto res_create_fail;
+		}
+
+		pool->base.mis[i] = dce60_mem_input_create(ctx, i);
+		if (pool->base.mis[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create memory input!\n");
+			goto res_create_fail;
+		}
+
+		pool->base.ipps[i] = dce60_ipp_create(ctx, i);
+		if (pool->base.ipps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create input pixel processor!\n");
+			goto res_create_fail;
+		}
+
+		pool->base.transforms[i] = dce60_transform_create(ctx, i);
+		if (pool->base.transforms[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create transform!\n");
+			goto res_create_fail;
+		}
+
+		pool->base.opps[i] = dce60_opp_create(ctx, i);
+		if (pool->base.opps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create output pixel processor!\n");
+			goto res_create_fail;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
+		if (pool->base.engines[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create aux engine!!\n");
+			goto res_create_fail;
+		}
+		pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
+		if (pool->base.hw_i2cs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create i2c engine!!\n");
+			goto res_create_fail;
+		}
+		pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
+		if (pool->base.sw_i2cs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create sw i2c!!\n");
+			goto res_create_fail;
+		}
+	}
+
+	dc->caps.max_planes =  pool->base.pipe_count;
+	dc->caps.disable_dp_clk_share = true;
+
+	if (!resource_construct(num_virtual_links, dc, &pool->base,
+			&res_create_funcs))
+		goto res_create_fail;
+
+	/* Create hardware sequencer */
+	dce60_hw_sequencer_construct(dc);
+
+	return true;
+
+res_create_fail:
+	destruct(pool);
+	return false;
+}
+
+struct resource_pool *dce61_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc)
+{
+	struct dce110_resource_pool *pool =
+		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
+
+	if (!pool)
+		return NULL;
+
+	if (dce61_construct(num_virtual_links, dc, pool))
+		return &pool->base;
+
+	BREAK_TO_DEBUGGER();
+	return NULL;
+}
+
+static bool dce64_construct(
+	uint8_t num_virtual_links,
+	struct dc *dc,
+	struct dce110_resource_pool *pool)
+{
+	unsigned int i;
+	struct dc_context *ctx = dc->ctx;
+	struct dc_firmware_info info;
+	struct dc_bios *bp;
+
+	ctx->dc_bios->regs = &bios_regs;
+
+	pool->base.res_cap = &res_cap_64;
+	pool->base.funcs = &dce60_res_pool_funcs;
+
+
+	/*************************************************
+	 *  Resource + asic cap harcoding                *
+	 *************************************************/
+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+	pool->base.pipe_count = res_cap_64.num_timing_generator;
+	pool->base.timing_generator_count = res_cap_64.num_timing_generator;
+	dc->caps.max_downscale_ratio = 200;
+	dc->caps.i2c_speed_in_khz = 40;
+	dc->caps.max_cursor_size = 128;
+	dc->caps.is_apu = true;
+
+	/*************************************************
+	 *  Create resources                             *
+	 *************************************************/
+
+	bp = ctx->dc_bios;
+
+	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+		info.external_clock_source_frequency_for_dp != 0) {
+		pool->base.dp_clock_source =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+
+		pool->base.clock_sources[0] =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
+		pool->base.clock_sources[1] =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
+		pool->base.clk_src_count = 2;
+
+	} else {
+		pool->base.dp_clock_source =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
+
+		pool->base.clock_sources[0] =
+				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
+		pool->base.clk_src_count = 1;
+	}
+
+	if (pool->base.dp_clock_source == NULL) {
+		dm_error("DC: failed to create dp clock source!\n");
+		BREAK_TO_DEBUGGER();
+		goto res_create_fail;
+	}
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] == NULL) {
+			dm_error("DC: failed to create clock sources!\n");
+			BREAK_TO_DEBUGGER();
+			goto res_create_fail;
+		}
+	}
+
+	pool->base.clk_mgr = dce_clk_mgr_create(ctx,
+			&disp_clk_regs,
+			&disp_clk_shift,
+			&disp_clk_mask);
+	if (pool->base.clk_mgr == NULL) {
+		dm_error("DC: failed to create display clock!\n");
+		BREAK_TO_DEBUGGER();
+		goto res_create_fail;
+	}
+
+	pool->base.dmcu = dce_dmcu_create(ctx,
+			&dmcu_regs,
+			&dmcu_shift,
+			&dmcu_mask);
+	if (pool->base.dmcu == NULL) {
+		dm_error("DC: failed to create dmcu!\n");
+		BREAK_TO_DEBUGGER();
+		goto res_create_fail;
+	}
+
+	pool->base.abm = dce_abm_create(ctx,
+			&abm_regs,
+			&abm_shift,
+			&abm_mask);
+	if (pool->base.abm == NULL) {
+		dm_error("DC: failed to create abm!\n");
+		BREAK_TO_DEBUGGER();
+		goto res_create_fail;
+	}
+
+	{
+		struct irq_service_init_data init_data;
+		init_data.ctx = dc->ctx;
+		pool->base.irqs = dal_irq_service_dce60_create(&init_data);
+		if (!pool->base.irqs)
+			goto res_create_fail;
+	}
+
+	for (i = 0; i < pool->base.pipe_count; i++) {
+		pool->base.timing_generators[i] = dce60_timing_generator_create(
+				ctx, i, &dce60_tg_offsets[i]);
+		if (pool->base.timing_generators[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create tg!\n");
+			goto res_create_fail;
+		}
+
+		pool->base.mis[i] = dce60_mem_input_create(ctx, i);
+		if (pool->base.mis[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create memory input!\n");
+			goto res_create_fail;
+		}
+
+		pool->base.ipps[i] = dce60_ipp_create(ctx, i);
+		if (pool->base.ipps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create input pixel processor!\n");
+			goto res_create_fail;
+		}
+
+		pool->base.transforms[i] = dce60_transform_create(ctx, i);
+		if (pool->base.transforms[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create transform!\n");
+			goto res_create_fail;
+		}
+
+		pool->base.opps[i] = dce60_opp_create(ctx, i);
+		if (pool->base.opps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create output pixel processor!\n");
+			goto res_create_fail;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
+		if (pool->base.engines[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create aux engine!!\n");
+			goto res_create_fail;
+		}
+		pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
+		if (pool->base.hw_i2cs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create i2c engine!!\n");
+			goto res_create_fail;
+		}
+		pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
+		if (pool->base.sw_i2cs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create sw i2c!!\n");
+			goto res_create_fail;
+		}
+	}
+
+	dc->caps.max_planes =  pool->base.pipe_count;
+	dc->caps.disable_dp_clk_share = true;
+
+	if (!resource_construct(num_virtual_links, dc, &pool->base,
+			&res_create_funcs))
+		goto res_create_fail;
+
+	/* Create hardware sequencer */
+	dce60_hw_sequencer_construct(dc);
+
+	return true;
+
+res_create_fail:
+	destruct(pool);
+	return false;
+}
+
+struct resource_pool *dce64_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc)
+{
+	struct dce110_resource_pool *pool =
+		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
+
+	if (!pool)
+		return NULL;
+
+	if (dce64_construct(num_virtual_links, dc, pool))
+		return &pool->base;
+
+	BREAK_TO_DEBUGGER();
+	return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
new file mode 100644
index 000000000000..b30e4e4ed7c0
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
@@ -0,0 +1,47 @@
+/*
+* Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_RESOURCE_DCE60_H__
+#define __DC_RESOURCE_DCE60_H__
+
+#include "core_types.h"
+
+struct dc;
+struct resource_pool;
+
+struct resource_pool *dce60_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc);
+
+struct resource_pool *dce61_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc);
+
+struct resource_pool *dce64_create_resource_pool(
+	uint8_t num_virtual_links,
+	struct dc *dc);
+
+#endif /* __DC_RESOURCE_DCE60_H__ */
+
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
new file mode 100644
index 000000000000..90b610367af8
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
@@ -0,0 +1,242 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/* include DCE6 register header files */
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+#include "dc_types.h"
+
+#include "include/grph_object_id.h"
+#include "include/logger_interface.h"
+#include "../dce110/dce110_timing_generator.h"
+#include "dce60_timing_generator.h"
+
+#include "timing_generator.h"
+
+enum black_color_format {
+	BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,	/* used as index in array */
+	BLACK_COLOR_FORMAT_RGB_LIMITED,
+	BLACK_COLOR_FORMAT_YUV_TV,
+	BLACK_COLOR_FORMAT_YUV_CV,
+	BLACK_COLOR_FORMAT_YUV_SUPER_AA,
+
+	BLACK_COLOR_FORMAT_COUNT
+};
+
+static const struct dce110_timing_generator_offsets reg_offsets[] = {
+{
+	.crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
+	.dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+},
+{
+	.crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
+	.dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+},
+{
+	.crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
+	.dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+},
+{
+	.crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
+	.dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+},
+{
+	.crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
+	.dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+},
+{
+	.crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
+	.dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+}
+};
+
+#define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
+
+#define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
+#define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
+
+#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
+#define DCP_REG(reg) (reg + tg110->offsets.dcp)
+#define DMIF_REG(reg) (reg + tg110->offsets.dmif)
+
+static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
+{
+	uint64_t pix_dur;
+	uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
+					+ DCE110TG_FROM_TG(tg)->offsets.dmif;
+	uint32_t value = dm_read_reg(tg->ctx, addr);
+
+	if (pix_clk_khz == 0)
+		return;
+
+	pix_dur = 1000000000 / pix_clk_khz;
+
+	set_reg_field_value(
+		value,
+		pix_dur,
+		DPG_PIPE_ARBITRATION_CONTROL1,
+		PIXEL_DURATION);
+
+	dm_write_reg(tg->ctx, addr, value);
+}
+
+static void program_timing(struct timing_generator *tg,
+	const struct dc_crtc_timing *timing,
+	bool use_vbios)
+{
+	if (!use_vbios)
+		program_pix_dur(tg, timing->pix_clk_khz);
+
+	dce110_tg_program_timing(tg, timing, use_vbios);
+}
+
+static void dce60_timing_generator_enable_advanced_request(
+	struct timing_generator *tg,
+	bool enable,
+	const struct dc_crtc_timing *timing)
+{
+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
+	uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
+	uint32_t value = dm_read_reg(tg->ctx, addr);
+
+	if (enable) {
+		set_reg_field_value(
+			value,
+			0,
+			CRTC_START_LINE_CONTROL,
+			CRTC_LEGACY_REQUESTOR_EN);
+	} else {
+		set_reg_field_value(
+			value,
+			1,
+			CRTC_START_LINE_CONTROL,
+			CRTC_LEGACY_REQUESTOR_EN);
+	}
+
+	if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
+		set_reg_field_value(
+			value,
+			3,
+			CRTC_START_LINE_CONTROL,
+			CRTC_ADVANCED_START_LINE_POSITION);
+		set_reg_field_value(
+			value,
+			0,
+			CRTC_START_LINE_CONTROL,
+			CRTC_PREFETCH_EN);
+	} else {
+		set_reg_field_value(
+			value,
+			4,
+			CRTC_START_LINE_CONTROL,
+			CRTC_ADVANCED_START_LINE_POSITION);
+		set_reg_field_value(
+			value,
+			1,
+			CRTC_START_LINE_CONTROL,
+			CRTC_PREFETCH_EN);
+	}
+
+	set_reg_field_value(
+		value,
+		1,
+		CRTC_START_LINE_CONTROL,
+		CRTC_PROGRESSIVE_START_LINE_EARLY);
+
+	set_reg_field_value(
+		value,
+		1,
+		CRTC_START_LINE_CONTROL,
+		CRTC_INTERLACE_START_LINE_EARLY);
+
+	dm_write_reg(tg->ctx, addr, value);
+}
+
+static const struct timing_generator_funcs dce60_tg_funcs = {
+		.validate_timing = dce110_tg_validate_timing,
+		.program_timing = program_timing,
+		.enable_crtc = dce110_timing_generator_enable_crtc,
+		.disable_crtc = dce110_timing_generator_disable_crtc,
+		.is_counter_moving = dce110_timing_generator_is_counter_moving,
+		.get_position = dce110_timing_generator_get_position,
+		.get_frame_count = dce110_timing_generator_get_vblank_counter,
+		.get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
+		.set_early_control = dce110_timing_generator_set_early_control,
+		.wait_for_state = dce110_tg_wait_for_state,
+		.set_blank = dce110_tg_set_blank,
+		.is_blanked = dce110_tg_is_blanked,
+		.set_colors = dce110_tg_set_colors,
+		.set_overscan_blank_color =
+				dce110_timing_generator_set_overscan_color_black,
+		.set_blank_color = dce110_timing_generator_program_blank_color,
+		.disable_vga = dce110_timing_generator_disable_vga,
+		.did_triggered_reset_occur =
+				dce110_timing_generator_did_triggered_reset_occur,
+		.setup_global_swap_lock =
+				dce110_timing_generator_setup_global_swap_lock,
+		.enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
+		.disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
+		.tear_down_global_swap_lock =
+				dce110_timing_generator_tear_down_global_swap_lock,
+		.set_drr = dce110_timing_generator_set_drr,
+		.set_static_screen_control =
+			dce110_timing_generator_set_static_screen_control,
+		.set_test_pattern = dce110_timing_generator_set_test_pattern,
+		.arm_vert_intr = dce110_arm_vert_intr,
+
+		/* DCE6.0 overrides */
+		.enable_advanced_request =
+				dce60_timing_generator_enable_advanced_request,
+		.configure_crc = dce110_configure_crc,
+		.get_crc = dce110_get_crc,
+};
+
+void dce60_timing_generator_construct(
+	struct dce110_timing_generator *tg110,
+	struct dc_context *ctx,
+	uint32_t instance,
+	const struct dce110_timing_generator_offsets *offsets)
+{
+	tg110->controller_id = CONTROLLER_ID_D0 + instance;
+	tg110->base.inst = instance;
+	tg110->offsets = *offsets;
+	tg110->derived_offsets = reg_offsets[instance];
+
+	tg110->base.funcs = &dce60_tg_funcs;
+
+	tg110->base.ctx = ctx;
+	tg110->base.bp = ctx->dc_bios;
+
+	tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
+	tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
+
+	tg110->min_h_blank = 56;
+	tg110->min_h_front_porch = 4;
+	tg110->min_h_back_porch = 4;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
new file mode 100644
index 000000000000..8972cd0d5815
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_TIMING_GENERATOR_DCE60_H__
+#define __DC_TIMING_GENERATOR_DCE60_H__
+
+#include "timing_generator.h"
+#include "../include/grph_object_id.h"
+
+/* DCE6.0 implementation inherits from DCE11.0 */
+void dce60_timing_generator_construct(
+	struct dce110_timing_generator *tg,
+	struct dc_context *ctx,
+	uint32_t instance,
+	const struct dce110_timing_generator_offsets *offsets);
+
+#endif /* __DC_TIMING_GENERATOR_DCE60_H__ */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
index abe05bc80752..5492c6b98525 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
@@ -2264,6 +2264,10 @@
 #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x00000010
 #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000100L
 #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x00000008
+#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100000
+#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x14
+#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000
+#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x1c
 #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
 #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x00000000
 #define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
-- 
2.17.1

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Re: [PATCH v2 02/10] drm/amd/display: dc/dce: add DCE6 support (v2)

[Wentland, Harry]

On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> DCE6 targets are added replicating existing DCE8 implementation.
> 
> NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
> only to build dce60_resource.c due to missing *_DCE60 macros/registers/masks
> 
> IMPORTANT: Coding of dce60_resource.c requires review to understand
> if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
> 
> (v2) updated dce60_{hw_sequencer,resources}.c as per amd-staging-drm-next
>      removed dce_version cases in dc/dce/dce_clock_source.c
> ---
>  drivers/gpu/drm/amd/display/dc/Makefile       |    4 +
>  drivers/gpu/drm/amd/display/dc/dce60/Makefile |   34 +
>  .../amd/display/dc/dce60/dce60_hw_sequencer.c |   82 +
>  .../amd/display/dc/dce60/dce60_hw_sequencer.h |   36 +
>  .../drm/amd/display/dc/dce60/dce60_resource.c | 1458 +++++++++++++++++
>  .../drm/amd/display/dc/dce60/dce60_resource.h |   47 +
>  .../display/dc/dce60/dce60_timing_generator.c |  242 +++
>  .../display/dc/dce60/dce60_timing_generator.h |   39 +
>  .../include/asic_reg/dce/dce_6_0_sh_mask.h    |    4 +
>  9 files changed, 1946 insertions(+)
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/Makefile
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
> index aed538a4d1ba..d5d5acd57559 100644
> --- a/drivers/gpu/drm/amd/display/dc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> @@ -36,6 +36,10 @@ DC_LIBS += dce110
>  DC_LIBS += dce100
>  DC_LIBS += dce80
>  
> +ifdef CONFIG_DRM_AMD_DC_SI
> +DC_LIBS += dce60
> +endif
> +
>  AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LIBS)))
>  
>  include $(AMD_DC)
> diff --git a/drivers/gpu/drm/amd/display/dc/dce60/Makefile b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
> new file mode 100644
> index 000000000000..39afd7c59a7c
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
> @@ -0,0 +1,34 @@
> +#
> +# Copyright 2017 Advanced Micro Devices, Inc.
> +#
> +# Permission is hereby granted, free of charge, to any person obtaining a
> +# copy of this software and associated documentation files (the "Software"),
> +# to deal in the Software without restriction, including without limitation
> +# the rights to use, copy, modify, merge, publish, distribute, sublicense,
> +# and/or sell copies of the Software, and to permit persons to whom the
> +# Software is furnished to do so, subject to the following conditions:
> +#
> +# The above copyright notice and this permission notice shall be included in
> +# all copies or substantial portions of the Software.
> +#
> +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> +# OTHER DEALINGS IN THE SOFTWARE.
> +#
> +#
> +# Makefile for the 'controller' sub-component of DAL.
> +# It provides the control and status of HW CRTC block.
> +
> +DCE60 = dce60_timing_generator.o dce60_hw_sequencer.o \
> +	dce60_resource.o
> +
> +AMD_DAL_DCE60 = $(addprefix $(AMDDALPATH)/dc/dce60/,$(DCE60))
> +
> +AMD_DISPLAY_FILES += $(AMD_DAL_DCE60)
> +
> +
> +
> diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
> new file mode 100644
> index 000000000000..502172bf6097
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
> @@ -0,0 +1,82 @@
> +/*
> + * Copyright 2015 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: AMD
> + *
> + */
> +
> +#include "dm_services.h"
> +#include "dc.h"
> +#include "core_types.h"
> +#include "dce60_hw_sequencer.h"
> +
> +#include "dce/dce_hwseq.h"
> +#include "dce110/dce110_hw_sequencer.h"
> +#include "dce100/dce100_hw_sequencer.h"
> +
> +/* include DCE8 register header files */

drop comment or change DCE8 to DCE6

> +#include "dce/dce_6_0_d.h"
> +#include "dce/dce_6_0_sh_mask.h"
> +
> +struct dce60_hw_seq_reg_offsets {
> +	uint32_t crtc;
> +};
> +
> +static const struct dce60_hw_seq_reg_offsets reg_offsets[] = {
> +{
> +	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> +},
> +{
> +	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> +},
> +{
> +	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> +},
> +{
> +	.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> +},
> +{
> +	.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> +},
> +{
> +	.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> +}
> +};
> +
> +#define HW_REG_CRTC(reg, id)\
> +	(reg + reg_offsets[id].crtc)
> +
> +/*******************************************************************************
> + * Private definitions
> + ******************************************************************************/
> +
> +/***************************PIPE_CONTROL***********************************/
> +
> +void dce60_hw_sequencer_construct(struct dc *dc)
> +{
> +	dce110_hw_sequencer_construct(dc);
> +
> +	dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
> +	dc->hwss.pipe_control_lock = dce_pipe_control_lock;
> +	dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
> +	dc->hwss.optimize_bandwidth = dce100_prepare_bandwidth;
> +}
> +
> diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
> new file mode 100644
> index 000000000000..e7ce63b1f75a
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
> @@ -0,0 +1,36 @@
> +/*
> +* Copyright 2012-15 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: AMD
> + *
> + */
> +
> +#ifndef __DC_HWSS_DCE60_H__
> +#define __DC_HWSS_DCE60_H__
> +
> +#include "core_types.h"
> +
> +struct dc;
> +
> +void dce60_hw_sequencer_construct(struct dc *dc);
> +
> +#endif /* __DC_HWSS_DCE60_H__ */
> +
> diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
> new file mode 100644
> index 000000000000..2731f31ce999
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
> @@ -0,0 +1,1458 @@
> +/*
> + * Copyright 2012-15 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: AMD
> + *
> + */
> +
> +#include "dce/dce_8_0_d.h"
> +#include "dce/dce_8_0_sh_mask.h"

This file should really use the dce6 headers. What happens if we build with the dce6 headers? If it's missing definitions I can probably send an update to the headers with what's missing.

> +
> +#include "dm_services.h"
> +
> +#include "link_encoder.h"
> +#include "stream_encoder.h"
> +
> +#include "resource.h"
> +#include "include/irq_service_interface.h"
> +#include "irq/dce60/irq_service_dce60.h"
> +#include "dce110/dce110_timing_generator.h"
> +#include "dce110/dce110_resource.h"
> +#include "dce60/dce60_timing_generator.h"
> +#include "dce/dce_clk_mgr.h"
> +#include "dce/dce_mem_input.h"
> +#include "dce/dce_link_encoder.h"
> +#include "dce/dce_stream_encoder.h"
> +#include "dce/dce_mem_input.h"
> +#include "dce/dce_ipp.h"
> +#include "dce/dce_transform.h"
> +#include "dce/dce_opp.h"
> +#include "dce/dce_clock_source.h"
> +#include "dce/dce_audio.h"
> +#include "dce/dce_hwseq.h"
> +#include "dce60/dce60_hw_sequencer.h"
> +#include "dce100/dce100_resource.h"
> +
> +#include "reg_helper.h"
> +
> +#include "dce/dce_dmcu.h"
> +#include "dce/dce_aux.h"
> +#include "dce/dce_abm.h"
> +#include "dce/dce_i2c.h"
> +/* TODO remove this include */
> +
> +#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
> +#include "gmc/gmc_6_0_d.h"
> +#include "gmc/gmc_6_0_sh_mask.h"
> +#endif
> +
> +#ifndef mmDP_DPHY_INTERNAL_CTRL
> +#define mmDP_DPHY_INTERNAL_CTRL                         0x1CDE
> +#define mmDP0_DP_DPHY_INTERNAL_CTRL                     0x1CDE
> +#define mmDP1_DP_DPHY_INTERNAL_CTRL                     0x1FDE
> +#define mmDP2_DP_DPHY_INTERNAL_CTRL                     0x42DE
> +#define mmDP3_DP_DPHY_INTERNAL_CTRL                     0x45DE
> +#define mmDP4_DP_DPHY_INTERNAL_CTRL                     0x48DE
> +#define mmDP5_DP_DPHY_INTERNAL_CTRL                     0x4BDE
> +#define mmDP6_DP_DPHY_INTERNAL_CTRL                     0x4EDE

No SI part has 7 pipes. Let's drop mmDP6_DP_DPHY_INTERNAL_CTRL.

> +#endif
> +
> +
> +#ifndef mmBIOS_SCRATCH_2
> +	#define mmBIOS_SCRATCH_2 0x05CB
> +	#define mmBIOS_SCRATCH_6 0x05CF
> +#endif
> +
> +#ifndef mmDP_DPHY_FAST_TRAINING
> +	#define mmDP_DPHY_FAST_TRAINING                         0x1CCE
> +	#define mmDP0_DP_DPHY_FAST_TRAINING                     0x1CCE
> +	#define mmDP1_DP_DPHY_FAST_TRAINING                     0x1FCE
> +	#define mmDP2_DP_DPHY_FAST_TRAINING                     0x42CE
> +	#define mmDP3_DP_DPHY_FAST_TRAINING                     0x45CE
> +	#define mmDP4_DP_DPHY_FAST_TRAINING                     0x48CE
> +	#define mmDP5_DP_DPHY_FAST_TRAINING                     0x4BCE
> +	#define mmDP6_DP_DPHY_FAST_TRAINING                     0x4ECE
> +#endif
> +

Drop mmDP6_DP_DPHY_FAST_TRAINING.

Otherwise the registers above this line look right.

> +
> +#ifndef mmHPD_DC_HPD_CONTROL
> +	#define mmHPD_DC_HPD_CONTROL                            0x189A
> +	#define mmHPD0_DC_HPD_CONTROL                           0x189A
> +	#define mmHPD1_DC_HPD_CONTROL                           0x18A2
> +	#define mmHPD2_DC_HPD_CONTROL                           0x18AA
> +	#define mmHPD3_DC_HPD_CONTROL                           0x18B2
> +	#define mmHPD4_DC_HPD_CONTROL                           0x18BA
> +	#define mmHPD5_DC_HPD_CONTROL                           0x18C2
> +#endif
> +
> +#define DCE11_DIG_FE_CNTL 0x4a00
> +#define DCE11_DIG_BE_CNTL 0x4a47
> +#define DCE11_DP_SEC 0x4ac3
> +

These registers (from mmHPD_DC_HPD_CONTROL down to here) are unused and can all be dropped. We should also drop them in dce80_resource.c in a separate patch. I leave it up to you if you want to do it.

> +static const struct dce110_timing_generator_offsets dce60_tg_offsets[] = {
> +		{
> +			.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
> +			.dcp =  (mmGRPH_CONTROL - mmGRPH_CONTROL),
> +			.dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
> +					- mmDPG_WATERMARK_MASK_CONTROL),
> +		},
> +		{
> +			.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
> +			.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
> +			.dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
> +					- mmDPG_WATERMARK_MASK_CONTROL),
> +		},
> +		{
> +			.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
> +			.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
> +			.dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
> +					- mmDPG_WATERMARK_MASK_CONTROL),
> +		},
> +		{
> +			.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
> +			.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
> +			.dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
> +					- mmDPG_WATERMARK_MASK_CONTROL),
> +		},
> +		{
> +			.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
> +			.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
> +			.dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
> +					- mmDPG_WATERMARK_MASK_CONTROL),
> +		},
> +		{
> +			.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
> +			.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
> +			.dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
> +					- mmDPG_WATERMARK_MASK_CONTROL),
> +		}
> +};
> +
> +/* set register offset */
> +#define SR(reg_name)\
> +	.reg_name = mm ## reg_name
> +
> +/* set register offset with instance */
> +#define SRI(reg_name, block, id)\
> +	.reg_name = mm ## block ## id ## _ ## reg_name
> +
> +
> +static const struct clk_mgr_registers disp_clk_regs = {
> +		CLK_COMMON_REG_LIST_DCE_BASE()
> +};
> +
> +static const struct clk_mgr_shift disp_clk_shift = {
> +		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
> +};
> +
> +static const struct clk_mgr_mask disp_clk_mask = {
> +		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> +};
> +
> +#define ipp_regs(id)\
> +[id] = {\
> +		IPP_COMMON_REG_LIST_DCE_BASE(id)\
> +}
> +
> +static const struct dce_ipp_registers ipp_regs[] = {
> +		ipp_regs(0),
> +		ipp_regs(1),
> +		ipp_regs(2),
> +		ipp_regs(3),
> +		ipp_regs(4),
> +		ipp_regs(5)
> +};
> +
> +static const struct dce_ipp_shift ipp_shift = {
> +		IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
> +};
> +
> +static const struct dce_ipp_mask ipp_mask = {
> +		IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> +};
> +
> +#define transform_regs(id)\
> +[id] = {\
> +		XFM_COMMON_REG_LIST_DCE80(id)\
> +}
> +
> +static const struct dce_transform_registers xfm_regs[] = {
> +		transform_regs(0),
> +		transform_regs(1),
> +		transform_regs(2),
> +		transform_regs(3),
> +		transform_regs(4),
> +		transform_regs(5)
> +};
> +
> +static const struct dce_transform_shift xfm_shift = {
> +		XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
> +};
> +
> +static const struct dce_transform_mask xfm_mask = {
> +		XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
> +};
> +
> +#define aux_regs(id)\
> +[id] = {\
> +	AUX_REG_LIST(id)\
> +}
> +
> +static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
> +	aux_regs(0),
> +	aux_regs(1),
> +	aux_regs(2),
> +	aux_regs(3),
> +	aux_regs(4),
> +	aux_regs(5)
> +};
> +
> +#define hpd_regs(id)\
> +[id] = {\
> +	HPD_REG_LIST(id)\
> +}
> +
> +static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
> +		hpd_regs(0),
> +		hpd_regs(1),
> +		hpd_regs(2),
> +		hpd_regs(3),
> +		hpd_regs(4),
> +		hpd_regs(5)
> +};
> +
> +#define link_regs(id)\
> +[id] = {\
> +	LE_DCE80_REG_LIST(id)\
> +}
> +
> +static const struct dce110_link_enc_registers link_enc_regs[] = {
> +	link_regs(0),
> +	link_regs(1),
> +	link_regs(2),
> +	link_regs(3),
> +	link_regs(4),
> +	link_regs(5),
> +	link_regs(6),
> +};
> +
> +#define stream_enc_regs(id)\
> +[id] = {\
> +	SE_COMMON_REG_LIST_DCE_BASE(id),\
> +	.AFMT_CNTL = 0,\
> +}
> +
> +static const struct dce110_stream_enc_registers stream_enc_regs[] = {
> +	stream_enc_regs(0),
> +	stream_enc_regs(1),
> +	stream_enc_regs(2),
> +	stream_enc_regs(3),
> +	stream_enc_regs(4),
> +	stream_enc_regs(5),
> +	stream_enc_regs(6)
> +};
> +
> +static const struct dce_stream_encoder_shift se_shift = {
> +		SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
> +};
> +
> +static const struct dce_stream_encoder_mask se_mask = {
> +		SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
> +};
> +
> +#define opp_regs(id)\
> +[id] = {\
> +	OPP_DCE_80_REG_LIST(id),\
> +}
> +
> +static const struct dce_opp_registers opp_regs[] = {
> +	opp_regs(0),
> +	opp_regs(1),
> +	opp_regs(2),
> +	opp_regs(3),
> +	opp_regs(4),
> +	opp_regs(5)
> +};
> +
> +static const struct dce_opp_shift opp_shift = {
> +	OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
> +};
> +
> +static const struct dce_opp_mask opp_mask = {
> +	OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
> +};
> +
> +#define aux_engine_regs(id)\
> +[id] = {\
> +	AUX_COMMON_REG_LIST(id), \
> +	.AUX_RESET_MASK = 0 \
> +}
> +
> +static const struct dce110_aux_registers aux_engine_regs[] = {
> +		aux_engine_regs(0),
> +		aux_engine_regs(1),
> +		aux_engine_regs(2),
> +		aux_engine_regs(3),
> +		aux_engine_regs(4),
> +		aux_engine_regs(5)
> +};
> +
> +#define audio_regs(id)\
> +[id] = {\
> +	AUD_COMMON_REG_LIST(id)\
> +}
> +
> +static const struct dce_audio_registers audio_regs[] = {
> +	audio_regs(0),
> +	audio_regs(1),
> +	audio_regs(2),
> +	audio_regs(3),
> +	audio_regs(4),
> +	audio_regs(5),
> +	audio_regs(6),

Only 6 audios on SI, so drop audio_regs(6).

> +};
> +
> +static const struct dce_audio_shift audio_shift = {
> +		AUD_COMMON_MASK_SH_LIST(__SHIFT)
> +};
> +
> +static const struct dce_aduio_mask audio_mask = {
> +		AUD_COMMON_MASK_SH_LIST(_MASK)
> +};
> +
> +#define clk_src_regs(id)\
> +[id] = {\
> +	CS_COMMON_REG_LIST_DCE_80(id),\
> +}
> +
> +
> +static const struct dce110_clk_src_regs clk_src_regs[] = {
> +	clk_src_regs(0),
> +	clk_src_regs(1),
> +	clk_src_regs(2)
> +};
> +
> +static const struct dce110_clk_src_shift cs_shift = {
> +		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
> +};
> +
> +static const struct dce110_clk_src_mask cs_mask = {
> +		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> +};
> +
> +static const struct bios_registers bios_regs = {
> +	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
> +};
> +
> +static const struct resource_caps res_cap = {
> +		.num_timing_generator = 6,
> +		.num_audio = 6,
> +		.num_stream_encoder = 6,
> +		.num_pll = 2,
> +		.num_ddc = 6,
> +};
> +
> +static const struct resource_caps res_cap_61 = {
> +		.num_timing_generator = 4,
> +		.num_audio = 6,
> +		.num_stream_encoder = 6,
> +		.num_pll = 2,
> +		.num_ddc = 6,
> +};
> +
> +static const struct resource_caps res_cap_64 = {
> +		.num_timing_generator = 2,
> +		.num_audio = 2,
> +		.num_stream_encoder = 2,
> +		.num_pll = 2,
> +		.num_ddc = 2,
> +};
> +
> +static const struct dce_dmcu_registers dmcu_regs = {
> +		DMCU_DCE80_REG_LIST()
> +};
> +
> +static const struct dce_dmcu_shift dmcu_shift = {
> +		DMCU_MASK_SH_LIST_DCE80(__SHIFT)
> +};
> +
> +static const struct dce_dmcu_mask dmcu_mask = {
> +		DMCU_MASK_SH_LIST_DCE80(_MASK)
> +};
> +static const struct dce_abm_registers abm_regs = {
> +		ABM_DCE110_COMMON_REG_LIST()
> +};
> +
> +static const struct dce_abm_shift abm_shift = {
> +		ABM_MASK_SH_LIST_DCE110(__SHIFT)
> +};
> +
> +static const struct dce_abm_mask abm_mask = {
> +		ABM_MASK_SH_LIST_DCE110(_MASK)
> +};
> +
> +#define CTX  ctx
> +#define REG(reg) mm ## reg
> +
> +#ifndef mmCC_DC_HDMI_STRAPS
> +#define mmCC_DC_HDMI_STRAPS 0x1918
> +#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
> +#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
> +#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
> +#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
> +#endif
> +

These registers defines are all good.

> +static void read_dce_straps(
> +	struct dc_context *ctx,
> +	struct resource_straps *straps)
> +{
> +	REG_GET_2(CC_DC_HDMI_STRAPS,
> +			HDMI_DISABLE, &straps->hdmi_disable,
> +			AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
> +
> +	REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
> +}
> +
> +static struct audio *create_audio(
> +		struct dc_context *ctx, unsigned int inst)
> +{
> +	return dce_audio_create(ctx, inst,
> +			&audio_regs[inst], &audio_shift, &audio_mask);
> +}
> +
> +static struct timing_generator *dce60_timing_generator_create(
> +		struct dc_context *ctx,
> +		uint32_t instance,
> +		const struct dce110_timing_generator_offsets *offsets)
> +{
> +	struct dce110_timing_generator *tg110 =
> +		kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
> +
> +	if (!tg110)
> +		return NULL;
> +
> +	dce60_timing_generator_construct(tg110, ctx, instance, offsets);
> +	return &tg110->base;
> +}
> +
> +static struct output_pixel_processor *dce60_opp_create(
> +	struct dc_context *ctx,
> +	uint32_t inst)
> +{
> +	struct dce110_opp *opp =
> +		kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
> +
> +	if (!opp)
> +		return NULL;
> +
> +	dce110_opp_construct(opp,
> +			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
> +	return &opp->base;
> +}
> +
> +struct aux_engine *dce60_aux_engine_create(
> +	struct dc_context *ctx,
> +	uint32_t inst)
> +{
> +	struct aux_engine_dce110 *aux_engine =
> +		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
> +
> +	if (!aux_engine)
> +		return NULL;
> +
> +	dce110_aux_engine_construct(aux_engine, ctx, inst,
> +				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
> +				    &aux_engine_regs[inst]);
> +
> +	return &aux_engine->base;
> +}
> +#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
> +
> +static const struct dce_i2c_registers i2c_hw_regs[] = {
> +		i2c_inst_regs(1),
> +		i2c_inst_regs(2),
> +		i2c_inst_regs(3),
> +		i2c_inst_regs(4),
> +		i2c_inst_regs(5),
> +		i2c_inst_regs(6),
> +};
> +
> +static const struct dce_i2c_shift i2c_shifts = {
> +		I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
> +};
> +
> +static const struct dce_i2c_mask i2c_masks = {
> +		I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> +};
> +
> +struct dce_i2c_hw *dce60_i2c_hw_create(
> +	struct dc_context *ctx,
> +	uint32_t inst)
> +{
> +	struct dce_i2c_hw *dce_i2c_hw =
> +		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
> +
> +	if (!dce_i2c_hw)
> +		return NULL;
> +
> +	dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
> +				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
> +
> +	return dce_i2c_hw;
> +}
> +
> +struct dce_i2c_sw *dce60_i2c_sw_create(
> +	struct dc_context *ctx)
> +{
> +	struct dce_i2c_sw *dce_i2c_sw =
> +		kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
> +
> +	if (!dce_i2c_sw)
> +		return NULL;
> +
> +	dce_i2c_sw_construct(dce_i2c_sw, ctx);
> +
> +	return dce_i2c_sw;
> +}
> +static struct stream_encoder *dce60_stream_encoder_create(
> +	enum engine_id eng_id,
> +	struct dc_context *ctx)
> +{
> +	struct dce110_stream_encoder *enc110 =
> +		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
> +
> +	if (!enc110)
> +		return NULL;
> +
> +	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
> +					&stream_enc_regs[eng_id],
> +					&se_shift, &se_mask);
> +	return &enc110->base;
> +}
> +
> +#define SRII(reg_name, block, id)\
> +	.reg_name[id] = mm ## block ## id ## _ ## reg_name
> +
> +static const struct dce_hwseq_registers hwseq_reg = {
> +		HWSEQ_DCE8_REG_LIST()
> +};
> +
> +static const struct dce_hwseq_shift hwseq_shift = {
> +		HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
> +};
> +
> +static const struct dce_hwseq_mask hwseq_mask = {
> +		HWSEQ_DCE8_MASK_SH_LIST(_MASK)
> +};
> +
> +static struct dce_hwseq *dce60_hwseq_create(
> +	struct dc_context *ctx)
> +{
> +	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
> +
> +	if (hws) {
> +		hws->ctx = ctx;
> +		hws->regs = &hwseq_reg;
> +		hws->shifts = &hwseq_shift;
> +		hws->masks = &hwseq_mask;
> +	}
> +	return hws;
> +}
> +
> +static const struct resource_create_funcs res_create_funcs = {
> +	.read_dce_straps = read_dce_straps,
> +	.create_audio = create_audio,
> +	.create_stream_encoder = dce60_stream_encoder_create,
> +	.create_hwseq = dce60_hwseq_create,
> +};
> +
> +#define mi_inst_regs(id) { \
> +	MI_DCE8_REG_LIST(id), \
> +	.MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
> +}
> +static const struct dce_mem_input_registers mi_regs[] = {
> +		mi_inst_regs(0),
> +		mi_inst_regs(1),
> +		mi_inst_regs(2),
> +		mi_inst_regs(3),
> +		mi_inst_regs(4),
> +		mi_inst_regs(5),
> +};
> +
> +static const struct dce_mem_input_shift mi_shifts = {
> +		MI_DCE8_MASK_SH_LIST(__SHIFT),
> +		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
> +};
> +
> +static const struct dce_mem_input_mask mi_masks = {
> +		MI_DCE8_MASK_SH_LIST(_MASK),
> +		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
> +};
> +
> +static struct mem_input *dce60_mem_input_create(
> +	struct dc_context *ctx,
> +	uint32_t inst)
> +{
> +	struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
> +					       GFP_KERNEL);
> +
> +	if (!dce_mi) {
> +		BREAK_TO_DEBUGGER();
> +		return NULL;
> +	}
> +
> +	dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
> +	dce_mi->wa.single_head_rdreq_dmif_limit = 2;
> +	return &dce_mi->base;
> +}
> +
> +static void dce60_transform_destroy(struct transform **xfm)
> +{
> +	kfree(TO_DCE_TRANSFORM(*xfm));
> +	*xfm = NULL;
> +}
> +
> +static struct transform *dce60_transform_create(
> +	struct dc_context *ctx,
> +	uint32_t inst)
> +{
> +	struct dce_transform *transform =
> +		kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
> +
> +	if (!transform)
> +		return NULL;
> +
> +	dce_transform_construct(transform, ctx, inst,
> +				&xfm_regs[inst], &xfm_shift, &xfm_mask);
> +	transform->prescaler_on = false;
> +	return &transform->base;
> +}
> +
> +static const struct encoder_feature_support link_enc_feature = {
> +		.max_hdmi_deep_color = COLOR_DEPTH_121212,
> +		.max_hdmi_pixel_clock = 297000,
> +		.flags.bits.IS_HBR2_CAPABLE = true,
> +		.flags.bits.IS_TPS3_CAPABLE = true
> +};
> +
> +struct link_encoder *dce60_link_encoder_create(
> +	const struct encoder_init_data *enc_init_data)
> +{
> +	struct dce110_link_encoder *enc110 =
> +		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
> +
> +	if (!enc110)
> +		return NULL;
> +
> +	dce110_link_encoder_construct(enc110,
> +				      enc_init_data,
> +				      &link_enc_feature,
> +				      &link_enc_regs[enc_init_data->transmitter],
> +				      &link_enc_aux_regs[enc_init_data->channel - 1],
> +				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
> +	return &enc110->base;
> +}
> +
> +struct clock_source *dce60_clock_source_create(
> +	struct dc_context *ctx,
> +	struct dc_bios *bios,
> +	enum clock_source_id id,
> +	const struct dce110_clk_src_regs *regs,
> +	bool dp_clk_src)
> +{
> +	struct dce110_clk_src *clk_src =
> +		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
> +
> +	if (!clk_src)
> +		return NULL;
> +
> +	if (dce110_clk_src_construct(clk_src, ctx, bios, id,
> +			regs, &cs_shift, &cs_mask)) {
> +		clk_src->base.dp_clk_src = dp_clk_src;
> +		return &clk_src->base;
> +	}
> +
> +	BREAK_TO_DEBUGGER();
> +	return NULL;
> +}
> +
> +void dce60_clock_source_destroy(struct clock_source **clk_src)
> +{
> +	kfree(TO_DCE110_CLK_SRC(*clk_src));
> +	*clk_src = NULL;
> +}
> +
> +static struct input_pixel_processor *dce60_ipp_create(
> +	struct dc_context *ctx, uint32_t inst)
> +{
> +	struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
> +
> +	if (!ipp) {
> +		BREAK_TO_DEBUGGER();
> +		return NULL;
> +	}
> +
> +	dce_ipp_construct(ipp, ctx, inst,
> +			&ipp_regs[inst], &ipp_shift, &ipp_mask);
> +	return &ipp->base;
> +}
> +
> +static void destruct(struct dce110_resource_pool *pool)
> +{
> +	unsigned int i;
> +
> +	for (i = 0; i < pool->base.pipe_count; i++) {
> +		if (pool->base.opps[i] != NULL)
> +			dce110_opp_destroy(&pool->base.opps[i]);
> +
> +		if (pool->base.transforms[i] != NULL)
> +			dce60_transform_destroy(&pool->base.transforms[i]);
> +
> +		if (pool->base.ipps[i] != NULL)
> +			dce_ipp_destroy(&pool->base.ipps[i]);
> +
> +		if (pool->base.mis[i] != NULL) {
> +			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
> +			pool->base.mis[i] = NULL;
> +		}
> +
> +		if (pool->base.timing_generators[i] != NULL)	{
> +			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
> +			pool->base.timing_generators[i] = NULL;
> +		}
> +	}
> +
> +	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
> +		if (pool->base.engines[i] != NULL)
> +			dce110_engine_destroy(&pool->base.engines[i]);
> +		if (pool->base.hw_i2cs[i] != NULL) {
> +			kfree(pool->base.hw_i2cs[i]);
> +			pool->base.hw_i2cs[i] = NULL;
> +		}
> +		if (pool->base.sw_i2cs[i] != NULL) {
> +			kfree(pool->base.sw_i2cs[i]);
> +			pool->base.sw_i2cs[i] = NULL;
> +		}
> +	}
> +
> +	for (i = 0; i < pool->base.stream_enc_count; i++) {
> +		if (pool->base.stream_enc[i] != NULL)
> +			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
> +	}
> +
> +	for (i = 0; i < pool->base.clk_src_count; i++) {
> +		if (pool->base.clock_sources[i] != NULL) {
> +			dce60_clock_source_destroy(&pool->base.clock_sources[i]);
> +		}
> +	}
> +
> +	if (pool->base.abm != NULL)
> +			dce_abm_destroy(&pool->base.abm);
> +
> +	if (pool->base.dmcu != NULL)
> +			dce_dmcu_destroy(&pool->base.dmcu);
> +
> +	if (pool->base.dp_clock_source != NULL)
> +		dce60_clock_source_destroy(&pool->base.dp_clock_source);
> +
> +	for (i = 0; i < pool->base.audio_count; i++)	{
> +		if (pool->base.audios[i] != NULL) {
> +			dce_aud_destroy(&pool->base.audios[i]);
> +		}
> +	}
> +
> +	if (pool->base.clk_mgr != NULL)
> +		dce_clk_mgr_destroy(&pool->base.clk_mgr);
> +
> +	if (pool->base.irqs != NULL) {
> +		dal_irq_service_destroy(&pool->base.irqs);
> +	}
> +}
> +
> +bool dce60_validate_bandwidth(
> +	struct dc *dc,
> +	struct dc_state *context)
> +{
> +	/* TODO implement when needed but for now hardcode max value*/
> +	context->bw.dce.dispclk_khz = 681000;
> +	context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
> +

Not sure where to find the actual values but this should be okay for now.

> +	return true;
> +}
> +
> +static bool dce60_validate_surface_sets(
> +		struct dc_state *context)
> +{
> +	int i;
> +
> +	for (i = 0; i < context->stream_count; i++) {
> +		if (context->stream_status[i].plane_count == 0)
> +			continue;
> +
> +		if (context->stream_status[i].plane_count > 1)
> +			return false;
> +
> +		if (context->stream_status[i].plane_states[0]->format
> +				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
> +			return false;
> +	}
> +
> +	return true;
> +}
> +
> +enum dc_status dce60_validate_global(
> +		struct dc *dc,
> +		struct dc_state *context)
> +{
> +	if (!dce60_validate_surface_sets(context))
> +		return DC_FAIL_SURFACE_VALIDATE;
> +
> +	return DC_OK;
> +}
> +
> +static void dce60_destroy_resource_pool(struct resource_pool **pool)
> +{
> +	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
> +
> +	destruct(dce110_pool);
> +	kfree(dce110_pool);
> +	*pool = NULL;
> +}
> +
> +static const struct resource_funcs dce60_res_pool_funcs = {
> +	.destroy = dce60_destroy_resource_pool,
> +	.link_enc_create = dce60_link_encoder_create,
> +	.validate_bandwidth = dce60_validate_bandwidth,
> +	.validate_plane = dce100_validate_plane,
> +	.add_stream_to_ctx = dce100_add_stream_to_ctx,
> +	.validate_global = dce60_validate_global
> +};
> +
> +static bool dce60_construct(
> +	uint8_t num_virtual_links,
> +	struct dc *dc,
> +	struct dce110_resource_pool *pool)
> +{
> +	unsigned int i;
> +	struct dc_context *ctx = dc->ctx;
> +	struct dc_firmware_info info;
> +	struct dc_bios *bp;
> +
> +	ctx->dc_bios->regs = &bios_regs;
> +
> +	pool->base.res_cap = &res_cap;
> +	pool->base.funcs = &dce60_res_pool_funcs;
> +
> +
> +	/*************************************************
> +	 *  Resource + asic cap harcoding                *
> +	 *************************************************/
> +	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
> +	pool->base.pipe_count = res_cap.num_timing_generator;
> +	pool->base.timing_generator_count = res_cap.num_timing_generator;
> +	dc->caps.max_downscale_ratio = 200;
> +	dc->caps.i2c_speed_in_khz = 40;
> +	dc->caps.max_cursor_size = 128;
> +	dc->caps.dual_link_dvi = true;
> +
> +	/*************************************************
> +	 *  Create resources                             *
> +	 *************************************************/
> +
> +	bp = ctx->dc_bios;
> +
> +	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
> +		info.external_clock_source_frequency_for_dp != 0) {
> +		pool->base.dp_clock_source =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
> +
> +		pool->base.clock_sources[0] =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
> +		pool->base.clock_sources[1] =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
> +		pool->base.clock_sources[2] =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
> +		pool->base.clk_src_count = 3;
> +
> +	} else {
> +		pool->base.dp_clock_source =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
> +
> +		pool->base.clock_sources[0] =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
> +		pool->base.clock_sources[1] =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
> +		pool->base.clk_src_count = 2;
> +	}
> +
> +	if (pool->base.dp_clock_source == NULL) {
> +		dm_error("DC: failed to create dp clock source!\n");
> +		BREAK_TO_DEBUGGER();
> +		goto res_create_fail;
> +	}
> +
> +	for (i = 0; i < pool->base.clk_src_count; i++) {
> +		if (pool->base.clock_sources[i] == NULL) {
> +			dm_error("DC: failed to create clock sources!\n");
> +			BREAK_TO_DEBUGGER();
> +			goto res_create_fail;
> +		}
> +	}
> +
> +	pool->base.clk_mgr = dce_clk_mgr_create(ctx,
> +			&disp_clk_regs,
> +			&disp_clk_shift,
> +			&disp_clk_mask);
> +	if (pool->base.clk_mgr == NULL) {
> +		dm_error("DC: failed to create display clock!\n");
> +		BREAK_TO_DEBUGGER();
> +		goto res_create_fail;
> +	}
> +
> +	pool->base.dmcu = dce_dmcu_create(ctx,
> +			&dmcu_regs,
> +			&dmcu_shift,
> +			&dmcu_mask);
> +	if (pool->base.dmcu == NULL) {
> +		dm_error("DC: failed to create dmcu!\n");
> +		BREAK_TO_DEBUGGER();
> +		goto res_create_fail;
> +	}
> +
> +	pool->base.abm = dce_abm_create(ctx,
> +			&abm_regs,
> +			&abm_shift,
> +			&abm_mask);
> +	if (pool->base.abm == NULL) {
> +		dm_error("DC: failed to create abm!\n");
> +		BREAK_TO_DEBUGGER();
> +		goto res_create_fail;
> +	}
> +
> +	{
> +		struct irq_service_init_data init_data;
> +		init_data.ctx = dc->ctx;
> +		pool->base.irqs = dal_irq_service_dce60_create(&init_data);
> +		if (!pool->base.irqs)
> +			goto res_create_fail;
> +	}
> +
> +	for (i = 0; i < pool->base.pipe_count; i++) {
> +		pool->base.timing_generators[i] = dce60_timing_generator_create(
> +				ctx, i, &dce60_tg_offsets[i]);
> +		if (pool->base.timing_generators[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error("DC: failed to create tg!\n");
> +			goto res_create_fail;
> +		}
> +
> +		pool->base.mis[i] = dce60_mem_input_create(ctx, i);
> +		if (pool->base.mis[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error("DC: failed to create memory input!\n");
> +			goto res_create_fail;
> +		}
> +
> +		pool->base.ipps[i] = dce60_ipp_create(ctx, i);
> +		if (pool->base.ipps[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error("DC: failed to create input pixel processor!\n");
> +			goto res_create_fail;
> +		}
> +
> +		pool->base.transforms[i] = dce60_transform_create(ctx, i);
> +		if (pool->base.transforms[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error("DC: failed to create transform!\n");
> +			goto res_create_fail;
> +		}
> +
> +		pool->base.opps[i] = dce60_opp_create(ctx, i);
> +		if (pool->base.opps[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error("DC: failed to create output pixel processor!\n");
> +			goto res_create_fail;
> +		}
> +	}
> +
> +	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
> +		pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
> +		if (pool->base.engines[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error(
> +				"DC:failed to create aux engine!!\n");
> +			goto res_create_fail;
> +		}
> +		pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
> +		if (pool->base.hw_i2cs[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error(
> +				"DC:failed to create i2c engine!!\n");
> +			goto res_create_fail;
> +		}
> +		pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
> +		if (pool->base.sw_i2cs[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error(
> +				"DC:failed to create sw i2c!!\n");
> +			goto res_create_fail;
> +		}
> +	}
> +
> +	dc->caps.max_planes =  pool->base.pipe_count;
> +	dc->caps.disable_dp_clk_share = true;
> +
> +	if (!resource_construct(num_virtual_links, dc, &pool->base,
> +			&res_create_funcs))
> +		goto res_create_fail;
> +
> +	/* Create hardware sequencer */
> +	dce60_hw_sequencer_construct(dc);
> +
> +	return true;
> +
> +res_create_fail:
> +	destruct(pool);
> +	return false;
> +}
> +
> +struct resource_pool *dce60_create_resource_pool(
> +	uint8_t num_virtual_links,
> +	struct dc *dc)
> +{
> +	struct dce110_resource_pool *pool =
> +		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
> +
> +	if (!pool)
> +		return NULL;
> +
> +	if (dce60_construct(num_virtual_links, dc, pool))
> +		return &pool->base;
> +
> +	BREAK_TO_DEBUGGER();
> +	return NULL;
> +}
> +
> +static bool dce61_construct(
> +	uint8_t num_virtual_links,
> +	struct dc *dc,
> +	struct dce110_resource_pool *pool)
> +{
> +	unsigned int i;
> +	struct dc_context *ctx = dc->ctx;
> +	struct dc_firmware_info info;
> +	struct dc_bios *bp;
> +
> +	ctx->dc_bios->regs = &bios_regs;
> +
> +	pool->base.res_cap = &res_cap_61;
> +	pool->base.funcs = &dce60_res_pool_funcs;
> +
> +
> +	/*************************************************
> +	 *  Resource + asic cap harcoding                *
> +	 *************************************************/
> +	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
> +	pool->base.pipe_count = res_cap_61.num_timing_generator;
> +	pool->base.timing_generator_count = res_cap_61.num_timing_generator;
> +	dc->caps.max_downscale_ratio = 200;
> +	dc->caps.i2c_speed_in_khz = 40;
> +	dc->caps.max_cursor_size = 128;
> +	dc->caps.is_apu = true;
> +
> +	/*************************************************
> +	 *  Create resources                             *
> +	 *************************************************/
> +
> +	bp = ctx->dc_bios;
> +
> +	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
> +		info.external_clock_source_frequency_for_dp != 0) {
> +		pool->base.dp_clock_source =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
> +
> +		pool->base.clock_sources[0] =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
> +		pool->base.clock_sources[1] =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
> +		pool->base.clock_sources[2] =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
> +		pool->base.clk_src_count = 3;
> +
> +	} else {
> +		pool->base.dp_clock_source =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
> +
> +		pool->base.clock_sources[0] =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
> +		pool->base.clock_sources[1] =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
> +		pool->base.clk_src_count = 2;
> +	}
> +
> +	if (pool->base.dp_clock_source == NULL) {
> +		dm_error("DC: failed to create dp clock source!\n");
> +		BREAK_TO_DEBUGGER();
> +		goto res_create_fail;
> +	}
> +
> +	for (i = 0; i < pool->base.clk_src_count; i++) {
> +		if (pool->base.clock_sources[i] == NULL) {
> +			dm_error("DC: failed to create clock sources!\n");
> +			BREAK_TO_DEBUGGER();
> +			goto res_create_fail;
> +		}
> +	}
> +
> +	pool->base.clk_mgr = dce_clk_mgr_create(ctx,
> +			&disp_clk_regs,
> +			&disp_clk_shift,
> +			&disp_clk_mask);
> +	if (pool->base.clk_mgr == NULL) {
> +		dm_error("DC: failed to create display clock!\n");
> +		BREAK_TO_DEBUGGER();
> +		goto res_create_fail;
> +	}
> +
> +	pool->base.dmcu = dce_dmcu_create(ctx,
> +			&dmcu_regs,
> +			&dmcu_shift,
> +			&dmcu_mask);
> +	if (pool->base.dmcu == NULL) {
> +		dm_error("DC: failed to create dmcu!\n");
> +		BREAK_TO_DEBUGGER();
> +		goto res_create_fail;
> +	}
> +
> +	pool->base.abm = dce_abm_create(ctx,
> +			&abm_regs,
> +			&abm_shift,
> +			&abm_mask);
> +	if (pool->base.abm == NULL) {
> +		dm_error("DC: failed to create abm!\n");
> +		BREAK_TO_DEBUGGER();
> +		goto res_create_fail;
> +	}
> +
> +	{
> +		struct irq_service_init_data init_data;
> +		init_data.ctx = dc->ctx;
> +		pool->base.irqs = dal_irq_service_dce60_create(&init_data);
> +		if (!pool->base.irqs)
> +			goto res_create_fail;
> +	}
> +
> +	for (i = 0; i < pool->base.pipe_count; i++) {
> +		pool->base.timing_generators[i] = dce60_timing_generator_create(
> +				ctx, i, &dce60_tg_offsets[i]);
> +		if (pool->base.timing_generators[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error("DC: failed to create tg!\n");
> +			goto res_create_fail;
> +		}
> +
> +		pool->base.mis[i] = dce60_mem_input_create(ctx, i);
> +		if (pool->base.mis[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error("DC: failed to create memory input!\n");
> +			goto res_create_fail;
> +		}
> +
> +		pool->base.ipps[i] = dce60_ipp_create(ctx, i);
> +		if (pool->base.ipps[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error("DC: failed to create input pixel processor!\n");
> +			goto res_create_fail;
> +		}
> +
> +		pool->base.transforms[i] = dce60_transform_create(ctx, i);
> +		if (pool->base.transforms[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error("DC: failed to create transform!\n");
> +			goto res_create_fail;
> +		}
> +
> +		pool->base.opps[i] = dce60_opp_create(ctx, i);
> +		if (pool->base.opps[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error("DC: failed to create output pixel processor!\n");
> +			goto res_create_fail;
> +		}
> +	}
> +
> +	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
> +		pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
> +		if (pool->base.engines[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error(
> +				"DC:failed to create aux engine!!\n");
> +			goto res_create_fail;
> +		}
> +		pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
> +		if (pool->base.hw_i2cs[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error(
> +				"DC:failed to create i2c engine!!\n");
> +			goto res_create_fail;
> +		}
> +		pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
> +		if (pool->base.sw_i2cs[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error(
> +				"DC:failed to create sw i2c!!\n");
> +			goto res_create_fail;
> +		}
> +	}
> +
> +	dc->caps.max_planes =  pool->base.pipe_count;
> +	dc->caps.disable_dp_clk_share = true;
> +
> +	if (!resource_construct(num_virtual_links, dc, &pool->base,
> +			&res_create_funcs))
> +		goto res_create_fail;
> +
> +	/* Create hardware sequencer */
> +	dce60_hw_sequencer_construct(dc);
> +
> +	return true;
> +
> +res_create_fail:
> +	destruct(pool);
> +	return false;
> +}
> +
> +struct resource_pool *dce61_create_resource_pool(
> +	uint8_t num_virtual_links,
> +	struct dc *dc)
> +{
> +	struct dce110_resource_pool *pool =
> +		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
> +
> +	if (!pool)
> +		return NULL;
> +
> +	if (dce61_construct(num_virtual_links, dc, pool))
> +		return &pool->base;
> +
> +	BREAK_TO_DEBUGGER();
> +	return NULL;
> +}
> +
> +static bool dce64_construct(
> +	uint8_t num_virtual_links,
> +	struct dc *dc,
> +	struct dce110_resource_pool *pool)
> +{
> +	unsigned int i;
> +	struct dc_context *ctx = dc->ctx;
> +	struct dc_firmware_info info;
> +	struct dc_bios *bp;
> +
> +	ctx->dc_bios->regs = &bios_regs;
> +
> +	pool->base.res_cap = &res_cap_64;
> +	pool->base.funcs = &dce60_res_pool_funcs;
> +
> +
> +	/*************************************************
> +	 *  Resource + asic cap harcoding                *
> +	 *************************************************/
> +	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
> +	pool->base.pipe_count = res_cap_64.num_timing_generator;
> +	pool->base.timing_generator_count = res_cap_64.num_timing_generator;
> +	dc->caps.max_downscale_ratio = 200;
> +	dc->caps.i2c_speed_in_khz = 40;
> +	dc->caps.max_cursor_size = 128;
> +	dc->caps.is_apu = true;
> +
> +	/*************************************************
> +	 *  Create resources                             *
> +	 *************************************************/
> +
> +	bp = ctx->dc_bios;
> +
> +	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
> +		info.external_clock_source_frequency_for_dp != 0) {
> +		pool->base.dp_clock_source =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
> +
> +		pool->base.clock_sources[0] =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
> +		pool->base.clock_sources[1] =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
> +		pool->base.clk_src_count = 2;
> +
> +	} else {
> +		pool->base.dp_clock_source =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
> +
> +		pool->base.clock_sources[0] =
> +				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
> +		pool->base.clk_src_count = 1;
> +	}
> +
> +	if (pool->base.dp_clock_source == NULL) {
> +		dm_error("DC: failed to create dp clock source!\n");
> +		BREAK_TO_DEBUGGER();
> +		goto res_create_fail;
> +	}
> +
> +	for (i = 0; i < pool->base.clk_src_count; i++) {
> +		if (pool->base.clock_sources[i] == NULL) {
> +			dm_error("DC: failed to create clock sources!\n");
> +			BREAK_TO_DEBUGGER();
> +			goto res_create_fail;
> +		}
> +	}
> +
> +	pool->base.clk_mgr = dce_clk_mgr_create(ctx,
> +			&disp_clk_regs,
> +			&disp_clk_shift,
> +			&disp_clk_mask);
> +	if (pool->base.clk_mgr == NULL) {
> +		dm_error("DC: failed to create display clock!\n");
> +		BREAK_TO_DEBUGGER();
> +		goto res_create_fail;
> +	}
> +
> +	pool->base.dmcu = dce_dmcu_create(ctx,
> +			&dmcu_regs,
> +			&dmcu_shift,
> +			&dmcu_mask);
> +	if (pool->base.dmcu == NULL) {
> +		dm_error("DC: failed to create dmcu!\n");
> +		BREAK_TO_DEBUGGER();
> +		goto res_create_fail;
> +	}
> +
> +	pool->base.abm = dce_abm_create(ctx,
> +			&abm_regs,
> +			&abm_shift,
> +			&abm_mask);
> +	if (pool->base.abm == NULL) {
> +		dm_error("DC: failed to create abm!\n");
> +		BREAK_TO_DEBUGGER();
> +		goto res_create_fail;
> +	}
> +
> +	{
> +		struct irq_service_init_data init_data;
> +		init_data.ctx = dc->ctx;
> +		pool->base.irqs = dal_irq_service_dce60_create(&init_data);
> +		if (!pool->base.irqs)
> +			goto res_create_fail;
> +	}
> +
> +	for (i = 0; i < pool->base.pipe_count; i++) {
> +		pool->base.timing_generators[i] = dce60_timing_generator_create(
> +				ctx, i, &dce60_tg_offsets[i]);
> +		if (pool->base.timing_generators[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error("DC: failed to create tg!\n");
> +			goto res_create_fail;
> +		}
> +
> +		pool->base.mis[i] = dce60_mem_input_create(ctx, i);
> +		if (pool->base.mis[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error("DC: failed to create memory input!\n");
> +			goto res_create_fail;
> +		}
> +
> +		pool->base.ipps[i] = dce60_ipp_create(ctx, i);
> +		if (pool->base.ipps[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error("DC: failed to create input pixel processor!\n");
> +			goto res_create_fail;
> +		}
> +
> +		pool->base.transforms[i] = dce60_transform_create(ctx, i);
> +		if (pool->base.transforms[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error("DC: failed to create transform!\n");
> +			goto res_create_fail;
> +		}
> +
> +		pool->base.opps[i] = dce60_opp_create(ctx, i);
> +		if (pool->base.opps[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error("DC: failed to create output pixel processor!\n");
> +			goto res_create_fail;
> +		}
> +	}
> +
> +	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
> +		pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
> +		if (pool->base.engines[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error(
> +				"DC:failed to create aux engine!!\n");
> +			goto res_create_fail;
> +		}
> +		pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
> +		if (pool->base.hw_i2cs[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error(
> +				"DC:failed to create i2c engine!!\n");
> +			goto res_create_fail;
> +		}
> +		pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
> +		if (pool->base.sw_i2cs[i] == NULL) {
> +			BREAK_TO_DEBUGGER();
> +			dm_error(
> +				"DC:failed to create sw i2c!!\n");
> +			goto res_create_fail;
> +		}
> +	}
> +
> +	dc->caps.max_planes =  pool->base.pipe_count;
> +	dc->caps.disable_dp_clk_share = true;
> +
> +	if (!resource_construct(num_virtual_links, dc, &pool->base,
> +			&res_create_funcs))
> +		goto res_create_fail;
> +
> +	/* Create hardware sequencer */
> +	dce60_hw_sequencer_construct(dc);
> +
> +	return true;
> +
> +res_create_fail:
> +	destruct(pool);
> +	return false;
> +}
> +
> +struct resource_pool *dce64_create_resource_pool(
> +	uint8_t num_virtual_links,
> +	struct dc *dc)
> +{
> +	struct dce110_resource_pool *pool =
> +		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
> +
> +	if (!pool)
> +		return NULL;
> +
> +	if (dce64_construct(num_virtual_links, dc, pool))
> +		return &pool->base;
> +
> +	BREAK_TO_DEBUGGER();
> +	return NULL;
> +}
> diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
> new file mode 100644
> index 000000000000..b30e4e4ed7c0
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
> @@ -0,0 +1,47 @@
> +/*
> +* Copyright 2012-15 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: AMD
> + *
> + */
> +
> +#ifndef __DC_RESOURCE_DCE60_H__
> +#define __DC_RESOURCE_DCE60_H__
> +
> +#include "core_types.h"
> +
> +struct dc;
> +struct resource_pool;
> +
> +struct resource_pool *dce60_create_resource_pool(
> +	uint8_t num_virtual_links,
> +	struct dc *dc);
> +
> +struct resource_pool *dce61_create_resource_pool(
> +	uint8_t num_virtual_links,
> +	struct dc *dc);
> +
> +struct resource_pool *dce64_create_resource_pool(
> +	uint8_t num_virtual_links,
> +	struct dc *dc);
> +
> +#endif /* __DC_RESOURCE_DCE60_H__ */
> +
> diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
> new file mode 100644
> index 000000000000..90b610367af8
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
> @@ -0,0 +1,242 @@
> +/*
> + * Copyright 2012-15 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: AMD
> + *
> + */
> +
> +#include "dm_services.h"
> +
> +/* include DCE6 register header files */
> +#include "dce/dce_6_0_d.h"
> +#include "dce/dce_6_0_sh_mask.h"
> +
> +#include "dc_types.h"
> +
> +#include "include/grph_object_id.h"
> +#include "include/logger_interface.h"
> +#include "../dce110/dce110_timing_generator.h"
> +#include "dce60_timing_generator.h"
> +
> +#include "timing_generator.h"
> +
> +enum black_color_format {
> +	BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,	/* used as index in array */
> +	BLACK_COLOR_FORMAT_RGB_LIMITED,
> +	BLACK_COLOR_FORMAT_YUV_TV,
> +	BLACK_COLOR_FORMAT_YUV_CV,
> +	BLACK_COLOR_FORMAT_YUV_SUPER_AA,
> +
> +	BLACK_COLOR_FORMAT_COUNT
> +};
> +
> +static const struct dce110_timing_generator_offsets reg_offsets[] = {
> +{
> +	.crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> +	.dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> +},
> +{
> +	.crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> +	.dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> +},
> +{
> +	.crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> +	.dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> +},
> +{
> +	.crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> +	.dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> +},
> +{
> +	.crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> +	.dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> +},
> +{
> +	.crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> +	.dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> +}
> +};
> +
> +#define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
> +
> +#define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
> +#define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
> +
> +#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
> +#define DCP_REG(reg) (reg + tg110->offsets.dcp)
> +#define DMIF_REG(reg) (reg + tg110->offsets.dmif)
> +
> +static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
> +{
> +	uint64_t pix_dur;
> +	uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
> +					+ DCE110TG_FROM_TG(tg)->offsets.dmif;
> +	uint32_t value = dm_read_reg(tg->ctx, addr);
> +
> +	if (pix_clk_khz == 0)
> +		return;
> +
> +	pix_dur = 1000000000 / pix_clk_khz;
> +
> +	set_reg_field_value(
> +		value,
> +		pix_dur,
> +		DPG_PIPE_ARBITRATION_CONTROL1,
> +		PIXEL_DURATION);
> +
> +	dm_write_reg(tg->ctx, addr, value);
> +}
> +
> +static void program_timing(struct timing_generator *tg,
> +	const struct dc_crtc_timing *timing,
> +	bool use_vbios)
> +{
> +	if (!use_vbios)
> +		program_pix_dur(tg, timing->pix_clk_khz);
> +
> +	dce110_tg_program_timing(tg, timing, use_vbios);
> +}
> +
> +static void dce60_timing_generator_enable_advanced_request(
> +	struct timing_generator *tg,
> +	bool enable,
> +	const struct dc_crtc_timing *timing)
> +{
> +	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
> +	uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
> +	uint32_t value = dm_read_reg(tg->ctx, addr);
> +
> +	if (enable) {
> +		set_reg_field_value(
> +			value,
> +			0,
> +			CRTC_START_LINE_CONTROL,
> +			CRTC_LEGACY_REQUESTOR_EN);
> +	} else {
> +		set_reg_field_value(
> +			value,
> +			1,
> +			CRTC_START_LINE_CONTROL,
> +			CRTC_LEGACY_REQUESTOR_EN);
> +	}
> +
> +	if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
> +		set_reg_field_value(
> +			value,
> +			3,
> +			CRTC_START_LINE_CONTROL,
> +			CRTC_ADVANCED_START_LINE_POSITION);
> +		set_reg_field_value(
> +			value,
> +			0,
> +			CRTC_START_LINE_CONTROL,
> +			CRTC_PREFETCH_EN);
> +	} else {
> +		set_reg_field_value(
> +			value,
> +			4,
> +			CRTC_START_LINE_CONTROL,
> +			CRTC_ADVANCED_START_LINE_POSITION);
> +		set_reg_field_value(
> +			value,
> +			1,
> +			CRTC_START_LINE_CONTROL,
> +			CRTC_PREFETCH_EN);
> +	}
> +
> +	set_reg_field_value(
> +		value,
> +		1,
> +		CRTC_START_LINE_CONTROL,
> +		CRTC_PROGRESSIVE_START_LINE_EARLY);
> +
> +	set_reg_field_value(
> +		value,
> +		1,
> +		CRTC_START_LINE_CONTROL,
> +		CRTC_INTERLACE_START_LINE_EARLY);
> +
> +	dm_write_reg(tg->ctx, addr, value);
> +}
> +
> +static const struct timing_generator_funcs dce60_tg_funcs = {
> +		.validate_timing = dce110_tg_validate_timing,
> +		.program_timing = program_timing,
> +		.enable_crtc = dce110_timing_generator_enable_crtc,
> +		.disable_crtc = dce110_timing_generator_disable_crtc,
> +		.is_counter_moving = dce110_timing_generator_is_counter_moving,
> +		.get_position = dce110_timing_generator_get_position,
> +		.get_frame_count = dce110_timing_generator_get_vblank_counter,
> +		.get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
> +		.set_early_control = dce110_timing_generator_set_early_control,
> +		.wait_for_state = dce110_tg_wait_for_state,
> +		.set_blank = dce110_tg_set_blank,
> +		.is_blanked = dce110_tg_is_blanked,
> +		.set_colors = dce110_tg_set_colors,
> +		.set_overscan_blank_color =
> +				dce110_timing_generator_set_overscan_color_black,
> +		.set_blank_color = dce110_timing_generator_program_blank_color,
> +		.disable_vga = dce110_timing_generator_disable_vga,
> +		.did_triggered_reset_occur =
> +				dce110_timing_generator_did_triggered_reset_occur,
> +		.setup_global_swap_lock =
> +				dce110_timing_generator_setup_global_swap_lock,
> +		.enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
> +		.disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
> +		.tear_down_global_swap_lock =
> +				dce110_timing_generator_tear_down_global_swap_lock,
> +		.set_drr = dce110_timing_generator_set_drr,
> +		.set_static_screen_control =
> +			dce110_timing_generator_set_static_screen_control,
> +		.set_test_pattern = dce110_timing_generator_set_test_pattern,
> +		.arm_vert_intr = dce110_arm_vert_intr,
> +
> +		/* DCE6.0 overrides */
> +		.enable_advanced_request =
> +				dce60_timing_generator_enable_advanced_request,

Drop the dce60 function and use the dce80 version. You can expose that through the dce80_timing_generator.h and include that here.

> +		.configure_crc = dce110_configure_crc,
> +		.get_crc = dce110_get_crc,
> +};
> +
> +void dce60_timing_generator_construct(
> +	struct dce110_timing_generator *tg110,
> +	struct dc_context *ctx,
> +	uint32_t instance,
> +	const struct dce110_timing_generator_offsets *offsets)
> +{
> +	tg110->controller_id = CONTROLLER_ID_D0 + instance;
> +	tg110->base.inst = instance;
> +	tg110->offsets = *offsets;
> +	tg110->derived_offsets = reg_offsets[instance];
> +
> +	tg110->base.funcs = &dce60_tg_funcs;
> +
> +	tg110->base.ctx = ctx;
> +	tg110->base.bp = ctx->dc_bios;
> +
> +	tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
> +	tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
> +
> +	tg110->min_h_blank = 56;
> +	tg110->min_h_front_porch = 4;
> +	tg110->min_h_back_porch = 4;
> +}
> +
> diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
> new file mode 100644
> index 000000000000..8972cd0d5815
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
> @@ -0,0 +1,39 @@
> +/*
> + * Copyright 2012-15 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + *  and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: AMD
> + *
> + */
> +
> +#ifndef __DC_TIMING_GENERATOR_DCE60_H__
> +#define __DC_TIMING_GENERATOR_DCE60_H__
> +
> +#include "timing_generator.h"
> +#include "../include/grph_object_id.h"
> +
> +/* DCE6.0 implementation inherits from DCE11.0 */
> +void dce60_timing_generator_construct(
> +	struct dce110_timing_generator *tg,
> +	struct dc_context *ctx,
> +	uint32_t instance,
> +	const struct dce110_timing_generator_offsets *offsets);
> +
> +#endif /* __DC_TIMING_GENERATOR_DCE60_H__ */
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
> index abe05bc80752..5492c6b98525 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
> @@ -2264,6 +2264,10 @@
>  #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x00000010
>  #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000100L
>  #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x00000008
> +#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100000
> +#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x14
> +#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000
> +#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x1c
>  #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
>  #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x00000000
>  #define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
> 

Would prefer the update to the register headers to be in a separate patch.

Harry
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Re: [PATCH v2 02/10] drm/amd/display: dc/dce: add DCE6 support (v2)

[Mauro Rossi]

 Hi,
sorry for pause/delay,
I've been caught in an android-x86 oreo-x86 tag update with Ubuntu 18.10 update
Now I have build system again ready

On Wed, Oct 17, 2018 at 9:47 PM Wentland, Harry <Harry.Wentland@amd.com> wrote:
>
> On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> > DCE6 targets are added replicating existing DCE8 implementation.
> >
> > NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
> > only to build dce60_resource.c due to missing *_DCE60 macros/registers/masks
> >
> > IMPORTANT: Coding of dce60_resource.c requires review to understand
> > if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
> >
> > (v2) updated dce60_{hw_sequencer,resources}.c as per amd-staging-drm-next
> >      removed dce_version cases in dc/dce/dce_clock_source.c
> > ---
> >  drivers/gpu/drm/amd/display/dc/Makefile       |    4 +
> >  drivers/gpu/drm/amd/display/dc/dce60/Makefile |   34 +
> >  .../amd/display/dc/dce60/dce60_hw_sequencer.c |   82 +
> >  .../amd/display/dc/dce60/dce60_hw_sequencer.h |   36 +
> >  .../drm/amd/display/dc/dce60/dce60_resource.c | 1458 +++++++++++++++++
> >  .../drm/amd/display/dc/dce60/dce60_resource.h |   47 +
> >  .../display/dc/dce60/dce60_timing_generator.c |  242 +++
> >  .../display/dc/dce60/dce60_timing_generator.h |   39 +
> >  .../include/asic_reg/dce/dce_6_0_sh_mask.h    |    4 +
> >  9 files changed, 1946 insertions(+)
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/Makefile
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
> > index aed538a4d1ba..d5d5acd57559 100644
> > --- a/drivers/gpu/drm/amd/display/dc/Makefile
> > +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> > @@ -36,6 +36,10 @@ DC_LIBS += dce110
> >  DC_LIBS += dce100
> >  DC_LIBS += dce80
> >
> > +ifdef CONFIG_DRM_AMD_DC_SI
> > +DC_LIBS += dce60
> > +endif
> > +
> >  AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LIBS)))
> >
> >  include $(AMD_DC)
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/Makefile b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
> > new file mode 100644
> > index 000000000000..39afd7c59a7c
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
> > @@ -0,0 +1,34 @@
> > +#
> > +# Copyright 2017 Advanced Micro Devices, Inc.
> > +#
> > +# Permission is hereby granted, free of charge, to any person obtaining a
> > +# copy of this software and associated documentation files (the "Software"),
> > +# to deal in the Software without restriction, including without limitation
> > +# the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > +# and/or sell copies of the Software, and to permit persons to whom the
> > +# Software is furnished to do so, subject to the following conditions:
> > +#
> > +# The above copyright notice and this permission notice shall be included in
> > +# all copies or substantial portions of the Software.
> > +#
> > +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > +# OTHER DEALINGS IN THE SOFTWARE.
> > +#
> > +#
> > +# Makefile for the 'controller' sub-component of DAL.
> > +# It provides the control and status of HW CRTC block.
> > +
> > +DCE60 = dce60_timing_generator.o dce60_hw_sequencer.o \
> > +     dce60_resource.o
> > +
> > +AMD_DAL_DCE60 = $(addprefix $(AMDDALPATH)/dc/dce60/,$(DCE60))
> > +
> > +AMD_DISPLAY_FILES += $(AMD_DAL_DCE60)
> > +
> > +
> > +
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
> > new file mode 100644
> > index 000000000000..502172bf6097
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
> > @@ -0,0 +1,82 @@
> > +/*
> > + * Copyright 2015 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> > + *
> > + */
> > +
> > +#include "dm_services.h"
> > +#include "dc.h"
> > +#include "core_types.h"
> > +#include "dce60_hw_sequencer.h"
> > +
> > +#include "dce/dce_hwseq.h"
> > +#include "dce110/dce110_hw_sequencer.h"
> > +#include "dce100/dce100_hw_sequencer.h"
> > +
> > +/* include DCE8 register header files */
>
> drop comment or change DCE8 to DCE6
>
> > +#include "dce/dce_6_0_d.h"
> > +#include "dce/dce_6_0_sh_mask.h"
> > +
> > +struct dce60_hw_seq_reg_offsets {
> > +     uint32_t crtc;
> > +};
> > +
> > +static const struct dce60_hw_seq_reg_offsets reg_offsets[] = {
> > +{
> > +     .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> > +}
> > +};
> > +
> > +#define HW_REG_CRTC(reg, id)\
> > +     (reg + reg_offsets[id].crtc)
> > +
> > +/*******************************************************************************
> > + * Private definitions
> > + ******************************************************************************/
> > +
> > +/***************************PIPE_CONTROL***********************************/
> > +
> > +void dce60_hw_sequencer_construct(struct dc *dc)
> > +{
> > +     dce110_hw_sequencer_construct(dc);
> > +
> > +     dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
> > +     dc->hwss.pipe_control_lock = dce_pipe_control_lock;
> > +     dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
> > +     dc->hwss.optimize_bandwidth = dce100_prepare_bandwidth;
> > +}
> > +
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
> > new file mode 100644
> > index 000000000000..e7ce63b1f75a
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
> > @@ -0,0 +1,36 @@
> > +/*
> > +* Copyright 2012-15 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> > + *
> > + */
> > +
> > +#ifndef __DC_HWSS_DCE60_H__
> > +#define __DC_HWSS_DCE60_H__
> > +
> > +#include "core_types.h"
> > +
> > +struct dc;
> > +
> > +void dce60_hw_sequencer_construct(struct dc *dc);
> > +
> > +#endif /* __DC_HWSS_DCE60_H__ */
> > +
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
> > new file mode 100644
> > index 000000000000..2731f31ce999
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
> > @@ -0,0 +1,1458 @@
> > +/*
> > + * Copyright 2012-15 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> > + *
> > + */
> > +
> > +#include "dce/dce_8_0_d.h"
> > +#include "dce/dce_8_0_sh_mask.h"
>
> This file should really use the dce6 headers. What happens if we build with the dce6 headers? If it's missing definitions I can probably send an update to the headers with what's missing.

Using dce6 headers and updating the necessary REG macros I've been
able to settle the watermark register changes (DCE6
DPG_PIPE_ARBITRATION_CONTROL3 vs DCE8 DPG_WATERMARK_MASK_CONTROL)
reducing the number of building errors from 761 to 631

In order to be pragmatic and considering that both parties do not want
this to take ages and that in the end  the register and mask
information will be public,
may I suggest to provide some information about the register and masks
renames from DCE6 to DCE8, for what it is available?

It would not be smart from my side not to propose this, since in the
end the registers would be anyway documented in the code, in plane
sight.
Also reverse engineering based on guesses is very bad way to proceed
if compared to looking into the specs and it will even increase the
efforts in review.

This long list of errors is reported just to show the current status
of my dce6 headers WIP,
as mean to get precious info on gropuing of registers and how to
quickly solve them.

I'm anyway proceeding but either specs or suggestions may certainly
speedup and improve quality of my next series.

  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.o
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:146:3:
error: 'mmDPREFCLK_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:150:1:
error: 'DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT' undeclared here (not
in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:154:1:
error: 'DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK' undeclared here (not in
a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:172:1:
error: 'DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:176:1:
error: 'DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:185:1:
error: 'mmLB0_LB_DATA_FORMAT' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:185:1:
error: 'mmDCP0_OUT_CLAMP_CONTROL_R_CR' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:185:1:
error: 'mmDCP0_OUT_CLAMP_CONTROL_G_Y' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:185:1:
error: 'mmDCP0_OUT_CLAMP_CONTROL_B_CB' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:185:1:
error: 'mmSCL0_SCL_MODE' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:185:1:
error: 'mmSCL0_SCL_HORZ_FILTER_INIT' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:185:1:
error: 'mmLB0_LB_MEMORY_CTRL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:186:1:
error: 'mmLB1_LB_DATA_FORMAT' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:186:1:
error: 'mmDCP1_OUT_CLAMP_CONTROL_R_CR' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:186:1:
error: 'mmDCP1_OUT_CLAMP_CONTROL_G_Y' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:186:1:
error: 'mmDCP1_OUT_CLAMP_CONTROL_B_CB' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:186:1:
error: 'mmSCL1_SCL_MODE' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:186:1:
error: 'mmSCL1_SCL_HORZ_FILTER_INIT' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:186:1:
error: 'mmLB1_LB_MEMORY_CTRL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:187:1:
error: 'mmLB2_LB_DATA_FORMAT' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:187:1:
error: 'mmDCP2_OUT_CLAMP_CONTROL_R_CR' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:187:1:
error: 'mmDCP2_OUT_CLAMP_CONTROL_G_Y' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:187:1:
error: 'mmDCP2_OUT_CLAMP_CONTROL_B_CB' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:187:1:
error: 'mmSCL2_SCL_MODE' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:187:1:
error: 'mmSCL2_SCL_HORZ_FILTER_INIT' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:187:1:
error: 'mmLB2_LB_MEMORY_CTRL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:188:1:
error: 'mmLB3_LB_DATA_FORMAT' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:188:1:
error: 'mmDCP3_OUT_CLAMP_CONTROL_R_CR' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:188:1:
error: 'mmDCP3_OUT_CLAMP_CONTROL_G_Y' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:188:1:
error: 'mmDCP3_OUT_CLAMP_CONTROL_B_CB' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:188:1:
error: 'mmSCL3_SCL_MODE' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:188:1:
error: 'mmSCL3_SCL_HORZ_FILTER_INIT' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:188:1:
error: 'mmLB3_LB_MEMORY_CTRL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:189:1:
error: 'mmLB4_LB_DATA_FORMAT' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:189:1:
error: 'mmDCP4_OUT_CLAMP_CONTROL_R_CR' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:189:1:
error: 'mmDCP4_OUT_CLAMP_CONTROL_G_Y' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:189:1:
error: 'mmDCP4_OUT_CLAMP_CONTROL_B_CB' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:189:1:
error: 'mmSCL4_SCL_MODE' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:189:1:
error: 'mmSCL4_SCL_HORZ_FILTER_INIT' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:189:1:
error: 'mmLB4_LB_MEMORY_CTRL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:190:1:
error: 'mmLB5_LB_DATA_FORMAT' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:190:1:
error: 'mmDCP5_OUT_CLAMP_CONTROL_R_CR' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:190:1:
error: 'mmDCP5_OUT_CLAMP_CONTROL_G_Y' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:190:1:
error: 'mmDCP5_OUT_CLAMP_CONTROL_B_CB' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:190:1:
error: 'mmSCL5_SCL_MODE' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:190:1:
error: 'mmSCL5_SCL_HORZ_FILTER_INIT' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:190:1:
error: 'mmLB5_LB_MEMORY_CTRL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.OUT_CLAMP_MIN_B_CB')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.OUT_CLAMP_MAX_B_CB')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.OUT_CLAMP_MIN_G_Y')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.OUT_CLAMP_MAX_G_Y')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.OUT_CLAMP_MIN_R_CR')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.OUT_CLAMP_MAX_R_CR')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.PIXEL_DEPTH')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT' undeclared here (not
in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.PIXEL_EXPAN_MODE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'SCL_MODE__SCL_MODE__SHIFT' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.SCL_MODE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.SCL_H_NUM_OF_TAPS')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.SCL_V_NUM_OF_TAPS')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT' undeclared here (not in
a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.SCL_BOUNDARY_MODE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.SCL_H_INIT_INT')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.SCL_H_INIT_FRAC')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT' undeclared here (not
in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.LB_MEMORY_CONFIG')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT' undeclared here (not in
a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.LB_MEMORY_SIZE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT'
undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for
'xfm_shift.SCL_V_2TAP_HARDCODE_COEF_EN')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT'
undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for
'xfm_shift.SCL_H_2TAP_HARDCODE_COEF_EN')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.SCL_COEF_UPDATE_COMPLETE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:1:
error: 'LB_DATA_FORMAT__ALPHA_EN__SHIFT' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:194:3:
error: (near initialization for 'xfm_shift.ALPHA_EN')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.OUT_CLAMP_MIN_B_CB')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.OUT_CLAMP_MAX_B_CB')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.OUT_CLAMP_MIN_G_Y')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.OUT_CLAMP_MAX_G_Y')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.OUT_CLAMP_MIN_R_CR')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.OUT_CLAMP_MAX_R_CR')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'LB_DATA_FORMAT__PIXEL_DEPTH_MASK' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.PIXEL_DEPTH')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK' undeclared here (not in
a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.PIXEL_EXPAN_MODE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'SCL_MODE__SCL_MODE_MASK' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.SCL_MODE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK' undeclared here (not
in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.SCL_H_NUM_OF_TAPS')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK' undeclared here (not
in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.SCL_V_NUM_OF_TAPS')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'SCL_CONTROL__SCL_BOUNDARY_MODE_MASK' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.SCL_BOUNDARY_MODE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.SCL_H_INIT_INT')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.SCL_H_INIT_FRAC')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK' undeclared here (not in
a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.LB_MEMORY_CONFIG')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.LB_MEMORY_SIZE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK'
undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for
'xfm_mask.SCL_V_2TAP_HARDCODE_COEF_EN')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK'
undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for
'xfm_mask.SCL_H_2TAP_HARDCODE_COEF_EN')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.SCL_COEF_UPDATE_COMPLETE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:1:
error: 'LB_DATA_FORMAT__ALPHA_EN_MASK' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:198:3:
error: (near initialization for 'xfm_mask.ALPHA_EN')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:221:1:
error: 'mmHPD0_DC_HPD_CONTROL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:221:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:221:3:
error: (near initialization for 'link_enc_hpd_regs[0].DC_HPD_CONTROL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:222:1:
error: 'mmHPD1_DC_HPD_CONTROL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:222:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:222:3:
error: (near initialization for 'link_enc_hpd_regs[1].DC_HPD_CONTROL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:223:1:
error: 'mmHPD2_DC_HPD_CONTROL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:223:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:223:3:
error: (near initialization for 'link_enc_hpd_regs[2].DC_HPD_CONTROL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:224:1:
error: 'mmHPD3_DC_HPD_CONTROL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:224:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:224:3:
error: (near initialization for 'link_enc_hpd_regs[3].DC_HPD_CONTROL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:225:1:
error: 'mmHPD4_DC_HPD_CONTROL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:225:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:225:3:
error: (near initialization for 'link_enc_hpd_regs[4].DC_HPD_CONTROL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:226:1:
error: 'mmHPD5_DC_HPD_CONTROL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:226:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:226:3:
error: (near initialization for 'link_enc_hpd_regs[5].DC_HPD_CONTROL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:235:1:
error: 'mmDP0_DP_DPHY_SCRAM_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:235:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:235:2:
error: (near initialization for 'link_enc_regs[0].DP_DPHY_SCRAM_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:236:1:
error: 'mmDP1_DP_DPHY_SCRAM_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:236:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:236:2:
error: (near initialization for 'link_enc_regs[1].DP_DPHY_SCRAM_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:237:1:
error: 'mmDP2_DP_DPHY_SCRAM_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:237:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:237:2:
error: (near initialization for 'link_enc_regs[2].DP_DPHY_SCRAM_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:238:1:
error: 'mmDP3_DP_DPHY_SCRAM_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:238:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:238:2:
error: (near initialization for 'link_enc_regs[3].DP_DPHY_SCRAM_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:239:1:
error: 'mmDP4_DP_DPHY_SCRAM_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:239:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:239:2:
error: (near initialization for 'link_enc_regs[4].DP_DPHY_SCRAM_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:240:1:
error: 'mmDP5_DP_DPHY_SCRAM_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:240:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:240:2:
error: (near initialization for 'link_enc_regs[5].DP_DPHY_SCRAM_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_DPHY_INTERNAL_CTRL' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for
'link_enc_regs[6].DP_DPHY_INTERNAL_CTRL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDIG6_DIG_BE_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DIG_BE_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDIG6_DIG_BE_EN_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DIG_BE_EN_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_CONFIG' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DP_CONFIG')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_DPHY_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DP_DPHY_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_DPHY_PRBS_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DP_DPHY_PRBS_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_DPHY_SCRAM_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DP_DPHY_SCRAM_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_DPHY_SYM0' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DP_DPHY_SYM0')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_DPHY_SYM1' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DP_DPHY_SYM1')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_DPHY_SYM2' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DP_DPHY_SYM2')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_DPHY_TRAINING_PATTERN_SEL' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for
'link_enc_regs[6].DP_DPHY_TRAINING_PATTERN_SEL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_LINK_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DP_LINK_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_LINK_FRAMING_CNTL' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for
'link_enc_regs[6].DP_LINK_FRAMING_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_MSE_SAT0' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DP_MSE_SAT0')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_MSE_SAT1' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DP_MSE_SAT1')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_MSE_SAT2' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DP_MSE_SAT2')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_MSE_SAT_UPDATE' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DP_MSE_SAT_UPDATE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_SEC_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DP_SEC_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_VID_STREAM_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DP_VID_STREAM_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_DPHY_FAST_TRAINING' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for
'link_enc_regs[6].DP_DPHY_FAST_TRAINING')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:1:
error: 'mmDP6_DP_SEC_CNTL1' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:241:2:
error: (near initialization for 'link_enc_regs[6].DP_SEC_CNTL1')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_GENERIC_0' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_GENERIC_0')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_GENERIC_1' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_GENERIC_1')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_GENERIC_2' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_GENERIC_2')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_GENERIC_3' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_GENERIC_3')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_GENERIC_4' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_GENERIC_4')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_GENERIC_5' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_GENERIC_5')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_GENERIC_6' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_GENERIC_6')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_GENERIC_7' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_GENERIC_7')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_GENERIC_HDR' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_GENERIC_HDR')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_INFOFRAME_CONTROL0' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for
'stream_enc_regs[6].AFMT_INFOFRAME_CONTROL0')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_VBI_PACKET_CONTROL' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for
'stream_enc_regs[6].AFMT_VBI_PACKET_CONTROL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_AUDIO_PACKET_CONTROL' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for
'stream_enc_regs[6].AFMT_AUDIO_PACKET_CONTROL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_AUDIO_PACKET_CONTROL2' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for
'stream_enc_regs[6].AFMT_AUDIO_PACKET_CONTROL2')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_AUDIO_SRC_CONTROL' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for
'stream_enc_regs[6].AFMT_AUDIO_SRC_CONTROL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_60958_0' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_60958_0')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_60958_1' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_60958_1')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_60958_2' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_60958_2')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_DIG_FE_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].DIG_FE_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_HDMI_CONTROL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].HDMI_CONTROL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_HDMI_GC' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].HDMI_GC')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_HDMI_GENERIC_PACKET_CONTROL0' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for
'stream_enc_regs[6].HDMI_GENERIC_PACKET_CONTROL0')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_HDMI_GENERIC_PACKET_CONTROL1' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for
'stream_enc_regs[6].HDMI_GENERIC_PACKET_CONTROL1')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_HDMI_INFOFRAME_CONTROL0' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for
'stream_enc_regs[6].HDMI_INFOFRAME_CONTROL0')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_HDMI_INFOFRAME_CONTROL1' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for
'stream_enc_regs[6].HDMI_INFOFRAME_CONTROL1')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_HDMI_VBI_PACKET_CONTROL' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for
'stream_enc_regs[6].HDMI_VBI_PACKET_CONTROL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_HDMI_AUDIO_PACKET_CONTROL' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for
'stream_enc_regs[6].HDMI_AUDIO_PACKET_CONTROL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_HDMI_ACR_PACKET_CONTROL' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for
'stream_enc_regs[6].HDMI_ACR_PACKET_CONTROL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_HDMI_ACR_32_0' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].HDMI_ACR_32_0')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_HDMI_ACR_32_1' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].HDMI_ACR_32_1')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_HDMI_ACR_44_0' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].HDMI_ACR_44_0')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_HDMI_ACR_44_1' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].HDMI_ACR_44_1')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_HDMI_ACR_48_0' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].HDMI_ACR_48_0')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_HDMI_ACR_48_1' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].HDMI_ACR_48_1')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_TMDS_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].TMDS_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDP6_DP_MSE_RATE_CNTL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].DP_MSE_RATE_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDP6_DP_MSE_RATE_UPDATE' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for
'stream_enc_regs[6].DP_MSE_RATE_UPDATE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDP6_DP_PIXEL_FORMAT' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].DP_PIXEL_FORMAT')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].DP_SEC_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDP6_DP_STEER_FIFO' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].DP_STEER_FIFO')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDP6_DP_VID_M' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].DP_VID_M')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDP6_DP_VID_N' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].DP_VID_N')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for
'stream_enc_regs[6].DP_VID_STREAM_CNTL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDP6_DP_VID_TIMING' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].DP_VID_TIMING')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDP6_DP_SEC_AUD_N' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].DP_SEC_AUD_N')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDP6_DP_SEC_TIMESTAMP' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].DP_SEC_TIMESTAMP')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_AVI_INFO0' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_AVI_INFO0')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_AVI_INFO1' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_AVI_INFO1')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_AVI_INFO2' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_AVI_INFO2')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:1:
error: 'mmDIG6_AFMT_AVI_INFO3' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:257:2:
error: (near initialization for 'stream_enc_regs[6].AFMT_AVI_INFO3')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:274:1:
error: 'mmFMT0_FMT_CLAMP_COMPONENT_R' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:274:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:274:2:
error: (near initialization for 'opp_regs[0].FMT_CLAMP_COMPONENT_R')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:274:1:
error: 'mmFMT0_FMT_CLAMP_COMPONENT_G' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:274:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:274:2:
error: (near initialization for 'opp_regs[0].FMT_CLAMP_COMPONENT_G')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:274:1:
error: 'mmFMT0_FMT_CLAMP_COMPONENT_B' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:274:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:274:2:
error: (near initialization for 'opp_regs[0].FMT_CLAMP_COMPONENT_B')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:275:1:
error: 'mmFMT1_FMT_CLAMP_COMPONENT_R' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:275:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:275:2:
error: (near initialization for 'opp_regs[1].FMT_CLAMP_COMPONENT_R')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:275:1:
error: 'mmFMT1_FMT_CLAMP_COMPONENT_G' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:275:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:275:2:
error: (near initialization for 'opp_regs[1].FMT_CLAMP_COMPONENT_G')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:275:1:
error: 'mmFMT1_FMT_CLAMP_COMPONENT_B' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:275:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:275:2:
error: (near initialization for 'opp_regs[1].FMT_CLAMP_COMPONENT_B')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:276:1:
error: 'mmFMT2_FMT_CLAMP_COMPONENT_R' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:276:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:276:2:
error: (near initialization for 'opp_regs[2].FMT_CLAMP_COMPONENT_R')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:276:1:
error: 'mmFMT2_FMT_CLAMP_COMPONENT_G' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:276:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:276:2:
error: (near initialization for 'opp_regs[2].FMT_CLAMP_COMPONENT_G')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:276:1:
error: 'mmFMT2_FMT_CLAMP_COMPONENT_B' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:276:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:276:2:
error: (near initialization for 'opp_regs[2].FMT_CLAMP_COMPONENT_B')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:277:1:
error: 'mmFMT3_FMT_CLAMP_COMPONENT_R' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:277:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:277:2:
error: (near initialization for 'opp_regs[3].FMT_CLAMP_COMPONENT_R')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:277:1:
error: 'mmFMT3_FMT_CLAMP_COMPONENT_G' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:277:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:277:2:
error: (near initialization for 'opp_regs[3].FMT_CLAMP_COMPONENT_G')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:277:1:
error: 'mmFMT3_FMT_CLAMP_COMPONENT_B' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:277:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:277:2:
error: (near initialization for 'opp_regs[3].FMT_CLAMP_COMPONENT_B')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:278:1:
error: 'mmFMT4_FMT_CLAMP_COMPONENT_R' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:278:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:278:2:
error: (near initialization for 'opp_regs[4].FMT_CLAMP_COMPONENT_R')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:278:1:
error: 'mmFMT4_FMT_CLAMP_COMPONENT_G' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:278:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:278:2:
error: (near initialization for 'opp_regs[4].FMT_CLAMP_COMPONENT_G')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:278:1:
error: 'mmFMT4_FMT_CLAMP_COMPONENT_B' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:278:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:278:2:
error: (near initialization for 'opp_regs[4].FMT_CLAMP_COMPONENT_B')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:279:1:
error: 'mmFMT5_FMT_CLAMP_COMPONENT_R' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:279:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:279:2:
error: (near initialization for 'opp_regs[5].FMT_CLAMP_COMPONENT_R')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:279:1:
error: 'mmFMT5_FMT_CLAMP_COMPONENT_G' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:279:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:279:2:
error: (near initialization for 'opp_regs[5].FMT_CLAMP_COMPONENT_G')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:279:1:
error: 'mmFMT5_FMT_CLAMP_COMPONENT_B' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:279:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:279:2:
error: (near initialization for 'opp_regs[5].FMT_CLAMP_COMPONENT_B')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:1:
error: 'FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: (near initialization for 'opp_shift.FMT_TRUNCATE_MODE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:1:
error: 'FMT_CONTROL__FMT_SRC_SELECT__SHIFT' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: (near initialization for 'opp_shift.FMT_SRC_SELECT')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:1:
error: 'FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: (near initialization for 'opp_shift.FMT_CLAMP_LOWER_R')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:1:
error: 'FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: (near initialization for 'opp_shift.FMT_CLAMP_UPPER_R')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:1:
error: 'FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: (near initialization for 'opp_shift.FMT_CLAMP_LOWER_G')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:1:
error: 'FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: (near initialization for 'opp_shift.FMT_CLAMP_UPPER_G')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:1:
error: 'FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: (near initialization for 'opp_shift.FMT_CLAMP_LOWER_B')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:1:
error: 'FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: (near initialization for 'opp_shift.FMT_CLAMP_UPPER_B')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:1:
error: 'FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT' undeclared here (not
in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:2:
error: (near initialization for 'opp_shift.FMT_SUBSAMPLING_MODE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:283:1:
error: 'FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:284:1:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:284:1:
error: (near initialization for 'opp_shift.FMT_SUBSAMPLING_ORDER')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:1:
error: 'FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: (near initialization for 'opp_mask.FMT_TRUNCATE_MODE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:1:
error: 'FMT_CONTROL__FMT_SRC_SELECT_MASK' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: (near initialization for 'opp_mask.FMT_SRC_SELECT')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:1:
error: 'FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: (near initialization for 'opp_mask.FMT_CLAMP_LOWER_R')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:1:
error: 'FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: (near initialization for 'opp_mask.FMT_CLAMP_UPPER_R')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:1:
error: 'FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: (near initialization for 'opp_mask.FMT_CLAMP_LOWER_G')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:1:
error: 'FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: (near initialization for 'opp_mask.FMT_CLAMP_UPPER_G')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:1:
error: 'FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: (near initialization for 'opp_mask.FMT_CLAMP_LOWER_B')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:1:
error: 'FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: (near initialization for 'opp_mask.FMT_CLAMP_UPPER_B')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:1:
error: 'FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK' undeclared here (not
in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:2:
error: (near initialization for 'opp_mask.FMT_SUBSAMPLING_MODE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:287:1:
error: 'FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK' undeclared here (not
in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:288:1:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:288:1:
error: (near initialization for 'opp_mask.FMT_SUBSAMPLING_ORDER')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:320:1:
error: 'DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT'
undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:320:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:320:3:
error: (near initialization for
'audio_shift.DCCG_AUDIO_DTO2_USE_512FBR_DTO')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:324:1:
error: 'DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK'
undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:324:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:324:3:
error: (near initialization for
'audio_mask.DCCG_AUDIO_DTO2_USE_512FBR_DTO')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:376:1:
error: 'mmSMU_INTERRUPT_CONTROL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:376:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:376:3:
error: (near initialization for 'dmcu_regs.SMU_INTERRUPT_CONTROL')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:380:1:
error: 'SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:381:1:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:381:1:
error: (near initialization for 'dmcu_shift.DC_SMU_INT_ENABLE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:384:1:
error: 'SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:385:1:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:385:1:
error: (near initialization for 'dmcu_mask.DC_SMU_INT_ENABLE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:1:
error: 'mmBLND0_BLND_V_UPDATE_LOCK' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: (near initialization for 'hwseq_reg.BLND_V_UPDATE_LOCK[0]')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:1:
error: 'mmBLND1_BLND_V_UPDATE_LOCK' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: (near initialization for 'hwseq_reg.BLND_V_UPDATE_LOCK[1]')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:1:
error: 'mmBLND2_BLND_V_UPDATE_LOCK' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: (near initialization for 'hwseq_reg.BLND_V_UPDATE_LOCK[2]')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:1:
error: 'mmBLND3_BLND_V_UPDATE_LOCK' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: (near initialization for 'hwseq_reg.BLND_V_UPDATE_LOCK[3]')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:1:
error: 'mmBLND4_BLND_V_UPDATE_LOCK' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: (near initialization for 'hwseq_reg.BLND_V_UPDATE_LOCK[4]')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:1:
error: 'mmBLND5_BLND_V_UPDATE_LOCK' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: (near initialization for 'hwseq_reg.BLND_V_UPDATE_LOCK[5]')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:1:
error: 'mmBLND0_BLND_CONTROL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: (near initialization for 'hwseq_reg.BLND_CONTROL[0]')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:1:
error: 'mmBLND1_BLND_CONTROL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: (near initialization for 'hwseq_reg.BLND_CONTROL[1]')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:1:
error: 'mmBLND2_BLND_CONTROL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: (near initialization for 'hwseq_reg.BLND_CONTROL[2]')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:1:
error: 'mmBLND3_BLND_CONTROL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: (near initialization for 'hwseq_reg.BLND_CONTROL[3]')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:1:
error: 'mmBLND4_BLND_CONTROL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: (near initialization for 'hwseq_reg.BLND_CONTROL[4]')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:1:
error: 'mmBLND5_BLND_CONTROL' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:541:3:
error: (near initialization for 'hwseq_reg.BLND_CONTROL[5]')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:545:1:
error: 'BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT'
undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:545:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:545:3:
error: (near initialization for
'hwseq_shift.BLND_DCP_GRPH_V_UPDATE_LOCK')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:545:1:
error: 'BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:545:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:545:3:
error: (near initialization for 'hwseq_shift.BLND_SCL_V_UPDATE_LOCK')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:545:1:
error: 'BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT'
undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:545:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:545:3:
error: (near initialization for
'hwseq_shift.BLND_DCP_GRPH_SURF_V_UPDATE_LOCK')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:545:1:
error: 'BLND_CONTROL__BLND_MODE__SHIFT' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:545:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:545:3:
error: (near initialization for 'hwseq_shift.BLND_MODE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:549:1:
error: 'BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK'
undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:549:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:549:3:
error: (near initialization for
'hwseq_mask.BLND_DCP_GRPH_V_UPDATE_LOCK')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:549:1:
error: 'BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK' undeclared
here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:549:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:549:3:
error: (near initialization for 'hwseq_mask.BLND_SCL_V_UPDATE_LOCK')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:549:1:
error: 'BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK'
undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:549:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:549:3:
error: (near initialization for
'hwseq_mask.BLND_DCP_GRPH_SURF_V_UPDATE_LOCK')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:549:1:
error: 'BLND_CONTROL__BLND_MODE_MASK' undeclared here (not in a
function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:549:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:549:3:
error: (near initialization for 'hwseq_mask.BLND_MODE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:578:1:
error: 'mmDCP0_HW_ROTATION' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:578:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:578:3:
error: (near initialization for 'mi_regs[0].HW_ROTATION')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:579:1:
error: 'mmDCP1_HW_ROTATION' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:579:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:579:3:
error: (near initialization for 'mi_regs[1].HW_ROTATION')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:580:1:
error: 'mmDCP2_HW_ROTATION' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:580:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:580:3:
error: (near initialization for 'mi_regs[2].HW_ROTATION')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:581:1:
error: 'mmDCP3_HW_ROTATION' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:581:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:581:3:
error: (near initialization for 'mi_regs[3].HW_ROTATION')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:582:1:
error: 'mmDCP4_HW_ROTATION' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:582:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:582:3:
error: (near initialization for 'mi_regs[4].HW_ROTATION')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:583:1:
error: 'mmDCP5_HW_ROTATION' undeclared here (not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:583:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:583:3:
error: (near initialization for 'mi_regs[5].HW_ROTATION')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:587:1:
error: 'HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT' undeclared here (not
in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:587:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:587:3:
error: (near initialization for 'mi_shifts.GRPH_ROTATION_ANGLE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:587:1:
error: 'GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT' undeclared here
(not in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:587:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:587:3:
error: (near initialization for 'mi_shifts.GRPH_MICRO_TILE_MODE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:592:1:
error: 'HW_ROTATION__GRPH_ROTATION_ANGLE_MASK' undeclared here (not in
a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:592:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:592:3:
error: (near initialization for 'mi_masks.GRPH_ROTATION_ANGLE')
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:592:1:
error: 'GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK' undeclared here (not
in a function)
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:592:3:
error: initializer element is not constant
/home/utente/oreo-x86_hwc2/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:592:3:
error: (near initialization for 'mi_masks.GRPH_MICRO_TILE_MODE')
make[5]: *** [/home/utente/oreo-x86_hwc2/kernel/scripts/Makefile.build:305:
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.o] Error
1


>
> > +
> > +#include "dm_services.h"
> > +
> > +#include "link_encoder.h"
> > +#include "stream_encoder.h"
> > +
> > +#include "resource.h"
> > +#include "include/irq_service_interface.h"
> > +#include "irq/dce60/irq_service_dce60.h"
> > +#include "dce110/dce110_timing_generator.h"
> > +#include "dce110/dce110_resource.h"
> > +#include "dce60/dce60_timing_generator.h"
> > +#include "dce/dce_clk_mgr.h"
> > +#include "dce/dce_mem_input.h"
> > +#include "dce/dce_link_encoder.h"
> > +#include "dce/dce_stream_encoder.h"
> > +#include "dce/dce_mem_input.h"
> > +#include "dce/dce_ipp.h"
> > +#include "dce/dce_transform.h"
> > +#include "dce/dce_opp.h"
> > +#include "dce/dce_clock_source.h"
> > +#include "dce/dce_audio.h"
> > +#include "dce/dce_hwseq.h"
> > +#include "dce60/dce60_hw_sequencer.h"
> > +#include "dce100/dce100_resource.h"
> > +
> > +#include "reg_helper.h"
> > +
> > +#include "dce/dce_dmcu.h"
> > +#include "dce/dce_aux.h"
> > +#include "dce/dce_abm.h"
> > +#include "dce/dce_i2c.h"
> > +/* TODO remove this include */
> > +
> > +#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
> > +#include "gmc/gmc_6_0_d.h"
> > +#include "gmc/gmc_6_0_sh_mask.h"
> > +#endif
> > +
> > +#ifndef mmDP_DPHY_INTERNAL_CTRL
> > +#define mmDP_DPHY_INTERNAL_CTRL                         0x1CDE
> > +#define mmDP0_DP_DPHY_INTERNAL_CTRL                     0x1CDE
> > +#define mmDP1_DP_DPHY_INTERNAL_CTRL                     0x1FDE
> > +#define mmDP2_DP_DPHY_INTERNAL_CTRL                     0x42DE
> > +#define mmDP3_DP_DPHY_INTERNAL_CTRL                     0x45DE
> > +#define mmDP4_DP_DPHY_INTERNAL_CTRL                     0x48DE
> > +#define mmDP5_DP_DPHY_INTERNAL_CTRL                     0x4BDE
> > +#define mmDP6_DP_DPHY_INTERNAL_CTRL                     0x4EDE
>
> No SI part has 7 pipes. Let's drop mmDP6_DP_DPHY_INTERNAL_CTRL.
>
> > +#endif
> > +
> > +
> > +#ifndef mmBIOS_SCRATCH_2
> > +     #define mmBIOS_SCRATCH_2 0x05CB
> > +     #define mmBIOS_SCRATCH_6 0x05CF
> > +#endif
> > +
> > +#ifndef mmDP_DPHY_FAST_TRAINING
> > +     #define mmDP_DPHY_FAST_TRAINING                         0x1CCE
> > +     #define mmDP0_DP_DPHY_FAST_TRAINING                     0x1CCE
> > +     #define mmDP1_DP_DPHY_FAST_TRAINING                     0x1FCE
> > +     #define mmDP2_DP_DPHY_FAST_TRAINING                     0x42CE
> > +     #define mmDP3_DP_DPHY_FAST_TRAINING                     0x45CE
> > +     #define mmDP4_DP_DPHY_FAST_TRAINING                     0x48CE
> > +     #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4BCE
> > +     #define mmDP6_DP_DPHY_FAST_TRAINING                     0x4ECE
> > +#endif
> > +
>
> Drop mmDP6_DP_DPHY_FAST_TRAINING.
>
> Otherwise the registers above this line look right.
>
> > +
> > +#ifndef mmHPD_DC_HPD_CONTROL
> > +     #define mmHPD_DC_HPD_CONTROL                            0x189A
> > +     #define mmHPD0_DC_HPD_CONTROL                           0x189A
> > +     #define mmHPD1_DC_HPD_CONTROL                           0x18A2
> > +     #define mmHPD2_DC_HPD_CONTROL                           0x18AA
> > +     #define mmHPD3_DC_HPD_CONTROL                           0x18B2
> > +     #define mmHPD4_DC_HPD_CONTROL                           0x18BA
> > +     #define mmHPD5_DC_HPD_CONTROL                           0x18C2
> > +#endif
> > +
> > +#define DCE11_DIG_FE_CNTL 0x4a00
> > +#define DCE11_DIG_BE_CNTL 0x4a47
> > +#define DCE11_DP_SEC 0x4ac3
> > +
>
> These registers (from mmHPD_DC_HPD_CONTROL down to here) are unused and can all be dropped. We should also drop them in dce80_resource.c in a separate patch. I leave it up to you if you want to do it.
>
> > +static const struct dce110_timing_generator_offsets dce60_tg_offsets[] = {
> > +             {
> > +                     .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
> > +                     .dcp =  (mmGRPH_CONTROL - mmGRPH_CONTROL),
> > +                     .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
> > +                                     - mmDPG_WATERMARK_MASK_CONTROL),
> > +             },
> > +             {
> > +                     .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
> > +                     .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
> > +                     .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
> > +                                     - mmDPG_WATERMARK_MASK_CONTROL),
> > +             },
> > +             {
> > +                     .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
> > +                     .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
> > +                     .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
> > +                                     - mmDPG_WATERMARK_MASK_CONTROL),
> > +             },
> > +             {
> > +                     .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
> > +                     .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
> > +                     .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
> > +                                     - mmDPG_WATERMARK_MASK_CONTROL),
> > +             },
> > +             {
> > +                     .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
> > +                     .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
> > +                     .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
> > +                                     - mmDPG_WATERMARK_MASK_CONTROL),
> > +             },
> > +             {
> > +                     .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
> > +                     .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
> > +                     .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
> > +                                     - mmDPG_WATERMARK_MASK_CONTROL),
> > +             }
> > +};
> > +
> > +/* set register offset */
> > +#define SR(reg_name)\
> > +     .reg_name = mm ## reg_name
> > +
> > +/* set register offset with instance */
> > +#define SRI(reg_name, block, id)\
> > +     .reg_name = mm ## block ## id ## _ ## reg_name
> > +
> > +
> > +static const struct clk_mgr_registers disp_clk_regs = {
> > +             CLK_COMMON_REG_LIST_DCE_BASE()
> > +};
> > +
> > +static const struct clk_mgr_shift disp_clk_shift = {
> > +             CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
> > +};
> > +
> > +static const struct clk_mgr_mask disp_clk_mask = {
> > +             CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> > +};
> > +
> > +#define ipp_regs(id)\
> > +[id] = {\
> > +             IPP_COMMON_REG_LIST_DCE_BASE(id)\
> > +}
> > +
> > +static const struct dce_ipp_registers ipp_regs[] = {
> > +             ipp_regs(0),
> > +             ipp_regs(1),
> > +             ipp_regs(2),
> > +             ipp_regs(3),
> > +             ipp_regs(4),
> > +             ipp_regs(5)
> > +};
> > +
> > +static const struct dce_ipp_shift ipp_shift = {
> > +             IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
> > +};
> > +
> > +static const struct dce_ipp_mask ipp_mask = {
> > +             IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> > +};
> > +
> > +#define transform_regs(id)\
> > +[id] = {\
> > +             XFM_COMMON_REG_LIST_DCE80(id)\
> > +}
> > +
> > +static const struct dce_transform_registers xfm_regs[] = {
> > +             transform_regs(0),
> > +             transform_regs(1),
> > +             transform_regs(2),
> > +             transform_regs(3),
> > +             transform_regs(4),
> > +             transform_regs(5)
> > +};
> > +
> > +static const struct dce_transform_shift xfm_shift = {
> > +             XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
> > +};
> > +
> > +static const struct dce_transform_mask xfm_mask = {
> > +             XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
> > +};
> > +
> > +#define aux_regs(id)\
> > +[id] = {\
> > +     AUX_REG_LIST(id)\
> > +}
> > +
> > +static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
> > +     aux_regs(0),
> > +     aux_regs(1),
> > +     aux_regs(2),
> > +     aux_regs(3),
> > +     aux_regs(4),
> > +     aux_regs(5)
> > +};
> > +
> > +#define hpd_regs(id)\
> > +[id] = {\
> > +     HPD_REG_LIST(id)\
> > +}
> > +
> > +static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
> > +             hpd_regs(0),
> > +             hpd_regs(1),
> > +             hpd_regs(2),
> > +             hpd_regs(3),
> > +             hpd_regs(4),
> > +             hpd_regs(5)
> > +};
> > +
> > +#define link_regs(id)\
> > +[id] = {\
> > +     LE_DCE80_REG_LIST(id)\
> > +}
> > +
> > +static const struct dce110_link_enc_registers link_enc_regs[] = {
> > +     link_regs(0),
> > +     link_regs(1),
> > +     link_regs(2),
> > +     link_regs(3),
> > +     link_regs(4),
> > +     link_regs(5),
> > +     link_regs(6),
> > +};
> > +
> > +#define stream_enc_regs(id)\
> > +[id] = {\
> > +     SE_COMMON_REG_LIST_DCE_BASE(id),\
> > +     .AFMT_CNTL = 0,\
> > +}
> > +
> > +static const struct dce110_stream_enc_registers stream_enc_regs[] = {
> > +     stream_enc_regs(0),
> > +     stream_enc_regs(1),
> > +     stream_enc_regs(2),
> > +     stream_enc_regs(3),
> > +     stream_enc_regs(4),
> > +     stream_enc_regs(5),
> > +     stream_enc_regs(6)
> > +};
> > +
> > +static const struct dce_stream_encoder_shift se_shift = {
> > +             SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
> > +};
> > +
> > +static const struct dce_stream_encoder_mask se_mask = {
> > +             SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
> > +};
> > +
> > +#define opp_regs(id)\
> > +[id] = {\
> > +     OPP_DCE_80_REG_LIST(id),\
> > +}
> > +
> > +static const struct dce_opp_registers opp_regs[] = {
> > +     opp_regs(0),
> > +     opp_regs(1),
> > +     opp_regs(2),
> > +     opp_regs(3),
> > +     opp_regs(4),
> > +     opp_regs(5)
> > +};
> > +
> > +static const struct dce_opp_shift opp_shift = {
> > +     OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
> > +};
> > +
> > +static const struct dce_opp_mask opp_mask = {
> > +     OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
> > +};
> > +
> > +#define aux_engine_regs(id)\
> > +[id] = {\
> > +     AUX_COMMON_REG_LIST(id), \
> > +     .AUX_RESET_MASK = 0 \
> > +}
> > +
> > +static const struct dce110_aux_registers aux_engine_regs[] = {
> > +             aux_engine_regs(0),
> > +             aux_engine_regs(1),
> > +             aux_engine_regs(2),
> > +             aux_engine_regs(3),
> > +             aux_engine_regs(4),
> > +             aux_engine_regs(5)
> > +};
> > +
> > +#define audio_regs(id)\
> > +[id] = {\
> > +     AUD_COMMON_REG_LIST(id)\
> > +}
> > +
> > +static const struct dce_audio_registers audio_regs[] = {
> > +     audio_regs(0),
> > +     audio_regs(1),
> > +     audio_regs(2),
> > +     audio_regs(3),
> > +     audio_regs(4),
> > +     audio_regs(5),
> > +     audio_regs(6),
>
> Only 6 audios on SI, so drop audio_regs(6).
>
> > +};
> > +
> > +static const struct dce_audio_shift audio_shift = {
> > +             AUD_COMMON_MASK_SH_LIST(__SHIFT)
> > +};
> > +
> > +static const struct dce_aduio_mask audio_mask = {
> > +             AUD_COMMON_MASK_SH_LIST(_MASK)
> > +};
> > +
> > +#define clk_src_regs(id)\
> > +[id] = {\
> > +     CS_COMMON_REG_LIST_DCE_80(id),\
> > +}
> > +
> > +
> > +static const struct dce110_clk_src_regs clk_src_regs[] = {
> > +     clk_src_regs(0),
> > +     clk_src_regs(1),
> > +     clk_src_regs(2)
> > +};
> > +
> > +static const struct dce110_clk_src_shift cs_shift = {
> > +             CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
> > +};
> > +
> > +static const struct dce110_clk_src_mask cs_mask = {
> > +             CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> > +};
> > +
> > +static const struct bios_registers bios_regs = {
> > +     .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
> > +};
> > +
> > +static const struct resource_caps res_cap = {
> > +             .num_timing_generator = 6,
> > +             .num_audio = 6,
> > +             .num_stream_encoder = 6,
> > +             .num_pll = 2,
> > +             .num_ddc = 6,
> > +};
> > +
> > +static const struct resource_caps res_cap_61 = {
> > +             .num_timing_generator = 4,
> > +             .num_audio = 6,
> > +             .num_stream_encoder = 6,
> > +             .num_pll = 2,
> > +             .num_ddc = 6,
> > +};
> > +
> > +static const struct resource_caps res_cap_64 = {
> > +             .num_timing_generator = 2,
> > +             .num_audio = 2,
> > +             .num_stream_encoder = 2,
> > +             .num_pll = 2,
> > +             .num_ddc = 2,
> > +};
> > +
> > +static const struct dce_dmcu_registers dmcu_regs = {
> > +             DMCU_DCE80_REG_LIST()
> > +};
> > +
> > +static const struct dce_dmcu_shift dmcu_shift = {
> > +             DMCU_MASK_SH_LIST_DCE80(__SHIFT)
> > +};
> > +
> > +static const struct dce_dmcu_mask dmcu_mask = {
> > +             DMCU_MASK_SH_LIST_DCE80(_MASK)
> > +};
> > +static const struct dce_abm_registers abm_regs = {
> > +             ABM_DCE110_COMMON_REG_LIST()
> > +};
> > +
> > +static const struct dce_abm_shift abm_shift = {
> > +             ABM_MASK_SH_LIST_DCE110(__SHIFT)
> > +};
> > +
> > +static const struct dce_abm_mask abm_mask = {
> > +             ABM_MASK_SH_LIST_DCE110(_MASK)
> > +};
> > +
> > +#define CTX  ctx
> > +#define REG(reg) mm ## reg
> > +
> > +#ifndef mmCC_DC_HDMI_STRAPS
> > +#define mmCC_DC_HDMI_STRAPS 0x1918
> > +#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
> > +#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
> > +#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
> > +#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
> > +#endif
> > +
>
> These registers defines are all good.
>
> > +static void read_dce_straps(
> > +     struct dc_context *ctx,
> > +     struct resource_straps *straps)
> > +{
> > +     REG_GET_2(CC_DC_HDMI_STRAPS,
> > +                     HDMI_DISABLE, &straps->hdmi_disable,
> > +                     AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
> > +
> > +     REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
> > +}
> > +
> > +static struct audio *create_audio(
> > +             struct dc_context *ctx, unsigned int inst)
> > +{
> > +     return dce_audio_create(ctx, inst,
> > +                     &audio_regs[inst], &audio_shift, &audio_mask);
> > +}
> > +
> > +static struct timing_generator *dce60_timing_generator_create(
> > +             struct dc_context *ctx,
> > +             uint32_t instance,
> > +             const struct dce110_timing_generator_offsets *offsets)
> > +{
> > +     struct dce110_timing_generator *tg110 =
> > +             kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
> > +
> > +     if (!tg110)
> > +             return NULL;
> > +
> > +     dce60_timing_generator_construct(tg110, ctx, instance, offsets);
> > +     return &tg110->base;
> > +}
> > +
> > +static struct output_pixel_processor *dce60_opp_create(
> > +     struct dc_context *ctx,
> > +     uint32_t inst)
> > +{
> > +     struct dce110_opp *opp =
> > +             kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
> > +
> > +     if (!opp)
> > +             return NULL;
> > +
> > +     dce110_opp_construct(opp,
> > +                          ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
> > +     return &opp->base;
> > +}
> > +
> > +struct aux_engine *dce60_aux_engine_create(
> > +     struct dc_context *ctx,
> > +     uint32_t inst)
> > +{
> > +     struct aux_engine_dce110 *aux_engine =
> > +             kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
> > +
> > +     if (!aux_engine)
> > +             return NULL;
> > +
> > +     dce110_aux_engine_construct(aux_engine, ctx, inst,
> > +                                 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
> > +                                 &aux_engine_regs[inst]);
> > +
> > +     return &aux_engine->base;
> > +}
> > +#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
> > +
> > +static const struct dce_i2c_registers i2c_hw_regs[] = {
> > +             i2c_inst_regs(1),
> > +             i2c_inst_regs(2),
> > +             i2c_inst_regs(3),
> > +             i2c_inst_regs(4),
> > +             i2c_inst_regs(5),
> > +             i2c_inst_regs(6),
> > +};
> > +
> > +static const struct dce_i2c_shift i2c_shifts = {
> > +             I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
> > +};
> > +
> > +static const struct dce_i2c_mask i2c_masks = {
> > +             I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> > +};
> > +
> > +struct dce_i2c_hw *dce60_i2c_hw_create(
> > +     struct dc_context *ctx,
> > +     uint32_t inst)
> > +{
> > +     struct dce_i2c_hw *dce_i2c_hw =
> > +             kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
> > +
> > +     if (!dce_i2c_hw)
> > +             return NULL;
> > +
> > +     dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
> > +                                 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
> > +
> > +     return dce_i2c_hw;
> > +}
> > +
> > +struct dce_i2c_sw *dce60_i2c_sw_create(
> > +     struct dc_context *ctx)
> > +{
> > +     struct dce_i2c_sw *dce_i2c_sw =
> > +             kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
> > +
> > +     if (!dce_i2c_sw)
> > +             return NULL;
> > +
> > +     dce_i2c_sw_construct(dce_i2c_sw, ctx);
> > +
> > +     return dce_i2c_sw;
> > +}
> > +static struct stream_encoder *dce60_stream_encoder_create(
> > +     enum engine_id eng_id,
> > +     struct dc_context *ctx)
> > +{
> > +     struct dce110_stream_encoder *enc110 =
> > +             kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
> > +
> > +     if (!enc110)
> > +             return NULL;
> > +
> > +     dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
> > +                                     &stream_enc_regs[eng_id],
> > +                                     &se_shift, &se_mask);
> > +     return &enc110->base;
> > +}
> > +
> > +#define SRII(reg_name, block, id)\
> > +     .reg_name[id] = mm ## block ## id ## _ ## reg_name
> > +
> > +static const struct dce_hwseq_registers hwseq_reg = {
> > +             HWSEQ_DCE8_REG_LIST()
> > +};
> > +
> > +static const struct dce_hwseq_shift hwseq_shift = {
> > +             HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
> > +};
> > +
> > +static const struct dce_hwseq_mask hwseq_mask = {
> > +             HWSEQ_DCE8_MASK_SH_LIST(_MASK)
> > +};
> > +
> > +static struct dce_hwseq *dce60_hwseq_create(
> > +     struct dc_context *ctx)
> > +{
> > +     struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
> > +
> > +     if (hws) {
> > +             hws->ctx = ctx;
> > +             hws->regs = &hwseq_reg;
> > +             hws->shifts = &hwseq_shift;
> > +             hws->masks = &hwseq_mask;
> > +     }
> > +     return hws;
> > +}
> > +
> > +static const struct resource_create_funcs res_create_funcs = {
> > +     .read_dce_straps = read_dce_straps,
> > +     .create_audio = create_audio,
> > +     .create_stream_encoder = dce60_stream_encoder_create,
> > +     .create_hwseq = dce60_hwseq_create,
> > +};
> > +
> > +#define mi_inst_regs(id) { \
> > +     MI_DCE8_REG_LIST(id), \
> > +     .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
> > +}
> > +static const struct dce_mem_input_registers mi_regs[] = {
> > +             mi_inst_regs(0),
> > +             mi_inst_regs(1),
> > +             mi_inst_regs(2),
> > +             mi_inst_regs(3),
> > +             mi_inst_regs(4),
> > +             mi_inst_regs(5),
> > +};
> > +
> > +static const struct dce_mem_input_shift mi_shifts = {
> > +             MI_DCE8_MASK_SH_LIST(__SHIFT),
> > +             .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
> > +};
> > +
> > +static const struct dce_mem_input_mask mi_masks = {
> > +             MI_DCE8_MASK_SH_LIST(_MASK),
> > +             .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
> > +};
> > +
> > +static struct mem_input *dce60_mem_input_create(
> > +     struct dc_context *ctx,
> > +     uint32_t inst)
> > +{
> > +     struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
> > +                                            GFP_KERNEL);
> > +
> > +     if (!dce_mi) {
> > +             BREAK_TO_DEBUGGER();
> > +             return NULL;
> > +     }
> > +
> > +     dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
> > +     dce_mi->wa.single_head_rdreq_dmif_limit = 2;
> > +     return &dce_mi->base;
> > +}
> > +
> > +static void dce60_transform_destroy(struct transform **xfm)
> > +{
> > +     kfree(TO_DCE_TRANSFORM(*xfm));
> > +     *xfm = NULL;
> > +}
> > +
> > +static struct transform *dce60_transform_create(
> > +     struct dc_context *ctx,
> > +     uint32_t inst)
> > +{
> > +     struct dce_transform *transform =
> > +             kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
> > +
> > +     if (!transform)
> > +             return NULL;
> > +
> > +     dce_transform_construct(transform, ctx, inst,
> > +                             &xfm_regs[inst], &xfm_shift, &xfm_mask);
> > +     transform->prescaler_on = false;
> > +     return &transform->base;
> > +}
> > +
> > +static const struct encoder_feature_support link_enc_feature = {
> > +             .max_hdmi_deep_color = COLOR_DEPTH_121212,
> > +             .max_hdmi_pixel_clock = 297000,
> > +             .flags.bits.IS_HBR2_CAPABLE = true,
> > +             .flags.bits.IS_TPS3_CAPABLE = true
> > +};
> > +
> > +struct link_encoder *dce60_link_encoder_create(
> > +     const struct encoder_init_data *enc_init_data)
> > +{
> > +     struct dce110_link_encoder *enc110 =
> > +             kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
> > +
> > +     if (!enc110)
> > +             return NULL;
> > +
> > +     dce110_link_encoder_construct(enc110,
> > +                                   enc_init_data,
> > +                                   &link_enc_feature,
> > +                                   &link_enc_regs[enc_init_data->transmitter],
> > +                                   &link_enc_aux_regs[enc_init_data->channel - 1],
> > +                                   &link_enc_hpd_regs[enc_init_data->hpd_source]);
> > +     return &enc110->base;
> > +}
> > +
> > +struct clock_source *dce60_clock_source_create(
> > +     struct dc_context *ctx,
> > +     struct dc_bios *bios,
> > +     enum clock_source_id id,
> > +     const struct dce110_clk_src_regs *regs,
> > +     bool dp_clk_src)
> > +{
> > +     struct dce110_clk_src *clk_src =
> > +             kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
> > +
> > +     if (!clk_src)
> > +             return NULL;
> > +
> > +     if (dce110_clk_src_construct(clk_src, ctx, bios, id,
> > +                     regs, &cs_shift, &cs_mask)) {
> > +             clk_src->base.dp_clk_src = dp_clk_src;
> > +             return &clk_src->base;
> > +     }
> > +
> > +     BREAK_TO_DEBUGGER();
> > +     return NULL;
> > +}
> > +
> > +void dce60_clock_source_destroy(struct clock_source **clk_src)
> > +{
> > +     kfree(TO_DCE110_CLK_SRC(*clk_src));
> > +     *clk_src = NULL;
> > +}
> > +
> > +static struct input_pixel_processor *dce60_ipp_create(
> > +     struct dc_context *ctx, uint32_t inst)
> > +{
> > +     struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
> > +
> > +     if (!ipp) {
> > +             BREAK_TO_DEBUGGER();
> > +             return NULL;
> > +     }
> > +
> > +     dce_ipp_construct(ipp, ctx, inst,
> > +                     &ipp_regs[inst], &ipp_shift, &ipp_mask);
> > +     return &ipp->base;
> > +}
> > +
> > +static void destruct(struct dce110_resource_pool *pool)
> > +{
> > +     unsigned int i;
> > +
> > +     for (i = 0; i < pool->base.pipe_count; i++) {
> > +             if (pool->base.opps[i] != NULL)
> > +                     dce110_opp_destroy(&pool->base.opps[i]);
> > +
> > +             if (pool->base.transforms[i] != NULL)
> > +                     dce60_transform_destroy(&pool->base.transforms[i]);
> > +
> > +             if (pool->base.ipps[i] != NULL)
> > +                     dce_ipp_destroy(&pool->base.ipps[i]);
> > +
> > +             if (pool->base.mis[i] != NULL) {
> > +                     kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
> > +                     pool->base.mis[i] = NULL;
> > +             }
> > +
> > +             if (pool->base.timing_generators[i] != NULL)    {
> > +                     kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
> > +                     pool->base.timing_generators[i] = NULL;
> > +             }
> > +     }
> > +
> > +     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
> > +             if (pool->base.engines[i] != NULL)
> > +                     dce110_engine_destroy(&pool->base.engines[i]);
> > +             if (pool->base.hw_i2cs[i] != NULL) {
> > +                     kfree(pool->base.hw_i2cs[i]);
> > +                     pool->base.hw_i2cs[i] = NULL;
> > +             }
> > +             if (pool->base.sw_i2cs[i] != NULL) {
> > +                     kfree(pool->base.sw_i2cs[i]);
> > +                     pool->base.sw_i2cs[i] = NULL;
> > +             }
> > +     }
> > +
> > +     for (i = 0; i < pool->base.stream_enc_count; i++) {
> > +             if (pool->base.stream_enc[i] != NULL)
> > +                     kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
> > +     }
> > +
> > +     for (i = 0; i < pool->base.clk_src_count; i++) {
> > +             if (pool->base.clock_sources[i] != NULL) {
> > +                     dce60_clock_source_destroy(&pool->base.clock_sources[i]);
> > +             }
> > +     }
> > +
> > +     if (pool->base.abm != NULL)
> > +                     dce_abm_destroy(&pool->base.abm);
> > +
> > +     if (pool->base.dmcu != NULL)
> > +                     dce_dmcu_destroy(&pool->base.dmcu);
> > +
> > +     if (pool->base.dp_clock_source != NULL)
> > +             dce60_clock_source_destroy(&pool->base.dp_clock_source);
> > +
> > +     for (i = 0; i < pool->base.audio_count; i++)    {
> > +             if (pool->base.audios[i] != NULL) {
> > +                     dce_aud_destroy(&pool->base.audios[i]);
> > +             }
> > +     }
> > +
> > +     if (pool->base.clk_mgr != NULL)
> > +             dce_clk_mgr_destroy(&pool->base.clk_mgr);
> > +
> > +     if (pool->base.irqs != NULL) {
> > +             dal_irq_service_destroy(&pool->base.irqs);
> > +     }
> > +}
> > +
> > +bool dce60_validate_bandwidth(
> > +     struct dc *dc,
> > +     struct dc_state *context)
> > +{
> > +     /* TODO implement when needed but for now hardcode max value*/
> > +     context->bw.dce.dispclk_khz = 681000;
> > +     context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
> > +
>
> Not sure where to find the actual values but this should be okay for now.
>
> > +     return true;
> > +}
> > +
> > +static bool dce60_validate_surface_sets(
> > +             struct dc_state *context)
> > +{
> > +     int i;
> > +
> > +     for (i = 0; i < context->stream_count; i++) {
> > +             if (context->stream_status[i].plane_count == 0)
> > +                     continue;
> > +
> > +             if (context->stream_status[i].plane_count > 1)
> > +                     return false;
> > +
> > +             if (context->stream_status[i].plane_states[0]->format
> > +                             >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
> > +                     return false;
> > +     }
> > +
> > +     return true;
> > +}
> > +
> > +enum dc_status dce60_validate_global(
> > +             struct dc *dc,
> > +             struct dc_state *context)
> > +{
> > +     if (!dce60_validate_surface_sets(context))
> > +             return DC_FAIL_SURFACE_VALIDATE;
> > +
> > +     return DC_OK;
> > +}
> > +
> > +static void dce60_destroy_resource_pool(struct resource_pool **pool)
> > +{
> > +     struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
> > +
> > +     destruct(dce110_pool);
> > +     kfree(dce110_pool);
> > +     *pool = NULL;
> > +}
> > +
> > +static const struct resource_funcs dce60_res_pool_funcs = {
> > +     .destroy = dce60_destroy_resource_pool,
> > +     .link_enc_create = dce60_link_encoder_create,
> > +     .validate_bandwidth = dce60_validate_bandwidth,
> > +     .validate_plane = dce100_validate_plane,
> > +     .add_stream_to_ctx = dce100_add_stream_to_ctx,
> > +     .validate_global = dce60_validate_global
> > +};
> > +
> > +static bool dce60_construct(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc,
> > +     struct dce110_resource_pool *pool)
> > +{
> > +     unsigned int i;
> > +     struct dc_context *ctx = dc->ctx;
> > +     struct dc_firmware_info info;
> > +     struct dc_bios *bp;
> > +
> > +     ctx->dc_bios->regs = &bios_regs;
> > +
> > +     pool->base.res_cap = &res_cap;
> > +     pool->base.funcs = &dce60_res_pool_funcs;
> > +
> > +
> > +     /*************************************************
> > +      *  Resource + asic cap harcoding                *
> > +      *************************************************/
> > +     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
> > +     pool->base.pipe_count = res_cap.num_timing_generator;
> > +     pool->base.timing_generator_count = res_cap.num_timing_generator;
> > +     dc->caps.max_downscale_ratio = 200;
> > +     dc->caps.i2c_speed_in_khz = 40;
> > +     dc->caps.max_cursor_size = 128;
> > +     dc->caps.dual_link_dvi = true;
> > +
> > +     /*************************************************
> > +      *  Create resources                             *
> > +      *************************************************/
> > +
> > +     bp = ctx->dc_bios;
> > +
> > +     if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
> > +             info.external_clock_source_frequency_for_dp != 0) {
> > +             pool->base.dp_clock_source =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
> > +
> > +             pool->base.clock_sources[0] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
> > +             pool->base.clock_sources[1] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
> > +             pool->base.clock_sources[2] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
> > +             pool->base.clk_src_count = 3;
> > +
> > +     } else {
> > +             pool->base.dp_clock_source =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
> > +
> > +             pool->base.clock_sources[0] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
> > +             pool->base.clock_sources[1] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
> > +             pool->base.clk_src_count = 2;
> > +     }
> > +
> > +     if (pool->base.dp_clock_source == NULL) {
> > +             dm_error("DC: failed to create dp clock source!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     for (i = 0; i < pool->base.clk_src_count; i++) {
> > +             if (pool->base.clock_sources[i] == NULL) {
> > +                     dm_error("DC: failed to create clock sources!\n");
> > +                     BREAK_TO_DEBUGGER();
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     pool->base.clk_mgr = dce_clk_mgr_create(ctx,
> > +                     &disp_clk_regs,
> > +                     &disp_clk_shift,
> > +                     &disp_clk_mask);
> > +     if (pool->base.clk_mgr == NULL) {
> > +             dm_error("DC: failed to create display clock!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     pool->base.dmcu = dce_dmcu_create(ctx,
> > +                     &dmcu_regs,
> > +                     &dmcu_shift,
> > +                     &dmcu_mask);
> > +     if (pool->base.dmcu == NULL) {
> > +             dm_error("DC: failed to create dmcu!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     pool->base.abm = dce_abm_create(ctx,
> > +                     &abm_regs,
> > +                     &abm_shift,
> > +                     &abm_mask);
> > +     if (pool->base.abm == NULL) {
> > +             dm_error("DC: failed to create abm!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     {
> > +             struct irq_service_init_data init_data;
> > +             init_data.ctx = dc->ctx;
> > +             pool->base.irqs = dal_irq_service_dce60_create(&init_data);
> > +             if (!pool->base.irqs)
> > +                     goto res_create_fail;
> > +     }
> > +
> > +     for (i = 0; i < pool->base.pipe_count; i++) {
> > +             pool->base.timing_generators[i] = dce60_timing_generator_create(
> > +                             ctx, i, &dce60_tg_offsets[i]);
> > +             if (pool->base.timing_generators[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create tg!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.mis[i] = dce60_mem_input_create(ctx, i);
> > +             if (pool->base.mis[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create memory input!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.ipps[i] = dce60_ipp_create(ctx, i);
> > +             if (pool->base.ipps[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create input pixel processor!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.transforms[i] = dce60_transform_create(ctx, i);
> > +             if (pool->base.transforms[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create transform!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.opps[i] = dce60_opp_create(ctx, i);
> > +             if (pool->base.opps[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create output pixel processor!\n");
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
> > +             pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
> > +             if (pool->base.engines[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create aux engine!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +             pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
> > +             if (pool->base.hw_i2cs[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create i2c engine!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +             pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
> > +             if (pool->base.sw_i2cs[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create sw i2c!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     dc->caps.max_planes =  pool->base.pipe_count;
> > +     dc->caps.disable_dp_clk_share = true;
> > +
> > +     if (!resource_construct(num_virtual_links, dc, &pool->base,
> > +                     &res_create_funcs))
> > +             goto res_create_fail;
> > +
> > +     /* Create hardware sequencer */
> > +     dce60_hw_sequencer_construct(dc);
> > +
> > +     return true;
> > +
> > +res_create_fail:
> > +     destruct(pool);
> > +     return false;
> > +}
> > +
> > +struct resource_pool *dce60_create_resource_pool(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc)
> > +{
> > +     struct dce110_resource_pool *pool =
> > +             kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
> > +
> > +     if (!pool)
> > +             return NULL;
> > +
> > +     if (dce60_construct(num_virtual_links, dc, pool))
> > +             return &pool->base;
> > +
> > +     BREAK_TO_DEBUGGER();
> > +     return NULL;
> > +}
> > +
> > +static bool dce61_construct(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc,
> > +     struct dce110_resource_pool *pool)
> > +{
> > +     unsigned int i;
> > +     struct dc_context *ctx = dc->ctx;
> > +     struct dc_firmware_info info;
> > +     struct dc_bios *bp;
> > +
> > +     ctx->dc_bios->regs = &bios_regs;
> > +
> > +     pool->base.res_cap = &res_cap_61;
> > +     pool->base.funcs = &dce60_res_pool_funcs;
> > +
> > +
> > +     /*************************************************
> > +      *  Resource + asic cap harcoding                *
> > +      *************************************************/
> > +     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
> > +     pool->base.pipe_count = res_cap_61.num_timing_generator;
> > +     pool->base.timing_generator_count = res_cap_61.num_timing_generator;
> > +     dc->caps.max_downscale_ratio = 200;
> > +     dc->caps.i2c_speed_in_khz = 40;
> > +     dc->caps.max_cursor_size = 128;
> > +     dc->caps.is_apu = true;
> > +
> > +     /*************************************************
> > +      *  Create resources                             *
> > +      *************************************************/
> > +
> > +     bp = ctx->dc_bios;
> > +
> > +     if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
> > +             info.external_clock_source_frequency_for_dp != 0) {
> > +             pool->base.dp_clock_source =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
> > +
> > +             pool->base.clock_sources[0] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
> > +             pool->base.clock_sources[1] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
> > +             pool->base.clock_sources[2] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
> > +             pool->base.clk_src_count = 3;
> > +
> > +     } else {
> > +             pool->base.dp_clock_source =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
> > +
> > +             pool->base.clock_sources[0] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
> > +             pool->base.clock_sources[1] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
> > +             pool->base.clk_src_count = 2;
> > +     }
> > +
> > +     if (pool->base.dp_clock_source == NULL) {
> > +             dm_error("DC: failed to create dp clock source!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     for (i = 0; i < pool->base.clk_src_count; i++) {
> > +             if (pool->base.clock_sources[i] == NULL) {
> > +                     dm_error("DC: failed to create clock sources!\n");
> > +                     BREAK_TO_DEBUGGER();
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     pool->base.clk_mgr = dce_clk_mgr_create(ctx,
> > +                     &disp_clk_regs,
> > +                     &disp_clk_shift,
> > +                     &disp_clk_mask);
> > +     if (pool->base.clk_mgr == NULL) {
> > +             dm_error("DC: failed to create display clock!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     pool->base.dmcu = dce_dmcu_create(ctx,
> > +                     &dmcu_regs,
> > +                     &dmcu_shift,
> > +                     &dmcu_mask);
> > +     if (pool->base.dmcu == NULL) {
> > +             dm_error("DC: failed to create dmcu!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     pool->base.abm = dce_abm_create(ctx,
> > +                     &abm_regs,
> > +                     &abm_shift,
> > +                     &abm_mask);
> > +     if (pool->base.abm == NULL) {
> > +             dm_error("DC: failed to create abm!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     {
> > +             struct irq_service_init_data init_data;
> > +             init_data.ctx = dc->ctx;
> > +             pool->base.irqs = dal_irq_service_dce60_create(&init_data);
> > +             if (!pool->base.irqs)
> > +                     goto res_create_fail;
> > +     }
> > +
> > +     for (i = 0; i < pool->base.pipe_count; i++) {
> > +             pool->base.timing_generators[i] = dce60_timing_generator_create(
> > +                             ctx, i, &dce60_tg_offsets[i]);
> > +             if (pool->base.timing_generators[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create tg!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.mis[i] = dce60_mem_input_create(ctx, i);
> > +             if (pool->base.mis[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create memory input!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.ipps[i] = dce60_ipp_create(ctx, i);
> > +             if (pool->base.ipps[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create input pixel processor!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.transforms[i] = dce60_transform_create(ctx, i);
> > +             if (pool->base.transforms[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create transform!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.opps[i] = dce60_opp_create(ctx, i);
> > +             if (pool->base.opps[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create output pixel processor!\n");
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
> > +             pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
> > +             if (pool->base.engines[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create aux engine!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +             pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
> > +             if (pool->base.hw_i2cs[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create i2c engine!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +             pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
> > +             if (pool->base.sw_i2cs[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create sw i2c!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     dc->caps.max_planes =  pool->base.pipe_count;
> > +     dc->caps.disable_dp_clk_share = true;
> > +
> > +     if (!resource_construct(num_virtual_links, dc, &pool->base,
> > +                     &res_create_funcs))
> > +             goto res_create_fail;
> > +
> > +     /* Create hardware sequencer */
> > +     dce60_hw_sequencer_construct(dc);
> > +
> > +     return true;
> > +
> > +res_create_fail:
> > +     destruct(pool);
> > +     return false;
> > +}
> > +
> > +struct resource_pool *dce61_create_resource_pool(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc)
> > +{
> > +     struct dce110_resource_pool *pool =
> > +             kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
> > +
> > +     if (!pool)
> > +             return NULL;
> > +
> > +     if (dce61_construct(num_virtual_links, dc, pool))
> > +             return &pool->base;
> > +
> > +     BREAK_TO_DEBUGGER();
> > +     return NULL;
> > +}
> > +
> > +static bool dce64_construct(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc,
> > +     struct dce110_resource_pool *pool)
> > +{
> > +     unsigned int i;
> > +     struct dc_context *ctx = dc->ctx;
> > +     struct dc_firmware_info info;
> > +     struct dc_bios *bp;
> > +
> > +     ctx->dc_bios->regs = &bios_regs;
> > +
> > +     pool->base.res_cap = &res_cap_64;
> > +     pool->base.funcs = &dce60_res_pool_funcs;
> > +
> > +
> > +     /*************************************************
> > +      *  Resource + asic cap harcoding                *
> > +      *************************************************/
> > +     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
> > +     pool->base.pipe_count = res_cap_64.num_timing_generator;
> > +     pool->base.timing_generator_count = res_cap_64.num_timing_generator;
> > +     dc->caps.max_downscale_ratio = 200;
> > +     dc->caps.i2c_speed_in_khz = 40;
> > +     dc->caps.max_cursor_size = 128;
> > +     dc->caps.is_apu = true;
> > +
> > +     /*************************************************
> > +      *  Create resources                             *
> > +      *************************************************/
> > +
> > +     bp = ctx->dc_bios;
> > +
> > +     if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
> > +             info.external_clock_source_frequency_for_dp != 0) {
> > +             pool->base.dp_clock_source =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
> > +
> > +             pool->base.clock_sources[0] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
> > +             pool->base.clock_sources[1] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
> > +             pool->base.clk_src_count = 2;
> > +
> > +     } else {
> > +             pool->base.dp_clock_source =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
> > +
> > +             pool->base.clock_sources[0] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
> > +             pool->base.clk_src_count = 1;
> > +     }
> > +
> > +     if (pool->base.dp_clock_source == NULL) {
> > +             dm_error("DC: failed to create dp clock source!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     for (i = 0; i < pool->base.clk_src_count; i++) {
> > +             if (pool->base.clock_sources[i] == NULL) {
> > +                     dm_error("DC: failed to create clock sources!\n");
> > +                     BREAK_TO_DEBUGGER();
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     pool->base.clk_mgr = dce_clk_mgr_create(ctx,
> > +                     &disp_clk_regs,
> > +                     &disp_clk_shift,
> > +                     &disp_clk_mask);
> > +     if (pool->base.clk_mgr == NULL) {
> > +             dm_error("DC: failed to create display clock!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     pool->base.dmcu = dce_dmcu_create(ctx,
> > +                     &dmcu_regs,
> > +                     &dmcu_shift,
> > +                     &dmcu_mask);
> > +     if (pool->base.dmcu == NULL) {
> > +             dm_error("DC: failed to create dmcu!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     pool->base.abm = dce_abm_create(ctx,
> > +                     &abm_regs,
> > +                     &abm_shift,
> > +                     &abm_mask);
> > +     if (pool->base.abm == NULL) {
> > +             dm_error("DC: failed to create abm!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     {
> > +             struct irq_service_init_data init_data;
> > +             init_data.ctx = dc->ctx;
> > +             pool->base.irqs = dal_irq_service_dce60_create(&init_data);
> > +             if (!pool->base.irqs)
> > +                     goto res_create_fail;
> > +     }
> > +
> > +     for (i = 0; i < pool->base.pipe_count; i++) {
> > +             pool->base.timing_generators[i] = dce60_timing_generator_create(
> > +                             ctx, i, &dce60_tg_offsets[i]);
> > +             if (pool->base.timing_generators[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create tg!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.mis[i] = dce60_mem_input_create(ctx, i);
> > +             if (pool->base.mis[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create memory input!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.ipps[i] = dce60_ipp_create(ctx, i);
> > +             if (pool->base.ipps[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create input pixel processor!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.transforms[i] = dce60_transform_create(ctx, i);
> > +             if (pool->base.transforms[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create transform!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.opps[i] = dce60_opp_create(ctx, i);
> > +             if (pool->base.opps[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create output pixel processor!\n");
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
> > +             pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
> > +             if (pool->base.engines[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create aux engine!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +             pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
> > +             if (pool->base.hw_i2cs[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create i2c engine!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +             pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
> > +             if (pool->base.sw_i2cs[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create sw i2c!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     dc->caps.max_planes =  pool->base.pipe_count;
> > +     dc->caps.disable_dp_clk_share = true;
> > +
> > +     if (!resource_construct(num_virtual_links, dc, &pool->base,
> > +                     &res_create_funcs))
> > +             goto res_create_fail;
> > +
> > +     /* Create hardware sequencer */
> > +     dce60_hw_sequencer_construct(dc);
> > +
> > +     return true;
> > +
> > +res_create_fail:
> > +     destruct(pool);
> > +     return false;
> > +}
> > +
> > +struct resource_pool *dce64_create_resource_pool(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc)
> > +{
> > +     struct dce110_resource_pool *pool =
> > +             kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
> > +
> > +     if (!pool)
> > +             return NULL;
> > +
> > +     if (dce64_construct(num_virtual_links, dc, pool))
> > +             return &pool->base;
> > +
> > +     BREAK_TO_DEBUGGER();
> > +     return NULL;
> > +}
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
> > new file mode 100644
> > index 000000000000..b30e4e4ed7c0
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
> > @@ -0,0 +1,47 @@
> > +/*
> > +* Copyright 2012-15 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> > + *
> > + */
> > +
> > +#ifndef __DC_RESOURCE_DCE60_H__
> > +#define __DC_RESOURCE_DCE60_H__
> > +
> > +#include "core_types.h"
> > +
> > +struct dc;
> > +struct resource_pool;
> > +
> > +struct resource_pool *dce60_create_resource_pool(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc);
> > +
> > +struct resource_pool *dce61_create_resource_pool(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc);
> > +
> > +struct resource_pool *dce64_create_resource_pool(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc);
> > +
> > +#endif /* __DC_RESOURCE_DCE60_H__ */
> > +
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
> > new file mode 100644
> > index 000000000000..90b610367af8
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
> > @@ -0,0 +1,242 @@
> > +/*
> > + * Copyright 2012-15 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> > + *
> > + */
> > +
> > +#include "dm_services.h"
> > +
> > +/* include DCE6 register header files */
> > +#include "dce/dce_6_0_d.h"
> > +#include "dce/dce_6_0_sh_mask.h"
> > +
> > +#include "dc_types.h"
> > +
> > +#include "include/grph_object_id.h"
> > +#include "include/logger_interface.h"
> > +#include "../dce110/dce110_timing_generator.h"
> > +#include "dce60_timing_generator.h"
> > +
> > +#include "timing_generator.h"
> > +
> > +enum black_color_format {
> > +     BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,   /* used as index in array */
> > +     BLACK_COLOR_FORMAT_RGB_LIMITED,
> > +     BLACK_COLOR_FORMAT_YUV_TV,
> > +     BLACK_COLOR_FORMAT_YUV_CV,
> > +     BLACK_COLOR_FORMAT_YUV_SUPER_AA,
> > +
> > +     BLACK_COLOR_FORMAT_COUNT
> > +};
> > +
> > +static const struct dce110_timing_generator_offsets reg_offsets[] = {
> > +{
> > +     .crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> > +     .dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> > +     .dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> > +     .dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> > +     .dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> > +     .dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> > +     .dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> > +}
> > +};
> > +
> > +#define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
> > +
> > +#define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
> > +#define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
> > +
> > +#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
> > +#define DCP_REG(reg) (reg + tg110->offsets.dcp)
> > +#define DMIF_REG(reg) (reg + tg110->offsets.dmif)
> > +
> > +static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
> > +{
> > +     uint64_t pix_dur;
> > +     uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
> > +                                     + DCE110TG_FROM_TG(tg)->offsets.dmif;
> > +     uint32_t value = dm_read_reg(tg->ctx, addr);
> > +
> > +     if (pix_clk_khz == 0)
> > +             return;
> > +
> > +     pix_dur = 1000000000 / pix_clk_khz;
> > +
> > +     set_reg_field_value(
> > +             value,
> > +             pix_dur,
> > +             DPG_PIPE_ARBITRATION_CONTROL1,
> > +             PIXEL_DURATION);
> > +
> > +     dm_write_reg(tg->ctx, addr, value);
> > +}
> > +
> > +static void program_timing(struct timing_generator *tg,
> > +     const struct dc_crtc_timing *timing,
> > +     bool use_vbios)
> > +{
> > +     if (!use_vbios)
> > +             program_pix_dur(tg, timing->pix_clk_khz);
> > +
> > +     dce110_tg_program_timing(tg, timing, use_vbios);
> > +}
> > +
> > +static void dce60_timing_generator_enable_advanced_request(
> > +     struct timing_generator *tg,
> > +     bool enable,
> > +     const struct dc_crtc_timing *timing)
> > +{
> > +     struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
> > +     uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
> > +     uint32_t value = dm_read_reg(tg->ctx, addr);
> > +
> > +     if (enable) {
> > +             set_reg_field_value(
> > +                     value,
> > +                     0,
> > +                     CRTC_START_LINE_CONTROL,
> > +                     CRTC_LEGACY_REQUESTOR_EN);
> > +     } else {
> > +             set_reg_field_value(
> > +                     value,
> > +                     1,
> > +                     CRTC_START_LINE_CONTROL,
> > +                     CRTC_LEGACY_REQUESTOR_EN);
> > +     }
> > +
> > +     if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
> > +             set_reg_field_value(
> > +                     value,
> > +                     3,
> > +                     CRTC_START_LINE_CONTROL,
> > +                     CRTC_ADVANCED_START_LINE_POSITION);
> > +             set_reg_field_value(
> > +                     value,
> > +                     0,
> > +                     CRTC_START_LINE_CONTROL,
> > +                     CRTC_PREFETCH_EN);
> > +     } else {
> > +             set_reg_field_value(
> > +                     value,
> > +                     4,
> > +                     CRTC_START_LINE_CONTROL,
> > +                     CRTC_ADVANCED_START_LINE_POSITION);
> > +             set_reg_field_value(
> > +                     value,
> > +                     1,
> > +                     CRTC_START_LINE_CONTROL,
> > +                     CRTC_PREFETCH_EN);
> > +     }
> > +
> > +     set_reg_field_value(
> > +             value,
> > +             1,
> > +             CRTC_START_LINE_CONTROL,
> > +             CRTC_PROGRESSIVE_START_LINE_EARLY);
> > +
> > +     set_reg_field_value(
> > +             value,
> > +             1,
> > +             CRTC_START_LINE_CONTROL,
> > +             CRTC_INTERLACE_START_LINE_EARLY);
> > +
> > +     dm_write_reg(tg->ctx, addr, value);
> > +}
> > +
> > +static const struct timing_generator_funcs dce60_tg_funcs = {
> > +             .validate_timing = dce110_tg_validate_timing,
> > +             .program_timing = program_timing,
> > +             .enable_crtc = dce110_timing_generator_enable_crtc,
> > +             .disable_crtc = dce110_timing_generator_disable_crtc,
> > +             .is_counter_moving = dce110_timing_generator_is_counter_moving,
> > +             .get_position = dce110_timing_generator_get_position,
> > +             .get_frame_count = dce110_timing_generator_get_vblank_counter,
> > +             .get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
> > +             .set_early_control = dce110_timing_generator_set_early_control,
> > +             .wait_for_state = dce110_tg_wait_for_state,
> > +             .set_blank = dce110_tg_set_blank,
> > +             .is_blanked = dce110_tg_is_blanked,
> > +             .set_colors = dce110_tg_set_colors,
> > +             .set_overscan_blank_color =
> > +                             dce110_timing_generator_set_overscan_color_black,
> > +             .set_blank_color = dce110_timing_generator_program_blank_color,
> > +             .disable_vga = dce110_timing_generator_disable_vga,
> > +             .did_triggered_reset_occur =
> > +                             dce110_timing_generator_did_triggered_reset_occur,
> > +             .setup_global_swap_lock =
> > +                             dce110_timing_generator_setup_global_swap_lock,
> > +             .enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
> > +             .disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
> > +             .tear_down_global_swap_lock =
> > +                             dce110_timing_generator_tear_down_global_swap_lock,
> > +             .set_drr = dce110_timing_generator_set_drr,
> > +             .set_static_screen_control =
> > +                     dce110_timing_generator_set_static_screen_control,
> > +             .set_test_pattern = dce110_timing_generator_set_test_pattern,
> > +             .arm_vert_intr = dce110_arm_vert_intr,
> > +
> > +             /* DCE6.0 overrides */
> > +             .enable_advanced_request =
> > +                             dce60_timing_generator_enable_advanced_request,
>
> Drop the dce60 function and use the dce80 version. You can expose that through the dce80_timing_generator.h and include that here.
>
> > +             .configure_crc = dce110_configure_crc,
> > +             .get_crc = dce110_get_crc,
> > +};
> > +
> > +void dce60_timing_generator_construct(
> > +     struct dce110_timing_generator *tg110,
> > +     struct dc_context *ctx,
> > +     uint32_t instance,
> > +     const struct dce110_timing_generator_offsets *offsets)
> > +{
> > +     tg110->controller_id = CONTROLLER_ID_D0 + instance;
> > +     tg110->base.inst = instance;
> > +     tg110->offsets = *offsets;
> > +     tg110->derived_offsets = reg_offsets[instance];
> > +
> > +     tg110->base.funcs = &dce60_tg_funcs;
> > +
> > +     tg110->base.ctx = ctx;
> > +     tg110->base.bp = ctx->dc_bios;
> > +
> > +     tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
> > +     tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
> > +
> > +     tg110->min_h_blank = 56;
> > +     tg110->min_h_front_porch = 4;
> > +     tg110->min_h_back_porch = 4;
> > +}
> > +
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
> > new file mode 100644
> > index 000000000000..8972cd0d5815
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
> > @@ -0,0 +1,39 @@
> > +/*
> > + * Copyright 2012-15 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + *  and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> > + *
> > + */
> > +
> > +#ifndef __DC_TIMING_GENERATOR_DCE60_H__
> > +#define __DC_TIMING_GENERATOR_DCE60_H__
> > +
> > +#include "timing_generator.h"
> > +#include "../include/grph_object_id.h"
> > +
> > +/* DCE6.0 implementation inherits from DCE11.0 */
> > +void dce60_timing_generator_construct(
> > +     struct dce110_timing_generator *tg,
> > +     struct dc_context *ctx,
> > +     uint32_t instance,
> > +     const struct dce110_timing_generator_offsets *offsets);
> > +
> > +#endif /* __DC_TIMING_GENERATOR_DCE60_H__ */
> > diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
> > index abe05bc80752..5492c6b98525 100644
> > --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
> > +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
> > @@ -2264,6 +2264,10 @@
> >  #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x00000010
> >  #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000100L
> >  #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x00000008
> > +#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100000
> > +#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x14
> > +#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000
> > +#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x1c
> >  #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
> >  #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x00000000
> >  #define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
> >
>
> Would prefer the update to the register headers to be in a separate patch.
>
> Harry
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Re: [PATCH v2 02/10] drm/amd/display: dc/dce: add DCE6 support (v2)

[Mauro Rossi]

Hi Harry,
On Wed, Oct 17, 2018 at 9:47 PM Wentland, Harry <Harry.Wentland@amd.com> wrote:
>
> On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> > DCE6 targets are added replicating existing DCE8 implementation.
> >
> > NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
> > only to build dce60_resource.c due to missing *_DCE60 macros/registers/masks
> >
> > IMPORTANT: Coding of dce60_resource.c requires review to understand
> > if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
> >
> > (v2) updated dce60_{hw_sequencer,resources}.c as per amd-staging-drm-next
> >      removed dce_version cases in dc/dce/dce_clock_source.c
> > ---
> >  drivers/gpu/drm/amd/display/dc/Makefile       |    4 +
> >  drivers/gpu/drm/amd/display/dc/dce60/Makefile |   34 +
> >  .../amd/display/dc/dce60/dce60_hw_sequencer.c |   82 +
> >  .../amd/display/dc/dce60/dce60_hw_sequencer.h |   36 +
> >  .../drm/amd/display/dc/dce60/dce60_resource.c | 1458 +++++++++++++++++
> >  .../drm/amd/display/dc/dce60/dce60_resource.h |   47 +
> >  .../display/dc/dce60/dce60_timing_generator.c |  242 +++
> >  .../display/dc/dce60/dce60_timing_generator.h |   39 +
> >  .../include/asic_reg/dce/dce_6_0_sh_mask.h    |    4 +
> >  9 files changed, 1946 insertions(+)
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/Makefile
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
> > index aed538a4d1ba..d5d5acd57559 100644
> > --- a/drivers/gpu/drm/amd/display/dc/Makefile
> > +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> > @@ -36,6 +36,10 @@ DC_LIBS += dce110
> >  DC_LIBS += dce100
> >  DC_LIBS += dce80
> >
> > +ifdef CONFIG_DRM_AMD_DC_SI
> > +DC_LIBS += dce60
> > +endif
> > +
> >  AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LIBS)))
> >
> >  include $(AMD_DC)
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/Makefile b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
> > new file mode 100644
> > index 000000000000..39afd7c59a7c
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
> > @@ -0,0 +1,34 @@
> > +#
> > +# Copyright 2017 Advanced Micro Devices, Inc.
> > +#
> > +# Permission is hereby granted, free of charge, to any person obtaining a
> > +# copy of this software and associated documentation files (the "Software"),
> > +# to deal in the Software without restriction, including without limitation
> > +# the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > +# and/or sell copies of the Software, and to permit persons to whom the
> > +# Software is furnished to do so, subject to the following conditions:
> > +#
> > +# The above copyright notice and this permission notice shall be included in
> > +# all copies or substantial portions of the Software.
> > +#
> > +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > +# OTHER DEALINGS IN THE SOFTWARE.
> > +#
> > +#
> > +# Makefile for the 'controller' sub-component of DAL.
> > +# It provides the control and status of HW CRTC block.
> > +
> > +DCE60 = dce60_timing_generator.o dce60_hw_sequencer.o \
> > +     dce60_resource.o
> > +
> > +AMD_DAL_DCE60 = $(addprefix $(AMDDALPATH)/dc/dce60/,$(DCE60))
> > +
> > +AMD_DISPLAY_FILES += $(AMD_DAL_DCE60)
> > +
> > +
> > +
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
> > new file mode 100644
> > index 000000000000..502172bf6097
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
> > @@ -0,0 +1,82 @@
> > +/*
> > + * Copyright 2015 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> > + *
> > + */
> > +
> > +#include "dm_services.h"
> > +#include "dc.h"
> > +#include "core_types.h"
> > +#include "dce60_hw_sequencer.h"
> > +
> > +#include "dce/dce_hwseq.h"
> > +#include "dce110/dce110_hw_sequencer.h"
> > +#include "dce100/dce100_hw_sequencer.h"
> > +
> > +/* include DCE8 register header files */
>
> drop comment or change DCE8 to DCE6
>
> > +#include "dce/dce_6_0_d.h"
> > +#include "dce/dce_6_0_sh_mask.h"
> > +
> > +struct dce60_hw_seq_reg_offsets {
> > +     uint32_t crtc;
> > +};
> > +
> > +static const struct dce60_hw_seq_reg_offsets reg_offsets[] = {
> > +{
> > +     .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
> > +}
> > +};
> > +
> > +#define HW_REG_CRTC(reg, id)\
> > +     (reg + reg_offsets[id].crtc)
> > +
> > +/*******************************************************************************
> > + * Private definitions
> > + ******************************************************************************/
> > +
> > +/***************************PIPE_CONTROL***********************************/
> > +
> > +void dce60_hw_sequencer_construct(struct dc *dc)
> > +{
> > +     dce110_hw_sequencer_construct(dc);
> > +
> > +     dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
> > +     dc->hwss.pipe_control_lock = dce_pipe_control_lock;
> > +     dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
> > +     dc->hwss.optimize_bandwidth = dce100_prepare_bandwidth;
> > +}
> > +
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
> > new file mode 100644
> > index 000000000000..e7ce63b1f75a
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
> > @@ -0,0 +1,36 @@
> > +/*
> > +* Copyright 2012-15 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> > + *
> > + */
> > +
> > +#ifndef __DC_HWSS_DCE60_H__
> > +#define __DC_HWSS_DCE60_H__
> > +
> > +#include "core_types.h"
> > +
> > +struct dc;
> > +
> > +void dce60_hw_sequencer_construct(struct dc *dc);
> > +
> > +#endif /* __DC_HWSS_DCE60_H__ */
> > +
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
> > new file mode 100644
> > index 000000000000..2731f31ce999
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
> > @@ -0,0 +1,1458 @@
> > +/*
> > + * Copyright 2012-15 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> > + *
> > + */
> > +
> > +#include "dce/dce_8_0_d.h"
> > +#include "dce/dce_8_0_sh_mask.h"
>
> This file should really use the dce6 headers. What happens if we build with the dce6 headers? If it's missing definitions I can probably send an update to the headers with what's missing.
>
> > +
> > +#include "dm_services.h"
> > +
> > +#include "link_encoder.h"
> > +#include "stream_encoder.h"
> > +
> > +#include "resource.h"
> > +#include "include/irq_service_interface.h"
> > +#include "irq/dce60/irq_service_dce60.h"
> > +#include "dce110/dce110_timing_generator.h"
> > +#include "dce110/dce110_resource.h"
> > +#include "dce60/dce60_timing_generator.h"
> > +#include "dce/dce_clk_mgr.h"
> > +#include "dce/dce_mem_input.h"
> > +#include "dce/dce_link_encoder.h"
> > +#include "dce/dce_stream_encoder.h"
> > +#include "dce/dce_mem_input.h"
> > +#include "dce/dce_ipp.h"
> > +#include "dce/dce_transform.h"
> > +#include "dce/dce_opp.h"
> > +#include "dce/dce_clock_source.h"
> > +#include "dce/dce_audio.h"
> > +#include "dce/dce_hwseq.h"
> > +#include "dce60/dce60_hw_sequencer.h"
> > +#include "dce100/dce100_resource.h"
> > +
> > +#include "reg_helper.h"
> > +
> > +#include "dce/dce_dmcu.h"
> > +#include "dce/dce_aux.h"
> > +#include "dce/dce_abm.h"
> > +#include "dce/dce_i2c.h"
> > +/* TODO remove this include */
> > +
> > +#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
> > +#include "gmc/gmc_6_0_d.h"
> > +#include "gmc/gmc_6_0_sh_mask.h"
> > +#endif
> > +
> > +#ifndef mmDP_DPHY_INTERNAL_CTRL
> > +#define mmDP_DPHY_INTERNAL_CTRL                         0x1CDE
> > +#define mmDP0_DP_DPHY_INTERNAL_CTRL                     0x1CDE
> > +#define mmDP1_DP_DPHY_INTERNAL_CTRL                     0x1FDE
> > +#define mmDP2_DP_DPHY_INTERNAL_CTRL                     0x42DE
> > +#define mmDP3_DP_DPHY_INTERNAL_CTRL                     0x45DE
> > +#define mmDP4_DP_DPHY_INTERNAL_CTRL                     0x48DE
> > +#define mmDP5_DP_DPHY_INTERNAL_CTRL                     0x4BDE
> > +#define mmDP6_DP_DPHY_INTERNAL_CTRL                     0x4EDE
>
> No SI part has 7 pipes. Let's drop mmDP6_DP_DPHY_INTERNAL_CTRL.
>
> > +#endif
> > +
> > +
> > +#ifndef mmBIOS_SCRATCH_2
> > +     #define mmBIOS_SCRATCH_2 0x05CB
> > +     #define mmBIOS_SCRATCH_6 0x05CF
> > +#endif
> > +
> > +#ifndef mmDP_DPHY_FAST_TRAINING
> > +     #define mmDP_DPHY_FAST_TRAINING                         0x1CCE
> > +     #define mmDP0_DP_DPHY_FAST_TRAINING                     0x1CCE
> > +     #define mmDP1_DP_DPHY_FAST_TRAINING                     0x1FCE
> > +     #define mmDP2_DP_DPHY_FAST_TRAINING                     0x42CE
> > +     #define mmDP3_DP_DPHY_FAST_TRAINING                     0x45CE
> > +     #define mmDP4_DP_DPHY_FAST_TRAINING                     0x48CE
> > +     #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4BCE
> > +     #define mmDP6_DP_DPHY_FAST_TRAINING                     0x4ECE
> > +#endif
> > +
>
> Drop mmDP6_DP_DPHY_FAST_TRAINING.
>
> Otherwise the registers above this line look right.
>
> > +
> > +#ifndef mmHPD_DC_HPD_CONTROL
> > +     #define mmHPD_DC_HPD_CONTROL                            0x189A
> > +     #define mmHPD0_DC_HPD_CONTROL                           0x189A
> > +     #define mmHPD1_DC_HPD_CONTROL                           0x18A2
> > +     #define mmHPD2_DC_HPD_CONTROL                           0x18AA
> > +     #define mmHPD3_DC_HPD_CONTROL                           0x18B2
> > +     #define mmHPD4_DC_HPD_CONTROL                           0x18BA
> > +     #define mmHPD5_DC_HPD_CONTROL                           0x18C2
> > +#endif
> > +
> > +#define DCE11_DIG_FE_CNTL 0x4a00
> > +#define DCE11_DIG_BE_CNTL 0x4a47
> > +#define DCE11_DP_SEC 0x4ac3
> > +
>
> These registers (from mmHPD_DC_HPD_CONTROL down to here) are unused and can all be dropped. We should also drop them in dce80_resource.c in a separate patch. I leave it up to you if you want to do it.
>
> > +static const struct dce110_timing_generator_offsets dce60_tg_offsets[] = {
> > +             {
> > +                     .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
> > +                     .dcp =  (mmGRPH_CONTROL - mmGRPH_CONTROL),
> > +                     .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
> > +                                     - mmDPG_WATERMARK_MASK_CONTROL),
> > +             },
> > +             {
> > +                     .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
> > +                     .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
> > +                     .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
> > +                                     - mmDPG_WATERMARK_MASK_CONTROL),
> > +             },
> > +             {
> > +                     .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
> > +                     .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
> > +                     .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
> > +                                     - mmDPG_WATERMARK_MASK_CONTROL),
> > +             },
> > +             {
> > +                     .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
> > +                     .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
> > +                     .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
> > +                                     - mmDPG_WATERMARK_MASK_CONTROL),
> > +             },
> > +             {
> > +                     .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
> > +                     .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
> > +                     .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
> > +                                     - mmDPG_WATERMARK_MASK_CONTROL),
> > +             },
> > +             {
> > +                     .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
> > +                     .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
> > +                     .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
> > +                                     - mmDPG_WATERMARK_MASK_CONTROL),
> > +             }
> > +};
> > +
> > +/* set register offset */
> > +#define SR(reg_name)\
> > +     .reg_name = mm ## reg_name
> > +
> > +/* set register offset with instance */
> > +#define SRI(reg_name, block, id)\
> > +     .reg_name = mm ## block ## id ## _ ## reg_name
> > +
> > +
> > +static const struct clk_mgr_registers disp_clk_regs = {
> > +             CLK_COMMON_REG_LIST_DCE_BASE()
> > +};
> > +
> > +static const struct clk_mgr_shift disp_clk_shift = {
> > +             CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
> > +};
> > +
> > +static const struct clk_mgr_mask disp_clk_mask = {
> > +             CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> > +};
> > +
> > +#define ipp_regs(id)\
> > +[id] = {\
> > +             IPP_COMMON_REG_LIST_DCE_BASE(id)\
> > +}
> > +
> > +static const struct dce_ipp_registers ipp_regs[] = {
> > +             ipp_regs(0),
> > +             ipp_regs(1),
> > +             ipp_regs(2),
> > +             ipp_regs(3),
> > +             ipp_regs(4),
> > +             ipp_regs(5)
> > +};
> > +
> > +static const struct dce_ipp_shift ipp_shift = {
> > +             IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
> > +};
> > +
> > +static const struct dce_ipp_mask ipp_mask = {
> > +             IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> > +};
> > +
> > +#define transform_regs(id)\
> > +[id] = {\
> > +             XFM_COMMON_REG_LIST_DCE80(id)\
> > +}
> > +
> > +static const struct dce_transform_registers xfm_regs[] = {
> > +             transform_regs(0),
> > +             transform_regs(1),
> > +             transform_regs(2),
> > +             transform_regs(3),
> > +             transform_regs(4),
> > +             transform_regs(5)
> > +};
> > +
> > +static const struct dce_transform_shift xfm_shift = {
> > +             XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
> > +};
> > +
> > +static const struct dce_transform_mask xfm_mask = {
> > +             XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
> > +};
> > +
> > +#define aux_regs(id)\
> > +[id] = {\
> > +     AUX_REG_LIST(id)\
> > +}
> > +
> > +static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
> > +     aux_regs(0),
> > +     aux_regs(1),
> > +     aux_regs(2),
> > +     aux_regs(3),
> > +     aux_regs(4),
> > +     aux_regs(5)
> > +};
> > +
> > +#define hpd_regs(id)\
> > +[id] = {\
> > +     HPD_REG_LIST(id)\
> > +}
> > +
> > +static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
> > +             hpd_regs(0),
> > +             hpd_regs(1),
> > +             hpd_regs(2),
> > +             hpd_regs(3),
> > +             hpd_regs(4),
> > +             hpd_regs(5)
> > +};
> > +

Is it correct that since the defines are unnecessary these all the
code from #define hpd_regs(id)\
to here can be removed?

Will it apply also to DCE8 separate cleaning patch?

> > +#define link_regs(id)\
> > +[id] = {\
> > +     LE_DCE80_REG_LIST(id)\
> > +}
> > +
> > +static const struct dce110_link_enc_registers link_enc_regs[] = {
> > +     link_regs(0),
> > +     link_regs(1),
> > +     link_regs(2),
> > +     link_regs(3),
> > +     link_regs(4),
> > +     link_regs(5),
> > +     link_regs(6),

May I drop link_regs(6) and the following stream_enc_regs(6)  i2c_inst_regs(6),
as they are all causing building errors on DCE6?

Thanks in advance for info
Mauro

> > +};
> > +
> > +#define stream_enc_regs(id)\
> > +[id] = {\
> > +     SE_COMMON_REG_LIST_DCE_BASE(id),\
> > +     .AFMT_CNTL = 0,\
> > +}
> > +
> > +static const struct dce110_stream_enc_registers stream_enc_regs[] = {
> > +     stream_enc_regs(0),
> > +     stream_enc_regs(1),
> > +     stream_enc_regs(2),
> > +     stream_enc_regs(3),
> > +     stream_enc_regs(4),
> > +     stream_enc_regs(5),
> > +     stream_enc_regs(6)
> > +};
> > +
> > +static const struct dce_stream_encoder_shift se_shift = {
> > +             SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
> > +};
> > +
> > +static const struct dce_stream_encoder_mask se_mask = {
> > +             SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
> > +};
> > +
> > +#define opp_regs(id)\
> > +[id] = {\
> > +     OPP_DCE_80_REG_LIST(id),\
> > +}
> > +
> > +static const struct dce_opp_registers opp_regs[] = {
> > +     opp_regs(0),
> > +     opp_regs(1),
> > +     opp_regs(2),
> > +     opp_regs(3),
> > +     opp_regs(4),
> > +     opp_regs(5)
> > +};
> > +
> > +static const struct dce_opp_shift opp_shift = {
> > +     OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
> > +};
> > +
> > +static const struct dce_opp_mask opp_mask = {
> > +     OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
> > +};
> > +
> > +#define aux_engine_regs(id)\
> > +[id] = {\
> > +     AUX_COMMON_REG_LIST(id), \
> > +     .AUX_RESET_MASK = 0 \
> > +}
> > +
> > +static const struct dce110_aux_registers aux_engine_regs[] = {
> > +             aux_engine_regs(0),
> > +             aux_engine_regs(1),
> > +             aux_engine_regs(2),
> > +             aux_engine_regs(3),
> > +             aux_engine_regs(4),
> > +             aux_engine_regs(5)
> > +};
> > +
> > +#define audio_regs(id)\
> > +[id] = {\
> > +     AUD_COMMON_REG_LIST(id)\
> > +}
> > +
> > +static const struct dce_audio_registers audio_regs[] = {
> > +     audio_regs(0),
> > +     audio_regs(1),
> > +     audio_regs(2),
> > +     audio_regs(3),
> > +     audio_regs(4),
> > +     audio_regs(5),
> > +     audio_regs(6),
>
> Only 6 audios on SI, so drop audio_regs(6).
>
> > +};
> > +
> > +static const struct dce_audio_shift audio_shift = {
> > +             AUD_COMMON_MASK_SH_LIST(__SHIFT)
> > +};
> > +
> > +static const struct dce_aduio_mask audio_mask = {
> > +             AUD_COMMON_MASK_SH_LIST(_MASK)
> > +};
> > +
> > +#define clk_src_regs(id)\
> > +[id] = {\
> > +     CS_COMMON_REG_LIST_DCE_80(id),\
> > +}
> > +
> > +
> > +static const struct dce110_clk_src_regs clk_src_regs[] = {
> > +     clk_src_regs(0),
> > +     clk_src_regs(1),
> > +     clk_src_regs(2)
> > +};
> > +
> > +static const struct dce110_clk_src_shift cs_shift = {
> > +             CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
> > +};
> > +
> > +static const struct dce110_clk_src_mask cs_mask = {
> > +             CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> > +};
> > +
> > +static const struct bios_registers bios_regs = {
> > +     .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
> > +};
> > +
> > +static const struct resource_caps res_cap = {
> > +             .num_timing_generator = 6,
> > +             .num_audio = 6,
> > +             .num_stream_encoder = 6,
> > +             .num_pll = 2,
> > +             .num_ddc = 6,
> > +};
> > +
> > +static const struct resource_caps res_cap_61 = {
> > +             .num_timing_generator = 4,
> > +             .num_audio = 6,
> > +             .num_stream_encoder = 6,
> > +             .num_pll = 2,
> > +             .num_ddc = 6,
> > +};
> > +
> > +static const struct resource_caps res_cap_64 = {
> > +             .num_timing_generator = 2,
> > +             .num_audio = 2,
> > +             .num_stream_encoder = 2,
> > +             .num_pll = 2,
> > +             .num_ddc = 2,
> > +};
> > +
> > +static const struct dce_dmcu_registers dmcu_regs = {
> > +             DMCU_DCE80_REG_LIST()
> > +};
> > +
> > +static const struct dce_dmcu_shift dmcu_shift = {
> > +             DMCU_MASK_SH_LIST_DCE80(__SHIFT)
> > +};
> > +
> > +static const struct dce_dmcu_mask dmcu_mask = {
> > +             DMCU_MASK_SH_LIST_DCE80(_MASK)
> > +};
> > +static const struct dce_abm_registers abm_regs = {
> > +             ABM_DCE110_COMMON_REG_LIST()
> > +};
> > +
> > +static const struct dce_abm_shift abm_shift = {
> > +             ABM_MASK_SH_LIST_DCE110(__SHIFT)
> > +};
> > +
> > +static const struct dce_abm_mask abm_mask = {
> > +             ABM_MASK_SH_LIST_DCE110(_MASK)
> > +};
> > +
> > +#define CTX  ctx
> > +#define REG(reg) mm ## reg
> > +
> > +#ifndef mmCC_DC_HDMI_STRAPS
> > +#define mmCC_DC_HDMI_STRAPS 0x1918
> > +#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
> > +#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
> > +#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
> > +#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
> > +#endif
> > +
>
> These registers defines are all good.
>
> > +static void read_dce_straps(
> > +     struct dc_context *ctx,
> > +     struct resource_straps *straps)
> > +{
> > +     REG_GET_2(CC_DC_HDMI_STRAPS,
> > +                     HDMI_DISABLE, &straps->hdmi_disable,
> > +                     AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
> > +
> > +     REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
> > +}
> > +
> > +static struct audio *create_audio(
> > +             struct dc_context *ctx, unsigned int inst)
> > +{
> > +     return dce_audio_create(ctx, inst,
> > +                     &audio_regs[inst], &audio_shift, &audio_mask);
> > +}
> > +
> > +static struct timing_generator *dce60_timing_generator_create(
> > +             struct dc_context *ctx,
> > +             uint32_t instance,
> > +             const struct dce110_timing_generator_offsets *offsets)
> > +{
> > +     struct dce110_timing_generator *tg110 =
> > +             kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
> > +
> > +     if (!tg110)
> > +             return NULL;
> > +
> > +     dce60_timing_generator_construct(tg110, ctx, instance, offsets);
> > +     return &tg110->base;
> > +}
> > +
> > +static struct output_pixel_processor *dce60_opp_create(
> > +     struct dc_context *ctx,
> > +     uint32_t inst)
> > +{
> > +     struct dce110_opp *opp =
> > +             kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
> > +
> > +     if (!opp)
> > +             return NULL;
> > +
> > +     dce110_opp_construct(opp,
> > +                          ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
> > +     return &opp->base;
> > +}
> > +
> > +struct aux_engine *dce60_aux_engine_create(
> > +     struct dc_context *ctx,
> > +     uint32_t inst)
> > +{
> > +     struct aux_engine_dce110 *aux_engine =
> > +             kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
> > +
> > +     if (!aux_engine)
> > +             return NULL;
> > +
> > +     dce110_aux_engine_construct(aux_engine, ctx, inst,
> > +                                 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
> > +                                 &aux_engine_regs[inst]);
> > +
> > +     return &aux_engine->base;
> > +}
> > +#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
> > +
> > +static const struct dce_i2c_registers i2c_hw_regs[] = {
> > +             i2c_inst_regs(1),
> > +             i2c_inst_regs(2),
> > +             i2c_inst_regs(3),
> > +             i2c_inst_regs(4),
> > +             i2c_inst_regs(5),
> > +             i2c_inst_regs(6),
> > +};
> > +
> > +static const struct dce_i2c_shift i2c_shifts = {
> > +             I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
> > +};
> > +
> > +static const struct dce_i2c_mask i2c_masks = {
> > +             I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> > +};
> > +
> > +struct dce_i2c_hw *dce60_i2c_hw_create(
> > +     struct dc_context *ctx,
> > +     uint32_t inst)
> > +{
> > +     struct dce_i2c_hw *dce_i2c_hw =
> > +             kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
> > +
> > +     if (!dce_i2c_hw)
> > +             return NULL;
> > +
> > +     dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
> > +                                 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
> > +
> > +     return dce_i2c_hw;
> > +}
> > +
> > +struct dce_i2c_sw *dce60_i2c_sw_create(
> > +     struct dc_context *ctx)
> > +{
> > +     struct dce_i2c_sw *dce_i2c_sw =
> > +             kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
> > +
> > +     if (!dce_i2c_sw)
> > +             return NULL;
> > +
> > +     dce_i2c_sw_construct(dce_i2c_sw, ctx);
> > +
> > +     return dce_i2c_sw;
> > +}
> > +static struct stream_encoder *dce60_stream_encoder_create(
> > +     enum engine_id eng_id,
> > +     struct dc_context *ctx)
> > +{
> > +     struct dce110_stream_encoder *enc110 =
> > +             kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
> > +
> > +     if (!enc110)
> > +             return NULL;
> > +
> > +     dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
> > +                                     &stream_enc_regs[eng_id],
> > +                                     &se_shift, &se_mask);
> > +     return &enc110->base;
> > +}
> > +
> > +#define SRII(reg_name, block, id)\
> > +     .reg_name[id] = mm ## block ## id ## _ ## reg_name
> > +
> > +static const struct dce_hwseq_registers hwseq_reg = {
> > +             HWSEQ_DCE8_REG_LIST()
> > +};
> > +
> > +static const struct dce_hwseq_shift hwseq_shift = {
> > +             HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
> > +};
> > +
> > +static const struct dce_hwseq_mask hwseq_mask = {
> > +             HWSEQ_DCE8_MASK_SH_LIST(_MASK)
> > +};
> > +
> > +static struct dce_hwseq *dce60_hwseq_create(
> > +     struct dc_context *ctx)
> > +{
> > +     struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
> > +
> > +     if (hws) {
> > +             hws->ctx = ctx;
> > +             hws->regs = &hwseq_reg;
> > +             hws->shifts = &hwseq_shift;
> > +             hws->masks = &hwseq_mask;
> > +     }
> > +     return hws;
> > +}
> > +
> > +static const struct resource_create_funcs res_create_funcs = {
> > +     .read_dce_straps = read_dce_straps,
> > +     .create_audio = create_audio,
> > +     .create_stream_encoder = dce60_stream_encoder_create,
> > +     .create_hwseq = dce60_hwseq_create,
> > +};
> > +
> > +#define mi_inst_regs(id) { \
> > +     MI_DCE8_REG_LIST(id), \
> > +     .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
> > +}
> > +static const struct dce_mem_input_registers mi_regs[] = {
> > +             mi_inst_regs(0),
> > +             mi_inst_regs(1),
> > +             mi_inst_regs(2),
> > +             mi_inst_regs(3),
> > +             mi_inst_regs(4),
> > +             mi_inst_regs(5),
> > +};
> > +
> > +static const struct dce_mem_input_shift mi_shifts = {
> > +             MI_DCE8_MASK_SH_LIST(__SHIFT),
> > +             .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
> > +};
> > +
> > +static const struct dce_mem_input_mask mi_masks = {
> > +             MI_DCE8_MASK_SH_LIST(_MASK),
> > +             .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
> > +};
> > +
> > +static struct mem_input *dce60_mem_input_create(
> > +     struct dc_context *ctx,
> > +     uint32_t inst)
> > +{
> > +     struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
> > +                                            GFP_KERNEL);
> > +
> > +     if (!dce_mi) {
> > +             BREAK_TO_DEBUGGER();
> > +             return NULL;
> > +     }
> > +
> > +     dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
> > +     dce_mi->wa.single_head_rdreq_dmif_limit = 2;
> > +     return &dce_mi->base;
> > +}
> > +
> > +static void dce60_transform_destroy(struct transform **xfm)
> > +{
> > +     kfree(TO_DCE_TRANSFORM(*xfm));
> > +     *xfm = NULL;
> > +}
> > +
> > +static struct transform *dce60_transform_create(
> > +     struct dc_context *ctx,
> > +     uint32_t inst)
> > +{
> > +     struct dce_transform *transform =
> > +             kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
> > +
> > +     if (!transform)
> > +             return NULL;
> > +
> > +     dce_transform_construct(transform, ctx, inst,
> > +                             &xfm_regs[inst], &xfm_shift, &xfm_mask);
> > +     transform->prescaler_on = false;
> > +     return &transform->base;
> > +}
> > +
> > +static const struct encoder_feature_support link_enc_feature = {
> > +             .max_hdmi_deep_color = COLOR_DEPTH_121212,
> > +             .max_hdmi_pixel_clock = 297000,
> > +             .flags.bits.IS_HBR2_CAPABLE = true,
> > +             .flags.bits.IS_TPS3_CAPABLE = true
> > +};
> > +
> > +struct link_encoder *dce60_link_encoder_create(
> > +     const struct encoder_init_data *enc_init_data)
> > +{
> > +     struct dce110_link_encoder *enc110 =
> > +             kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
> > +
> > +     if (!enc110)
> > +             return NULL;
> > +
> > +     dce110_link_encoder_construct(enc110,
> > +                                   enc_init_data,
> > +                                   &link_enc_feature,
> > +                                   &link_enc_regs[enc_init_data->transmitter],
> > +                                   &link_enc_aux_regs[enc_init_data->channel - 1],
> > +                                   &link_enc_hpd_regs[enc_init_data->hpd_source]);
> > +     return &enc110->base;
> > +}
> > +
> > +struct clock_source *dce60_clock_source_create(
> > +     struct dc_context *ctx,
> > +     struct dc_bios *bios,
> > +     enum clock_source_id id,
> > +     const struct dce110_clk_src_regs *regs,
> > +     bool dp_clk_src)
> > +{
> > +     struct dce110_clk_src *clk_src =
> > +             kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
> > +
> > +     if (!clk_src)
> > +             return NULL;
> > +
> > +     if (dce110_clk_src_construct(clk_src, ctx, bios, id,
> > +                     regs, &cs_shift, &cs_mask)) {
> > +             clk_src->base.dp_clk_src = dp_clk_src;
> > +             return &clk_src->base;
> > +     }
> > +
> > +     BREAK_TO_DEBUGGER();
> > +     return NULL;
> > +}
> > +
> > +void dce60_clock_source_destroy(struct clock_source **clk_src)
> > +{
> > +     kfree(TO_DCE110_CLK_SRC(*clk_src));
> > +     *clk_src = NULL;
> > +}
> > +
> > +static struct input_pixel_processor *dce60_ipp_create(
> > +     struct dc_context *ctx, uint32_t inst)
> > +{
> > +     struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
> > +
> > +     if (!ipp) {
> > +             BREAK_TO_DEBUGGER();
> > +             return NULL;
> > +     }
> > +
> > +     dce_ipp_construct(ipp, ctx, inst,
> > +                     &ipp_regs[inst], &ipp_shift, &ipp_mask);
> > +     return &ipp->base;
> > +}
> > +
> > +static void destruct(struct dce110_resource_pool *pool)
> > +{
> > +     unsigned int i;
> > +
> > +     for (i = 0; i < pool->base.pipe_count; i++) {
> > +             if (pool->base.opps[i] != NULL)
> > +                     dce110_opp_destroy(&pool->base.opps[i]);
> > +
> > +             if (pool->base.transforms[i] != NULL)
> > +                     dce60_transform_destroy(&pool->base.transforms[i]);
> > +
> > +             if (pool->base.ipps[i] != NULL)
> > +                     dce_ipp_destroy(&pool->base.ipps[i]);
> > +
> > +             if (pool->base.mis[i] != NULL) {
> > +                     kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
> > +                     pool->base.mis[i] = NULL;
> > +             }
> > +
> > +             if (pool->base.timing_generators[i] != NULL)    {
> > +                     kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
> > +                     pool->base.timing_generators[i] = NULL;
> > +             }
> > +     }
> > +
> > +     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
> > +             if (pool->base.engines[i] != NULL)
> > +                     dce110_engine_destroy(&pool->base.engines[i]);
> > +             if (pool->base.hw_i2cs[i] != NULL) {
> > +                     kfree(pool->base.hw_i2cs[i]);
> > +                     pool->base.hw_i2cs[i] = NULL;
> > +             }
> > +             if (pool->base.sw_i2cs[i] != NULL) {
> > +                     kfree(pool->base.sw_i2cs[i]);
> > +                     pool->base.sw_i2cs[i] = NULL;
> > +             }
> > +     }
> > +
> > +     for (i = 0; i < pool->base.stream_enc_count; i++) {
> > +             if (pool->base.stream_enc[i] != NULL)
> > +                     kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
> > +     }
> > +
> > +     for (i = 0; i < pool->base.clk_src_count; i++) {
> > +             if (pool->base.clock_sources[i] != NULL) {
> > +                     dce60_clock_source_destroy(&pool->base.clock_sources[i]);
> > +             }
> > +     }
> > +
> > +     if (pool->base.abm != NULL)
> > +                     dce_abm_destroy(&pool->base.abm);
> > +
> > +     if (pool->base.dmcu != NULL)
> > +                     dce_dmcu_destroy(&pool->base.dmcu);
> > +
> > +     if (pool->base.dp_clock_source != NULL)
> > +             dce60_clock_source_destroy(&pool->base.dp_clock_source);
> > +
> > +     for (i = 0; i < pool->base.audio_count; i++)    {
> > +             if (pool->base.audios[i] != NULL) {
> > +                     dce_aud_destroy(&pool->base.audios[i]);
> > +             }
> > +     }
> > +
> > +     if (pool->base.clk_mgr != NULL)
> > +             dce_clk_mgr_destroy(&pool->base.clk_mgr);
> > +
> > +     if (pool->base.irqs != NULL) {
> > +             dal_irq_service_destroy(&pool->base.irqs);
> > +     }
> > +}
> > +
> > +bool dce60_validate_bandwidth(
> > +     struct dc *dc,
> > +     struct dc_state *context)
> > +{
> > +     /* TODO implement when needed but for now hardcode max value*/
> > +     context->bw.dce.dispclk_khz = 681000;
> > +     context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
> > +
>
> Not sure where to find the actual values but this should be okay for now.
>
> > +     return true;
> > +}
> > +
> > +static bool dce60_validate_surface_sets(
> > +             struct dc_state *context)
> > +{
> > +     int i;
> > +
> > +     for (i = 0; i < context->stream_count; i++) {
> > +             if (context->stream_status[i].plane_count == 0)
> > +                     continue;
> > +
> > +             if (context->stream_status[i].plane_count > 1)
> > +                     return false;
> > +
> > +             if (context->stream_status[i].plane_states[0]->format
> > +                             >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
> > +                     return false;
> > +     }
> > +
> > +     return true;
> > +}
> > +
> > +enum dc_status dce60_validate_global(
> > +             struct dc *dc,
> > +             struct dc_state *context)
> > +{
> > +     if (!dce60_validate_surface_sets(context))
> > +             return DC_FAIL_SURFACE_VALIDATE;
> > +
> > +     return DC_OK;
> > +}
> > +
> > +static void dce60_destroy_resource_pool(struct resource_pool **pool)
> > +{
> > +     struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
> > +
> > +     destruct(dce110_pool);
> > +     kfree(dce110_pool);
> > +     *pool = NULL;
> > +}
> > +
> > +static const struct resource_funcs dce60_res_pool_funcs = {
> > +     .destroy = dce60_destroy_resource_pool,
> > +     .link_enc_create = dce60_link_encoder_create,
> > +     .validate_bandwidth = dce60_validate_bandwidth,
> > +     .validate_plane = dce100_validate_plane,
> > +     .add_stream_to_ctx = dce100_add_stream_to_ctx,
> > +     .validate_global = dce60_validate_global
> > +};
> > +
> > +static bool dce60_construct(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc,
> > +     struct dce110_resource_pool *pool)
> > +{
> > +     unsigned int i;
> > +     struct dc_context *ctx = dc->ctx;
> > +     struct dc_firmware_info info;
> > +     struct dc_bios *bp;
> > +
> > +     ctx->dc_bios->regs = &bios_regs;
> > +
> > +     pool->base.res_cap = &res_cap;
> > +     pool->base.funcs = &dce60_res_pool_funcs;
> > +
> > +
> > +     /*************************************************
> > +      *  Resource + asic cap harcoding                *
> > +      *************************************************/
> > +     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
> > +     pool->base.pipe_count = res_cap.num_timing_generator;
> > +     pool->base.timing_generator_count = res_cap.num_timing_generator;
> > +     dc->caps.max_downscale_ratio = 200;
> > +     dc->caps.i2c_speed_in_khz = 40;
> > +     dc->caps.max_cursor_size = 128;
> > +     dc->caps.dual_link_dvi = true;
> > +
> > +     /*************************************************
> > +      *  Create resources                             *
> > +      *************************************************/
> > +
> > +     bp = ctx->dc_bios;
> > +
> > +     if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
> > +             info.external_clock_source_frequency_for_dp != 0) {
> > +             pool->base.dp_clock_source =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
> > +
> > +             pool->base.clock_sources[0] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
> > +             pool->base.clock_sources[1] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
> > +             pool->base.clock_sources[2] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
> > +             pool->base.clk_src_count = 3;
> > +
> > +     } else {
> > +             pool->base.dp_clock_source =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
> > +
> > +             pool->base.clock_sources[0] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
> > +             pool->base.clock_sources[1] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
> > +             pool->base.clk_src_count = 2;
> > +     }
> > +
> > +     if (pool->base.dp_clock_source == NULL) {
> > +             dm_error("DC: failed to create dp clock source!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     for (i = 0; i < pool->base.clk_src_count; i++) {
> > +             if (pool->base.clock_sources[i] == NULL) {
> > +                     dm_error("DC: failed to create clock sources!\n");
> > +                     BREAK_TO_DEBUGGER();
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     pool->base.clk_mgr = dce_clk_mgr_create(ctx,
> > +                     &disp_clk_regs,
> > +                     &disp_clk_shift,
> > +                     &disp_clk_mask);
> > +     if (pool->base.clk_mgr == NULL) {
> > +             dm_error("DC: failed to create display clock!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     pool->base.dmcu = dce_dmcu_create(ctx,
> > +                     &dmcu_regs,
> > +                     &dmcu_shift,
> > +                     &dmcu_mask);
> > +     if (pool->base.dmcu == NULL) {
> > +             dm_error("DC: failed to create dmcu!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     pool->base.abm = dce_abm_create(ctx,
> > +                     &abm_regs,
> > +                     &abm_shift,
> > +                     &abm_mask);
> > +     if (pool->base.abm == NULL) {
> > +             dm_error("DC: failed to create abm!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     {
> > +             struct irq_service_init_data init_data;
> > +             init_data.ctx = dc->ctx;
> > +             pool->base.irqs = dal_irq_service_dce60_create(&init_data);
> > +             if (!pool->base.irqs)
> > +                     goto res_create_fail;
> > +     }
> > +
> > +     for (i = 0; i < pool->base.pipe_count; i++) {
> > +             pool->base.timing_generators[i] = dce60_timing_generator_create(
> > +                             ctx, i, &dce60_tg_offsets[i]);
> > +             if (pool->base.timing_generators[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create tg!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.mis[i] = dce60_mem_input_create(ctx, i);
> > +             if (pool->base.mis[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create memory input!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.ipps[i] = dce60_ipp_create(ctx, i);
> > +             if (pool->base.ipps[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create input pixel processor!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.transforms[i] = dce60_transform_create(ctx, i);
> > +             if (pool->base.transforms[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create transform!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.opps[i] = dce60_opp_create(ctx, i);
> > +             if (pool->base.opps[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create output pixel processor!\n");
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
> > +             pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
> > +             if (pool->base.engines[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create aux engine!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +             pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
> > +             if (pool->base.hw_i2cs[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create i2c engine!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +             pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
> > +             if (pool->base.sw_i2cs[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create sw i2c!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     dc->caps.max_planes =  pool->base.pipe_count;
> > +     dc->caps.disable_dp_clk_share = true;
> > +
> > +     if (!resource_construct(num_virtual_links, dc, &pool->base,
> > +                     &res_create_funcs))
> > +             goto res_create_fail;
> > +
> > +     /* Create hardware sequencer */
> > +     dce60_hw_sequencer_construct(dc);
> > +
> > +     return true;
> > +
> > +res_create_fail:
> > +     destruct(pool);
> > +     return false;
> > +}
> > +
> > +struct resource_pool *dce60_create_resource_pool(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc)
> > +{
> > +     struct dce110_resource_pool *pool =
> > +             kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
> > +
> > +     if (!pool)
> > +             return NULL;
> > +
> > +     if (dce60_construct(num_virtual_links, dc, pool))
> > +             return &pool->base;
> > +
> > +     BREAK_TO_DEBUGGER();
> > +     return NULL;
> > +}
> > +
> > +static bool dce61_construct(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc,
> > +     struct dce110_resource_pool *pool)
> > +{
> > +     unsigned int i;
> > +     struct dc_context *ctx = dc->ctx;
> > +     struct dc_firmware_info info;
> > +     struct dc_bios *bp;
> > +
> > +     ctx->dc_bios->regs = &bios_regs;
> > +
> > +     pool->base.res_cap = &res_cap_61;
> > +     pool->base.funcs = &dce60_res_pool_funcs;
> > +
> > +
> > +     /*************************************************
> > +      *  Resource + asic cap harcoding                *
> > +      *************************************************/
> > +     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
> > +     pool->base.pipe_count = res_cap_61.num_timing_generator;
> > +     pool->base.timing_generator_count = res_cap_61.num_timing_generator;
> > +     dc->caps.max_downscale_ratio = 200;
> > +     dc->caps.i2c_speed_in_khz = 40;
> > +     dc->caps.max_cursor_size = 128;
> > +     dc->caps.is_apu = true;
> > +
> > +     /*************************************************
> > +      *  Create resources                             *
> > +      *************************************************/
> > +
> > +     bp = ctx->dc_bios;
> > +
> > +     if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
> > +             info.external_clock_source_frequency_for_dp != 0) {
> > +             pool->base.dp_clock_source =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
> > +
> > +             pool->base.clock_sources[0] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
> > +             pool->base.clock_sources[1] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
> > +             pool->base.clock_sources[2] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
> > +             pool->base.clk_src_count = 3;
> > +
> > +     } else {
> > +             pool->base.dp_clock_source =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
> > +
> > +             pool->base.clock_sources[0] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
> > +             pool->base.clock_sources[1] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
> > +             pool->base.clk_src_count = 2;
> > +     }
> > +
> > +     if (pool->base.dp_clock_source == NULL) {
> > +             dm_error("DC: failed to create dp clock source!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     for (i = 0; i < pool->base.clk_src_count; i++) {
> > +             if (pool->base.clock_sources[i] == NULL) {
> > +                     dm_error("DC: failed to create clock sources!\n");
> > +                     BREAK_TO_DEBUGGER();
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     pool->base.clk_mgr = dce_clk_mgr_create(ctx,
> > +                     &disp_clk_regs,
> > +                     &disp_clk_shift,
> > +                     &disp_clk_mask);
> > +     if (pool->base.clk_mgr == NULL) {
> > +             dm_error("DC: failed to create display clock!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     pool->base.dmcu = dce_dmcu_create(ctx,
> > +                     &dmcu_regs,
> > +                     &dmcu_shift,
> > +                     &dmcu_mask);
> > +     if (pool->base.dmcu == NULL) {
> > +             dm_error("DC: failed to create dmcu!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     pool->base.abm = dce_abm_create(ctx,
> > +                     &abm_regs,
> > +                     &abm_shift,
> > +                     &abm_mask);
> > +     if (pool->base.abm == NULL) {
> > +             dm_error("DC: failed to create abm!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     {
> > +             struct irq_service_init_data init_data;
> > +             init_data.ctx = dc->ctx;
> > +             pool->base.irqs = dal_irq_service_dce60_create(&init_data);
> > +             if (!pool->base.irqs)
> > +                     goto res_create_fail;
> > +     }
> > +
> > +     for (i = 0; i < pool->base.pipe_count; i++) {
> > +             pool->base.timing_generators[i] = dce60_timing_generator_create(
> > +                             ctx, i, &dce60_tg_offsets[i]);
> > +             if (pool->base.timing_generators[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create tg!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.mis[i] = dce60_mem_input_create(ctx, i);
> > +             if (pool->base.mis[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create memory input!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.ipps[i] = dce60_ipp_create(ctx, i);
> > +             if (pool->base.ipps[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create input pixel processor!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.transforms[i] = dce60_transform_create(ctx, i);
> > +             if (pool->base.transforms[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create transform!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.opps[i] = dce60_opp_create(ctx, i);
> > +             if (pool->base.opps[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create output pixel processor!\n");
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
> > +             pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
> > +             if (pool->base.engines[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create aux engine!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +             pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
> > +             if (pool->base.hw_i2cs[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create i2c engine!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +             pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
> > +             if (pool->base.sw_i2cs[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create sw i2c!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     dc->caps.max_planes =  pool->base.pipe_count;
> > +     dc->caps.disable_dp_clk_share = true;
> > +
> > +     if (!resource_construct(num_virtual_links, dc, &pool->base,
> > +                     &res_create_funcs))
> > +             goto res_create_fail;
> > +
> > +     /* Create hardware sequencer */
> > +     dce60_hw_sequencer_construct(dc);
> > +
> > +     return true;
> > +
> > +res_create_fail:
> > +     destruct(pool);
> > +     return false;
> > +}
> > +
> > +struct resource_pool *dce61_create_resource_pool(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc)
> > +{
> > +     struct dce110_resource_pool *pool =
> > +             kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
> > +
> > +     if (!pool)
> > +             return NULL;
> > +
> > +     if (dce61_construct(num_virtual_links, dc, pool))
> > +             return &pool->base;
> > +
> > +     BREAK_TO_DEBUGGER();
> > +     return NULL;
> > +}
> > +
> > +static bool dce64_construct(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc,
> > +     struct dce110_resource_pool *pool)
> > +{
> > +     unsigned int i;
> > +     struct dc_context *ctx = dc->ctx;
> > +     struct dc_firmware_info info;
> > +     struct dc_bios *bp;
> > +
> > +     ctx->dc_bios->regs = &bios_regs;
> > +
> > +     pool->base.res_cap = &res_cap_64;
> > +     pool->base.funcs = &dce60_res_pool_funcs;
> > +
> > +
> > +     /*************************************************
> > +      *  Resource + asic cap harcoding                *
> > +      *************************************************/
> > +     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
> > +     pool->base.pipe_count = res_cap_64.num_timing_generator;
> > +     pool->base.timing_generator_count = res_cap_64.num_timing_generator;
> > +     dc->caps.max_downscale_ratio = 200;
> > +     dc->caps.i2c_speed_in_khz = 40;
> > +     dc->caps.max_cursor_size = 128;
> > +     dc->caps.is_apu = true;
> > +
> > +     /*************************************************
> > +      *  Create resources                             *
> > +      *************************************************/
> > +
> > +     bp = ctx->dc_bios;
> > +
> > +     if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
> > +             info.external_clock_source_frequency_for_dp != 0) {
> > +             pool->base.dp_clock_source =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
> > +
> > +             pool->base.clock_sources[0] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
> > +             pool->base.clock_sources[1] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
> > +             pool->base.clk_src_count = 2;
> > +
> > +     } else {
> > +             pool->base.dp_clock_source =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
> > +
> > +             pool->base.clock_sources[0] =
> > +                             dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
> > +             pool->base.clk_src_count = 1;
> > +     }
> > +
> > +     if (pool->base.dp_clock_source == NULL) {
> > +             dm_error("DC: failed to create dp clock source!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     for (i = 0; i < pool->base.clk_src_count; i++) {
> > +             if (pool->base.clock_sources[i] == NULL) {
> > +                     dm_error("DC: failed to create clock sources!\n");
> > +                     BREAK_TO_DEBUGGER();
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     pool->base.clk_mgr = dce_clk_mgr_create(ctx,
> > +                     &disp_clk_regs,
> > +                     &disp_clk_shift,
> > +                     &disp_clk_mask);
> > +     if (pool->base.clk_mgr == NULL) {
> > +             dm_error("DC: failed to create display clock!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     pool->base.dmcu = dce_dmcu_create(ctx,
> > +                     &dmcu_regs,
> > +                     &dmcu_shift,
> > +                     &dmcu_mask);
> > +     if (pool->base.dmcu == NULL) {
> > +             dm_error("DC: failed to create dmcu!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     pool->base.abm = dce_abm_create(ctx,
> > +                     &abm_regs,
> > +                     &abm_shift,
> > +                     &abm_mask);
> > +     if (pool->base.abm == NULL) {
> > +             dm_error("DC: failed to create abm!\n");
> > +             BREAK_TO_DEBUGGER();
> > +             goto res_create_fail;
> > +     }
> > +
> > +     {
> > +             struct irq_service_init_data init_data;
> > +             init_data.ctx = dc->ctx;
> > +             pool->base.irqs = dal_irq_service_dce60_create(&init_data);
> > +             if (!pool->base.irqs)
> > +                     goto res_create_fail;
> > +     }
> > +
> > +     for (i = 0; i < pool->base.pipe_count; i++) {
> > +             pool->base.timing_generators[i] = dce60_timing_generator_create(
> > +                             ctx, i, &dce60_tg_offsets[i]);
> > +             if (pool->base.timing_generators[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create tg!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.mis[i] = dce60_mem_input_create(ctx, i);
> > +             if (pool->base.mis[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create memory input!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.ipps[i] = dce60_ipp_create(ctx, i);
> > +             if (pool->base.ipps[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create input pixel processor!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.transforms[i] = dce60_transform_create(ctx, i);
> > +             if (pool->base.transforms[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create transform!\n");
> > +                     goto res_create_fail;
> > +             }
> > +
> > +             pool->base.opps[i] = dce60_opp_create(ctx, i);
> > +             if (pool->base.opps[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error("DC: failed to create output pixel processor!\n");
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
> > +             pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
> > +             if (pool->base.engines[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create aux engine!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +             pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
> > +             if (pool->base.hw_i2cs[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create i2c engine!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +             pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
> > +             if (pool->base.sw_i2cs[i] == NULL) {
> > +                     BREAK_TO_DEBUGGER();
> > +                     dm_error(
> > +                             "DC:failed to create sw i2c!!\n");
> > +                     goto res_create_fail;
> > +             }
> > +     }
> > +
> > +     dc->caps.max_planes =  pool->base.pipe_count;
> > +     dc->caps.disable_dp_clk_share = true;
> > +
> > +     if (!resource_construct(num_virtual_links, dc, &pool->base,
> > +                     &res_create_funcs))
> > +             goto res_create_fail;
> > +
> > +     /* Create hardware sequencer */
> > +     dce60_hw_sequencer_construct(dc);
> > +
> > +     return true;
> > +
> > +res_create_fail:
> > +     destruct(pool);
> > +     return false;
> > +}
> > +
> > +struct resource_pool *dce64_create_resource_pool(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc)
> > +{
> > +     struct dce110_resource_pool *pool =
> > +             kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
> > +
> > +     if (!pool)
> > +             return NULL;
> > +
> > +     if (dce64_construct(num_virtual_links, dc, pool))
> > +             return &pool->base;
> > +
> > +     BREAK_TO_DEBUGGER();
> > +     return NULL;
> > +}
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
> > new file mode 100644
> > index 000000000000..b30e4e4ed7c0
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
> > @@ -0,0 +1,47 @@
> > +/*
> > +* Copyright 2012-15 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> > + *
> > + */
> > +
> > +#ifndef __DC_RESOURCE_DCE60_H__
> > +#define __DC_RESOURCE_DCE60_H__
> > +
> > +#include "core_types.h"
> > +
> > +struct dc;
> > +struct resource_pool;
> > +
> > +struct resource_pool *dce60_create_resource_pool(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc);
> > +
> > +struct resource_pool *dce61_create_resource_pool(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc);
> > +
> > +struct resource_pool *dce64_create_resource_pool(
> > +     uint8_t num_virtual_links,
> > +     struct dc *dc);
> > +
> > +#endif /* __DC_RESOURCE_DCE60_H__ */
> > +
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
> > new file mode 100644
> > index 000000000000..90b610367af8
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
> > @@ -0,0 +1,242 @@
> > +/*
> > + * Copyright 2012-15 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> > + *
> > + */
> > +
> > +#include "dm_services.h"
> > +
> > +/* include DCE6 register header files */
> > +#include "dce/dce_6_0_d.h"
> > +#include "dce/dce_6_0_sh_mask.h"
> > +
> > +#include "dc_types.h"
> > +
> > +#include "include/grph_object_id.h"
> > +#include "include/logger_interface.h"
> > +#include "../dce110/dce110_timing_generator.h"
> > +#include "dce60_timing_generator.h"
> > +
> > +#include "timing_generator.h"
> > +
> > +enum black_color_format {
> > +     BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,   /* used as index in array */
> > +     BLACK_COLOR_FORMAT_RGB_LIMITED,
> > +     BLACK_COLOR_FORMAT_YUV_TV,
> > +     BLACK_COLOR_FORMAT_YUV_CV,
> > +     BLACK_COLOR_FORMAT_YUV_SUPER_AA,
> > +
> > +     BLACK_COLOR_FORMAT_COUNT
> > +};
> > +
> > +static const struct dce110_timing_generator_offsets reg_offsets[] = {
> > +{
> > +     .crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> > +     .dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> > +     .dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> > +     .dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> > +     .dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> > +     .dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> > +},
> > +{
> > +     .crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
> > +     .dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
> > +}
> > +};
> > +
> > +#define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
> > +
> > +#define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
> > +#define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
> > +
> > +#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
> > +#define DCP_REG(reg) (reg + tg110->offsets.dcp)
> > +#define DMIF_REG(reg) (reg + tg110->offsets.dmif)
> > +
> > +static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
> > +{
> > +     uint64_t pix_dur;
> > +     uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
> > +                                     + DCE110TG_FROM_TG(tg)->offsets.dmif;
> > +     uint32_t value = dm_read_reg(tg->ctx, addr);
> > +
> > +     if (pix_clk_khz == 0)
> > +             return;
> > +
> > +     pix_dur = 1000000000 / pix_clk_khz;
> > +
> > +     set_reg_field_value(
> > +             value,
> > +             pix_dur,
> > +             DPG_PIPE_ARBITRATION_CONTROL1,
> > +             PIXEL_DURATION);
> > +
> > +     dm_write_reg(tg->ctx, addr, value);
> > +}
> > +
> > +static void program_timing(struct timing_generator *tg,
> > +     const struct dc_crtc_timing *timing,
> > +     bool use_vbios)
> > +{
> > +     if (!use_vbios)
> > +             program_pix_dur(tg, timing->pix_clk_khz);
> > +
> > +     dce110_tg_program_timing(tg, timing, use_vbios);
> > +}
> > +
> > +static void dce60_timing_generator_enable_advanced_request(
> > +     struct timing_generator *tg,
> > +     bool enable,
> > +     const struct dc_crtc_timing *timing)
> > +{
> > +     struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
> > +     uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
> > +     uint32_t value = dm_read_reg(tg->ctx, addr);
> > +
> > +     if (enable) {
> > +             set_reg_field_value(
> > +                     value,
> > +                     0,
> > +                     CRTC_START_LINE_CONTROL,
> > +                     CRTC_LEGACY_REQUESTOR_EN);
> > +     } else {
> > +             set_reg_field_value(
> > +                     value,
> > +                     1,
> > +                     CRTC_START_LINE_CONTROL,
> > +                     CRTC_LEGACY_REQUESTOR_EN);
> > +     }
> > +
> > +     if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
> > +             set_reg_field_value(
> > +                     value,
> > +                     3,
> > +                     CRTC_START_LINE_CONTROL,
> > +                     CRTC_ADVANCED_START_LINE_POSITION);
> > +             set_reg_field_value(
> > +                     value,
> > +                     0,
> > +                     CRTC_START_LINE_CONTROL,
> > +                     CRTC_PREFETCH_EN);
> > +     } else {
> > +             set_reg_field_value(
> > +                     value,
> > +                     4,
> > +                     CRTC_START_LINE_CONTROL,
> > +                     CRTC_ADVANCED_START_LINE_POSITION);
> > +             set_reg_field_value(
> > +                     value,
> > +                     1,
> > +                     CRTC_START_LINE_CONTROL,
> > +                     CRTC_PREFETCH_EN);
> > +     }
> > +
> > +     set_reg_field_value(
> > +             value,
> > +             1,
> > +             CRTC_START_LINE_CONTROL,
> > +             CRTC_PROGRESSIVE_START_LINE_EARLY);
> > +
> > +     set_reg_field_value(
> > +             value,
> > +             1,
> > +             CRTC_START_LINE_CONTROL,
> > +             CRTC_INTERLACE_START_LINE_EARLY);
> > +
> > +     dm_write_reg(tg->ctx, addr, value);
> > +}
> > +
> > +static const struct timing_generator_funcs dce60_tg_funcs = {
> > +             .validate_timing = dce110_tg_validate_timing,
> > +             .program_timing = program_timing,
> > +             .enable_crtc = dce110_timing_generator_enable_crtc,
> > +             .disable_crtc = dce110_timing_generator_disable_crtc,
> > +             .is_counter_moving = dce110_timing_generator_is_counter_moving,
> > +             .get_position = dce110_timing_generator_get_position,
> > +             .get_frame_count = dce110_timing_generator_get_vblank_counter,
> > +             .get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
> > +             .set_early_control = dce110_timing_generator_set_early_control,
> > +             .wait_for_state = dce110_tg_wait_for_state,
> > +             .set_blank = dce110_tg_set_blank,
> > +             .is_blanked = dce110_tg_is_blanked,
> > +             .set_colors = dce110_tg_set_colors,
> > +             .set_overscan_blank_color =
> > +                             dce110_timing_generator_set_overscan_color_black,
> > +             .set_blank_color = dce110_timing_generator_program_blank_color,
> > +             .disable_vga = dce110_timing_generator_disable_vga,
> > +             .did_triggered_reset_occur =
> > +                             dce110_timing_generator_did_triggered_reset_occur,
> > +             .setup_global_swap_lock =
> > +                             dce110_timing_generator_setup_global_swap_lock,
> > +             .enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
> > +             .disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
> > +             .tear_down_global_swap_lock =
> > +                             dce110_timing_generator_tear_down_global_swap_lock,
> > +             .set_drr = dce110_timing_generator_set_drr,
> > +             .set_static_screen_control =
> > +                     dce110_timing_generator_set_static_screen_control,
> > +             .set_test_pattern = dce110_timing_generator_set_test_pattern,
> > +             .arm_vert_intr = dce110_arm_vert_intr,
> > +
> > +             /* DCE6.0 overrides */
> > +             .enable_advanced_request =
> > +                             dce60_timing_generator_enable_advanced_request,
>
> Drop the dce60 function and use the dce80 version. You can expose that through the dce80_timing_generator.h and include that here.
>
> > +             .configure_crc = dce110_configure_crc,
> > +             .get_crc = dce110_get_crc,
> > +};
> > +
> > +void dce60_timing_generator_construct(
> > +     struct dce110_timing_generator *tg110,
> > +     struct dc_context *ctx,
> > +     uint32_t instance,
> > +     const struct dce110_timing_generator_offsets *offsets)
> > +{
> > +     tg110->controller_id = CONTROLLER_ID_D0 + instance;
> > +     tg110->base.inst = instance;
> > +     tg110->offsets = *offsets;
> > +     tg110->derived_offsets = reg_offsets[instance];
> > +
> > +     tg110->base.funcs = &dce60_tg_funcs;
> > +
> > +     tg110->base.ctx = ctx;
> > +     tg110->base.bp = ctx->dc_bios;
> > +
> > +     tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
> > +     tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
> > +
> > +     tg110->min_h_blank = 56;
> > +     tg110->min_h_front_porch = 4;
> > +     tg110->min_h_back_porch = 4;
> > +}
> > +
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
> > new file mode 100644
> > index 000000000000..8972cd0d5815
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
> > @@ -0,0 +1,39 @@
> > +/*
> > + * Copyright 2012-15 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + *  and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> > + *
> > + */
> > +
> > +#ifndef __DC_TIMING_GENERATOR_DCE60_H__
> > +#define __DC_TIMING_GENERATOR_DCE60_H__
> > +
> > +#include "timing_generator.h"
> > +#include "../include/grph_object_id.h"
> > +
> > +/* DCE6.0 implementation inherits from DCE11.0 */
> > +void dce60_timing_generator_construct(
> > +     struct dce110_timing_generator *tg,
> > +     struct dc_context *ctx,
> > +     uint32_t instance,
> > +     const struct dce110_timing_generator_offsets *offsets);
> > +
> > +#endif /* __DC_TIMING_GENERATOR_DCE60_H__ */
> > diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
> > index abe05bc80752..5492c6b98525 100644
> > --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
> > +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
> > @@ -2264,6 +2264,10 @@
> >  #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x00000010
> >  #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000100L
> >  #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x00000008
> > +#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100000
> > +#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x14
> > +#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000
> > +#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x1c
> >  #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
> >  #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x00000000
> >  #define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
> >
>
> Would prefer the update to the register headers to be in a separate patch.
>
> Harry
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[PATCH v2 03/10] drm/amd/display: dc/core: add DCE6 support

[Mauro Rossi]

DCE6 targets are added as branching of existing DCE8 implementation.
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index a5eb80aa3dd9..07bd4f72acc5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -37,6 +37,9 @@
 #include "virtual/virtual_stream_encoder.h"
 #include "dpcd_defs.h"
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/dce60_resource.h"
+#endif
 #include "dce80/dce80_resource.h"
 #include "dce100/dce100_resource.h"
 #include "dce110/dce110_resource.h"
@@ -53,6 +56,18 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
 	enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 	switch (asic_id.chip_family) {
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+	case FAMILY_SI:
+		if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
+		    ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
+		    ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
+		dc_version = DCE_VERSION_6_0;
+		else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
+			dc_version = DCE_VERSION_6_4;
+		else
+			dc_version = DCE_VERSION_6_1;
+		break;
+#endif
 	case FAMILY_CI:
 		dc_version = DCE_VERSION_8_0;
 		break;
@@ -110,6 +125,20 @@ struct resource_pool *dc_create_resource_pool(
 	struct resource_pool *res_pool = NULL;
 
 	switch (dc_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+	case DCE_VERSION_6_0:
+		res_pool = dce60_create_resource_pool(
+			num_virtual_links, dc);
+		break;
+	case DCE_VERSION_6_1:
+		res_pool = dce61_create_resource_pool(
+			num_virtual_links, dc);
+		break;
+	case DCE_VERSION_6_4:
+		res_pool = dce64_create_resource_pool(
+			num_virtual_links, dc);
+		break;
+#endif
 	case DCE_VERSION_8_0:
 		res_pool = dce80_create_resource_pool(
 			num_virtual_links, dc);
-- 
2.17.1

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Re: [PATCH v2 03/10] drm/amd/display: dc/core: add DCE6 support

[Wentland, Harry]

On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> DCE6 targets are added as branching of existing DCE8 implementation.

All your parents require a Signed-off-by. See https://www.kernel.org/doc/html/v4.17/process/submitting-patches.html#developer-s-certificate-of-origin-1-1

Harry

> ---
>  .../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> index a5eb80aa3dd9..07bd4f72acc5 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> @@ -37,6 +37,9 @@
>  #include "virtual/virtual_stream_encoder.h"
>  #include "dpcd_defs.h"
>  
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> +#include "dce60/dce60_resource.h"
> +#endif
>  #include "dce80/dce80_resource.h"
>  #include "dce100/dce100_resource.h"
>  #include "dce110/dce110_resource.h"
> @@ -53,6 +56,18 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
>  	enum dce_version dc_version = DCE_VERSION_UNKNOWN;
>  	switch (asic_id.chip_family) {
>  
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> +	case FAMILY_SI:
> +		if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
> +		    ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
> +		    ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
> +		dc_version = DCE_VERSION_6_0;
> +		else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
> +			dc_version = DCE_VERSION_6_4;
> +		else
> +			dc_version = DCE_VERSION_6_1;
> +		break;
> +#endif
>  	case FAMILY_CI:
>  		dc_version = DCE_VERSION_8_0;
>  		break;
> @@ -110,6 +125,20 @@ struct resource_pool *dc_create_resource_pool(
>  	struct resource_pool *res_pool = NULL;
>  
>  	switch (dc_version) {
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> +	case DCE_VERSION_6_0:
> +		res_pool = dce60_create_resource_pool(
> +			num_virtual_links, dc);
> +		break;
> +	case DCE_VERSION_6_1:
> +		res_pool = dce61_create_resource_pool(
> +			num_virtual_links, dc);
> +		break;
> +	case DCE_VERSION_6_4:
> +		res_pool = dce64_create_resource_pool(
> +			num_virtual_links, dc);
> +		break;
> +#endif
>  	case DCE_VERSION_8_0:
>  		res_pool = dce80_create_resource_pool(
>  			num_virtual_links, dc);
> 
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Re: [PATCH v2 03/10] drm/amd/display: dc/core: add DCE6 support

[Wentland, Harry]

On 2018-10-17 3:50 p.m., Wentland, Harry wrote:
> On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
>> DCE6 targets are added as branching of existing DCE8 implementation.
> 
> All your parents require a Signed-off-by. See https://www.kernel.org/doc/html/v4.17/process/submitting-patches.html#developer-s-certificate-of-origin-1-1

s/parents/patches

Harry

> 
> Harry
> 
>> ---
>>  .../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++++++++++++++++++
>>  1 file changed, 29 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> index a5eb80aa3dd9..07bd4f72acc5 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> @@ -37,6 +37,9 @@
>>  #include "virtual/virtual_stream_encoder.h"
>>  #include "dpcd_defs.h"
>>  
>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>> +#include "dce60/dce60_resource.h"
>> +#endif
>>  #include "dce80/dce80_resource.h"
>>  #include "dce100/dce100_resource.h"
>>  #include "dce110/dce110_resource.h"
>> @@ -53,6 +56,18 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
>>  	enum dce_version dc_version = DCE_VERSION_UNKNOWN;
>>  	switch (asic_id.chip_family) {
>>  
>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>> +	case FAMILY_SI:
>> +		if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
>> +		    ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
>> +		    ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
>> +		dc_version = DCE_VERSION_6_0;
>> +		else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
>> +			dc_version = DCE_VERSION_6_4;
>> +		else
>> +			dc_version = DCE_VERSION_6_1;
>> +		break;
>> +#endif
>>  	case FAMILY_CI:
>>  		dc_version = DCE_VERSION_8_0;
>>  		break;
>> @@ -110,6 +125,20 @@ struct resource_pool *dc_create_resource_pool(
>>  	struct resource_pool *res_pool = NULL;
>>  
>>  	switch (dc_version) {
>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>> +	case DCE_VERSION_6_0:
>> +		res_pool = dce60_create_resource_pool(
>> +			num_virtual_links, dc);
>> +		break;
>> +	case DCE_VERSION_6_1:
>> +		res_pool = dce61_create_resource_pool(
>> +			num_virtual_links, dc);
>> +		break;
>> +	case DCE_VERSION_6_4:
>> +		res_pool = dce64_create_resource_pool(
>> +			num_virtual_links, dc);
>> +		break;
>> +#endif
>>  	case DCE_VERSION_8_0:
>>  		res_pool = dce80_create_resource_pool(
>>  			num_virtual_links, dc);
>>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> 
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[PATCH v2 04/10] drm/amd/display: dc/bios: add support for DCE6

[Mauro Rossi]

DCE6 targets are added replicating existing DCE8 implementation.
---
 drivers/gpu/drm/amd/display/dc/bios/Makefile  |   9 +
 .../display/dc/bios/command_table_helper.c    |   8 +
 .../display/dc/bios/command_table_helper.h    |   3 +
 .../display/dc/bios/command_table_helper2.c   |   8 +
 .../display/dc/bios/command_table_helper2.h   |   3 +
 .../bios/dce60/command_table_helper_dce60.c   | 354 ++++++++++++++++++
 .../bios/dce60/command_table_helper_dce60.h   |  33 ++
 7 files changed, 418 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h

diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile
index 239e86bbec5a..ed6b5e9763f6 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
@@ -31,6 +31,15 @@ AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
 
+###############################################################################
+# DCE 6x
+###############################################################################
+# All DCE6.x are derived from DCE6.0, so 6.0 MUST be defined if ANY of
+# DCE6.x is compiled.
+ifdef CONFIG_DRM_AMD_DC_SI
+AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce60/command_table_helper_dce60.o
+endif
+
 ###############################################################################
 # DCE 8x
 ###############################################################################
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
index 253bbb1eea60..48b4ef03fc8f 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
@@ -36,6 +36,14 @@ bool dal_bios_parser_init_cmd_tbl_helper(
 	enum dce_version dce)
 {
 	switch (dce) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+	case DCE_VERSION_6_0:
+	case DCE_VERSION_6_1:
+	case DCE_VERSION_6_4:
+		*h = dal_cmd_tbl_helper_dce60_get_table();
+		return true;
+#endif
+
 	case DCE_VERSION_8_0:
 	case DCE_VERSION_8_1:
 	case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
index 4c3789df253d..dfd30aaf4032 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
@@ -26,6 +26,9 @@
 #ifndef __DAL_COMMAND_TABLE_HELPER_H__
 #define __DAL_COMMAND_TABLE_HELPER_H__
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/command_table_helper_dce60.h"
+#endif
 #include "dce80/command_table_helper_dce80.h"
 #include "dce110/command_table_helper_dce110.h"
 #include "dce112/command_table_helper_dce112.h"
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index 65b006ad372e..92288c582934 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -37,6 +37,14 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
 	enum dce_version dce)
 {
 	switch (dce) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+	case DCE_VERSION_6_0:
+	case DCE_VERSION_6_1:
+	case DCE_VERSION_6_4:
+		*h = dal_cmd_tbl_helper_dce60_get_table();
+		return true;
+#endif
+
 	case DCE_VERSION_8_0:
 	case DCE_VERSION_8_1:
 	case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
index 785fcb20a1b9..66e0a3e73768 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
@@ -26,6 +26,9 @@
 #ifndef __DAL_COMMAND_TABLE_HELPER2_H__
 #define __DAL_COMMAND_TABLE_HELPER2_H__
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/command_table_helper_dce60.h"
+#endif
 #include "dce80/command_table_helper_dce80.h"
 #include "dce110/command_table_helper_dce110.h"
 #include "dce112/command_table_helper2_dce112.h"
diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
new file mode 100644
index 000000000000..552778ce9835
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "atom.h"
+
+#include "include/grph_object_id.h"
+#include "include/grph_object_defs.h"
+#include "include/bios_parser_types.h"
+
+#include "../command_table_helper.h"
+
+static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
+{
+	uint8_t atom_action = 0;
+
+	switch (action) {
+	case ENCODER_CONTROL_ENABLE:
+		atom_action = ATOM_ENABLE;
+		break;
+	case ENCODER_CONTROL_DISABLE:
+		atom_action = ATOM_DISABLE;
+		break;
+	case ENCODER_CONTROL_SETUP:
+		atom_action = ATOM_ENCODER_CMD_SETUP;
+		break;
+	case ENCODER_CONTROL_INIT:
+		atom_action = ATOM_ENCODER_INIT;
+		break;
+	default:
+		BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
+		break;
+	}
+
+	return atom_action;
+}
+
+static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
+{
+	bool result = false;
+
+	if (atom_engine_id != NULL)
+		switch (id) {
+		case ENGINE_ID_DIGA:
+			*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
+			result = true;
+			break;
+		case ENGINE_ID_DIGB:
+			*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
+			result = true;
+			break;
+		case ENGINE_ID_DIGC:
+			*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
+			result = true;
+			break;
+		case ENGINE_ID_DIGD:
+			*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
+			result = true;
+			break;
+		case ENGINE_ID_DIGE:
+			*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
+			result = true;
+			break;
+		case ENGINE_ID_DIGF:
+			*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
+			result = true;
+			break;
+		case ENGINE_ID_DIGG:
+			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
+			result = true;
+			break;
+		case ENGINE_ID_DACA:
+			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
+			result = true;
+			break;
+		default:
+			break;
+		}
+
+	return result;
+}
+
+static bool clock_source_id_to_atom(
+	enum clock_source_id id,
+	uint32_t *atom_pll_id)
+{
+	bool result = true;
+
+	if (atom_pll_id != NULL)
+		switch (id) {
+		case CLOCK_SOURCE_ID_PLL0:
+			*atom_pll_id = ATOM_PPLL0;
+			break;
+		case CLOCK_SOURCE_ID_PLL1:
+			*atom_pll_id = ATOM_PPLL1;
+			break;
+		case CLOCK_SOURCE_ID_PLL2:
+			*atom_pll_id = ATOM_PPLL2;
+			break;
+		case CLOCK_SOURCE_ID_EXTERNAL:
+			*atom_pll_id = ATOM_PPLL_INVALID;
+			break;
+		case CLOCK_SOURCE_ID_DFS:
+			*atom_pll_id = ATOM_EXT_PLL1;
+			break;
+		case CLOCK_SOURCE_ID_VCE:
+			/* for VCE encoding,
+			 * we need to pass in ATOM_PPLL_INVALID
+			 */
+			*atom_pll_id = ATOM_PPLL_INVALID;
+			break;
+		case CLOCK_SOURCE_ID_DP_DTO:
+			/* When programming DP DTO PLL ID should be invalid */
+			*atom_pll_id = ATOM_PPLL_INVALID;
+			break;
+		case CLOCK_SOURCE_ID_UNDEFINED:
+			BREAK_TO_DEBUGGER(); /* check when this will happen! */
+			*atom_pll_id = ATOM_PPLL_INVALID;
+			result = false;
+			break;
+		default:
+			result = false;
+			break;
+		}
+
+	return result;
+}
+
+static uint8_t clock_source_id_to_atom_phy_clk_src_id(
+		enum clock_source_id id)
+{
+	uint8_t atom_phy_clk_src_id = 0;
+
+	switch (id) {
+	case CLOCK_SOURCE_ID_PLL0:
+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
+		break;
+	case CLOCK_SOURCE_ID_PLL1:
+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
+		break;
+	case CLOCK_SOURCE_ID_PLL2:
+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
+		break;
+	case CLOCK_SOURCE_ID_EXTERNAL:
+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
+		break;
+	default:
+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
+		break;
+	}
+
+	return atom_phy_clk_src_id >> 2;
+}
+
+static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
+{
+	uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
+
+	switch (s) {
+	case SIGNAL_TYPE_DISPLAY_PORT:
+	case SIGNAL_TYPE_EDP:
+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
+		break;
+	case SIGNAL_TYPE_LVDS:
+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_LVDS;
+		break;
+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
+	case SIGNAL_TYPE_DVI_DUAL_LINK:
+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
+		break;
+	case SIGNAL_TYPE_HDMI_TYPE_A:
+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_HDMI;
+		break;
+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP_MST;
+		break;
+	default:
+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
+		break;
+	}
+
+	return atom_dig_mode;
+}
+
+static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
+{
+	uint8_t atom_hpd_sel = 0;
+
+	switch (id) {
+	case HPD_SOURCEID1:
+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL;
+		break;
+	case HPD_SOURCEID2:
+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL;
+		break;
+	case HPD_SOURCEID3:
+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL;
+		break;
+	case HPD_SOURCEID4:
+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL;
+		break;
+	case HPD_SOURCEID5:
+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL;
+		break;
+	case HPD_SOURCEID6:
+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL;
+		break;
+	case HPD_SOURCEID_UNKNOWN:
+	default:
+		atom_hpd_sel = 0;
+		break;
+	}
+	return atom_hpd_sel >> 4;
+}
+
+static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
+{
+	uint8_t atom_dig_encoder_sel = 0;
+
+	switch (id) {
+	case ENGINE_ID_DIGA:
+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
+		break;
+	case ENGINE_ID_DIGB:
+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
+		break;
+	case ENGINE_ID_DIGC:
+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
+		break;
+	case ENGINE_ID_DIGD:
+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
+		break;
+	case ENGINE_ID_DIGE:
+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
+		break;
+	case ENGINE_ID_DIGF:
+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
+		break;
+	case ENGINE_ID_DIGG:
+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
+		break;
+	default:
+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
+		break;
+	}
+
+	return atom_dig_encoder_sel;
+}
+
+static uint8_t phy_id_to_atom(enum transmitter t)
+{
+	uint8_t atom_phy_id;
+
+	switch (t) {
+	case TRANSMITTER_UNIPHY_A:
+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
+		break;
+	case TRANSMITTER_UNIPHY_B:
+		atom_phy_id = ATOM_PHY_ID_UNIPHYB;
+		break;
+	case TRANSMITTER_UNIPHY_C:
+		atom_phy_id = ATOM_PHY_ID_UNIPHYC;
+		break;
+	case TRANSMITTER_UNIPHY_D:
+		atom_phy_id = ATOM_PHY_ID_UNIPHYD;
+		break;
+	case TRANSMITTER_UNIPHY_E:
+		atom_phy_id = ATOM_PHY_ID_UNIPHYE;
+		break;
+	case TRANSMITTER_UNIPHY_F:
+		atom_phy_id = ATOM_PHY_ID_UNIPHYF;
+		break;
+	case TRANSMITTER_UNIPHY_G:
+		atom_phy_id = ATOM_PHY_ID_UNIPHYG;
+		break;
+	default:
+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
+		break;
+	}
+	return atom_phy_id;
+}
+
+static uint8_t disp_power_gating_action_to_atom(
+	enum bp_pipe_control_action action)
+{
+	uint8_t atom_pipe_action = 0;
+
+	switch (action) {
+	case ASIC_PIPE_DISABLE:
+		atom_pipe_action = ATOM_DISABLE;
+		break;
+	case ASIC_PIPE_ENABLE:
+		atom_pipe_action = ATOM_ENABLE;
+		break;
+	case ASIC_PIPE_INIT:
+		atom_pipe_action = ATOM_INIT;
+		break;
+	default:
+		BREAK_TO_DEBUGGER(); /* Unhandle action in driver! */
+		break;
+	}
+
+	return atom_pipe_action;
+}
+
+static const struct command_table_helper command_table_helper_funcs = {
+	.controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
+	.encoder_action_to_atom = encoder_action_to_atom,
+	.engine_bp_to_atom = engine_bp_to_atom,
+	.clock_source_id_to_atom = clock_source_id_to_atom,
+	.clock_source_id_to_atom_phy_clk_src_id =
+		clock_source_id_to_atom_phy_clk_src_id,
+	.signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
+	.hpd_sel_to_atom = hpd_sel_to_atom,
+	.dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
+	.phy_id_to_atom = phy_id_to_atom,
+	.disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
+	.assign_control_parameter =
+		dal_cmd_table_helper_assign_control_parameter,
+	.clock_source_id_to_ref_clk_src =
+		dal_cmd_table_helper_clock_source_id_to_ref_clk_src,
+	.transmitter_bp_to_atom = dal_cmd_table_helper_transmitter_bp_to_atom,
+	.encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
+	.encoder_mode_bp_to_atom =
+		dal_cmd_table_helper_encoder_mode_bp_to_atom,
+};
+
+const struct command_table_helper *dal_cmd_tbl_helper_dce60_get_table(void)
+{
+	return &command_table_helper_funcs;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
new file mode 100644
index 000000000000..591c796d0bf1
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_COMMAND_TABLE_HELPER_DCE60_H__
+#define __DAL_COMMAND_TABLE_HELPER_DCE60_H__
+
+struct command_table_helper;
+
+const struct command_table_helper *dal_cmd_tbl_helper_dce60_get_table(void);
+
+#endif
-- 
2.17.1

_______________________________________________
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amd-gfx@lists.freedesktop.org
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Re: [PATCH v2 04/10] drm/amd/display: dc/bios: add support for DCE6

[Wentland, Harry]

On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> DCE6 targets are added replicating existing DCE8 implementation.
> ---
>  drivers/gpu/drm/amd/display/dc/bios/Makefile  |   9 +
>  .../display/dc/bios/command_table_helper.c    |   8 +
>  .../display/dc/bios/command_table_helper.h    |   3 +
>  .../display/dc/bios/command_table_helper2.c   |   8 +
>  .../display/dc/bios/command_table_helper2.h   |   3 +
>  .../bios/dce60/command_table_helper_dce60.c   | 354 ++++++++++++++++++
>  .../bios/dce60/command_table_helper_dce60.h   |  33 ++
>  7 files changed, 418 insertions(+)
>  create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
>  create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile
> index 239e86bbec5a..ed6b5e9763f6 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
> @@ -31,6 +31,15 @@ AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
>  
>  AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
>  
> +###############################################################################
> +# DCE 6x
> +###############################################################################
> +# All DCE6.x are derived from DCE6.0, so 6.0 MUST be defined if ANY of
> +# DCE6.x is compiled.
> +ifdef CONFIG_DRM_AMD_DC_SI
> +AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce60/command_table_helper_dce60.o
> +endif
> +
>  ###############################################################################
>  # DCE 8x
>  ###############################################################################
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> index 253bbb1eea60..48b4ef03fc8f 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> @@ -36,6 +36,14 @@ bool dal_bios_parser_init_cmd_tbl_helper(
>  	enum dce_version dce)
>  {
>  	switch (dce) {
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> +	case DCE_VERSION_6_0:
> +	case DCE_VERSION_6_1:
> +	case DCE_VERSION_6_4:
> +		*h = dal_cmd_tbl_helper_dce60_get_table();

Can we just point these to the dce80 version since they're exactly the same?

> +		return true;
> +#endif
> +
>  	case DCE_VERSION_8_0:
>  	case DCE_VERSION_8_1:
>  	case DCE_VERSION_8_3:
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> index 4c3789df253d..dfd30aaf4032 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> @@ -26,6 +26,9 @@
>  #ifndef __DAL_COMMAND_TABLE_HELPER_H__
>  #define __DAL_COMMAND_TABLE_HELPER_H__
>  
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> +#include "dce60/command_table_helper_dce60.h"
> +#endif
>  #include "dce80/command_table_helper_dce80.h"
>  #include "dce110/command_table_helper_dce110.h"
>  #include "dce112/command_table_helper_dce112.h"
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> index 65b006ad372e..92288c582934 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> @@ -37,6 +37,14 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>  	enum dce_version dce)
>  {
>  	switch (dce) {
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> +	case DCE_VERSION_6_0:
> +	case DCE_VERSION_6_1:
> +	case DCE_VERSION_6_4:
> +		*h = dal_cmd_tbl_helper_dce60_get_table();

Same as above.

Harry

> +		return true;
> +#endif
> +
>  	case DCE_VERSION_8_0:
>  	case DCE_VERSION_8_1:
>  	case DCE_VERSION_8_3:
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> index 785fcb20a1b9..66e0a3e73768 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> @@ -26,6 +26,9 @@
>  #ifndef __DAL_COMMAND_TABLE_HELPER2_H__
>  #define __DAL_COMMAND_TABLE_HELPER2_H__
>  
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> +#include "dce60/command_table_helper_dce60.h"
> +#endif
>  #include "dce80/command_table_helper_dce80.h"
>  #include "dce110/command_table_helper_dce110.h"
>  #include "dce112/command_table_helper2_dce112.h"
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
> new file mode 100644
> index 000000000000..552778ce9835
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
> @@ -0,0 +1,354 @@
> +/*
> + * Copyright 2012-15 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: AMD
> + *
> + */
> +
> +#include "dm_services.h"
> +
> +#include "atom.h"
> +
> +#include "include/grph_object_id.h"
> +#include "include/grph_object_defs.h"
> +#include "include/bios_parser_types.h"
> +
> +#include "../command_table_helper.h"
> +
> +static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
> +{
> +	uint8_t atom_action = 0;
> +
> +	switch (action) {
> +	case ENCODER_CONTROL_ENABLE:
> +		atom_action = ATOM_ENABLE;
> +		break;
> +	case ENCODER_CONTROL_DISABLE:
> +		atom_action = ATOM_DISABLE;
> +		break;
> +	case ENCODER_CONTROL_SETUP:
> +		atom_action = ATOM_ENCODER_CMD_SETUP;
> +		break;
> +	case ENCODER_CONTROL_INIT:
> +		atom_action = ATOM_ENCODER_INIT;
> +		break;
> +	default:
> +		BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
> +		break;
> +	}
> +
> +	return atom_action;
> +}
> +
> +static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
> +{
> +	bool result = false;
> +
> +	if (atom_engine_id != NULL)
> +		switch (id) {
> +		case ENGINE_ID_DIGA:
> +			*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
> +			result = true;
> +			break;
> +		case ENGINE_ID_DIGB:
> +			*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
> +			result = true;
> +			break;
> +		case ENGINE_ID_DIGC:
> +			*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
> +			result = true;
> +			break;
> +		case ENGINE_ID_DIGD:
> +			*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
> +			result = true;
> +			break;
> +		case ENGINE_ID_DIGE:
> +			*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
> +			result = true;
> +			break;
> +		case ENGINE_ID_DIGF:
> +			*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
> +			result = true;
> +			break;
> +		case ENGINE_ID_DIGG:
> +			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
> +			result = true;
> +			break;
> +		case ENGINE_ID_DACA:
> +			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
> +			result = true;
> +			break;
> +		default:
> +			break;
> +		}
> +
> +	return result;
> +}
> +
> +static bool clock_source_id_to_atom(
> +	enum clock_source_id id,
> +	uint32_t *atom_pll_id)
> +{
> +	bool result = true;
> +
> +	if (atom_pll_id != NULL)
> +		switch (id) {
> +		case CLOCK_SOURCE_ID_PLL0:
> +			*atom_pll_id = ATOM_PPLL0;
> +			break;
> +		case CLOCK_SOURCE_ID_PLL1:
> +			*atom_pll_id = ATOM_PPLL1;
> +			break;
> +		case CLOCK_SOURCE_ID_PLL2:
> +			*atom_pll_id = ATOM_PPLL2;
> +			break;
> +		case CLOCK_SOURCE_ID_EXTERNAL:
> +			*atom_pll_id = ATOM_PPLL_INVALID;
> +			break;
> +		case CLOCK_SOURCE_ID_DFS:
> +			*atom_pll_id = ATOM_EXT_PLL1;
> +			break;
> +		case CLOCK_SOURCE_ID_VCE:
> +			/* for VCE encoding,
> +			 * we need to pass in ATOM_PPLL_INVALID
> +			 */
> +			*atom_pll_id = ATOM_PPLL_INVALID;
> +			break;
> +		case CLOCK_SOURCE_ID_DP_DTO:
> +			/* When programming DP DTO PLL ID should be invalid */
> +			*atom_pll_id = ATOM_PPLL_INVALID;
> +			break;
> +		case CLOCK_SOURCE_ID_UNDEFINED:
> +			BREAK_TO_DEBUGGER(); /* check when this will happen! */
> +			*atom_pll_id = ATOM_PPLL_INVALID;
> +			result = false;
> +			break;
> +		default:
> +			result = false;
> +			break;
> +		}
> +
> +	return result;
> +}
> +
> +static uint8_t clock_source_id_to_atom_phy_clk_src_id(
> +		enum clock_source_id id)
> +{
> +	uint8_t atom_phy_clk_src_id = 0;
> +
> +	switch (id) {
> +	case CLOCK_SOURCE_ID_PLL0:
> +		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
> +		break;
> +	case CLOCK_SOURCE_ID_PLL1:
> +		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
> +		break;
> +	case CLOCK_SOURCE_ID_PLL2:
> +		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
> +		break;
> +	case CLOCK_SOURCE_ID_EXTERNAL:
> +		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
> +		break;
> +	default:
> +		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
> +		break;
> +	}
> +
> +	return atom_phy_clk_src_id >> 2;
> +}
> +
> +static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
> +{
> +	uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
> +
> +	switch (s) {
> +	case SIGNAL_TYPE_DISPLAY_PORT:
> +	case SIGNAL_TYPE_EDP:
> +		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
> +		break;
> +	case SIGNAL_TYPE_LVDS:
> +		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_LVDS;
> +		break;
> +	case SIGNAL_TYPE_DVI_SINGLE_LINK:
> +	case SIGNAL_TYPE_DVI_DUAL_LINK:
> +		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
> +		break;
> +	case SIGNAL_TYPE_HDMI_TYPE_A:
> +		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_HDMI;
> +		break;
> +	case SIGNAL_TYPE_DISPLAY_PORT_MST:
> +		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP_MST;
> +		break;
> +	default:
> +		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
> +		break;
> +	}
> +
> +	return atom_dig_mode;
> +}
> +
> +static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
> +{
> +	uint8_t atom_hpd_sel = 0;
> +
> +	switch (id) {
> +	case HPD_SOURCEID1:
> +		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL;
> +		break;
> +	case HPD_SOURCEID2:
> +		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL;
> +		break;
> +	case HPD_SOURCEID3:
> +		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL;
> +		break;
> +	case HPD_SOURCEID4:
> +		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL;
> +		break;
> +	case HPD_SOURCEID5:
> +		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL;
> +		break;
> +	case HPD_SOURCEID6:
> +		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL;
> +		break;
> +	case HPD_SOURCEID_UNKNOWN:
> +	default:
> +		atom_hpd_sel = 0;
> +		break;
> +	}
> +	return atom_hpd_sel >> 4;
> +}
> +
> +static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
> +{
> +	uint8_t atom_dig_encoder_sel = 0;
> +
> +	switch (id) {
> +	case ENGINE_ID_DIGA:
> +		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
> +		break;
> +	case ENGINE_ID_DIGB:
> +		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
> +		break;
> +	case ENGINE_ID_DIGC:
> +		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
> +		break;
> +	case ENGINE_ID_DIGD:
> +		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
> +		break;
> +	case ENGINE_ID_DIGE:
> +		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
> +		break;
> +	case ENGINE_ID_DIGF:
> +		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
> +		break;
> +	case ENGINE_ID_DIGG:
> +		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
> +		break;
> +	default:
> +		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
> +		break;
> +	}
> +
> +	return atom_dig_encoder_sel;
> +}
> +
> +static uint8_t phy_id_to_atom(enum transmitter t)
> +{
> +	uint8_t atom_phy_id;
> +
> +	switch (t) {
> +	case TRANSMITTER_UNIPHY_A:
> +		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
> +		break;
> +	case TRANSMITTER_UNIPHY_B:
> +		atom_phy_id = ATOM_PHY_ID_UNIPHYB;
> +		break;
> +	case TRANSMITTER_UNIPHY_C:
> +		atom_phy_id = ATOM_PHY_ID_UNIPHYC;
> +		break;
> +	case TRANSMITTER_UNIPHY_D:
> +		atom_phy_id = ATOM_PHY_ID_UNIPHYD;
> +		break;
> +	case TRANSMITTER_UNIPHY_E:
> +		atom_phy_id = ATOM_PHY_ID_UNIPHYE;
> +		break;
> +	case TRANSMITTER_UNIPHY_F:
> +		atom_phy_id = ATOM_PHY_ID_UNIPHYF;
> +		break;
> +	case TRANSMITTER_UNIPHY_G:
> +		atom_phy_id = ATOM_PHY_ID_UNIPHYG;
> +		break;
> +	default:
> +		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
> +		break;
> +	}
> +	return atom_phy_id;
> +}
> +
> +static uint8_t disp_power_gating_action_to_atom(
> +	enum bp_pipe_control_action action)
> +{
> +	uint8_t atom_pipe_action = 0;
> +
> +	switch (action) {
> +	case ASIC_PIPE_DISABLE:
> +		atom_pipe_action = ATOM_DISABLE;
> +		break;
> +	case ASIC_PIPE_ENABLE:
> +		atom_pipe_action = ATOM_ENABLE;
> +		break;
> +	case ASIC_PIPE_INIT:
> +		atom_pipe_action = ATOM_INIT;
> +		break;
> +	default:
> +		BREAK_TO_DEBUGGER(); /* Unhandle action in driver! */
> +		break;
> +	}
> +
> +	return atom_pipe_action;
> +}
> +
> +static const struct command_table_helper command_table_helper_funcs = {
> +	.controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
> +	.encoder_action_to_atom = encoder_action_to_atom,
> +	.engine_bp_to_atom = engine_bp_to_atom,
> +	.clock_source_id_to_atom = clock_source_id_to_atom,
> +	.clock_source_id_to_atom_phy_clk_src_id =
> +		clock_source_id_to_atom_phy_clk_src_id,
> +	.signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
> +	.hpd_sel_to_atom = hpd_sel_to_atom,
> +	.dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
> +	.phy_id_to_atom = phy_id_to_atom,
> +	.disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
> +	.assign_control_parameter =
> +		dal_cmd_table_helper_assign_control_parameter,
> +	.clock_source_id_to_ref_clk_src =
> +		dal_cmd_table_helper_clock_source_id_to_ref_clk_src,
> +	.transmitter_bp_to_atom = dal_cmd_table_helper_transmitter_bp_to_atom,
> +	.encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
> +	.encoder_mode_bp_to_atom =
> +		dal_cmd_table_helper_encoder_mode_bp_to_atom,
> +};
> +
> +const struct command_table_helper *dal_cmd_tbl_helper_dce60_get_table(void)
> +{
> +	return &command_table_helper_funcs;
> +}
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
> new file mode 100644
> index 000000000000..591c796d0bf1
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
> @@ -0,0 +1,33 @@
> +/*
> + * Copyright 2012-15 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: AMD
> + *
> + */
> +
> +#ifndef __DAL_COMMAND_TABLE_HELPER_DCE60_H__
> +#define __DAL_COMMAND_TABLE_HELPER_DCE60_H__
> +
> +struct command_table_helper;
> +
> +const struct command_table_helper *dal_cmd_tbl_helper_dce60_get_table(void);
> +
> +#endif
> 
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Re: [PATCH v2 04/10] drm/amd/display: dc/bios: add support for DCE6

[Alex Deucher]

On Wed, Oct 17, 2018 at 3:54 PM Wentland, Harry <Harry.Wentland@amd.com> wrote:
>
> On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> > DCE6 targets are added replicating existing DCE8 implementation.
> > ---
> >  drivers/gpu/drm/amd/display/dc/bios/Makefile  |   9 +
> >  .../display/dc/bios/command_table_helper.c    |   8 +
> >  .../display/dc/bios/command_table_helper.h    |   3 +
> >  .../display/dc/bios/command_table_helper2.c   |   8 +
> >  .../display/dc/bios/command_table_helper2.h   |   3 +
> >  .../bios/dce60/command_table_helper_dce60.c   | 354 ++++++++++++++++++
> >  .../bios/dce60/command_table_helper_dce60.h   |  33 ++
> >  7 files changed, 418 insertions(+)
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
> >  create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile
> > index 239e86bbec5a..ed6b5e9763f6 100644
> > --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
> > +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
> > @@ -31,6 +31,15 @@ AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
> >
> >  AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
> >
> > +###############################################################################
> > +# DCE 6x
> > +###############################################################################
> > +# All DCE6.x are derived from DCE6.0, so 6.0 MUST be defined if ANY of
> > +# DCE6.x is compiled.
> > +ifdef CONFIG_DRM_AMD_DC_SI
> > +AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce60/command_table_helper_dce60.o
> > +endif
> > +
> >  ###############################################################################
> >  # DCE 8x
> >  ###############################################################################
> > diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> > index 253bbb1eea60..48b4ef03fc8f 100644
> > --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> > +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> > @@ -36,6 +36,14 @@ bool dal_bios_parser_init_cmd_tbl_helper(
> >       enum dce_version dce)
> >  {
> >       switch (dce) {
> > +#if defined(CONFIG_DRM_AMD_DC_SI)
> > +     case DCE_VERSION_6_0:
> > +     case DCE_VERSION_6_1:
> > +     case DCE_VERSION_6_4:
> > +             *h = dal_cmd_tbl_helper_dce60_get_table();
>
> Can we just point these to the dce80 version since they're exactly the same?

Some of the dig transmitter and encoder cmd tables had different
versions on DCE6 vs 8.  I'm not sure if we need to do any different
translations for some of these.

Alex

>
> > +             return true;
> > +#endif
> > +
> >       case DCE_VERSION_8_0:
> >       case DCE_VERSION_8_1:
> >       case DCE_VERSION_8_3:
> > diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> > index 4c3789df253d..dfd30aaf4032 100644
> > --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> > +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> > @@ -26,6 +26,9 @@
> >  #ifndef __DAL_COMMAND_TABLE_HELPER_H__
> >  #define __DAL_COMMAND_TABLE_HELPER_H__
> >
> > +#if defined(CONFIG_DRM_AMD_DC_SI)
> > +#include "dce60/command_table_helper_dce60.h"
> > +#endif
> >  #include "dce80/command_table_helper_dce80.h"
> >  #include "dce110/command_table_helper_dce110.h"
> >  #include "dce112/command_table_helper_dce112.h"
> > diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> > index 65b006ad372e..92288c582934 100644
> > --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> > +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> > @@ -37,6 +37,14 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
> >       enum dce_version dce)
> >  {
> >       switch (dce) {
> > +#if defined(CONFIG_DRM_AMD_DC_SI)
> > +     case DCE_VERSION_6_0:
> > +     case DCE_VERSION_6_1:
> > +     case DCE_VERSION_6_4:
> > +             *h = dal_cmd_tbl_helper_dce60_get_table();
>
> Same as above.
>
> Harry
>
> > +             return true;
> > +#endif
> > +
> >       case DCE_VERSION_8_0:
> >       case DCE_VERSION_8_1:
> >       case DCE_VERSION_8_3:
> > diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> > index 785fcb20a1b9..66e0a3e73768 100644
> > --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> > +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> > @@ -26,6 +26,9 @@
> >  #ifndef __DAL_COMMAND_TABLE_HELPER2_H__
> >  #define __DAL_COMMAND_TABLE_HELPER2_H__
> >
> > +#if defined(CONFIG_DRM_AMD_DC_SI)
> > +#include "dce60/command_table_helper_dce60.h"
> > +#endif
> >  #include "dce80/command_table_helper_dce80.h"
> >  #include "dce110/command_table_helper_dce110.h"
> >  #include "dce112/command_table_helper2_dce112.h"
> > diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
> > new file mode 100644
> > index 000000000000..552778ce9835
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
> > @@ -0,0 +1,354 @@
> > +/*
> > + * Copyright 2012-15 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> > + *
> > + */
> > +
> > +#include "dm_services.h"
> > +
> > +#include "atom.h"
> > +
> > +#include "include/grph_object_id.h"
> > +#include "include/grph_object_defs.h"
> > +#include "include/bios_parser_types.h"
> > +
> > +#include "../command_table_helper.h"
> > +
> > +static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
> > +{
> > +     uint8_t atom_action = 0;
> > +
> > +     switch (action) {
> > +     case ENCODER_CONTROL_ENABLE:
> > +             atom_action = ATOM_ENABLE;
> > +             break;
> > +     case ENCODER_CONTROL_DISABLE:
> > +             atom_action = ATOM_DISABLE;
> > +             break;
> > +     case ENCODER_CONTROL_SETUP:
> > +             atom_action = ATOM_ENCODER_CMD_SETUP;
> > +             break;
> > +     case ENCODER_CONTROL_INIT:
> > +             atom_action = ATOM_ENCODER_INIT;
> > +             break;
> > +     default:
> > +             BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
> > +             break;
> > +     }
> > +
> > +     return atom_action;
> > +}
> > +
> > +static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
> > +{
> > +     bool result = false;
> > +
> > +     if (atom_engine_id != NULL)
> > +             switch (id) {
> > +             case ENGINE_ID_DIGA:
> > +                     *atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
> > +                     result = true;
> > +                     break;
> > +             case ENGINE_ID_DIGB:
> > +                     *atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
> > +                     result = true;
> > +                     break;
> > +             case ENGINE_ID_DIGC:
> > +                     *atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
> > +                     result = true;
> > +                     break;
> > +             case ENGINE_ID_DIGD:
> > +                     *atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
> > +                     result = true;
> > +                     break;
> > +             case ENGINE_ID_DIGE:
> > +                     *atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
> > +                     result = true;
> > +                     break;
> > +             case ENGINE_ID_DIGF:
> > +                     *atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
> > +                     result = true;
> > +                     break;
> > +             case ENGINE_ID_DIGG:
> > +                     *atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
> > +                     result = true;
> > +                     break;
> > +             case ENGINE_ID_DACA:
> > +                     *atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
> > +                     result = true;
> > +                     break;
> > +             default:
> > +                     break;
> > +             }
> > +
> > +     return result;
> > +}
> > +
> > +static bool clock_source_id_to_atom(
> > +     enum clock_source_id id,
> > +     uint32_t *atom_pll_id)
> > +{
> > +     bool result = true;
> > +
> > +     if (atom_pll_id != NULL)
> > +             switch (id) {
> > +             case CLOCK_SOURCE_ID_PLL0:
> > +                     *atom_pll_id = ATOM_PPLL0;
> > +                     break;
> > +             case CLOCK_SOURCE_ID_PLL1:
> > +                     *atom_pll_id = ATOM_PPLL1;
> > +                     break;
> > +             case CLOCK_SOURCE_ID_PLL2:
> > +                     *atom_pll_id = ATOM_PPLL2;
> > +                     break;
> > +             case CLOCK_SOURCE_ID_EXTERNAL:
> > +                     *atom_pll_id = ATOM_PPLL_INVALID;
> > +                     break;
> > +             case CLOCK_SOURCE_ID_DFS:
> > +                     *atom_pll_id = ATOM_EXT_PLL1;
> > +                     break;
> > +             case CLOCK_SOURCE_ID_VCE:
> > +                     /* for VCE encoding,
> > +                      * we need to pass in ATOM_PPLL_INVALID
> > +                      */
> > +                     *atom_pll_id = ATOM_PPLL_INVALID;
> > +                     break;
> > +             case CLOCK_SOURCE_ID_DP_DTO:
> > +                     /* When programming DP DTO PLL ID should be invalid */
> > +                     *atom_pll_id = ATOM_PPLL_INVALID;
> > +                     break;
> > +             case CLOCK_SOURCE_ID_UNDEFINED:
> > +                     BREAK_TO_DEBUGGER(); /* check when this will happen! */
> > +                     *atom_pll_id = ATOM_PPLL_INVALID;
> > +                     result = false;
> > +                     break;
> > +             default:
> > +                     result = false;
> > +                     break;
> > +             }
> > +
> > +     return result;
> > +}
> > +
> > +static uint8_t clock_source_id_to_atom_phy_clk_src_id(
> > +             enum clock_source_id id)
> > +{
> > +     uint8_t atom_phy_clk_src_id = 0;
> > +
> > +     switch (id) {
> > +     case CLOCK_SOURCE_ID_PLL0:
> > +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
> > +             break;
> > +     case CLOCK_SOURCE_ID_PLL1:
> > +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
> > +             break;
> > +     case CLOCK_SOURCE_ID_PLL2:
> > +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
> > +             break;
> > +     case CLOCK_SOURCE_ID_EXTERNAL:
> > +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
> > +             break;
> > +     default:
> > +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
> > +             break;
> > +     }
> > +
> > +     return atom_phy_clk_src_id >> 2;
> > +}
> > +
> > +static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
> > +{
> > +     uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
> > +
> > +     switch (s) {
> > +     case SIGNAL_TYPE_DISPLAY_PORT:
> > +     case SIGNAL_TYPE_EDP:
> > +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
> > +             break;
> > +     case SIGNAL_TYPE_LVDS:
> > +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_LVDS;
> > +             break;
> > +     case SIGNAL_TYPE_DVI_SINGLE_LINK:
> > +     case SIGNAL_TYPE_DVI_DUAL_LINK:
> > +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
> > +             break;
> > +     case SIGNAL_TYPE_HDMI_TYPE_A:
> > +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_HDMI;
> > +             break;
> > +     case SIGNAL_TYPE_DISPLAY_PORT_MST:
> > +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP_MST;
> > +             break;
> > +     default:
> > +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
> > +             break;
> > +     }
> > +
> > +     return atom_dig_mode;
> > +}
> > +
> > +static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
> > +{
> > +     uint8_t atom_hpd_sel = 0;
> > +
> > +     switch (id) {
> > +     case HPD_SOURCEID1:
> > +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL;
> > +             break;
> > +     case HPD_SOURCEID2:
> > +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL;
> > +             break;
> > +     case HPD_SOURCEID3:
> > +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL;
> > +             break;
> > +     case HPD_SOURCEID4:
> > +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL;
> > +             break;
> > +     case HPD_SOURCEID5:
> > +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL;
> > +             break;
> > +     case HPD_SOURCEID6:
> > +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL;
> > +             break;
> > +     case HPD_SOURCEID_UNKNOWN:
> > +     default:
> > +             atom_hpd_sel = 0;
> > +             break;
> > +     }
> > +     return atom_hpd_sel >> 4;
> > +}
> > +
> > +static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
> > +{
> > +     uint8_t atom_dig_encoder_sel = 0;
> > +
> > +     switch (id) {
> > +     case ENGINE_ID_DIGA:
> > +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
> > +             break;
> > +     case ENGINE_ID_DIGB:
> > +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
> > +             break;
> > +     case ENGINE_ID_DIGC:
> > +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
> > +             break;
> > +     case ENGINE_ID_DIGD:
> > +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
> > +             break;
> > +     case ENGINE_ID_DIGE:
> > +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
> > +             break;
> > +     case ENGINE_ID_DIGF:
> > +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
> > +             break;
> > +     case ENGINE_ID_DIGG:
> > +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
> > +             break;
> > +     default:
> > +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
> > +             break;
> > +     }
> > +
> > +     return atom_dig_encoder_sel;
> > +}
> > +
> > +static uint8_t phy_id_to_atom(enum transmitter t)
> > +{
> > +     uint8_t atom_phy_id;
> > +
> > +     switch (t) {
> > +     case TRANSMITTER_UNIPHY_A:
> > +             atom_phy_id = ATOM_PHY_ID_UNIPHYA;
> > +             break;
> > +     case TRANSMITTER_UNIPHY_B:
> > +             atom_phy_id = ATOM_PHY_ID_UNIPHYB;
> > +             break;
> > +     case TRANSMITTER_UNIPHY_C:
> > +             atom_phy_id = ATOM_PHY_ID_UNIPHYC;
> > +             break;
> > +     case TRANSMITTER_UNIPHY_D:
> > +             atom_phy_id = ATOM_PHY_ID_UNIPHYD;
> > +             break;
> > +     case TRANSMITTER_UNIPHY_E:
> > +             atom_phy_id = ATOM_PHY_ID_UNIPHYE;
> > +             break;
> > +     case TRANSMITTER_UNIPHY_F:
> > +             atom_phy_id = ATOM_PHY_ID_UNIPHYF;
> > +             break;
> > +     case TRANSMITTER_UNIPHY_G:
> > +             atom_phy_id = ATOM_PHY_ID_UNIPHYG;
> > +             break;
> > +     default:
> > +             atom_phy_id = ATOM_PHY_ID_UNIPHYA;
> > +             break;
> > +     }
> > +     return atom_phy_id;
> > +}
> > +
> > +static uint8_t disp_power_gating_action_to_atom(
> > +     enum bp_pipe_control_action action)
> > +{
> > +     uint8_t atom_pipe_action = 0;
> > +
> > +     switch (action) {
> > +     case ASIC_PIPE_DISABLE:
> > +             atom_pipe_action = ATOM_DISABLE;
> > +             break;
> > +     case ASIC_PIPE_ENABLE:
> > +             atom_pipe_action = ATOM_ENABLE;
> > +             break;
> > +     case ASIC_PIPE_INIT:
> > +             atom_pipe_action = ATOM_INIT;
> > +             break;
> > +     default:
> > +             BREAK_TO_DEBUGGER(); /* Unhandle action in driver! */
> > +             break;
> > +     }
> > +
> > +     return atom_pipe_action;
> > +}
> > +
> > +static const struct command_table_helper command_table_helper_funcs = {
> > +     .controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
> > +     .encoder_action_to_atom = encoder_action_to_atom,
> > +     .engine_bp_to_atom = engine_bp_to_atom,
> > +     .clock_source_id_to_atom = clock_source_id_to_atom,
> > +     .clock_source_id_to_atom_phy_clk_src_id =
> > +             clock_source_id_to_atom_phy_clk_src_id,
> > +     .signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
> > +     .hpd_sel_to_atom = hpd_sel_to_atom,
> > +     .dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
> > +     .phy_id_to_atom = phy_id_to_atom,
> > +     .disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
> > +     .assign_control_parameter =
> > +             dal_cmd_table_helper_assign_control_parameter,
> > +     .clock_source_id_to_ref_clk_src =
> > +             dal_cmd_table_helper_clock_source_id_to_ref_clk_src,
> > +     .transmitter_bp_to_atom = dal_cmd_table_helper_transmitter_bp_to_atom,
> > +     .encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
> > +     .encoder_mode_bp_to_atom =
> > +             dal_cmd_table_helper_encoder_mode_bp_to_atom,
> > +};
> > +
> > +const struct command_table_helper *dal_cmd_tbl_helper_dce60_get_table(void)
> > +{
> > +     return &command_table_helper_funcs;
> > +}
> > diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
> > new file mode 100644
> > index 000000000000..591c796d0bf1
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
> > @@ -0,0 +1,33 @@
> > +/*
> > + * Copyright 2012-15 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> > + *
> > + */
> > +
> > +#ifndef __DAL_COMMAND_TABLE_HELPER_DCE60_H__
> > +#define __DAL_COMMAND_TABLE_HELPER_DCE60_H__
> > +
> > +struct command_table_helper;
> > +
> > +const struct command_table_helper *dal_cmd_tbl_helper_dce60_get_table(void);
> > +
> > +#endif
> >
> _______________________________________________
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Re: [PATCH v2 04/10] drm/amd/display: dc/bios: add support for DCE6

[Wentland, Harry]

On 2018-10-17 4:10 p.m., Alex Deucher wrote:
> On Wed, Oct 17, 2018 at 3:54 PM Wentland, Harry <Harry.Wentland@amd.com> wrote:
>>
>> On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
>>> DCE6 targets are added replicating existing DCE8 implementation.
>>> ---
>>>  drivers/gpu/drm/amd/display/dc/bios/Makefile  |   9 +
>>>  .../display/dc/bios/command_table_helper.c    |   8 +
>>>  .../display/dc/bios/command_table_helper.h    |   3 +
>>>  .../display/dc/bios/command_table_helper2.c   |   8 +
>>>  .../display/dc/bios/command_table_helper2.h   |   3 +
>>>  .../bios/dce60/command_table_helper_dce60.c   | 354 ++++++++++++++++++
>>>  .../bios/dce60/command_table_helper_dce60.h   |  33 ++
>>>  7 files changed, 418 insertions(+)
>>>  create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
>>>  create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile
>>> index 239e86bbec5a..ed6b5e9763f6 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
>>> @@ -31,6 +31,15 @@ AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
>>>
>>>  AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
>>>
>>> +###############################################################################
>>> +# DCE 6x
>>> +###############################################################################
>>> +# All DCE6.x are derived from DCE6.0, so 6.0 MUST be defined if ANY of
>>> +# DCE6.x is compiled.
>>> +ifdef CONFIG_DRM_AMD_DC_SI
>>> +AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce60/command_table_helper_dce60.o
>>> +endif
>>> +
>>>  ###############################################################################
>>>  # DCE 8x
>>>  ###############################################################################
>>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
>>> index 253bbb1eea60..48b4ef03fc8f 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
>>> @@ -36,6 +36,14 @@ bool dal_bios_parser_init_cmd_tbl_helper(
>>>       enum dce_version dce)
>>>  {
>>>       switch (dce) {
>>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>>> +     case DCE_VERSION_6_0:
>>> +     case DCE_VERSION_6_1:
>>> +     case DCE_VERSION_6_4:
>>> +             *h = dal_cmd_tbl_helper_dce60_get_table();
>>
>> Can we just point these to the dce80 version since they're exactly the same?
> 
> Some of the dig transmitter and encoder cmd tables had different
> versions on DCE6 vs 8.  I'm not sure if we need to do any different
> translations for some of these.
> 

Currently it's an exact copy. Since you remember differences it makes sense to duplicate this for DCE6 so we can update it for any difference if we'll need that.

Mauro, ignore my comments in this case. :)

Harry

> Alex
> 
>>
>>> +             return true;
>>> +#endif
>>> +
>>>       case DCE_VERSION_8_0:
>>>       case DCE_VERSION_8_1:
>>>       case DCE_VERSION_8_3:
>>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
>>> index 4c3789df253d..dfd30aaf4032 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
>>> @@ -26,6 +26,9 @@
>>>  #ifndef __DAL_COMMAND_TABLE_HELPER_H__
>>>  #define __DAL_COMMAND_TABLE_HELPER_H__
>>>
>>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>>> +#include "dce60/command_table_helper_dce60.h"
>>> +#endif
>>>  #include "dce80/command_table_helper_dce80.h"
>>>  #include "dce110/command_table_helper_dce110.h"
>>>  #include "dce112/command_table_helper_dce112.h"
>>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>> index 65b006ad372e..92288c582934 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>> @@ -37,6 +37,14 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>>>       enum dce_version dce)
>>>  {
>>>       switch (dce) {
>>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>>> +     case DCE_VERSION_6_0:
>>> +     case DCE_VERSION_6_1:
>>> +     case DCE_VERSION_6_4:
>>> +             *h = dal_cmd_tbl_helper_dce60_get_table();
>>
>> Same as above.
>>
>> Harry
>>
>>> +             return true;
>>> +#endif
>>> +
>>>       case DCE_VERSION_8_0:
>>>       case DCE_VERSION_8_1:
>>>       case DCE_VERSION_8_3:
>>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
>>> index 785fcb20a1b9..66e0a3e73768 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
>>> @@ -26,6 +26,9 @@
>>>  #ifndef __DAL_COMMAND_TABLE_HELPER2_H__
>>>  #define __DAL_COMMAND_TABLE_HELPER2_H__
>>>
>>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>>> +#include "dce60/command_table_helper_dce60.h"
>>> +#endif
>>>  #include "dce80/command_table_helper_dce80.h"
>>>  #include "dce110/command_table_helper_dce110.h"
>>>  #include "dce112/command_table_helper2_dce112.h"
>>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
>>> new file mode 100644
>>> index 000000000000..552778ce9835
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
>>> @@ -0,0 +1,354 @@
>>> +/*
>>> + * Copyright 2012-15 Advanced Micro Devices, Inc.
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>> + * copy of this software and associated documentation files (the "Software"),
>>> + * to deal in the Software without restriction, including without limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>> + * Software is furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be included in
>>> + * all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>> + *
>>> + * Authors: AMD
>>> + *
>>> + */
>>> +
>>> +#include "dm_services.h"
>>> +
>>> +#include "atom.h"
>>> +
>>> +#include "include/grph_object_id.h"
>>> +#include "include/grph_object_defs.h"
>>> +#include "include/bios_parser_types.h"
>>> +
>>> +#include "../command_table_helper.h"
>>> +
>>> +static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
>>> +{
>>> +     uint8_t atom_action = 0;
>>> +
>>> +     switch (action) {
>>> +     case ENCODER_CONTROL_ENABLE:
>>> +             atom_action = ATOM_ENABLE;
>>> +             break;
>>> +     case ENCODER_CONTROL_DISABLE:
>>> +             atom_action = ATOM_DISABLE;
>>> +             break;
>>> +     case ENCODER_CONTROL_SETUP:
>>> +             atom_action = ATOM_ENCODER_CMD_SETUP;
>>> +             break;
>>> +     case ENCODER_CONTROL_INIT:
>>> +             atom_action = ATOM_ENCODER_INIT;
>>> +             break;
>>> +     default:
>>> +             BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
>>> +             break;
>>> +     }
>>> +
>>> +     return atom_action;
>>> +}
>>> +
>>> +static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
>>> +{
>>> +     bool result = false;
>>> +
>>> +     if (atom_engine_id != NULL)
>>> +             switch (id) {
>>> +             case ENGINE_ID_DIGA:
>>> +                     *atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
>>> +                     result = true;
>>> +                     break;
>>> +             case ENGINE_ID_DIGB:
>>> +                     *atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
>>> +                     result = true;
>>> +                     break;
>>> +             case ENGINE_ID_DIGC:
>>> +                     *atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
>>> +                     result = true;
>>> +                     break;
>>> +             case ENGINE_ID_DIGD:
>>> +                     *atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
>>> +                     result = true;
>>> +                     break;
>>> +             case ENGINE_ID_DIGE:
>>> +                     *atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
>>> +                     result = true;
>>> +                     break;
>>> +             case ENGINE_ID_DIGF:
>>> +                     *atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
>>> +                     result = true;
>>> +                     break;
>>> +             case ENGINE_ID_DIGG:
>>> +                     *atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
>>> +                     result = true;
>>> +                     break;
>>> +             case ENGINE_ID_DACA:
>>> +                     *atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
>>> +                     result = true;
>>> +                     break;
>>> +             default:
>>> +                     break;
>>> +             }
>>> +
>>> +     return result;
>>> +}
>>> +
>>> +static bool clock_source_id_to_atom(
>>> +     enum clock_source_id id,
>>> +     uint32_t *atom_pll_id)
>>> +{
>>> +     bool result = true;
>>> +
>>> +     if (atom_pll_id != NULL)
>>> +             switch (id) {
>>> +             case CLOCK_SOURCE_ID_PLL0:
>>> +                     *atom_pll_id = ATOM_PPLL0;
>>> +                     break;
>>> +             case CLOCK_SOURCE_ID_PLL1:
>>> +                     *atom_pll_id = ATOM_PPLL1;
>>> +                     break;
>>> +             case CLOCK_SOURCE_ID_PLL2:
>>> +                     *atom_pll_id = ATOM_PPLL2;
>>> +                     break;
>>> +             case CLOCK_SOURCE_ID_EXTERNAL:
>>> +                     *atom_pll_id = ATOM_PPLL_INVALID;
>>> +                     break;
>>> +             case CLOCK_SOURCE_ID_DFS:
>>> +                     *atom_pll_id = ATOM_EXT_PLL1;
>>> +                     break;
>>> +             case CLOCK_SOURCE_ID_VCE:
>>> +                     /* for VCE encoding,
>>> +                      * we need to pass in ATOM_PPLL_INVALID
>>> +                      */
>>> +                     *atom_pll_id = ATOM_PPLL_INVALID;
>>> +                     break;
>>> +             case CLOCK_SOURCE_ID_DP_DTO:
>>> +                     /* When programming DP DTO PLL ID should be invalid */
>>> +                     *atom_pll_id = ATOM_PPLL_INVALID;
>>> +                     break;
>>> +             case CLOCK_SOURCE_ID_UNDEFINED:
>>> +                     BREAK_TO_DEBUGGER(); /* check when this will happen! */
>>> +                     *atom_pll_id = ATOM_PPLL_INVALID;
>>> +                     result = false;
>>> +                     break;
>>> +             default:
>>> +                     result = false;
>>> +                     break;
>>> +             }
>>> +
>>> +     return result;
>>> +}
>>> +
>>> +static uint8_t clock_source_id_to_atom_phy_clk_src_id(
>>> +             enum clock_source_id id)
>>> +{
>>> +     uint8_t atom_phy_clk_src_id = 0;
>>> +
>>> +     switch (id) {
>>> +     case CLOCK_SOURCE_ID_PLL0:
>>> +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
>>> +             break;
>>> +     case CLOCK_SOURCE_ID_PLL1:
>>> +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
>>> +             break;
>>> +     case CLOCK_SOURCE_ID_PLL2:
>>> +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
>>> +             break;
>>> +     case CLOCK_SOURCE_ID_EXTERNAL:
>>> +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
>>> +             break;
>>> +     default:
>>> +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
>>> +             break;
>>> +     }
>>> +
>>> +     return atom_phy_clk_src_id >> 2;
>>> +}
>>> +
>>> +static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
>>> +{
>>> +     uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
>>> +
>>> +     switch (s) {
>>> +     case SIGNAL_TYPE_DISPLAY_PORT:
>>> +     case SIGNAL_TYPE_EDP:
>>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
>>> +             break;
>>> +     case SIGNAL_TYPE_LVDS:
>>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_LVDS;
>>> +             break;
>>> +     case SIGNAL_TYPE_DVI_SINGLE_LINK:
>>> +     case SIGNAL_TYPE_DVI_DUAL_LINK:
>>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
>>> +             break;
>>> +     case SIGNAL_TYPE_HDMI_TYPE_A:
>>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_HDMI;
>>> +             break;
>>> +     case SIGNAL_TYPE_DISPLAY_PORT_MST:
>>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP_MST;
>>> +             break;
>>> +     default:
>>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
>>> +             break;
>>> +     }
>>> +
>>> +     return atom_dig_mode;
>>> +}
>>> +
>>> +static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
>>> +{
>>> +     uint8_t atom_hpd_sel = 0;
>>> +
>>> +     switch (id) {
>>> +     case HPD_SOURCEID1:
>>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL;
>>> +             break;
>>> +     case HPD_SOURCEID2:
>>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL;
>>> +             break;
>>> +     case HPD_SOURCEID3:
>>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL;
>>> +             break;
>>> +     case HPD_SOURCEID4:
>>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL;
>>> +             break;
>>> +     case HPD_SOURCEID5:
>>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL;
>>> +             break;
>>> +     case HPD_SOURCEID6:
>>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL;
>>> +             break;
>>> +     case HPD_SOURCEID_UNKNOWN:
>>> +     default:
>>> +             atom_hpd_sel = 0;
>>> +             break;
>>> +     }
>>> +     return atom_hpd_sel >> 4;
>>> +}
>>> +
>>> +static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
>>> +{
>>> +     uint8_t atom_dig_encoder_sel = 0;
>>> +
>>> +     switch (id) {
>>> +     case ENGINE_ID_DIGA:
>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
>>> +             break;
>>> +     case ENGINE_ID_DIGB:
>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
>>> +             break;
>>> +     case ENGINE_ID_DIGC:
>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
>>> +             break;
>>> +     case ENGINE_ID_DIGD:
>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
>>> +             break;
>>> +     case ENGINE_ID_DIGE:
>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
>>> +             break;
>>> +     case ENGINE_ID_DIGF:
>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
>>> +             break;
>>> +     case ENGINE_ID_DIGG:
>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
>>> +             break;
>>> +     default:
>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
>>> +             break;
>>> +     }
>>> +
>>> +     return atom_dig_encoder_sel;
>>> +}
>>> +
>>> +static uint8_t phy_id_to_atom(enum transmitter t)
>>> +{
>>> +     uint8_t atom_phy_id;
>>> +
>>> +     switch (t) {
>>> +     case TRANSMITTER_UNIPHY_A:
>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYA;
>>> +             break;
>>> +     case TRANSMITTER_UNIPHY_B:
>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYB;
>>> +             break;
>>> +     case TRANSMITTER_UNIPHY_C:
>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYC;
>>> +             break;
>>> +     case TRANSMITTER_UNIPHY_D:
>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYD;
>>> +             break;
>>> +     case TRANSMITTER_UNIPHY_E:
>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYE;
>>> +             break;
>>> +     case TRANSMITTER_UNIPHY_F:
>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYF;
>>> +             break;
>>> +     case TRANSMITTER_UNIPHY_G:
>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYG;
>>> +             break;
>>> +     default:
>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYA;
>>> +             break;
>>> +     }
>>> +     return atom_phy_id;
>>> +}
>>> +
>>> +static uint8_t disp_power_gating_action_to_atom(
>>> +     enum bp_pipe_control_action action)
>>> +{
>>> +     uint8_t atom_pipe_action = 0;
>>> +
>>> +     switch (action) {
>>> +     case ASIC_PIPE_DISABLE:
>>> +             atom_pipe_action = ATOM_DISABLE;
>>> +             break;
>>> +     case ASIC_PIPE_ENABLE:
>>> +             atom_pipe_action = ATOM_ENABLE;
>>> +             break;
>>> +     case ASIC_PIPE_INIT:
>>> +             atom_pipe_action = ATOM_INIT;
>>> +             break;
>>> +     default:
>>> +             BREAK_TO_DEBUGGER(); /* Unhandle action in driver! */
>>> +             break;
>>> +     }
>>> +
>>> +     return atom_pipe_action;
>>> +}
>>> +
>>> +static const struct command_table_helper command_table_helper_funcs = {
>>> +     .controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
>>> +     .encoder_action_to_atom = encoder_action_to_atom,
>>> +     .engine_bp_to_atom = engine_bp_to_atom,
>>> +     .clock_source_id_to_atom = clock_source_id_to_atom,
>>> +     .clock_source_id_to_atom_phy_clk_src_id =
>>> +             clock_source_id_to_atom_phy_clk_src_id,
>>> +     .signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
>>> +     .hpd_sel_to_atom = hpd_sel_to_atom,
>>> +     .dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
>>> +     .phy_id_to_atom = phy_id_to_atom,
>>> +     .disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
>>> +     .assign_control_parameter =
>>> +             dal_cmd_table_helper_assign_control_parameter,
>>> +     .clock_source_id_to_ref_clk_src =
>>> +             dal_cmd_table_helper_clock_source_id_to_ref_clk_src,
>>> +     .transmitter_bp_to_atom = dal_cmd_table_helper_transmitter_bp_to_atom,
>>> +     .encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
>>> +     .encoder_mode_bp_to_atom =
>>> +             dal_cmd_table_helper_encoder_mode_bp_to_atom,
>>> +};
>>> +
>>> +const struct command_table_helper *dal_cmd_tbl_helper_dce60_get_table(void)
>>> +{
>>> +     return &command_table_helper_funcs;
>>> +}
>>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
>>> new file mode 100644
>>> index 000000000000..591c796d0bf1
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
>>> @@ -0,0 +1,33 @@
>>> +/*
>>> + * Copyright 2012-15 Advanced Micro Devices, Inc.
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>> + * copy of this software and associated documentation files (the "Software"),
>>> + * to deal in the Software without restriction, including without limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>> + * Software is furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be included in
>>> + * all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>> + *
>>> + * Authors: AMD
>>> + *
>>> + */
>>> +
>>> +#ifndef __DAL_COMMAND_TABLE_HELPER_DCE60_H__
>>> +#define __DAL_COMMAND_TABLE_HELPER_DCE60_H__
>>> +
>>> +struct command_table_helper;
>>> +
>>> +const struct command_table_helper *dal_cmd_tbl_helper_dce60_get_table(void);
>>> +
>>> +#endif
>>>
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Re: [PATCH v2 04/10] drm/amd/display: dc/bios: add support for DCE6

[Alex Deucher]

On Wed, Oct 17, 2018 at 4:16 PM Wentland, Harry <Harry.Wentland@amd.com> wrote:
>
> On 2018-10-17 4:10 p.m., Alex Deucher wrote:
> > On Wed, Oct 17, 2018 at 3:54 PM Wentland, Harry <Harry.Wentland@amd.com> wrote:
> >>
> >> On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> >>> DCE6 targets are added replicating existing DCE8 implementation.
> >>> ---
> >>>  drivers/gpu/drm/amd/display/dc/bios/Makefile  |   9 +
> >>>  .../display/dc/bios/command_table_helper.c    |   8 +
> >>>  .../display/dc/bios/command_table_helper.h    |   3 +
> >>>  .../display/dc/bios/command_table_helper2.c   |   8 +
> >>>  .../display/dc/bios/command_table_helper2.h   |   3 +
> >>>  .../bios/dce60/command_table_helper_dce60.c   | 354 ++++++++++++++++++
> >>>  .../bios/dce60/command_table_helper_dce60.h   |  33 ++
> >>>  7 files changed, 418 insertions(+)
> >>>  create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
> >>>  create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile
> >>> index 239e86bbec5a..ed6b5e9763f6 100644
> >>> --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
> >>> +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
> >>> @@ -31,6 +31,15 @@ AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
> >>>
> >>>  AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
> >>>
> >>> +###############################################################################
> >>> +# DCE 6x
> >>> +###############################################################################
> >>> +# All DCE6.x are derived from DCE6.0, so 6.0 MUST be defined if ANY of
> >>> +# DCE6.x is compiled.
> >>> +ifdef CONFIG_DRM_AMD_DC_SI
> >>> +AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce60/command_table_helper_dce60.o
> >>> +endif
> >>> +
> >>>  ###############################################################################
> >>>  # DCE 8x
> >>>  ###############################################################################
> >>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> >>> index 253bbb1eea60..48b4ef03fc8f 100644
> >>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> >>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> >>> @@ -36,6 +36,14 @@ bool dal_bios_parser_init_cmd_tbl_helper(
> >>>       enum dce_version dce)
> >>>  {
> >>>       switch (dce) {
> >>> +#if defined(CONFIG_DRM_AMD_DC_SI)
> >>> +     case DCE_VERSION_6_0:
> >>> +     case DCE_VERSION_6_1:
> >>> +     case DCE_VERSION_6_4:
> >>> +             *h = dal_cmd_tbl_helper_dce60_get_table();
> >>
> >> Can we just point these to the dce80 version since they're exactly the same?
> >
> > Some of the dig transmitter and encoder cmd tables had different
> > versions on DCE6 vs 8.  I'm not sure if we need to do any different
> > translations for some of these.
> >
>
> Currently it's an exact copy. Since you remember differences it makes sense to duplicate this for DCE6 so we can update it for any difference if we'll need that.
>
> Mauro, ignore my comments in this case. :)

I just double checked the vbios DCE8 design documents and the cmd
tables are compatible (the only major difference was the addition of
the 7th phy which won't show up on DCE6, so not an issue).  I also
double check the cmd table versions on a few bioses and they are the
same.  We should be fine with just sharing the DCE8 code for DCE6 as
well.  Sorry for the noise.

Alex

>
> Harry
>
> > Alex
> >
> >>
> >>> +             return true;
> >>> +#endif
> >>> +
> >>>       case DCE_VERSION_8_0:
> >>>       case DCE_VERSION_8_1:
> >>>       case DCE_VERSION_8_3:
> >>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> >>> index 4c3789df253d..dfd30aaf4032 100644
> >>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> >>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> >>> @@ -26,6 +26,9 @@
> >>>  #ifndef __DAL_COMMAND_TABLE_HELPER_H__
> >>>  #define __DAL_COMMAND_TABLE_HELPER_H__
> >>>
> >>> +#if defined(CONFIG_DRM_AMD_DC_SI)
> >>> +#include "dce60/command_table_helper_dce60.h"
> >>> +#endif
> >>>  #include "dce80/command_table_helper_dce80.h"
> >>>  #include "dce110/command_table_helper_dce110.h"
> >>>  #include "dce112/command_table_helper_dce112.h"
> >>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> >>> index 65b006ad372e..92288c582934 100644
> >>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> >>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> >>> @@ -37,6 +37,14 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
> >>>       enum dce_version dce)
> >>>  {
> >>>       switch (dce) {
> >>> +#if defined(CONFIG_DRM_AMD_DC_SI)
> >>> +     case DCE_VERSION_6_0:
> >>> +     case DCE_VERSION_6_1:
> >>> +     case DCE_VERSION_6_4:
> >>> +             *h = dal_cmd_tbl_helper_dce60_get_table();
> >>
> >> Same as above.
> >>
> >> Harry
> >>
> >>> +             return true;
> >>> +#endif
> >>> +
> >>>       case DCE_VERSION_8_0:
> >>>       case DCE_VERSION_8_1:
> >>>       case DCE_VERSION_8_3:
> >>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> >>> index 785fcb20a1b9..66e0a3e73768 100644
> >>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> >>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> >>> @@ -26,6 +26,9 @@
> >>>  #ifndef __DAL_COMMAND_TABLE_HELPER2_H__
> >>>  #define __DAL_COMMAND_TABLE_HELPER2_H__
> >>>
> >>> +#if defined(CONFIG_DRM_AMD_DC_SI)
> >>> +#include "dce60/command_table_helper_dce60.h"
> >>> +#endif
> >>>  #include "dce80/command_table_helper_dce80.h"
> >>>  #include "dce110/command_table_helper_dce110.h"
> >>>  #include "dce112/command_table_helper2_dce112.h"
> >>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
> >>> new file mode 100644
> >>> index 000000000000..552778ce9835
> >>> --- /dev/null
> >>> +++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
> >>> @@ -0,0 +1,354 @@
> >>> +/*
> >>> + * Copyright 2012-15 Advanced Micro Devices, Inc.
> >>> + *
> >>> + * Permission is hereby granted, free of charge, to any person obtaining a
> >>> + * copy of this software and associated documentation files (the "Software"),
> >>> + * to deal in the Software without restriction, including without limitation
> >>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> >>> + * and/or sell copies of the Software, and to permit persons to whom the
> >>> + * Software is furnished to do so, subject to the following conditions:
> >>> + *
> >>> + * The above copyright notice and this permission notice shall be included in
> >>> + * all copies or substantial portions of the Software.
> >>> + *
> >>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> >>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> >>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> >>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> >>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> >>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> >>> + * OTHER DEALINGS IN THE SOFTWARE.
> >>> + *
> >>> + * Authors: AMD
> >>> + *
> >>> + */
> >>> +
> >>> +#include "dm_services.h"
> >>> +
> >>> +#include "atom.h"
> >>> +
> >>> +#include "include/grph_object_id.h"
> >>> +#include "include/grph_object_defs.h"
> >>> +#include "include/bios_parser_types.h"
> >>> +
> >>> +#include "../command_table_helper.h"
> >>> +
> >>> +static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
> >>> +{
> >>> +     uint8_t atom_action = 0;
> >>> +
> >>> +     switch (action) {
> >>> +     case ENCODER_CONTROL_ENABLE:
> >>> +             atom_action = ATOM_ENABLE;
> >>> +             break;
> >>> +     case ENCODER_CONTROL_DISABLE:
> >>> +             atom_action = ATOM_DISABLE;
> >>> +             break;
> >>> +     case ENCODER_CONTROL_SETUP:
> >>> +             atom_action = ATOM_ENCODER_CMD_SETUP;
> >>> +             break;
> >>> +     case ENCODER_CONTROL_INIT:
> >>> +             atom_action = ATOM_ENCODER_INIT;
> >>> +             break;
> >>> +     default:
> >>> +             BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
> >>> +             break;
> >>> +     }
> >>> +
> >>> +     return atom_action;
> >>> +}
> >>> +
> >>> +static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
> >>> +{
> >>> +     bool result = false;
> >>> +
> >>> +     if (atom_engine_id != NULL)
> >>> +             switch (id) {
> >>> +             case ENGINE_ID_DIGA:
> >>> +                     *atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
> >>> +                     result = true;
> >>> +                     break;
> >>> +             case ENGINE_ID_DIGB:
> >>> +                     *atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
> >>> +                     result = true;
> >>> +                     break;
> >>> +             case ENGINE_ID_DIGC:
> >>> +                     *atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
> >>> +                     result = true;
> >>> +                     break;
> >>> +             case ENGINE_ID_DIGD:
> >>> +                     *atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
> >>> +                     result = true;
> >>> +                     break;
> >>> +             case ENGINE_ID_DIGE:
> >>> +                     *atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
> >>> +                     result = true;
> >>> +                     break;
> >>> +             case ENGINE_ID_DIGF:
> >>> +                     *atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
> >>> +                     result = true;
> >>> +                     break;
> >>> +             case ENGINE_ID_DIGG:
> >>> +                     *atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
> >>> +                     result = true;
> >>> +                     break;
> >>> +             case ENGINE_ID_DACA:
> >>> +                     *atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
> >>> +                     result = true;
> >>> +                     break;
> >>> +             default:
> >>> +                     break;
> >>> +             }
> >>> +
> >>> +     return result;
> >>> +}
> >>> +
> >>> +static bool clock_source_id_to_atom(
> >>> +     enum clock_source_id id,
> >>> +     uint32_t *atom_pll_id)
> >>> +{
> >>> +     bool result = true;
> >>> +
> >>> +     if (atom_pll_id != NULL)
> >>> +             switch (id) {
> >>> +             case CLOCK_SOURCE_ID_PLL0:
> >>> +                     *atom_pll_id = ATOM_PPLL0;
> >>> +                     break;
> >>> +             case CLOCK_SOURCE_ID_PLL1:
> >>> +                     *atom_pll_id = ATOM_PPLL1;
> >>> +                     break;
> >>> +             case CLOCK_SOURCE_ID_PLL2:
> >>> +                     *atom_pll_id = ATOM_PPLL2;
> >>> +                     break;
> >>> +             case CLOCK_SOURCE_ID_EXTERNAL:
> >>> +                     *atom_pll_id = ATOM_PPLL_INVALID;
> >>> +                     break;
> >>> +             case CLOCK_SOURCE_ID_DFS:
> >>> +                     *atom_pll_id = ATOM_EXT_PLL1;
> >>> +                     break;
> >>> +             case CLOCK_SOURCE_ID_VCE:
> >>> +                     /* for VCE encoding,
> >>> +                      * we need to pass in ATOM_PPLL_INVALID
> >>> +                      */
> >>> +                     *atom_pll_id = ATOM_PPLL_INVALID;
> >>> +                     break;
> >>> +             case CLOCK_SOURCE_ID_DP_DTO:
> >>> +                     /* When programming DP DTO PLL ID should be invalid */
> >>> +                     *atom_pll_id = ATOM_PPLL_INVALID;
> >>> +                     break;
> >>> +             case CLOCK_SOURCE_ID_UNDEFINED:
> >>> +                     BREAK_TO_DEBUGGER(); /* check when this will happen! */
> >>> +                     *atom_pll_id = ATOM_PPLL_INVALID;
> >>> +                     result = false;
> >>> +                     break;
> >>> +             default:
> >>> +                     result = false;
> >>> +                     break;
> >>> +             }
> >>> +
> >>> +     return result;
> >>> +}
> >>> +
> >>> +static uint8_t clock_source_id_to_atom_phy_clk_src_id(
> >>> +             enum clock_source_id id)
> >>> +{
> >>> +     uint8_t atom_phy_clk_src_id = 0;
> >>> +
> >>> +     switch (id) {
> >>> +     case CLOCK_SOURCE_ID_PLL0:
> >>> +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
> >>> +             break;
> >>> +     case CLOCK_SOURCE_ID_PLL1:
> >>> +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
> >>> +             break;
> >>> +     case CLOCK_SOURCE_ID_PLL2:
> >>> +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
> >>> +             break;
> >>> +     case CLOCK_SOURCE_ID_EXTERNAL:
> >>> +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
> >>> +             break;
> >>> +     default:
> >>> +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
> >>> +             break;
> >>> +     }
> >>> +
> >>> +     return atom_phy_clk_src_id >> 2;
> >>> +}
> >>> +
> >>> +static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
> >>> +{
> >>> +     uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
> >>> +
> >>> +     switch (s) {
> >>> +     case SIGNAL_TYPE_DISPLAY_PORT:
> >>> +     case SIGNAL_TYPE_EDP:
> >>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
> >>> +             break;
> >>> +     case SIGNAL_TYPE_LVDS:
> >>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_LVDS;
> >>> +             break;
> >>> +     case SIGNAL_TYPE_DVI_SINGLE_LINK:
> >>> +     case SIGNAL_TYPE_DVI_DUAL_LINK:
> >>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
> >>> +             break;
> >>> +     case SIGNAL_TYPE_HDMI_TYPE_A:
> >>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_HDMI;
> >>> +             break;
> >>> +     case SIGNAL_TYPE_DISPLAY_PORT_MST:
> >>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP_MST;
> >>> +             break;
> >>> +     default:
> >>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
> >>> +             break;
> >>> +     }
> >>> +
> >>> +     return atom_dig_mode;
> >>> +}
> >>> +
> >>> +static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
> >>> +{
> >>> +     uint8_t atom_hpd_sel = 0;
> >>> +
> >>> +     switch (id) {
> >>> +     case HPD_SOURCEID1:
> >>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL;
> >>> +             break;
> >>> +     case HPD_SOURCEID2:
> >>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL;
> >>> +             break;
> >>> +     case HPD_SOURCEID3:
> >>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL;
> >>> +             break;
> >>> +     case HPD_SOURCEID4:
> >>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL;
> >>> +             break;
> >>> +     case HPD_SOURCEID5:
> >>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL;
> >>> +             break;
> >>> +     case HPD_SOURCEID6:
> >>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL;
> >>> +             break;
> >>> +     case HPD_SOURCEID_UNKNOWN:
> >>> +     default:
> >>> +             atom_hpd_sel = 0;
> >>> +             break;
> >>> +     }
> >>> +     return atom_hpd_sel >> 4;
> >>> +}
> >>> +
> >>> +static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
> >>> +{
> >>> +     uint8_t atom_dig_encoder_sel = 0;
> >>> +
> >>> +     switch (id) {
> >>> +     case ENGINE_ID_DIGA:
> >>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
> >>> +             break;
> >>> +     case ENGINE_ID_DIGB:
> >>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
> >>> +             break;
> >>> +     case ENGINE_ID_DIGC:
> >>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
> >>> +             break;
> >>> +     case ENGINE_ID_DIGD:
> >>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
> >>> +             break;
> >>> +     case ENGINE_ID_DIGE:
> >>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
> >>> +             break;
> >>> +     case ENGINE_ID_DIGF:
> >>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
> >>> +             break;
> >>> +     case ENGINE_ID_DIGG:
> >>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
> >>> +             break;
> >>> +     default:
> >>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
> >>> +             break;
> >>> +     }
> >>> +
> >>> +     return atom_dig_encoder_sel;
> >>> +}
> >>> +
> >>> +static uint8_t phy_id_to_atom(enum transmitter t)
> >>> +{
> >>> +     uint8_t atom_phy_id;
> >>> +
> >>> +     switch (t) {
> >>> +     case TRANSMITTER_UNIPHY_A:
> >>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYA;
> >>> +             break;
> >>> +     case TRANSMITTER_UNIPHY_B:
> >>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYB;
> >>> +             break;
> >>> +     case TRANSMITTER_UNIPHY_C:
> >>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYC;
> >>> +             break;
> >>> +     case TRANSMITTER_UNIPHY_D:
> >>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYD;
> >>> +             break;
> >>> +     case TRANSMITTER_UNIPHY_E:
> >>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYE;
> >>> +             break;
> >>> +     case TRANSMITTER_UNIPHY_F:
> >>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYF;
> >>> +             break;
> >>> +     case TRANSMITTER_UNIPHY_G:
> >>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYG;
> >>> +             break;
> >>> +     default:
> >>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYA;
> >>> +             break;
> >>> +     }
> >>> +     return atom_phy_id;
> >>> +}
> >>> +
> >>> +static uint8_t disp_power_gating_action_to_atom(
> >>> +     enum bp_pipe_control_action action)
> >>> +{
> >>> +     uint8_t atom_pipe_action = 0;
> >>> +
> >>> +     switch (action) {
> >>> +     case ASIC_PIPE_DISABLE:
> >>> +             atom_pipe_action = ATOM_DISABLE;
> >>> +             break;
> >>> +     case ASIC_PIPE_ENABLE:
> >>> +             atom_pipe_action = ATOM_ENABLE;
> >>> +             break;
> >>> +     case ASIC_PIPE_INIT:
> >>> +             atom_pipe_action = ATOM_INIT;
> >>> +             break;
> >>> +     default:
> >>> +             BREAK_TO_DEBUGGER(); /* Unhandle action in driver! */
> >>> +             break;
> >>> +     }
> >>> +
> >>> +     return atom_pipe_action;
> >>> +}
> >>> +
> >>> +static const struct command_table_helper command_table_helper_funcs = {
> >>> +     .controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
> >>> +     .encoder_action_to_atom = encoder_action_to_atom,
> >>> +     .engine_bp_to_atom = engine_bp_to_atom,
> >>> +     .clock_source_id_to_atom = clock_source_id_to_atom,
> >>> +     .clock_source_id_to_atom_phy_clk_src_id =
> >>> +             clock_source_id_to_atom_phy_clk_src_id,
> >>> +     .signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
> >>> +     .hpd_sel_to_atom = hpd_sel_to_atom,
> >>> +     .dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
> >>> +     .phy_id_to_atom = phy_id_to_atom,
> >>> +     .disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
> >>> +     .assign_control_parameter =
> >>> +             dal_cmd_table_helper_assign_control_parameter,
> >>> +     .clock_source_id_to_ref_clk_src =
> >>> +             dal_cmd_table_helper_clock_source_id_to_ref_clk_src,
> >>> +     .transmitter_bp_to_atom = dal_cmd_table_helper_transmitter_bp_to_atom,
> >>> +     .encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
> >>> +     .encoder_mode_bp_to_atom =
> >>> +             dal_cmd_table_helper_encoder_mode_bp_to_atom,
> >>> +};
> >>> +
> >>> +const struct command_table_helper *dal_cmd_tbl_helper_dce60_get_table(void)
> >>> +{
> >>> +     return &command_table_helper_funcs;
> >>> +}
> >>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
> >>> new file mode 100644
> >>> index 000000000000..591c796d0bf1
> >>> --- /dev/null
> >>> +++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
> >>> @@ -0,0 +1,33 @@
> >>> +/*
> >>> + * Copyright 2012-15 Advanced Micro Devices, Inc.
> >>> + *
> >>> + * Permission is hereby granted, free of charge, to any person obtaining a
> >>> + * copy of this software and associated documentation files (the "Software"),
> >>> + * to deal in the Software without restriction, including without limitation
> >>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> >>> + * and/or sell copies of the Software, and to permit persons to whom the
> >>> + * Software is furnished to do so, subject to the following conditions:
> >>> + *
> >>> + * The above copyright notice and this permission notice shall be included in
> >>> + * all copies or substantial portions of the Software.
> >>> + *
> >>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> >>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> >>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> >>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> >>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> >>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> >>> + * OTHER DEALINGS IN THE SOFTWARE.
> >>> + *
> >>> + * Authors: AMD
> >>> + *
> >>> + */
> >>> +
> >>> +#ifndef __DAL_COMMAND_TABLE_HELPER_DCE60_H__
> >>> +#define __DAL_COMMAND_TABLE_HELPER_DCE60_H__
> >>> +
> >>> +struct command_table_helper;
> >>> +
> >>> +const struct command_table_helper *dal_cmd_tbl_helper_dce60_get_table(void);
> >>> +
> >>> +#endif
> >>>
> >> _______________________________________________
> >> amd-gfx mailing list
> >> amd-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> >
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Re: [PATCH v2 04/10] drm/amd/display: dc/bios: add support for DCE6

[Wentland, Harry]

On 2018-10-17 4:42 p.m., Alex Deucher wrote:
> On Wed, Oct 17, 2018 at 4:16 PM Wentland, Harry <Harry.Wentland@amd.com> wrote:
>>
>> On 2018-10-17 4:10 p.m., Alex Deucher wrote:
>>> On Wed, Oct 17, 2018 at 3:54 PM Wentland, Harry <Harry.Wentland@amd.com> wrote:
>>>>
>>>> On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
>>>>> DCE6 targets are added replicating existing DCE8 implementation.
>>>>> ---
>>>>>  drivers/gpu/drm/amd/display/dc/bios/Makefile  |   9 +
>>>>>  .../display/dc/bios/command_table_helper.c    |   8 +
>>>>>  .../display/dc/bios/command_table_helper.h    |   3 +
>>>>>  .../display/dc/bios/command_table_helper2.c   |   8 +
>>>>>  .../display/dc/bios/command_table_helper2.h   |   3 +
>>>>>  .../bios/dce60/command_table_helper_dce60.c   | 354 ++++++++++++++++++
>>>>>  .../bios/dce60/command_table_helper_dce60.h   |  33 ++
>>>>>  7 files changed, 418 insertions(+)
>>>>>  create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
>>>>>  create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile
>>>>> index 239e86bbec5a..ed6b5e9763f6 100644
>>>>> --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
>>>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
>>>>> @@ -31,6 +31,15 @@ AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
>>>>>
>>>>>  AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
>>>>>
>>>>> +###############################################################################
>>>>> +# DCE 6x
>>>>> +###############################################################################
>>>>> +# All DCE6.x are derived from DCE6.0, so 6.0 MUST be defined if ANY of
>>>>> +# DCE6.x is compiled.
>>>>> +ifdef CONFIG_DRM_AMD_DC_SI
>>>>> +AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce60/command_table_helper_dce60.o
>>>>> +endif
>>>>> +
>>>>>  ###############################################################################
>>>>>  # DCE 8x
>>>>>  ###############################################################################
>>>>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
>>>>> index 253bbb1eea60..48b4ef03fc8f 100644
>>>>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
>>>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
>>>>> @@ -36,6 +36,14 @@ bool dal_bios_parser_init_cmd_tbl_helper(
>>>>>       enum dce_version dce)
>>>>>  {
>>>>>       switch (dce) {
>>>>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>>>>> +     case DCE_VERSION_6_0:
>>>>> +     case DCE_VERSION_6_1:
>>>>> +     case DCE_VERSION_6_4:
>>>>> +             *h = dal_cmd_tbl_helper_dce60_get_table();
>>>>
>>>> Can we just point these to the dce80 version since they're exactly the same?
>>>
>>> Some of the dig transmitter and encoder cmd tables had different
>>> versions on DCE6 vs 8.  I'm not sure if we need to do any different
>>> translations for some of these.
>>>
>>
>> Currently it's an exact copy. Since you remember differences it makes sense to duplicate this for DCE6 so we can update it for any difference if we'll need that.
>>
>> Mauro, ignore my comments in this case. :)
> 
> I just double checked the vbios DCE8 design documents and the cmd
> tables are compatible (the only major difference was the addition of
> the 7th phy which won't show up on DCE6, so not an issue).  I also
> double check the cmd table versions on a few bioses and they are the
> same.  We should be fine with just sharing the DCE8 code for DCE6 as
> well.  Sorry for the noise.
> 

Thanks for looking into the design docs. Looks like we're good to share this code then.

Harry

> Alex
> 
>>
>> Harry
>>
>>> Alex
>>>
>>>>
>>>>> +             return true;
>>>>> +#endif
>>>>> +
>>>>>       case DCE_VERSION_8_0:
>>>>>       case DCE_VERSION_8_1:
>>>>>       case DCE_VERSION_8_3:
>>>>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
>>>>> index 4c3789df253d..dfd30aaf4032 100644
>>>>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
>>>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
>>>>> @@ -26,6 +26,9 @@
>>>>>  #ifndef __DAL_COMMAND_TABLE_HELPER_H__
>>>>>  #define __DAL_COMMAND_TABLE_HELPER_H__
>>>>>
>>>>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>>>>> +#include "dce60/command_table_helper_dce60.h"
>>>>> +#endif
>>>>>  #include "dce80/command_table_helper_dce80.h"
>>>>>  #include "dce110/command_table_helper_dce110.h"
>>>>>  #include "dce112/command_table_helper_dce112.h"
>>>>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>>>> index 65b006ad372e..92288c582934 100644
>>>>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>>>> @@ -37,6 +37,14 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>>>>>       enum dce_version dce)
>>>>>  {
>>>>>       switch (dce) {
>>>>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>>>>> +     case DCE_VERSION_6_0:
>>>>> +     case DCE_VERSION_6_1:
>>>>> +     case DCE_VERSION_6_4:
>>>>> +             *h = dal_cmd_tbl_helper_dce60_get_table();
>>>>
>>>> Same as above.
>>>>
>>>> Harry
>>>>
>>>>> +             return true;
>>>>> +#endif
>>>>> +
>>>>>       case DCE_VERSION_8_0:
>>>>>       case DCE_VERSION_8_1:
>>>>>       case DCE_VERSION_8_3:
>>>>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
>>>>> index 785fcb20a1b9..66e0a3e73768 100644
>>>>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
>>>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
>>>>> @@ -26,6 +26,9 @@
>>>>>  #ifndef __DAL_COMMAND_TABLE_HELPER2_H__
>>>>>  #define __DAL_COMMAND_TABLE_HELPER2_H__
>>>>>
>>>>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>>>>> +#include "dce60/command_table_helper_dce60.h"
>>>>> +#endif
>>>>>  #include "dce80/command_table_helper_dce80.h"
>>>>>  #include "dce110/command_table_helper_dce110.h"
>>>>>  #include "dce112/command_table_helper2_dce112.h"
>>>>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
>>>>> new file mode 100644
>>>>> index 000000000000..552778ce9835
>>>>> --- /dev/null
>>>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
>>>>> @@ -0,0 +1,354 @@
>>>>> +/*
>>>>> + * Copyright 2012-15 Advanced Micro Devices, Inc.
>>>>> + *
>>>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>>>> + * copy of this software and associated documentation files (the "Software"),
>>>>> + * to deal in the Software without restriction, including without limitation
>>>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>>>> + * Software is furnished to do so, subject to the following conditions:
>>>>> + *
>>>>> + * The above copyright notice and this permission notice shall be included in
>>>>> + * all copies or substantial portions of the Software.
>>>>> + *
>>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>>>>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>>>>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>>>>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>>>> + *
>>>>> + * Authors: AMD
>>>>> + *
>>>>> + */
>>>>> +
>>>>> +#include "dm_services.h"
>>>>> +
>>>>> +#include "atom.h"
>>>>> +
>>>>> +#include "include/grph_object_id.h"
>>>>> +#include "include/grph_object_defs.h"
>>>>> +#include "include/bios_parser_types.h"
>>>>> +
>>>>> +#include "../command_table_helper.h"
>>>>> +
>>>>> +static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
>>>>> +{
>>>>> +     uint8_t atom_action = 0;
>>>>> +
>>>>> +     switch (action) {
>>>>> +     case ENCODER_CONTROL_ENABLE:
>>>>> +             atom_action = ATOM_ENABLE;
>>>>> +             break;
>>>>> +     case ENCODER_CONTROL_DISABLE:
>>>>> +             atom_action = ATOM_DISABLE;
>>>>> +             break;
>>>>> +     case ENCODER_CONTROL_SETUP:
>>>>> +             atom_action = ATOM_ENCODER_CMD_SETUP;
>>>>> +             break;
>>>>> +     case ENCODER_CONTROL_INIT:
>>>>> +             atom_action = ATOM_ENCODER_INIT;
>>>>> +             break;
>>>>> +     default:
>>>>> +             BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
>>>>> +             break;
>>>>> +     }
>>>>> +
>>>>> +     return atom_action;
>>>>> +}
>>>>> +
>>>>> +static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
>>>>> +{
>>>>> +     bool result = false;
>>>>> +
>>>>> +     if (atom_engine_id != NULL)
>>>>> +             switch (id) {
>>>>> +             case ENGINE_ID_DIGA:
>>>>> +                     *atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
>>>>> +                     result = true;
>>>>> +                     break;
>>>>> +             case ENGINE_ID_DIGB:
>>>>> +                     *atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
>>>>> +                     result = true;
>>>>> +                     break;
>>>>> +             case ENGINE_ID_DIGC:
>>>>> +                     *atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
>>>>> +                     result = true;
>>>>> +                     break;
>>>>> +             case ENGINE_ID_DIGD:
>>>>> +                     *atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
>>>>> +                     result = true;
>>>>> +                     break;
>>>>> +             case ENGINE_ID_DIGE:
>>>>> +                     *atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
>>>>> +                     result = true;
>>>>> +                     break;
>>>>> +             case ENGINE_ID_DIGF:
>>>>> +                     *atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
>>>>> +                     result = true;
>>>>> +                     break;
>>>>> +             case ENGINE_ID_DIGG:
>>>>> +                     *atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
>>>>> +                     result = true;
>>>>> +                     break;
>>>>> +             case ENGINE_ID_DACA:
>>>>> +                     *atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
>>>>> +                     result = true;
>>>>> +                     break;
>>>>> +             default:
>>>>> +                     break;
>>>>> +             }
>>>>> +
>>>>> +     return result;
>>>>> +}
>>>>> +
>>>>> +static bool clock_source_id_to_atom(
>>>>> +     enum clock_source_id id,
>>>>> +     uint32_t *atom_pll_id)
>>>>> +{
>>>>> +     bool result = true;
>>>>> +
>>>>> +     if (atom_pll_id != NULL)
>>>>> +             switch (id) {
>>>>> +             case CLOCK_SOURCE_ID_PLL0:
>>>>> +                     *atom_pll_id = ATOM_PPLL0;
>>>>> +                     break;
>>>>> +             case CLOCK_SOURCE_ID_PLL1:
>>>>> +                     *atom_pll_id = ATOM_PPLL1;
>>>>> +                     break;
>>>>> +             case CLOCK_SOURCE_ID_PLL2:
>>>>> +                     *atom_pll_id = ATOM_PPLL2;
>>>>> +                     break;
>>>>> +             case CLOCK_SOURCE_ID_EXTERNAL:
>>>>> +                     *atom_pll_id = ATOM_PPLL_INVALID;
>>>>> +                     break;
>>>>> +             case CLOCK_SOURCE_ID_DFS:
>>>>> +                     *atom_pll_id = ATOM_EXT_PLL1;
>>>>> +                     break;
>>>>> +             case CLOCK_SOURCE_ID_VCE:
>>>>> +                     /* for VCE encoding,
>>>>> +                      * we need to pass in ATOM_PPLL_INVALID
>>>>> +                      */
>>>>> +                     *atom_pll_id = ATOM_PPLL_INVALID;
>>>>> +                     break;
>>>>> +             case CLOCK_SOURCE_ID_DP_DTO:
>>>>> +                     /* When programming DP DTO PLL ID should be invalid */
>>>>> +                     *atom_pll_id = ATOM_PPLL_INVALID;
>>>>> +                     break;
>>>>> +             case CLOCK_SOURCE_ID_UNDEFINED:
>>>>> +                     BREAK_TO_DEBUGGER(); /* check when this will happen! */
>>>>> +                     *atom_pll_id = ATOM_PPLL_INVALID;
>>>>> +                     result = false;
>>>>> +                     break;
>>>>> +             default:
>>>>> +                     result = false;
>>>>> +                     break;
>>>>> +             }
>>>>> +
>>>>> +     return result;
>>>>> +}
>>>>> +
>>>>> +static uint8_t clock_source_id_to_atom_phy_clk_src_id(
>>>>> +             enum clock_source_id id)
>>>>> +{
>>>>> +     uint8_t atom_phy_clk_src_id = 0;
>>>>> +
>>>>> +     switch (id) {
>>>>> +     case CLOCK_SOURCE_ID_PLL0:
>>>>> +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
>>>>> +             break;
>>>>> +     case CLOCK_SOURCE_ID_PLL1:
>>>>> +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
>>>>> +             break;
>>>>> +     case CLOCK_SOURCE_ID_PLL2:
>>>>> +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
>>>>> +             break;
>>>>> +     case CLOCK_SOURCE_ID_EXTERNAL:
>>>>> +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
>>>>> +             break;
>>>>> +     default:
>>>>> +             atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
>>>>> +             break;
>>>>> +     }
>>>>> +
>>>>> +     return atom_phy_clk_src_id >> 2;
>>>>> +}
>>>>> +
>>>>> +static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
>>>>> +{
>>>>> +     uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
>>>>> +
>>>>> +     switch (s) {
>>>>> +     case SIGNAL_TYPE_DISPLAY_PORT:
>>>>> +     case SIGNAL_TYPE_EDP:
>>>>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
>>>>> +             break;
>>>>> +     case SIGNAL_TYPE_LVDS:
>>>>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_LVDS;
>>>>> +             break;
>>>>> +     case SIGNAL_TYPE_DVI_SINGLE_LINK:
>>>>> +     case SIGNAL_TYPE_DVI_DUAL_LINK:
>>>>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
>>>>> +             break;
>>>>> +     case SIGNAL_TYPE_HDMI_TYPE_A:
>>>>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_HDMI;
>>>>> +             break;
>>>>> +     case SIGNAL_TYPE_DISPLAY_PORT_MST:
>>>>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP_MST;
>>>>> +             break;
>>>>> +     default:
>>>>> +             atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
>>>>> +             break;
>>>>> +     }
>>>>> +
>>>>> +     return atom_dig_mode;
>>>>> +}
>>>>> +
>>>>> +static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
>>>>> +{
>>>>> +     uint8_t atom_hpd_sel = 0;
>>>>> +
>>>>> +     switch (id) {
>>>>> +     case HPD_SOURCEID1:
>>>>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL;
>>>>> +             break;
>>>>> +     case HPD_SOURCEID2:
>>>>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL;
>>>>> +             break;
>>>>> +     case HPD_SOURCEID3:
>>>>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL;
>>>>> +             break;
>>>>> +     case HPD_SOURCEID4:
>>>>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL;
>>>>> +             break;
>>>>> +     case HPD_SOURCEID5:
>>>>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL;
>>>>> +             break;
>>>>> +     case HPD_SOURCEID6:
>>>>> +             atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL;
>>>>> +             break;
>>>>> +     case HPD_SOURCEID_UNKNOWN:
>>>>> +     default:
>>>>> +             atom_hpd_sel = 0;
>>>>> +             break;
>>>>> +     }
>>>>> +     return atom_hpd_sel >> 4;
>>>>> +}
>>>>> +
>>>>> +static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
>>>>> +{
>>>>> +     uint8_t atom_dig_encoder_sel = 0;
>>>>> +
>>>>> +     switch (id) {
>>>>> +     case ENGINE_ID_DIGA:
>>>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
>>>>> +             break;
>>>>> +     case ENGINE_ID_DIGB:
>>>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
>>>>> +             break;
>>>>> +     case ENGINE_ID_DIGC:
>>>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
>>>>> +             break;
>>>>> +     case ENGINE_ID_DIGD:
>>>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
>>>>> +             break;
>>>>> +     case ENGINE_ID_DIGE:
>>>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
>>>>> +             break;
>>>>> +     case ENGINE_ID_DIGF:
>>>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
>>>>> +             break;
>>>>> +     case ENGINE_ID_DIGG:
>>>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
>>>>> +             break;
>>>>> +     default:
>>>>> +             atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
>>>>> +             break;
>>>>> +     }
>>>>> +
>>>>> +     return atom_dig_encoder_sel;
>>>>> +}
>>>>> +
>>>>> +static uint8_t phy_id_to_atom(enum transmitter t)
>>>>> +{
>>>>> +     uint8_t atom_phy_id;
>>>>> +
>>>>> +     switch (t) {
>>>>> +     case TRANSMITTER_UNIPHY_A:
>>>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYA;
>>>>> +             break;
>>>>> +     case TRANSMITTER_UNIPHY_B:
>>>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYB;
>>>>> +             break;
>>>>> +     case TRANSMITTER_UNIPHY_C:
>>>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYC;
>>>>> +             break;
>>>>> +     case TRANSMITTER_UNIPHY_D:
>>>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYD;
>>>>> +             break;
>>>>> +     case TRANSMITTER_UNIPHY_E:
>>>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYE;
>>>>> +             break;
>>>>> +     case TRANSMITTER_UNIPHY_F:
>>>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYF;
>>>>> +             break;
>>>>> +     case TRANSMITTER_UNIPHY_G:
>>>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYG;
>>>>> +             break;
>>>>> +     default:
>>>>> +             atom_phy_id = ATOM_PHY_ID_UNIPHYA;
>>>>> +             break;
>>>>> +     }
>>>>> +     return atom_phy_id;
>>>>> +}
>>>>> +
>>>>> +static uint8_t disp_power_gating_action_to_atom(
>>>>> +     enum bp_pipe_control_action action)
>>>>> +{
>>>>> +     uint8_t atom_pipe_action = 0;
>>>>> +
>>>>> +     switch (action) {
>>>>> +     case ASIC_PIPE_DISABLE:
>>>>> +             atom_pipe_action = ATOM_DISABLE;
>>>>> +             break;
>>>>> +     case ASIC_PIPE_ENABLE:
>>>>> +             atom_pipe_action = ATOM_ENABLE;
>>>>> +             break;
>>>>> +     case ASIC_PIPE_INIT:
>>>>> +             atom_pipe_action = ATOM_INIT;
>>>>> +             break;
>>>>> +     default:
>>>>> +             BREAK_TO_DEBUGGER(); /* Unhandle action in driver! */
>>>>> +             break;
>>>>> +     }
>>>>> +
>>>>> +     return atom_pipe_action;
>>>>> +}
>>>>> +
>>>>> +static const struct command_table_helper command_table_helper_funcs = {
>>>>> +     .controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
>>>>> +     .encoder_action_to_atom = encoder_action_to_atom,
>>>>> +     .engine_bp_to_atom = engine_bp_to_atom,
>>>>> +     .clock_source_id_to_atom = clock_source_id_to_atom,
>>>>> +     .clock_source_id_to_atom_phy_clk_src_id =
>>>>> +             clock_source_id_to_atom_phy_clk_src_id,
>>>>> +     .signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
>>>>> +     .hpd_sel_to_atom = hpd_sel_to_atom,
>>>>> +     .dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
>>>>> +     .phy_id_to_atom = phy_id_to_atom,
>>>>> +     .disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
>>>>> +     .assign_control_parameter =
>>>>> +             dal_cmd_table_helper_assign_control_parameter,
>>>>> +     .clock_source_id_to_ref_clk_src =
>>>>> +             dal_cmd_table_helper_clock_source_id_to_ref_clk_src,
>>>>> +     .transmitter_bp_to_atom = dal_cmd_table_helper_transmitter_bp_to_atom,
>>>>> +     .encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
>>>>> +     .encoder_mode_bp_to_atom =
>>>>> +             dal_cmd_table_helper_encoder_mode_bp_to_atom,
>>>>> +};
>>>>> +
>>>>> +const struct command_table_helper *dal_cmd_tbl_helper_dce60_get_table(void)
>>>>> +{
>>>>> +     return &command_table_helper_funcs;
>>>>> +}
>>>>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
>>>>> new file mode 100644
>>>>> index 000000000000..591c796d0bf1
>>>>> --- /dev/null
>>>>> +++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
>>>>> @@ -0,0 +1,33 @@
>>>>> +/*
>>>>> + * Copyright 2012-15 Advanced Micro Devices, Inc.
>>>>> + *
>>>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>>>> + * copy of this software and associated documentation files (the "Software"),
>>>>> + * to deal in the Software without restriction, including without limitation
>>>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>>>> + * Software is furnished to do so, subject to the following conditions:
>>>>> + *
>>>>> + * The above copyright notice and this permission notice shall be included in
>>>>> + * all copies or substantial portions of the Software.
>>>>> + *
>>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>>>>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>>>>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>>>>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>>>> + *
>>>>> + * Authors: AMD
>>>>> + *
>>>>> + */
>>>>> +
>>>>> +#ifndef __DAL_COMMAND_TABLE_HELPER_DCE60_H__
>>>>> +#define __DAL_COMMAND_TABLE_HELPER_DCE60_H__
>>>>> +
>>>>> +struct command_table_helper;
>>>>> +
>>>>> +const struct command_table_helper *dal_cmd_tbl_helper_dce60_get_table(void);
>>>>> +
>>>>> +#endif
>>>>>
>>>> _______________________________________________
>>>> amd-gfx mailing list
>>>> amd-gfx@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 05/10] drm/amd/display: dc/gpio: add support for DCE6

[Mauro Rossi]

DCE6 targets are added replicating existing DCE8 implementation.
---
 drivers/gpu/drm/amd/display/dc/gpio/Makefile  |  12 +
 .../display/dc/gpio/dce60/hw_factory_dce60.c  | 174 ++++++++
 .../display/dc/gpio/dce60/hw_factory_dce60.h  |  32 ++
 .../dc/gpio/dce60/hw_translate_dce60.c        | 411 ++++++++++++++++++
 .../dc/gpio/dce60/hw_translate_dce60.h        |  32 ++
 .../gpu/drm/amd/display/dc/gpio/hw_factory.c  |  10 +
 .../drm/amd/display/dc/gpio/hw_translate.c    |  10 +
 7 files changed, 681 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.h

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
index 562ee189d780..122ca9991100 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
@@ -30,6 +30,18 @@ AMD_DAL_GPIO = $(addprefix $(AMDDALPATH)/dc/gpio/,$(GPIO))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_GPIO)
 
+###############################################################################
+# DCE 6x
+###############################################################################
+# all DCE6.x are derived from DCE6.0
+ifdef CONFIG_DRM_AMD_DC_SI
+GPIO_DCE60 = hw_translate_dce60.o hw_factory_dce60.o
+
+AMD_DAL_GPIO_DCE60 = $(addprefix $(AMDDALPATH)/dc/gpio/dce60/,$(GPIO_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE60)
+endif
+
 ###############################################################################
 # DCE 8x
 ###############################################################################
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
new file mode 100644
index 000000000000..64afe9b48c5f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2018 Mauro Rossi <issor.oruam@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/gpio_types.h"
+#include "../hw_factory.h"
+
+#include "hw_factory_dce60.h"
+
+#include "../hw_gpio.h"
+#include "../hw_ddc.h"
+#include "../hw_hpd.h"
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+#define REG(reg_name)\
+		mm ## reg_name
+
+#include "reg_helper.h"
+#include "../hpd_regs.h"
+
+#define HPD_REG_LIST_DCE6(id) \
+	HPD_GPIO_REG_LIST(id), \
+	.int_status = mmDC_HPD ## id ## _INT_STATUS,\
+	.toggle_filt_cntl = mmDC_HPD ## id ## _TOGGLE_FILT_CNTL
+
+#define HPD_MASK_SH_LIST_DCE6(mask_sh) \
+		.DC_HPD_SENSE_DELAYED = DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED ## mask_sh,\
+		.DC_HPD_SENSE = DC_HPD1_INT_STATUS__DC_HPD1_SENSE ## mask_sh,\
+		.DC_HPD_CONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY ## mask_sh,\
+		.DC_HPD_DISCONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY ## mask_sh
+
+#define hpd_regs(id) \
+{\
+	HPD_REG_LIST_DCE6(id)\
+}
+
+static const struct hpd_registers hpd_regs[] = {
+	hpd_regs(1),
+	hpd_regs(2),
+	hpd_regs(3),
+	hpd_regs(4),
+	hpd_regs(5),
+	hpd_regs(6)
+};
+
+static const struct hpd_sh_mask hpd_shift = {
+		HPD_MASK_SH_LIST_DCE6(__SHIFT)
+};
+
+static const struct hpd_sh_mask hpd_mask = {
+		HPD_MASK_SH_LIST_DCE6(_MASK)
+};
+
+#include "../ddc_regs.h"
+
+ /* set field name */
+#define SF_DDC(reg_name, field_name, post_fix)\
+	.field_name = reg_name ## __ ## field_name ## post_fix
+
+static const struct ddc_registers ddc_data_regs[] = {
+	ddc_data_regs(1),
+	ddc_data_regs(2),
+	ddc_data_regs(3),
+	ddc_data_regs(4),
+	ddc_data_regs(5),
+	ddc_data_regs(6),
+	ddc_vga_data_regs,
+	ddc_i2c_data_regs
+};
+
+static const struct ddc_registers ddc_clk_regs[] = {
+	ddc_clk_regs(1),
+	ddc_clk_regs(2),
+	ddc_clk_regs(3),
+	ddc_clk_regs(4),
+	ddc_clk_regs(5),
+	ddc_clk_regs(6),
+	ddc_vga_clk_regs,
+	ddc_i2c_clk_regs
+};
+
+static const struct ddc_sh_mask ddc_shift = {
+		DDC_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct ddc_sh_mask ddc_mask = {
+		DDC_MASK_SH_LIST(_MASK)
+};
+
+static void define_ddc_registers(
+		struct hw_gpio_pin *pin,
+		uint32_t en)
+{
+	struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
+
+	switch (pin->id) {
+	case GPIO_ID_DDC_DATA:
+		ddc->regs = &ddc_data_regs[en];
+		ddc->base.regs = &ddc_data_regs[en].gpio;
+		break;
+	case GPIO_ID_DDC_CLOCK:
+		ddc->regs = &ddc_clk_regs[en];
+		ddc->base.regs = &ddc_clk_regs[en].gpio;
+		break;
+	default:
+		ASSERT_CRITICAL(false);
+		return;
+	}
+
+	ddc->shifts = &ddc_shift;
+	ddc->masks = &ddc_mask;
+
+}
+
+static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
+{
+	struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
+
+	hpd->regs = &hpd_regs[en];
+	hpd->shifts = &hpd_shift;
+	hpd->masks = &hpd_mask;
+	hpd->base.regs = &hpd_regs[en].gpio;
+}
+
+static const struct hw_factory_funcs funcs = {
+	.create_ddc_data = dal_hw_ddc_create,
+	.create_ddc_clock = dal_hw_ddc_create,
+	.create_generic = NULL,
+	.create_hpd = dal_hw_hpd_create,
+	.create_sync = NULL,
+	.create_gsl = NULL,
+	.define_hpd_registers = define_hpd_registers,
+	.define_ddc_registers = define_ddc_registers
+};
+
+void dal_hw_factory_dce60_init(
+	struct hw_factory *factory)
+{
+	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
+	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
+	factory->number_of_pins[GPIO_ID_GENERIC] = 7;
+	factory->number_of_pins[GPIO_ID_HPD] = 6;
+	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
+	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
+	factory->number_of_pins[GPIO_ID_SYNC] = 2;
+	factory->number_of_pins[GPIO_ID_GSL] = 4;
+
+	factory->funcs = &funcs;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.h b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.h
new file mode 100644
index 000000000000..52fd436533ed
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_HW_FACTORY_DCE60_H__
+#define __DAL_HW_FACTORY_DCE60_H__
+
+void dal_hw_factory_dce60_init(
+	struct hw_factory *factory);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
new file mode 100644
index 000000000000..f86ee8587f1b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
@@ -0,0 +1,411 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/*
+ * Pre-requisites: headers required by header of this unit
+ */
+#include "include/gpio_types.h"
+#include "../hw_translate.h"
+
+#include "hw_translate_dce60.h"
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+#include "smu/smu_6_0_d.h"
+
+/*
+ * @brief
+ * Returns index of first bit (starting with LSB) which is set
+ */
+static uint32_t index_from_vector(
+	uint32_t vector)
+{
+	uint32_t result = 0;
+	uint32_t mask = 1;
+
+	do {
+		if (vector == mask)
+			return result;
+
+		++result;
+		mask <<= 1;
+	} while (mask);
+
+	BREAK_TO_DEBUGGER();
+
+	return GPIO_ENUM_UNKNOWN;
+}
+
+static bool offset_to_id(
+	uint32_t offset,
+	uint32_t mask,
+	enum gpio_id *id,
+	uint32_t *en)
+{
+	switch (offset) {
+	/* GENERIC */
+	case mmDC_GPIO_GENERIC_A:
+		*id = GPIO_ID_GENERIC;
+		switch (mask) {
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
+			*en = GPIO_GENERIC_A;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
+			*en = GPIO_GENERIC_B;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
+			*en = GPIO_GENERIC_C;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
+			*en = GPIO_GENERIC_D;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
+			*en = GPIO_GENERIC_E;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
+			*en = GPIO_GENERIC_F;
+			return true;
+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
+			*en = GPIO_GENERIC_G;
+			return true;
+		default:
+			BREAK_TO_DEBUGGER();
+			return false;
+		}
+	break;
+	/* HPD */
+	case mmDC_GPIO_HPD_A:
+		*id = GPIO_ID_HPD;
+		switch (mask) {
+		case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
+			*en = GPIO_HPD_1;
+			return true;
+		case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
+			*en = GPIO_HPD_2;
+			return true;
+		case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
+			*en = GPIO_HPD_3;
+			return true;
+		case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
+			*en = GPIO_HPD_4;
+			return true;
+		case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
+			*en = GPIO_HPD_5;
+			return true;
+		case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
+			*en = GPIO_HPD_6;
+			return true;
+		default:
+			BREAK_TO_DEBUGGER();
+			return false;
+		}
+	break;
+	/* SYNCA */
+	case mmDC_GPIO_SYNCA_A:
+		*id = GPIO_ID_SYNC;
+		switch (mask) {
+		case DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK:
+			*en = GPIO_SYNC_HSYNC_A;
+			return true;
+		case DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK:
+			*en = GPIO_SYNC_VSYNC_A;
+			return true;
+		default:
+			BREAK_TO_DEBUGGER();
+			return false;
+		}
+	break;
+	/* mmDC_GPIO_GENLK_MASK */
+	case mmDC_GPIO_GENLK_A:
+		*id = GPIO_ID_GSL;
+		switch (mask) {
+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
+			*en = GPIO_GSL_GENLOCK_CLOCK;
+			return true;
+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
+			*en = GPIO_GSL_GENLOCK_VSYNC;
+			return true;
+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
+			*en = GPIO_GSL_SWAPLOCK_A;
+			return true;
+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
+			*en = GPIO_GSL_SWAPLOCK_B;
+			return true;
+		default:
+			BREAK_TO_DEBUGGER();
+			return false;
+		}
+	break;
+	/* GPIOPAD */
+	case mmGPIOPAD_A:
+		*id = GPIO_ID_GPIO_PAD;
+		*en = index_from_vector(mask);
+		return (*en <= GPIO_GPIO_PAD_MAX);
+	/* DDC */
+	/* we don't care about the GPIO_ID for DDC
+	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
+	 * directly in the create method */
+	case mmDC_GPIO_DDC1_A:
+		*en = GPIO_DDC_LINE_DDC1;
+		return true;
+	case mmDC_GPIO_DDC2_A:
+		*en = GPIO_DDC_LINE_DDC2;
+		return true;
+	case mmDC_GPIO_DDC3_A:
+		*en = GPIO_DDC_LINE_DDC3;
+		return true;
+	case mmDC_GPIO_DDC4_A:
+		*en = GPIO_DDC_LINE_DDC4;
+		return true;
+	case mmDC_GPIO_DDC5_A:
+		*en = GPIO_DDC_LINE_DDC5;
+		return true;
+	case mmDC_GPIO_DDC6_A:
+		*en = GPIO_DDC_LINE_DDC6;
+		return true;
+	case mmDC_GPIO_DDCVGA_A:
+		*en = GPIO_DDC_LINE_DDC_VGA;
+		return true;
+	/* GPIO_I2CPAD */
+	case mmDC_GPIO_I2CPAD_A:
+		*en = GPIO_DDC_LINE_I2C_PAD;
+		return true;
+	/* Not implemented */
+	case mmDC_GPIO_PWRSEQ_A:
+	case mmDC_GPIO_PAD_STRENGTH_1:
+	case mmDC_GPIO_PAD_STRENGTH_2:
+	case mmDC_GPIO_DEBUG:
+		return false;
+	/* UNEXPECTED */
+	default:
+		BREAK_TO_DEBUGGER();
+		return false;
+	}
+}
+
+static bool id_to_offset(
+	enum gpio_id id,
+	uint32_t en,
+	struct gpio_pin_info *info)
+{
+	bool result = true;
+
+	switch (id) {
+	case GPIO_ID_DDC_DATA:
+		info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
+		switch (en) {
+		case GPIO_DDC_LINE_DDC1:
+			info->offset = mmDC_GPIO_DDC1_A;
+		break;
+		case GPIO_DDC_LINE_DDC2:
+			info->offset = mmDC_GPIO_DDC2_A;
+		break;
+		case GPIO_DDC_LINE_DDC3:
+			info->offset = mmDC_GPIO_DDC3_A;
+		break;
+		case GPIO_DDC_LINE_DDC4:
+			info->offset = mmDC_GPIO_DDC4_A;
+		break;
+		case GPIO_DDC_LINE_DDC5:
+			info->offset = mmDC_GPIO_DDC5_A;
+		break;
+		case GPIO_DDC_LINE_DDC6:
+			info->offset = mmDC_GPIO_DDC6_A;
+		break;
+		case GPIO_DDC_LINE_DDC_VGA:
+			info->offset = mmDC_GPIO_DDCVGA_A;
+		break;
+		case GPIO_DDC_LINE_I2C_PAD:
+			info->offset = mmDC_GPIO_I2CPAD_A;
+		break;
+		default:
+			BREAK_TO_DEBUGGER();
+			result = false;
+		}
+	break;
+	case GPIO_ID_DDC_CLOCK:
+		info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;
+		switch (en) {
+		case GPIO_DDC_LINE_DDC1:
+			info->offset = mmDC_GPIO_DDC1_A;
+		break;
+		case GPIO_DDC_LINE_DDC2:
+			info->offset = mmDC_GPIO_DDC2_A;
+		break;
+		case GPIO_DDC_LINE_DDC3:
+			info->offset = mmDC_GPIO_DDC3_A;
+		break;
+		case GPIO_DDC_LINE_DDC4:
+			info->offset = mmDC_GPIO_DDC4_A;
+		break;
+		case GPIO_DDC_LINE_DDC5:
+			info->offset = mmDC_GPIO_DDC5_A;
+		break;
+		case GPIO_DDC_LINE_DDC6:
+			info->offset = mmDC_GPIO_DDC6_A;
+		break;
+		case GPIO_DDC_LINE_DDC_VGA:
+			info->offset = mmDC_GPIO_DDCVGA_A;
+		break;
+		case GPIO_DDC_LINE_I2C_PAD:
+			info->offset = mmDC_GPIO_I2CPAD_A;
+		break;
+		default:
+			BREAK_TO_DEBUGGER();
+			result = false;
+		}
+	break;
+	case GPIO_ID_GENERIC:
+		info->offset = mmDC_GPIO_GENERIC_A;
+		switch (en) {
+		case GPIO_GENERIC_A:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
+		break;
+		case GPIO_GENERIC_B:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
+		break;
+		case GPIO_GENERIC_C:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
+		break;
+		case GPIO_GENERIC_D:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
+		break;
+		case GPIO_GENERIC_E:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
+		break;
+		case GPIO_GENERIC_F:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
+		break;
+		case GPIO_GENERIC_G:
+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
+		break;
+		default:
+			BREAK_TO_DEBUGGER();
+			result = false;
+		}
+	break;
+	case GPIO_ID_HPD:
+		info->offset = mmDC_GPIO_HPD_A;
+		switch (en) {
+		case GPIO_HPD_1:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
+		break;
+		case GPIO_HPD_2:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
+		break;
+		case GPIO_HPD_3:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
+		break;
+		case GPIO_HPD_4:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
+		break;
+		case GPIO_HPD_5:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
+		break;
+		case GPIO_HPD_6:
+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
+		break;
+		default:
+			BREAK_TO_DEBUGGER();
+			result = false;
+		}
+	break;
+	case GPIO_ID_SYNC:
+		switch (en) {
+		case GPIO_SYNC_HSYNC_A:
+			info->offset = mmDC_GPIO_SYNCA_A;
+			info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;
+		break;
+		case GPIO_SYNC_VSYNC_A:
+			info->offset = mmDC_GPIO_SYNCA_A;
+			info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;
+		break;
+		case GPIO_SYNC_HSYNC_B:
+		case GPIO_SYNC_VSYNC_B:
+		default:
+			BREAK_TO_DEBUGGER();
+			result = false;
+		}
+	break;
+	case GPIO_ID_GSL:
+		switch (en) {
+		case GPIO_GSL_GENLOCK_CLOCK:
+			info->offset = mmDC_GPIO_GENLK_A;
+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;
+		break;
+		case GPIO_GSL_GENLOCK_VSYNC:
+			info->offset = mmDC_GPIO_GENLK_A;
+			info->mask =
+				DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK;
+		break;
+		case GPIO_GSL_SWAPLOCK_A:
+			info->offset = mmDC_GPIO_GENLK_A;
+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;
+		break;
+		case GPIO_GSL_SWAPLOCK_B:
+			info->offset = mmDC_GPIO_GENLK_A;
+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;
+		break;
+		default:
+			BREAK_TO_DEBUGGER();
+			result = false;
+		}
+	break;
+	case GPIO_ID_GPIO_PAD:
+		info->offset = mmGPIOPAD_A;
+		info->mask = (1 << en);
+		result = (info->mask <= GPIO_GPIO_PAD_MAX);
+	break;
+	case GPIO_ID_VIP_PAD:
+	default:
+		BREAK_TO_DEBUGGER();
+		result = false;
+	}
+
+	if (result) {
+		info->offset_y = info->offset + 2;
+		info->offset_en = info->offset + 1;
+		info->offset_mask = info->offset - 1;
+
+		info->mask_y = info->mask;
+		info->mask_en = info->mask;
+		info->mask_mask = info->mask;
+	}
+
+	return result;
+}
+
+static const struct hw_translate_funcs funcs = {
+		.offset_to_id = offset_to_id,
+		.id_to_offset = id_to_offset,
+};
+
+void dal_hw_translate_dce60_init(
+	struct hw_translate *translate)
+{
+	translate->funcs = &funcs;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.h b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.h
new file mode 100644
index 000000000000..c65a9d80c53c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_HW_TRANSLATE_DCE60_H__
+#define __DAL_HW_TRANSLATE_DCE60_H__
+
+void dal_hw_translate_dce60_init(
+	struct hw_translate *tr);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index a683f4102e65..b06c9e190078 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -40,6 +40,9 @@
  * Post-requisites: headers required by this unit
  */
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/hw_factory_dce60.h"
+#endif
 #include "dce80/hw_factory_dce80.h"
 #include "dce110/hw_factory_dce110.h"
 #include "dce120/hw_factory_dce120.h"
@@ -64,6 +67,13 @@ bool dal_hw_factory_init(
 	}
 
 	switch (dce_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+	case DCE_VERSION_6_0:
+	case DCE_VERSION_6_1:
+	case DCE_VERSION_6_4:
+		dal_hw_factory_dce60_init(factory);
+		return true;
+#endif
 	case DCE_VERSION_8_0:
 	case DCE_VERSION_8_1:
 	case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index 096f45628630..77c0aca735b0 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -40,6 +40,9 @@
  * Post-requisites: headers required by this unit
  */
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/hw_translate_dce60.h"
+#endif
 #include "dce80/hw_translate_dce80.h"
 #include "dce110/hw_translate_dce110.h"
 #include "dce120/hw_translate_dce120.h"
@@ -64,6 +67,13 @@ bool dal_hw_translate_init(
 	}
 
 	switch (dce_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+	case DCE_VERSION_6_0:
+	case DCE_VERSION_6_1:
+	case DCE_VERSION_6_4:
+		dal_hw_translate_dce60_init(translate);
+		return true;
+#endif
 	case DCE_VERSION_8_0:
 	case DCE_VERSION_8_1:
 	case DCE_VERSION_8_3:
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 06/10] drm/amd/display: dc/i2caux: add support for DCE6

[Mauro Rossi]

DCE6 targets are added replicating existing DCE8 implementation.
---
 .../gpu/drm/amd/display/dc/i2caux/Makefile    |  12 +
 .../dc/i2caux/dce60/i2c_hw_engine_dce60.c     | 875 ++++++++++++++++++
 .../dc/i2caux/dce60/i2c_hw_engine_dce60.h     |  54 ++
 .../dc/i2caux/dce60/i2c_sw_engine_dce60.c     | 173 ++++
 .../dc/i2caux/dce60/i2c_sw_engine_dce60.h     |  43 +
 .../display/dc/i2caux/dce60/i2caux_dce60.c    | 284 ++++++
 .../display/dc/i2caux/dce60/i2caux_dce60.h    |  38 +
 .../gpu/drm/amd/display/dc/i2caux/i2caux.c    |  10 +
 8 files changed, 1489 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.h

diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
index 352885cb4d07..80f58a357879 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
@@ -30,6 +30,18 @@ AMD_DAL_I2CAUX = $(addprefix $(AMDDALPATH)/dc/i2caux/,$(I2CAUX))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX)
 
+###############################################################################
+# DCE 6x family
+###############################################################################
+ifdef CONFIG_DRM_AMD_DC_SI
+I2CAUX_DCE60 = i2caux_dce60.o i2c_hw_engine_dce60.o \
+	i2c_sw_engine_dce60.o
+
+AMD_DAL_I2CAUX_DCE60 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce60/,$(I2CAUX_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE60)
+endif
+
 ###############################################################################
 # DCE 8x family
 ###############################################################################
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
new file mode 100644
index 000000000000..a945e00ce913
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
@@ -0,0 +1,875 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/*
+ * Pre-requisites: headers required by header of this unit
+ */
+#include "include/i2caux_interface.h"
+#include "../engine.h"
+#include "../i2c_engine.h"
+#include "../i2c_hw_engine.h"
+#include "../i2c_generic_hw_engine.h"
+/*
+ * Header of this unit
+ */
+
+#include "i2c_hw_engine_dce60.h"
+
+/*
+ * Post-requisites: headers required by this unit
+ */
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+/*
+ * This unit
+ */
+
+enum dc_i2c_status {
+	DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
+	DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
+	DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
+};
+
+enum dc_i2c_arbitration {
+	DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
+	DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
+};
+
+enum {
+	/* No timeout in HW
+	 * (timeout implemented in SW by querying status) */
+	I2C_SETUP_TIME_LIMIT = 255,
+	I2C_HW_BUFFER_SIZE = 144
+};
+
+/*
+ * @brief
+ * Cast 'struct i2c_hw_engine *'
+ * to 'struct i2c_hw_engine_dce60 *'
+ */
+#define FROM_I2C_HW_ENGINE(ptr) \
+	container_of((ptr), struct i2c_hw_engine_dce60, base)
+
+/*
+ * @brief
+ * Cast pointer to 'struct i2c_engine *'
+ * to pointer to 'struct i2c_hw_engine_dce60 *'
+ */
+#define FROM_I2C_ENGINE(ptr) \
+	FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
+
+/*
+ * @brief
+ * Cast pointer to 'struct engine *'
+ * to 'pointer to struct i2c_hw_engine_dce60 *'
+ */
+#define FROM_ENGINE(ptr) \
+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
+
+static void disable_i2c_hw_engine(
+	struct i2c_hw_engine_dce60 *engine)
+{
+	const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
+	uint32_t value = 0;
+
+	struct dc_context *ctx = NULL;
+
+	ctx = engine->base.base.base.ctx;
+
+	value = dm_read_reg(ctx, addr);
+
+	set_reg_field_value(
+		value,
+		0,
+		DC_I2C_DDC1_SETUP,
+		DC_I2C_DDC1_ENABLE);
+
+	dm_write_reg(ctx, addr, value);
+}
+
+static void release_engine(
+	struct engine *engine)
+{
+	struct i2c_hw_engine_dce60 *hw_engine = FROM_ENGINE(engine);
+
+	struct i2c_engine *base = NULL;
+	bool safe_to_reset;
+	uint32_t value = 0;
+
+	base = &hw_engine->base.base;
+
+	/* Restore original HW engine speed */
+
+	base->funcs->set_speed(base, hw_engine->base.original_speed);
+
+	/* Release I2C */
+	{
+		value = dm_read_reg(engine->ctx, mmDC_I2C_ARBITRATION);
+
+		set_reg_field_value(
+				value,
+				1,
+				DC_I2C_ARBITRATION,
+				DC_I2C_SW_DONE_USING_I2C_REG);
+
+		dm_write_reg(engine->ctx, mmDC_I2C_ARBITRATION, value);
+	}
+
+	/* Reset HW engine */
+	{
+		uint32_t i2c_sw_status = 0;
+
+		value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
+
+		i2c_sw_status = get_reg_field_value(
+				value,
+				DC_I2C_SW_STATUS,
+				DC_I2C_SW_STATUS);
+		/* if used by SW, safe to reset */
+		safe_to_reset = (i2c_sw_status == 1);
+	}
+	{
+		value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
+
+		if (safe_to_reset)
+			set_reg_field_value(
+				value,
+				1,
+				DC_I2C_CONTROL,
+				DC_I2C_SOFT_RESET);
+
+		set_reg_field_value(
+			value,
+			1,
+			DC_I2C_CONTROL,
+			DC_I2C_SW_STATUS_RESET);
+
+		dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
+	}
+
+	/* HW I2c engine - clock gating feature */
+	if (!hw_engine->engine_keep_power_up_count)
+		disable_i2c_hw_engine(hw_engine);
+}
+
+static void destruct(
+	struct i2c_hw_engine_dce60 *engine)
+{
+	dal_i2c_hw_engine_destruct(&engine->base);
+}
+
+static void destroy(
+	struct i2c_engine **i2c_engine)
+{
+	struct i2c_hw_engine_dce60 *engine = FROM_I2C_ENGINE(*i2c_engine);
+
+	destruct(engine);
+
+	kfree(engine);
+
+	*i2c_engine = NULL;
+}
+
+static bool setup_engine(
+	struct i2c_engine *i2c_engine)
+{
+	uint32_t value = 0;
+	struct i2c_hw_engine_dce60 *engine = FROM_I2C_ENGINE(i2c_engine);
+
+	/* Program pin select */
+	{
+		const uint32_t addr = mmDC_I2C_CONTROL;
+
+		value = dm_read_reg(i2c_engine->base.ctx, addr);
+
+		set_reg_field_value(
+			value,
+			0,
+			DC_I2C_CONTROL,
+			DC_I2C_GO);
+
+		set_reg_field_value(
+			value,
+			0,
+			DC_I2C_CONTROL,
+			DC_I2C_SOFT_RESET);
+
+		set_reg_field_value(
+			value,
+			0,
+			DC_I2C_CONTROL,
+			DC_I2C_SEND_RESET);
+
+		set_reg_field_value(
+			value,
+			0,
+			DC_I2C_CONTROL,
+			DC_I2C_SW_STATUS_RESET);
+
+		set_reg_field_value(
+			value,
+			0,
+			DC_I2C_CONTROL,
+			DC_I2C_TRANSACTION_COUNT);
+
+		set_reg_field_value(
+			value,
+			engine->engine_id,
+			DC_I2C_CONTROL,
+			DC_I2C_DDC_SELECT);
+
+		dm_write_reg(i2c_engine->base.ctx, addr, value);
+	}
+
+	/* Program time limit */
+	{
+		const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
+
+		value = dm_read_reg(i2c_engine->base.ctx, addr);
+
+		set_reg_field_value(
+			value,
+			I2C_SETUP_TIME_LIMIT,
+			DC_I2C_DDC1_SETUP,
+			DC_I2C_DDC1_TIME_LIMIT);
+
+		set_reg_field_value(
+			value,
+			1,
+			DC_I2C_DDC1_SETUP,
+			DC_I2C_DDC1_ENABLE);
+
+		dm_write_reg(i2c_engine->base.ctx, addr, value);
+	}
+
+	/* Program HW priority
+	 * set to High - interrupt software I2C at any time
+	 * Enable restart of SW I2C that was interrupted by HW
+	 * disable queuing of software while I2C is in use by HW */
+	{
+		value = dm_read_reg(i2c_engine->base.ctx,
+				mmDC_I2C_ARBITRATION);
+
+		set_reg_field_value(
+			value,
+			0,
+			DC_I2C_ARBITRATION,
+			DC_I2C_NO_QUEUED_SW_GO);
+
+		set_reg_field_value(
+			value,
+			DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
+			DC_I2C_ARBITRATION,
+			DC_I2C_SW_PRIORITY);
+
+		dm_write_reg(i2c_engine->base.ctx,
+				mmDC_I2C_ARBITRATION, value);
+	}
+
+	return true;
+}
+
+static uint32_t get_speed(
+	const struct i2c_engine *i2c_engine)
+{
+	const struct i2c_hw_engine_dce60 *engine = FROM_I2C_ENGINE(i2c_engine);
+
+	const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
+
+	uint32_t pre_scale = 0;
+
+	uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
+
+	pre_scale = get_reg_field_value(
+			value,
+			DC_I2C_DDC1_SPEED,
+			DC_I2C_DDC1_PRESCALE);
+
+	/* [anaumov] it seems following is unnecessary */
+	/*ASSERT(value.bits.DC_I2C_DDC1_PRESCALE);*/
+
+	return pre_scale ?
+		engine->reference_frequency / pre_scale :
+		engine->base.default_speed;
+}
+
+static void set_speed(
+	struct i2c_engine *i2c_engine,
+	uint32_t speed)
+{
+	struct i2c_hw_engine_dce60 *engine = FROM_I2C_ENGINE(i2c_engine);
+
+	if (speed) {
+		const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
+
+		uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
+
+		set_reg_field_value(
+			value,
+			engine->reference_frequency / speed,
+			DC_I2C_DDC1_SPEED,
+			DC_I2C_DDC1_PRESCALE);
+
+		set_reg_field_value(
+			value,
+			2,
+			DC_I2C_DDC1_SPEED,
+			DC_I2C_DDC1_THRESHOLD);
+
+		dm_write_reg(i2c_engine->base.ctx, addr, value);
+	}
+}
+
+static inline void reset_hw_engine(struct engine *engine)
+{
+	uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
+
+	set_reg_field_value(
+		value,
+		1,
+		DC_I2C_CONTROL,
+		DC_I2C_SOFT_RESET);
+
+	set_reg_field_value(
+		value,
+		1,
+		DC_I2C_CONTROL,
+		DC_I2C_SW_STATUS_RESET);
+
+	dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
+}
+
+static bool is_hw_busy(struct engine *engine)
+{
+	uint32_t i2c_sw_status = 0;
+
+	uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
+
+	i2c_sw_status = get_reg_field_value(
+			value,
+			DC_I2C_SW_STATUS,
+			DC_I2C_SW_STATUS);
+
+	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
+		return false;
+
+	reset_hw_engine(engine);
+
+	value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
+
+	i2c_sw_status = get_reg_field_value(
+			value,
+			DC_I2C_SW_STATUS,
+			DC_I2C_SW_STATUS);
+
+	return i2c_sw_status != DC_I2C_STATUS__DC_I2C_STATUS_IDLE;
+}
+
+/*
+ * @brief
+ * DC_GPIO_DDC MM register offsets
+ */
+static const uint32_t transaction_addr[] = {
+	mmDC_I2C_TRANSACTION0,
+	mmDC_I2C_TRANSACTION1,
+	mmDC_I2C_TRANSACTION2,
+	mmDC_I2C_TRANSACTION3
+};
+
+static bool process_transaction(
+	struct i2c_hw_engine_dce60 *engine,
+	struct i2c_request_transaction_data *request)
+{
+	uint32_t length = request->length;
+	uint8_t *buffer = request->data;
+
+	bool last_transaction = false;
+	uint32_t value = 0;
+
+	struct dc_context *ctx = NULL;
+
+	ctx = engine->base.base.base.ctx;
+
+	{
+		const uint32_t addr =
+			transaction_addr[engine->transaction_count];
+
+		value = dm_read_reg(ctx, addr);
+
+		set_reg_field_value(
+			value,
+			1,
+			DC_I2C_TRANSACTION0,
+			DC_I2C_STOP_ON_NACK0);
+
+		set_reg_field_value(
+			value,
+			1,
+			DC_I2C_TRANSACTION0,
+			DC_I2C_START0);
+
+		if ((engine->transaction_count == 3) ||
+		(request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
+		(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
+
+			set_reg_field_value(
+				value,
+				1,
+				DC_I2C_TRANSACTION0,
+				DC_I2C_STOP0);
+
+			last_transaction = true;
+		} else
+			set_reg_field_value(
+				value,
+				0,
+				DC_I2C_TRANSACTION0,
+				DC_I2C_STOP0);
+
+		set_reg_field_value(
+			value,
+			(0 != (request->action &
+					I2CAUX_TRANSACTION_ACTION_I2C_READ)),
+			DC_I2C_TRANSACTION0,
+			DC_I2C_RW0);
+
+		set_reg_field_value(
+			value,
+			length,
+			DC_I2C_TRANSACTION0,
+			DC_I2C_COUNT0);
+
+		dm_write_reg(ctx, addr, value);
+	}
+
+	/* Write the I2C address and I2C data
+	 * into the hardware circular buffer, one byte per entry.
+	 * As an example, the 7-bit I2C slave address for CRT monitor
+	 * for reading DDC/EDID information is 0b1010001.
+	 * For an I2C send operation, the LSB must be programmed to 0;
+	 * for I2C receive operation, the LSB must be programmed to 1. */
+
+	{
+		value = 0;
+
+		set_reg_field_value(
+			value,
+			false,
+			DC_I2C_DATA,
+			DC_I2C_DATA_RW);
+
+		set_reg_field_value(
+			value,
+			request->address,
+			DC_I2C_DATA,
+			DC_I2C_DATA);
+
+		if (engine->transaction_count == 0) {
+			set_reg_field_value(
+				value,
+				0,
+				DC_I2C_DATA,
+				DC_I2C_INDEX);
+
+			/*enable index write*/
+			set_reg_field_value(
+				value,
+				1,
+				DC_I2C_DATA,
+				DC_I2C_INDEX_WRITE);
+		}
+
+		dm_write_reg(ctx, mmDC_I2C_DATA, value);
+
+		if (!(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
+
+			set_reg_field_value(
+				value,
+				0,
+				DC_I2C_DATA,
+				DC_I2C_INDEX_WRITE);
+
+			while (length) {
+
+				set_reg_field_value(
+					value,
+					*buffer++,
+					DC_I2C_DATA,
+					DC_I2C_DATA);
+
+				dm_write_reg(ctx, mmDC_I2C_DATA, value);
+				--length;
+			}
+		}
+	}
+
+	++engine->transaction_count;
+	engine->buffer_used_bytes += length + 1;
+
+	return last_transaction;
+}
+
+static void execute_transaction(
+	struct i2c_hw_engine_dce60 *engine)
+{
+	uint32_t value = 0;
+	struct dc_context *ctx = NULL;
+
+	ctx = engine->base.base.base.ctx;
+
+	{
+		const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
+
+		value = dm_read_reg(ctx, addr);
+
+		set_reg_field_value(
+			value,
+			0,
+			DC_I2C_DDC1_SETUP,
+			DC_I2C_DDC1_DATA_DRIVE_EN);
+
+		set_reg_field_value(
+			value,
+			0,
+			DC_I2C_DDC1_SETUP,
+			DC_I2C_DDC1_CLK_DRIVE_EN);
+
+		set_reg_field_value(
+			value,
+			0,
+			DC_I2C_DDC1_SETUP,
+			DC_I2C_DDC1_DATA_DRIVE_SEL);
+
+		set_reg_field_value(
+			value,
+			0,
+			DC_I2C_DDC1_SETUP,
+			DC_I2C_DDC1_INTRA_TRANSACTION_DELAY);
+
+		set_reg_field_value(
+			value,
+			0,
+			DC_I2C_DDC1_SETUP,
+			DC_I2C_DDC1_INTRA_BYTE_DELAY);
+
+		dm_write_reg(ctx, addr, value);
+	}
+
+	{
+		const uint32_t addr = mmDC_I2C_CONTROL;
+
+		value = dm_read_reg(ctx, addr);
+
+		set_reg_field_value(
+			value,
+			0,
+			DC_I2C_CONTROL,
+			DC_I2C_SOFT_RESET);
+
+		set_reg_field_value(
+			value,
+			0,
+			DC_I2C_CONTROL,
+			DC_I2C_SW_STATUS_RESET);
+
+		set_reg_field_value(
+			value,
+			0,
+			DC_I2C_CONTROL,
+			DC_I2C_SEND_RESET);
+
+		set_reg_field_value(
+			value,
+			0,
+			DC_I2C_CONTROL,
+			DC_I2C_GO);
+
+		set_reg_field_value(
+			value,
+			engine->transaction_count - 1,
+			DC_I2C_CONTROL,
+			DC_I2C_TRANSACTION_COUNT);
+
+		dm_write_reg(ctx, addr, value);
+	}
+
+	/* start I2C transfer */
+	{
+		const uint32_t addr = mmDC_I2C_CONTROL;
+
+		value	= dm_read_reg(ctx, addr);
+
+		set_reg_field_value(
+			value,
+			1,
+			DC_I2C_CONTROL,
+			DC_I2C_GO);
+
+		dm_write_reg(ctx, addr, value);
+	}
+
+	/* all transactions were executed and HW buffer became empty
+	 * (even though it actually happens when status becomes DONE) */
+	engine->transaction_count = 0;
+	engine->buffer_used_bytes = 0;
+}
+
+static void submit_channel_request(
+	struct i2c_engine *engine,
+	struct i2c_request_transaction_data *request)
+{
+	request->status = I2C_CHANNEL_OPERATION_SUCCEEDED;
+
+	if (!process_transaction(FROM_I2C_ENGINE(engine), request))
+		return;
+
+	if (is_hw_busy(&engine->base)) {
+		request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
+		return;
+	}
+
+	execute_transaction(FROM_I2C_ENGINE(engine));
+}
+
+static void process_channel_reply(
+	struct i2c_engine *engine,
+	struct i2c_reply_transaction_data *reply)
+{
+	uint32_t length = reply->length;
+	uint8_t *buffer = reply->data;
+
+	uint32_t value = 0;
+
+	/*set index*/
+	set_reg_field_value(
+		value,
+		length - 1,
+		DC_I2C_DATA,
+		DC_I2C_INDEX);
+
+	set_reg_field_value(
+		value,
+		1,
+		DC_I2C_DATA,
+		DC_I2C_DATA_RW);
+
+	set_reg_field_value(
+		value,
+		1,
+		DC_I2C_DATA,
+		DC_I2C_INDEX_WRITE);
+
+	dm_write_reg(engine->base.ctx, mmDC_I2C_DATA, value);
+
+	while (length) {
+		/* after reading the status,
+		 * if the I2C operation executed successfully
+		 * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
+		 * should read data bytes from I2C circular data buffer */
+
+		value = dm_read_reg(engine->base.ctx, mmDC_I2C_DATA);
+
+		*buffer++ = get_reg_field_value(
+				value,
+				DC_I2C_DATA,
+				DC_I2C_DATA);
+
+		--length;
+	}
+}
+
+static enum i2c_channel_operation_result get_channel_status(
+	struct i2c_engine *engine,
+	uint8_t *returned_bytes)
+{
+	uint32_t i2c_sw_status = 0;
+	uint32_t value = dm_read_reg(engine->base.ctx, mmDC_I2C_SW_STATUS);
+
+	i2c_sw_status = get_reg_field_value(
+			value,
+			DC_I2C_SW_STATUS,
+			DC_I2C_SW_STATUS);
+
+	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
+		return I2C_CHANNEL_OPERATION_ENGINE_BUSY;
+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK)
+		return I2C_CHANNEL_OPERATION_NO_RESPONSE;
+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK)
+		return I2C_CHANNEL_OPERATION_TIMEOUT;
+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK)
+		return I2C_CHANNEL_OPERATION_FAILED;
+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK)
+		return I2C_CHANNEL_OPERATION_SUCCEEDED;
+
+	/*
+	 * this is the case when HW used for communication, I2C_SW_STATUS
+	 * could be zero
+	 */
+	return I2C_CHANNEL_OPERATION_SUCCEEDED;
+}
+
+static uint32_t get_hw_buffer_available_size(
+	const struct i2c_hw_engine *engine)
+{
+	return I2C_HW_BUFFER_SIZE -
+		FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes;
+}
+
+static uint32_t get_transaction_timeout(
+	const struct i2c_hw_engine *engine,
+	uint32_t length)
+{
+	uint32_t speed = engine->base.funcs->get_speed(&engine->base);
+
+	uint32_t period_timeout;
+	uint32_t num_of_clock_stretches;
+
+	if (!speed)
+		return 0;
+
+	period_timeout = (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed;
+
+	num_of_clock_stretches = 1 + (length << 3) + 1;
+	num_of_clock_stretches +=
+		(FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes << 3) +
+		(FROM_I2C_HW_ENGINE(engine)->transaction_count << 1);
+
+	return period_timeout * num_of_clock_stretches;
+}
+
+/*
+ * @brief
+ * DC_I2C_DDC1_SETUP MM register offsets
+ *
+ * @note
+ * The indices of this offset array are DDC engine IDs
+ */
+static const int32_t ddc_setup_offset[] = {
+
+	mmDC_I2C_DDC1_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 1 */
+	mmDC_I2C_DDC2_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 2 */
+	mmDC_I2C_DDC3_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 3 */
+	mmDC_I2C_DDC4_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 4 */
+	mmDC_I2C_DDC5_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 5 */
+	mmDC_I2C_DDC6_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 6 */
+	mmDC_I2C_DDCVGA_SETUP - mmDC_I2C_DDC1_SETUP /* DDC Engine 7 */
+};
+
+/*
+ * @brief
+ * DC_I2C_DDC1_SPEED MM register offsets
+ *
+ * @note
+ * The indices of this offset array are DDC engine IDs
+ */
+static const int32_t ddc_speed_offset[] = {
+	mmDC_I2C_DDC1_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 1 */
+	mmDC_I2C_DDC2_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 2 */
+	mmDC_I2C_DDC3_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 3 */
+	mmDC_I2C_DDC4_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 4 */
+	mmDC_I2C_DDC5_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 5 */
+	mmDC_I2C_DDC6_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 6 */
+	mmDC_I2C_DDCVGA_SPEED - mmDC_I2C_DDC1_SPEED /* DDC Engine 7 */
+};
+
+static const struct i2c_engine_funcs i2c_engine_funcs = {
+	.destroy = destroy,
+	.get_speed = get_speed,
+	.set_speed = set_speed,
+	.setup_engine = setup_engine,
+	.submit_channel_request = submit_channel_request,
+	.process_channel_reply = process_channel_reply,
+	.get_channel_status = get_channel_status,
+	.acquire_engine = dal_i2c_hw_engine_acquire_engine,
+};
+
+static const struct engine_funcs engine_funcs = {
+	.release_engine = release_engine,
+	.get_engine_type = dal_i2c_hw_engine_get_engine_type,
+	.acquire = dal_i2c_engine_acquire,
+	.submit_request = dal_i2c_hw_engine_submit_request,
+};
+
+static const struct i2c_hw_engine_funcs i2c_hw_engine_funcs = {
+	.get_hw_buffer_available_size =
+		get_hw_buffer_available_size,
+	.get_transaction_timeout =
+		get_transaction_timeout,
+	.wait_on_operation_result =
+		dal_i2c_hw_engine_wait_on_operation_result,
+};
+
+static void construct(
+	struct i2c_hw_engine_dce60 *engine,
+	const struct i2c_hw_engine_dce60_create_arg *arg)
+{
+	dal_i2c_hw_engine_construct(&engine->base, arg->ctx);
+
+	engine->base.base.base.funcs = &engine_funcs;
+	engine->base.base.funcs = &i2c_engine_funcs;
+	engine->base.funcs = &i2c_hw_engine_funcs;
+	engine->base.default_speed = arg->default_speed;
+	engine->addr.DC_I2C_DDCX_SETUP =
+		mmDC_I2C_DDC1_SETUP + ddc_setup_offset[arg->engine_id];
+	engine->addr.DC_I2C_DDCX_SPEED =
+		mmDC_I2C_DDC1_SPEED + ddc_speed_offset[arg->engine_id];
+
+	engine->engine_id = arg->engine_id;
+	engine->reference_frequency = arg->reference_frequency;
+	engine->buffer_used_bytes = 0;
+	engine->transaction_count = 0;
+	engine->engine_keep_power_up_count = 1;
+}
+
+struct i2c_engine *dal_i2c_hw_engine_dce60_create(
+	const struct i2c_hw_engine_dce60_create_arg *arg)
+{
+	struct i2c_hw_engine_dce60 *engine;
+
+	if (!arg) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	if ((arg->engine_id >= sizeof(ddc_setup_offset) / sizeof(int32_t)) ||
+	    (arg->engine_id >= sizeof(ddc_speed_offset) / sizeof(int32_t)) ||
+	    !arg->reference_frequency) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	engine = kzalloc(sizeof(struct i2c_hw_engine_dce60), GFP_KERNEL);
+
+	if (!engine) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	construct(engine, arg);
+	return &engine->base.base;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.h b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.h
new file mode 100644
index 000000000000..48954265133d
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_I2C_HW_ENGINE_DCE60_H__
+#define __DAL_I2C_HW_ENGINE_DCE60_H__
+
+struct i2c_hw_engine_dce60 {
+	struct i2c_hw_engine base;
+	struct {
+		uint32_t DC_I2C_DDCX_SETUP;
+		uint32_t DC_I2C_DDCX_SPEED;
+	} addr;
+	uint32_t engine_id;
+	/* expressed in kilohertz */
+	uint32_t reference_frequency;
+	/* number of bytes currently used in HW buffer */
+	uint32_t buffer_used_bytes;
+	/* number of pending transactions (before GO) */
+	uint32_t transaction_count;
+	uint32_t engine_keep_power_up_count;
+};
+
+struct i2c_hw_engine_dce60_create_arg {
+	uint32_t engine_id;
+	uint32_t reference_frequency;
+	uint32_t default_speed;
+	struct dc_context *ctx;
+};
+
+struct i2c_engine *dal_i2c_hw_engine_dce60_create(
+	const struct i2c_hw_engine_dce60_create_arg *arg);
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.c
new file mode 100644
index 000000000000..9830dc6698e0
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/*
+ * Pre-requisites: headers required by header of this unit
+ */
+#include "include/i2caux_interface.h"
+#include "../engine.h"
+#include "../i2c_engine.h"
+#include "../i2c_sw_engine.h"
+
+/*
+ * Header of this unit
+ */
+
+#include "i2c_sw_engine_dce60.h"
+
+/*
+ * Post-requisites: headers required by this unit
+ */
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+/*
+ * This unit
+ */
+
+static const uint32_t ddc_hw_status_addr[] = {
+	mmDC_I2C_DDC1_HW_STATUS,
+	mmDC_I2C_DDC2_HW_STATUS,
+	mmDC_I2C_DDC3_HW_STATUS,
+	mmDC_I2C_DDC4_HW_STATUS,
+	mmDC_I2C_DDC5_HW_STATUS,
+	mmDC_I2C_DDC6_HW_STATUS,
+	mmDC_I2C_DDCVGA_HW_STATUS
+};
+
+/*
+ * @brief
+ * Cast 'struct i2c_sw_engine *'
+ * to 'struct i2c_sw_engine_dce60 *'
+ */
+#define FROM_I2C_SW_ENGINE(ptr) \
+	container_of((ptr), struct i2c_sw_engine_dce60, base)
+
+/*
+ * @brief
+ * Cast 'struct i2c_engine *'
+ * to 'struct i2c_sw_engine_dce60 *'
+ */
+#define FROM_I2C_ENGINE(ptr) \
+	FROM_I2C_SW_ENGINE(container_of((ptr), struct i2c_sw_engine, base))
+
+/*
+ * @brief
+ * Cast 'struct engine *'
+ * to 'struct i2c_sw_engine_dce60 *'
+ */
+#define FROM_ENGINE(ptr) \
+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
+
+static void release_engine(
+	struct engine *engine)
+{
+
+}
+
+static void destruct(
+	struct i2c_sw_engine_dce60 *engine)
+{
+	dal_i2c_sw_engine_destruct(&engine->base);
+}
+
+static void destroy(
+	struct i2c_engine **engine)
+{
+	struct i2c_sw_engine_dce60 *sw_engine = FROM_I2C_ENGINE(*engine);
+
+	destruct(sw_engine);
+
+	kfree(sw_engine);
+
+	*engine = NULL;
+}
+
+static bool acquire_engine(
+	struct i2c_engine *engine,
+	struct ddc *ddc_handle)
+{
+	return dal_i2caux_i2c_sw_engine_acquire_engine(engine, ddc_handle);
+}
+
+static const struct i2c_engine_funcs i2c_engine_funcs = {
+	.acquire_engine = acquire_engine,
+	.destroy = destroy,
+	.get_speed = dal_i2c_sw_engine_get_speed,
+	.set_speed = dal_i2c_sw_engine_set_speed,
+	.setup_engine = dal_i2c_engine_setup_i2c_engine,
+	.submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
+	.process_channel_reply = dal_i2c_engine_process_channel_reply,
+	.get_channel_status = dal_i2c_sw_engine_get_channel_status,
+};
+
+static const struct engine_funcs engine_funcs = {
+	.release_engine = release_engine,
+	.get_engine_type = dal_i2c_sw_engine_get_engine_type,
+	.acquire = dal_i2c_engine_acquire,
+	.submit_request = dal_i2c_sw_engine_submit_request,
+};
+
+static void construct(
+	struct i2c_sw_engine_dce60 *engine,
+	const struct i2c_sw_engine_dce60_create_arg *arg)
+{
+	struct i2c_sw_engine_create_arg arg_base;
+
+	arg_base.ctx = arg->ctx;
+	arg_base.default_speed = arg->default_speed;
+
+	dal_i2c_sw_engine_construct(&engine->base, &arg_base);
+
+	engine->base.base.base.funcs = &engine_funcs;
+	engine->base.base.funcs = &i2c_engine_funcs;
+	engine->base.default_speed = arg->default_speed;
+	engine->engine_id = arg->engine_id;
+}
+
+struct i2c_engine *dal_i2c_sw_engine_dce60_create(
+	const struct i2c_sw_engine_dce60_create_arg *arg)
+{
+	struct i2c_sw_engine_dce60 *engine;
+
+	if (!arg) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	engine = kzalloc(sizeof(struct i2c_sw_engine_dce60), GFP_KERNEL);
+
+	if (!engine) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	construct(engine, arg);
+	return &engine->base.base;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.h b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.h
new file mode 100644
index 000000000000..5a65a5139e76
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_I2C_SW_ENGINE_DCE60_H__
+#define __DAL_I2C_SW_ENGINE_DCE60_H__
+
+struct i2c_sw_engine_dce60 {
+	struct i2c_sw_engine base;
+	uint32_t engine_id;
+};
+
+struct i2c_sw_engine_dce60_create_arg {
+	uint32_t engine_id;
+	uint32_t default_speed;
+	struct dc_context *ctx;
+};
+
+struct i2c_engine *dal_i2c_sw_engine_dce60_create(
+	const struct i2c_sw_engine_dce60_create_arg *arg);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.c
new file mode 100644
index 000000000000..5aaa7cf83807
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.c
@@ -0,0 +1,284 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/*
+ * Pre-requisites: headers required by header of this unit
+ */
+#include "include/i2caux_interface.h"
+#include "../i2caux.h"
+
+/*
+ * Header of this unit
+ */
+
+#include "i2caux_dce60.h"
+
+/*
+ * Post-requisites: headers required by this unit
+ */
+
+#include "../engine.h"
+#include "../i2c_engine.h"
+#include "../i2c_sw_engine.h"
+#include "i2c_sw_engine_dce60.h"
+#include "../i2c_hw_engine.h"
+#include "i2c_hw_engine_dce60.h"
+#include "../i2c_generic_hw_engine.h"
+#include "../aux_engine.h"
+
+
+#include "../dce110/aux_engine_dce110.h"
+#include "../dce110/i2caux_dce110.h"
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+
+/* set register offset */
+#define SR(reg_name)\
+	.reg_name = mm ## reg_name
+
+/* set register offset with instance */
+#define SRI(reg_name, block, id)\
+	.reg_name = mm ## block ## id ## _ ## reg_name
+
+#define aux_regs(id)\
+[id] = {\
+	AUX_COMMON_REG_LIST(id), \
+	.AUX_RESET_MASK = 0 \
+}
+
+static const struct dce110_aux_registers dce60_aux_regs[] = {
+		aux_regs(0),
+		aux_regs(1),
+		aux_regs(2),
+		aux_regs(3),
+		aux_regs(4),
+		aux_regs(5)
+};
+
+/*
+ * This unit
+ */
+
+#define FROM_I2C_AUX(ptr) \
+	container_of((ptr), struct i2caux_dce60, base)
+
+static void destruct(
+	struct i2caux_dce60 *i2caux_dce60)
+{
+	dal_i2caux_destruct(&i2caux_dce60->base);
+}
+
+static void destroy(
+	struct i2caux **i2c_engine)
+{
+	struct i2caux_dce60 *i2caux_dce60 = FROM_I2C_AUX(*i2c_engine);
+
+	destruct(i2caux_dce60);
+
+	kfree(i2caux_dce60);
+
+	*i2c_engine = NULL;
+}
+
+static struct i2c_engine *acquire_i2c_hw_engine(
+	struct i2caux *i2caux,
+	struct ddc *ddc)
+{
+	struct i2caux_dce60 *i2caux_dce60 = FROM_I2C_AUX(i2caux);
+
+	struct i2c_engine *engine = NULL;
+	bool non_generic;
+
+	if (!ddc)
+		return NULL;
+
+	if (ddc->hw_info.hw_supported) {
+		enum gpio_ddc_line line = dal_ddc_get_line(ddc);
+
+		if (line < GPIO_DDC_LINE_COUNT) {
+			non_generic = true;
+			engine = i2caux->i2c_hw_engines[line];
+		}
+	}
+
+	if (!engine) {
+		non_generic = false;
+		engine = i2caux->i2c_generic_hw_engine;
+	}
+
+	if (!engine)
+		return NULL;
+
+	if (non_generic) {
+		if (!i2caux_dce60->i2c_hw_buffer_in_use &&
+			engine->base.funcs->acquire(&engine->base, ddc)) {
+			i2caux_dce60->i2c_hw_buffer_in_use = true;
+			return engine;
+		}
+	} else {
+		if (engine->base.funcs->acquire(&engine->base, ddc))
+			return engine;
+	}
+
+	return NULL;
+}
+
+static void release_engine(
+	struct i2caux *i2caux,
+	struct engine *engine)
+{
+	if (engine->funcs->get_engine_type(engine) ==
+		I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
+		FROM_I2C_AUX(i2caux)->i2c_hw_buffer_in_use = false;
+
+	dal_i2caux_release_engine(i2caux, engine);
+}
+
+static const enum gpio_ddc_line hw_ddc_lines[] = {
+	GPIO_DDC_LINE_DDC1,
+	GPIO_DDC_LINE_DDC2,
+	GPIO_DDC_LINE_DDC3,
+	GPIO_DDC_LINE_DDC4,
+	GPIO_DDC_LINE_DDC5,
+	GPIO_DDC_LINE_DDC6,
+	GPIO_DDC_LINE_DDC_VGA
+};
+
+static const enum gpio_ddc_line hw_aux_lines[] = {
+	GPIO_DDC_LINE_DDC1,
+	GPIO_DDC_LINE_DDC2,
+	GPIO_DDC_LINE_DDC3,
+	GPIO_DDC_LINE_DDC4,
+	GPIO_DDC_LINE_DDC5,
+	GPIO_DDC_LINE_DDC6
+};
+
+static const struct i2caux_funcs i2caux_funcs = {
+	.destroy = destroy,
+	.acquire_i2c_hw_engine = acquire_i2c_hw_engine,
+	.release_engine = release_engine,
+	.acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
+	.acquire_aux_engine = dal_i2caux_acquire_aux_engine,
+};
+
+static void construct(
+	struct i2caux_dce60 *i2caux_dce60,
+	struct dc_context *ctx)
+{
+	/* Entire family have I2C engine reference clock frequency
+	 * changed from XTALIN (27) to XTALIN/2 (13.5) */
+
+	struct i2caux *base = &i2caux_dce60->base;
+
+	uint32_t reference_frequency =
+		dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
+
+	/*bool use_i2c_sw_engine = dal_adapter_service_is_feature_supported(as,
+		FEATURE_RESTORE_USAGE_I2C_SW_ENGINE);*/
+
+	/* Use SWI2C for dce8 currently, sicne we have bug with hwi2c */
+	bool use_i2c_sw_engine = true;
+
+	uint32_t i;
+
+	dal_i2caux_construct(base, ctx);
+
+	i2caux_dce60->base.funcs = &i2caux_funcs;
+	i2caux_dce60->i2c_hw_buffer_in_use = false;
+
+	/* Create I2C HW engines (HW + SW pairs)
+	 * for all lines which has assisted HW DDC
+	 * 'i' (loop counter) used as DDC/AUX engine_id */
+
+	i = 0;
+
+	do {
+		enum gpio_ddc_line line_id = hw_ddc_lines[i];
+
+		struct i2c_hw_engine_dce60_create_arg hw_arg;
+
+		if (use_i2c_sw_engine) {
+			struct i2c_sw_engine_dce60_create_arg sw_arg;
+
+			sw_arg.engine_id = i;
+			sw_arg.default_speed = base->default_i2c_sw_speed;
+			sw_arg.ctx = ctx;
+			base->i2c_sw_engines[line_id] =
+				dal_i2c_sw_engine_dce60_create(&sw_arg);
+		}
+
+		hw_arg.engine_id = i;
+		hw_arg.reference_frequency = reference_frequency;
+		hw_arg.default_speed = base->default_i2c_hw_speed;
+		hw_arg.ctx = ctx;
+
+		base->i2c_hw_engines[line_id] =
+			dal_i2c_hw_engine_dce60_create(&hw_arg);
+
+		++i;
+	} while (i < ARRAY_SIZE(hw_ddc_lines));
+
+	/* Create AUX engines for all lines which has assisted HW AUX
+	 * 'i' (loop counter) used as DDC/AUX engine_id */
+
+	i = 0;
+
+	do {
+		enum gpio_ddc_line line_id = hw_aux_lines[i];
+
+		struct aux_engine_dce110_init_data arg;
+
+		arg.engine_id = i;
+		arg.timeout_period = base->aux_timeout_period;
+		arg.ctx = ctx;
+		arg.regs = &dce60_aux_regs[i];
+
+		base->aux_engines[line_id] =
+			dal_aux_engine_dce110_create(&arg);
+
+		++i;
+	} while (i < ARRAY_SIZE(hw_aux_lines));
+
+	/* TODO Generic I2C SW and HW */
+}
+
+struct i2caux *dal_i2caux_dce60_create(
+	struct dc_context *ctx)
+{
+	struct i2caux_dce60 *i2caux_dce60 =
+		kzalloc(sizeof(struct i2caux_dce60), GFP_KERNEL);
+
+	if (!i2caux_dce60) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	construct(i2caux_dce60, ctx);
+	return &i2caux_dce60->base;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.h b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.h
new file mode 100644
index 000000000000..819b5ccbf977
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_I2C_AUX_DCE60_H__
+#define __DAL_I2C_AUX_DCE60_H__
+
+struct i2caux_dce60 {
+	struct i2caux base;
+	/* indicate the I2C HW circular buffer is in use */
+	bool i2c_hw_buffer_in_use;
+};
+
+struct i2caux *dal_i2caux_dce60_create(
+	struct dc_context *ctx);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
index e56093f26eed..6ca70c19a237 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
@@ -49,6 +49,10 @@
  * This unit
  */
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/i2caux_dce60.h"
+#endif
+
 #include "dce80/i2caux_dce80.h"
 
 #include "dce100/i2caux_dce100.h"
@@ -78,6 +82,12 @@ struct i2caux *dal_i2caux_create(
 	}
 
 	switch (ctx->dce_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+	case DCE_VERSION_6_0:
+	case DCE_VERSION_6_1:
+	case DCE_VERSION_6_4:
+		return dal_i2caux_dce60_create(ctx);
+#endif
 	case DCE_VERSION_8_0:
 	case DCE_VERSION_8_1:
 	case DCE_VERSION_8_3:
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 07/10] drm/amd/display: dc/irq: add support for DCE6

[Mauro Rossi]

DCE6 targets are added replicating existing DCE8 implementation.

NOTE: due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
dce/dce_8_0_{d,sh_mask}.h headers were used instead of dce/dce_6_0_{d,sh_mask}.h
but only as exception in dce/irq_service_dce60.c

IMPORTANT: Coding of dce/irq_service_dce60.c requires review to understand
if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
---
 drivers/gpu/drm/amd/display/dc/irq/Makefile   |  11 +
 .../display/dc/irq/dce60/irq_service_dce60.c  | 303 ++++++++++++++++++
 .../display/dc/irq/dce60/irq_service_dce60.h  |  35 ++
 .../gpu/drm/amd/display/dc/irq/irq_service.c  |   3 +
 4 files changed, 352 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h

diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index 498515aad4a5..e38b6d8d614d 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -30,6 +30,17 @@ AMD_DAL_IRQ = $(addprefix $(AMDDALPATH)/dc/irq/,$(IRQ))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_IRQ)
 
+###############################################################################
+# DCE 6x
+###############################################################################
+ifdef CONFIG_DRM_AMD_DC_SI
+IRQ_DCE60 = irq_service_dce60.o
+
+AMD_DAL_IRQ_DCE60 = $(addprefix $(AMDDALPATH)/dc/irq/dce60/,$(IRQ_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE60)
+endif
+
 ###############################################################################
 # DCE 8x
 ###############################################################################
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
new file mode 100644
index 000000000000..107e0dcb5f80
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/logger_interface.h"
+
+#include "irq_service_dce60.h"
+#include "../dce110/irq_service_dce110.h"
+
+#include "dce/dce_8_0_d.h"
+#include "dce/dce_8_0_sh_mask.h"
+
+#include "ivsrcid/ivsrcid_vislands30.h"
+
+#include "dc_types.h"
+
+static bool hpd_ack(
+	struct irq_service *irq_service,
+	const struct irq_source_info *info)
+{
+	uint32_t addr = info->status_reg;
+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
+	uint32_t current_status =
+		get_reg_field_value(
+			value,
+			DC_HPD1_INT_STATUS,
+			DC_HPD1_SENSE_DELAYED);
+
+	dal_irq_service_ack_generic(irq_service, info);
+
+	value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+	set_reg_field_value(
+		value,
+		current_status ? 0 : 1,
+		DC_HPD1_INT_CONTROL,
+		DC_HPD1_INT_POLARITY);
+
+	dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+	return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+	.set = NULL,
+	.ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+	.set = dce110_vblank_set,
+	.ack = NULL
+};
+
+
+#define hpd_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_INVALID + reg_num] = {\
+		.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
+		.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
+		.enable_value = {\
+			DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
+			~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
+		},\
+		.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
+		.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
+		.ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
+		.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
+		.funcs = &hpd_irq_info_funcs\
+	}
+
+#define hpd_rx_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_HPD6 + reg_num] = {\
+		.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
+		.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
+		.enable_value = {\
+				DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
+			~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
+		.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
+		.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
+		.ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
+		.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
+		.funcs = &hpd_rx_irq_info_funcs\
+	}
+
+#define pflip_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
+		.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
+		.enable_mask =\
+		GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
+		.enable_value = {\
+			GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
+			~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
+		.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
+		.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
+		.ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
+		.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
+		.funcs = &pflip_irq_info_funcs\
+ 	}
+
+#define vupdate_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
+		.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
+		.enable_mask =\
+		CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
+		.enable_value = {\
+			CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
+			~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
+		.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
+		.ack_mask =\
+		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
+		.ack_value =\
+		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
+		.funcs = &vblank_irq_info_funcs\
+	}
+
+#define vblank_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
+		.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
+		.enable_mask =\
+		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
+		.enable_value = {\
+			CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
+			~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
+		.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
+		.ack_mask =\
+		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
+		.ack_value =\
+		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
+		.funcs = &vblank_irq_info_funcs,\
+		.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
+	}
+
+#define dummy_irq_entry() \
+	{\
+		.funcs = &dummy_irq_info_funcs\
+	}
+
+#define i2c_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
+
+#define dp_sink_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
+
+#define gpio_pad_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
+
+#define dc_underflow_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
+
+
+static const struct irq_source_info_funcs dummy_irq_info_funcs = {
+	.set = dal_irq_service_dummy_set,
+	.ack = dal_irq_service_dummy_ack
+};
+
+static const struct irq_source_info
+irq_source_info_dce60[DAL_IRQ_SOURCES_NUMBER] = {
+	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
+	hpd_int_entry(1),
+	hpd_int_entry(2),
+	hpd_int_entry(3),
+	hpd_int_entry(4),
+	hpd_int_entry(5),
+	hpd_int_entry(6),
+	hpd_rx_int_entry(1),
+	hpd_rx_int_entry(2),
+	hpd_rx_int_entry(3),
+	hpd_rx_int_entry(4),
+	hpd_rx_int_entry(5),
+	hpd_rx_int_entry(6),
+	i2c_int_entry(1),
+	i2c_int_entry(2),
+	i2c_int_entry(3),
+	i2c_int_entry(4),
+	i2c_int_entry(5),
+	i2c_int_entry(6),
+	dp_sink_int_entry(1),
+	dp_sink_int_entry(2),
+	dp_sink_int_entry(3),
+	dp_sink_int_entry(4),
+	dp_sink_int_entry(5),
+	dp_sink_int_entry(6),
+	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
+	pflip_int_entry(0),
+	pflip_int_entry(1),
+	pflip_int_entry(2),
+	pflip_int_entry(3),
+	pflip_int_entry(4),
+	pflip_int_entry(5),
+	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
+	gpio_pad_int_entry(0),
+	gpio_pad_int_entry(1),
+	gpio_pad_int_entry(2),
+	gpio_pad_int_entry(3),
+	gpio_pad_int_entry(4),
+	gpio_pad_int_entry(5),
+	gpio_pad_int_entry(6),
+	gpio_pad_int_entry(7),
+	gpio_pad_int_entry(8),
+	gpio_pad_int_entry(9),
+	gpio_pad_int_entry(10),
+	gpio_pad_int_entry(11),
+	gpio_pad_int_entry(12),
+	gpio_pad_int_entry(13),
+	gpio_pad_int_entry(14),
+	gpio_pad_int_entry(15),
+	gpio_pad_int_entry(16),
+	gpio_pad_int_entry(17),
+	gpio_pad_int_entry(18),
+	gpio_pad_int_entry(19),
+	gpio_pad_int_entry(20),
+	gpio_pad_int_entry(21),
+	gpio_pad_int_entry(22),
+	gpio_pad_int_entry(23),
+	gpio_pad_int_entry(24),
+	gpio_pad_int_entry(25),
+	gpio_pad_int_entry(26),
+	gpio_pad_int_entry(27),
+	gpio_pad_int_entry(28),
+	gpio_pad_int_entry(29),
+	gpio_pad_int_entry(30),
+	dc_underflow_int_entry(1),
+	dc_underflow_int_entry(2),
+	dc_underflow_int_entry(3),
+	dc_underflow_int_entry(4),
+	dc_underflow_int_entry(5),
+	dc_underflow_int_entry(6),
+	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
+	vupdate_int_entry(0),
+	vupdate_int_entry(1),
+	vupdate_int_entry(2),
+	vupdate_int_entry(3),
+	vupdate_int_entry(4),
+	vupdate_int_entry(5),
+	vblank_int_entry(0),
+	vblank_int_entry(1),
+	vblank_int_entry(2),
+	vblank_int_entry(3),
+	vblank_int_entry(4),
+	vblank_int_entry(5),
+};
+
+static const struct irq_service_funcs irq_service_funcs_dce60 = {
+		.to_dal_irq_source = to_dal_irq_source_dce110
+};
+
+static void construct(
+	struct irq_service *irq_service,
+	struct irq_service_init_data *init_data)
+{
+	dal_irq_service_construct(irq_service, init_data);
+
+	irq_service->info = irq_source_info_dce60;
+	irq_service->funcs = &irq_service_funcs_dce60;
+}
+
+struct irq_service *dal_irq_service_dce60_create(
+	struct irq_service_init_data *init_data)
+{
+	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
+						  GFP_KERNEL);
+
+	if (!irq_service)
+		return NULL;
+
+	construct(irq_service, init_data);
+	return irq_service;
+}
+
+
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
new file mode 100644
index 000000000000..7314268c739c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_IRQ_SERVICE_DCE60_H__
+#define __DAL_IRQ_SERVICE_DCE60_H__
+
+#include "../irq_service.h"
+
+struct irq_service *dal_irq_service_dce60_create(
+	struct irq_service_init_data *init_data);
+
+#endif
+
diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
index 604bea01fc13..190543cdff60 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
@@ -30,6 +30,9 @@
 
 #include "dce110/irq_service_dce110.h"
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/irq_service_dce60.h"
+#endif
 
 #include "dce80/irq_service_dce80.h"
 
-- 
2.17.1

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Re: [PATCH v2 07/10] drm/amd/display: dc/irq: add support for DCE6

[Wentland, Harry]

On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> DCE6 targets are added replicating existing DCE8 implementation.
> 
> NOTE: due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
> dce/dce_8_0_{d,sh_mask}.h headers were used instead of dce/dce_6_0_{d,sh_mask}.h
> but only as exception in dce/irq_service_dce60.c
> 
> IMPORTANT: Coding of dce/irq_service_dce60.c requires review to understand
> if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
> ---
>  drivers/gpu/drm/amd/display/dc/irq/Makefile   |  11 +
>  .../display/dc/irq/dce60/irq_service_dce60.c  | 303 ++++++++++++++++++
>  .../display/dc/irq/dce60/irq_service_dce60.h  |  35 ++
>  .../gpu/drm/amd/display/dc/irq/irq_service.c  |   3 +
>  4 files changed, 352 insertions(+)
>  create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
>  create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile
> index 498515aad4a5..e38b6d8d614d 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
> @@ -30,6 +30,17 @@ AMD_DAL_IRQ = $(addprefix $(AMDDALPATH)/dc/irq/,$(IRQ))
>  
>  AMD_DISPLAY_FILES += $(AMD_DAL_IRQ)
>  
> +###############################################################################
> +# DCE 6x
> +###############################################################################
> +ifdef CONFIG_DRM_AMD_DC_SI
> +IRQ_DCE60 = irq_service_dce60.o
> +
> +AMD_DAL_IRQ_DCE60 = $(addprefix $(AMDDALPATH)/dc/irq/dce60/,$(IRQ_DCE60))
> +
> +AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE60)
> +endif
> +
>  ###############################################################################
>  # DCE 8x
>  ###############################################################################
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> new file mode 100644
> index 000000000000..107e0dcb5f80
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> @@ -0,0 +1,303 @@
> +/*
> + * Copyright 2012-15 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: AMD
> + *
> + */
> +
> +#include "dm_services.h"
> +
> +#include "include/logger_interface.h"
> +
> +#include "irq_service_dce60.h"
> +#include "../dce110/irq_service_dce110.h"
> +
> +#include "dce/dce_8_0_d.h"
> +#include "dce/dce_8_0_sh_mask.h"
> +
> +#include "ivsrcid/ivsrcid_vislands30.h"
> +
> +#include "dc_types.h"
> +
> +static bool hpd_ack(
> +	struct irq_service *irq_service,
> +	const struct irq_source_info *info)
> +{
> +	uint32_t addr = info->status_reg;
> +	uint32_t value = dm_read_reg(irq_service->ctx, addr);
> +	uint32_t current_status =
> +		get_reg_field_value(
> +			value,
> +			DC_HPD1_INT_STATUS,
> +			DC_HPD1_SENSE_DELAYED);
> +
> +	dal_irq_service_ack_generic(irq_service, info);
> +
> +	value = dm_read_reg(irq_service->ctx, info->enable_reg);
> +
> +	set_reg_field_value(
> +		value,
> +		current_status ? 0 : 1,
> +		DC_HPD1_INT_CONTROL,
> +		DC_HPD1_INT_POLARITY);
> +
> +	dm_write_reg(irq_service->ctx, info->enable_reg, value);
> +
> +	return true;
> +}
> +
> +static const struct irq_source_info_funcs hpd_irq_info_funcs = {
> +	.set = NULL,
> +	.ack = hpd_ack
> +};
> +
> +static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
> +	.set = NULL,
> +	.ack = NULL
> +};
> +
> +static const struct irq_source_info_funcs pflip_irq_info_funcs = {
> +	.set = NULL,
> +	.ack = NULL
> +};
> +
> +static const struct irq_source_info_funcs vblank_irq_info_funcs = {
> +	.set = dce110_vblank_set,
> +	.ack = NULL
> +};
> +
> +
> +#define hpd_int_entry(reg_num)\
> +	[DC_IRQ_SOURCE_INVALID + reg_num] = {\
> +		.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
> +		.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
> +		.enable_value = {\
> +			DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
> +			~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
> +		},\
> +		.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
> +		.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
> +		.ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
> +		.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
> +		.funcs = &hpd_irq_info_funcs\
> +	}
> +
> +#define hpd_rx_int_entry(reg_num)\
> +	[DC_IRQ_SOURCE_HPD6 + reg_num] = {\
> +		.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
> +		.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
> +		.enable_value = {\
> +				DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
> +			~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
> +		.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
> +		.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
> +		.ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
> +		.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
> +		.funcs = &hpd_rx_irq_info_funcs\
> +	}
> +
> +#define pflip_int_entry(reg_num)\
> +	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
> +		.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
> +		.enable_mask =\
> +		GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
> +		.enable_value = {\
> +			GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
> +			~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
> +		.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
> +		.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
> +		.ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
> +		.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
> +		.funcs = &pflip_irq_info_funcs\
> + 	}
> +
> +#define vupdate_int_entry(reg_num)\
> +	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
> +		.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
> +		.enable_mask =\
> +		CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
> +		.enable_value = {\
> +			CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
> +			~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
> +		.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
> +		.ack_mask =\
> +		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
> +		.ack_value =\
> +		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
> +		.funcs = &vblank_irq_info_funcs\
> +	}
> +
> +#define vblank_int_entry(reg_num)\
> +	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
> +		.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
> +		.enable_mask =\
> +		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
> +		.enable_value = {\
> +			CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
> +			~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
> +		.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
> +		.ack_mask =\
> +		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
> +		.ack_value =\
> +		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
> +		.funcs = &vblank_irq_info_funcs,\
> +		.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
> +	}
> +

Looks like that register doesn't exist in DCE6. At least I can't see it. Can you see if you can adapt the registers from dce_v6_0_set_crtc_vblank_interrupt_state() and dce_v6_0_crtc_irq() in conjunction with interrupt_status_offsets[] in amdgpu/dce_v6_0.c?

As-is I don't expect you get vblank interrupts.

Harry

> +#define dummy_irq_entry() \
> +	{\
> +		.funcs = &dummy_irq_info_funcs\
> +	}
> +
> +#define i2c_int_entry(reg_num) \
> +	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
> +
> +#define dp_sink_int_entry(reg_num) \
> +	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
> +
> +#define gpio_pad_int_entry(reg_num) \
> +	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
> +
> +#define dc_underflow_int_entry(reg_num) \
> +	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
> +
> +
> +static const struct irq_source_info_funcs dummy_irq_info_funcs = {
> +	.set = dal_irq_service_dummy_set,
> +	.ack = dal_irq_service_dummy_ack
> +};
> +
> +static const struct irq_source_info
> +irq_source_info_dce60[DAL_IRQ_SOURCES_NUMBER] = {
> +	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
> +	hpd_int_entry(1),
> +	hpd_int_entry(2),
> +	hpd_int_entry(3),
> +	hpd_int_entry(4),
> +	hpd_int_entry(5),
> +	hpd_int_entry(6),
> +	hpd_rx_int_entry(1),
> +	hpd_rx_int_entry(2),
> +	hpd_rx_int_entry(3),
> +	hpd_rx_int_entry(4),
> +	hpd_rx_int_entry(5),
> +	hpd_rx_int_entry(6),
> +	i2c_int_entry(1),
> +	i2c_int_entry(2),
> +	i2c_int_entry(3),
> +	i2c_int_entry(4),
> +	i2c_int_entry(5),
> +	i2c_int_entry(6),
> +	dp_sink_int_entry(1),
> +	dp_sink_int_entry(2),
> +	dp_sink_int_entry(3),
> +	dp_sink_int_entry(4),
> +	dp_sink_int_entry(5),
> +	dp_sink_int_entry(6),
> +	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
> +	pflip_int_entry(0),
> +	pflip_int_entry(1),
> +	pflip_int_entry(2),
> +	pflip_int_entry(3),
> +	pflip_int_entry(4),
> +	pflip_int_entry(5),
> +	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
> +	gpio_pad_int_entry(0),
> +	gpio_pad_int_entry(1),
> +	gpio_pad_int_entry(2),
> +	gpio_pad_int_entry(3),
> +	gpio_pad_int_entry(4),
> +	gpio_pad_int_entry(5),
> +	gpio_pad_int_entry(6),
> +	gpio_pad_int_entry(7),
> +	gpio_pad_int_entry(8),
> +	gpio_pad_int_entry(9),
> +	gpio_pad_int_entry(10),
> +	gpio_pad_int_entry(11),
> +	gpio_pad_int_entry(12),
> +	gpio_pad_int_entry(13),
> +	gpio_pad_int_entry(14),
> +	gpio_pad_int_entry(15),
> +	gpio_pad_int_entry(16),
> +	gpio_pad_int_entry(17),
> +	gpio_pad_int_entry(18),
> +	gpio_pad_int_entry(19),
> +	gpio_pad_int_entry(20),
> +	gpio_pad_int_entry(21),
> +	gpio_pad_int_entry(22),
> +	gpio_pad_int_entry(23),
> +	gpio_pad_int_entry(24),
> +	gpio_pad_int_entry(25),
> +	gpio_pad_int_entry(26),
> +	gpio_pad_int_entry(27),
> +	gpio_pad_int_entry(28),
> +	gpio_pad_int_entry(29),
> +	gpio_pad_int_entry(30),
> +	dc_underflow_int_entry(1),
> +	dc_underflow_int_entry(2),
> +	dc_underflow_int_entry(3),
> +	dc_underflow_int_entry(4),
> +	dc_underflow_int_entry(5),
> +	dc_underflow_int_entry(6),
> +	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
> +	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
> +	vupdate_int_entry(0),
> +	vupdate_int_entry(1),
> +	vupdate_int_entry(2),
> +	vupdate_int_entry(3),
> +	vupdate_int_entry(4),
> +	vupdate_int_entry(5),
> +	vblank_int_entry(0),
> +	vblank_int_entry(1),
> +	vblank_int_entry(2),
> +	vblank_int_entry(3),
> +	vblank_int_entry(4),
> +	vblank_int_entry(5),
> +};
> +
> +static const struct irq_service_funcs irq_service_funcs_dce60 = {
> +		.to_dal_irq_source = to_dal_irq_source_dce110
> +};
> +
> +static void construct(
> +	struct irq_service *irq_service,
> +	struct irq_service_init_data *init_data)
> +{
> +	dal_irq_service_construct(irq_service, init_data);
> +
> +	irq_service->info = irq_source_info_dce60;
> +	irq_service->funcs = &irq_service_funcs_dce60;
> +}
> +
> +struct irq_service *dal_irq_service_dce60_create(
> +	struct irq_service_init_data *init_data)
> +{
> +	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
> +						  GFP_KERNEL);
> +
> +	if (!irq_service)
> +		return NULL;
> +
> +	construct(irq_service, init_data);
> +	return irq_service;
> +}
> +
> +
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
> new file mode 100644
> index 000000000000..7314268c739c
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright 2012-15 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: AMD
> + *
> + */
> +
> +#ifndef __DAL_IRQ_SERVICE_DCE60_H__
> +#define __DAL_IRQ_SERVICE_DCE60_H__
> +
> +#include "../irq_service.h"
> +
> +struct irq_service *dal_irq_service_dce60_create(
> +	struct irq_service_init_data *init_data);
> +
> +#endif
> +
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
> index 604bea01fc13..190543cdff60 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
> +++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
> @@ -30,6 +30,9 @@
>  
>  #include "dce110/irq_service_dce110.h"
>  
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> +#include "dce60/irq_service_dce60.h"
> +#endif
>  
>  #include "dce80/irq_service_dce80.h"
>  
> 
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[PATCH] WIP: drm/amd/display: dc/irq: use dce_6_0_{d,sh_mask}.h

[Mauro Rossi]

Work In Progress for using DCE6 headers
vblank registers and masks where identified,
but using them gives a glipse with monitor screen active,
followed by monitor screen in standby

Please review to identify the problem
as the DCE6 vblank irq do not map exactlyto DC irq code,
it's not clear how to_dal_irq_source_dce60 should be defined and used
and it's not clear how to manage the DCE6 registers
in the following struct:

static const struct irq_source_info_funcs vblank_irq_info_funcs = {
	.set = dce110_vblank_set,
	.ack = NULL
};
---
 .../display/dc/irq/dce60/irq_service_dce60.c  | 116 +++++++++++++++---
 .../display/dc/irq/dce60/irq_service_dce60.h  |   5 +
 .../drm/amd/include/asic_reg/dce/dce_6_0_d.h  |  14 +++
 .../include/asic_reg/dce/dce_6_0_sh_mask.h    |  24 ++++
 4 files changed, 145 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
index 107e0dcb5f80..c3befab49374 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
@@ -30,10 +30,17 @@
 #include "irq_service_dce60.h"
 #include "../dce110/irq_service_dce110.h"
 
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+/* Q1: Are the DCE8 Interrupt Vector tables applicable to DCE6? */
 #include "ivsrcid/ivsrcid_vislands30.h"
+/* See b10d51f8 ("drm/amd/display: Add interrupt entries for VBLANK isr.") */
+#define VISLANDS30_IV_SRCID_D1_VBLANK                        1
+#define VISLANDS30_IV_SRCID_D2_VBLANK                        2
+#define VISLANDS30_IV_SRCID_D3_VBLANK                        3
+#define VISLANDS30_IV_SRCID_D4_VBLANK                        4
+#define VISLANDS30_IV_SRCID_D5_VBLANK                        5
+#define VISLANDS30_IV_SRCID_D6_VBLANK                        6
 
 #include "dc_types.h"
 
@@ -78,7 +85,7 @@ static const struct irq_source_info_funcs pflip_irq_info_funcs = {
 	.set = NULL,
 	.ack = NULL
 };
-
+ /* NOTE: .set = NULL in commit b10d51f8 Q2: Can dce110_vblank_set be used here? */
 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
 	.set = dce110_vblank_set,
 	.ack = NULL
@@ -145,21 +152,21 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
 		.funcs = &vblank_irq_info_funcs\
 	}
 
+/* NOTE: vblank_irq_info_funcs.set = dce110_vblank instead of NULL (see b10d51f8) */
 #define vblank_int_entry(reg_num)\
 	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
-		.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
+		.enable_reg = mmLB ## reg_num ## _INT_MASK,\
 		.enable_mask =\
-		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
+			INT_MASK__VBLANK_INT_MASK,\
 		.enable_value = {\
-			CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
-			~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
-		.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
+			INT_MASK__VBLANK_INT_MASK,\
+			~INT_MASK__VBLANK_INT_MASK},\
+		.ack_reg = mmLB ## reg_num ## _VBLANK_STATUS,\
 		.ack_mask =\
-		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
+		VBLANK_STATUS__VBLANK_ACK_MASK,\
 		.ack_value =\
-		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
-		.funcs = &vblank_irq_info_funcs,\
-		.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
+		VBLANK_STATUS__VBLANK_ACK_MASK,\
+		.funcs = &vblank_irq_info_funcs\
 	}
 
 #define dummy_irq_entry() \
@@ -273,8 +280,89 @@ irq_source_info_dce60[DAL_IRQ_SOURCES_NUMBER] = {
 	vblank_int_entry(5),
 };
 
+/* to_dal_irq_source_dce60 treats VBLANK differently from common dce110 one */
+enum dc_irq_source to_dal_irq_source_dce60(
+		struct irq_service *irq_service,
+		uint32_t src_id,
+		uint32_t ext_id)
+{
+	switch (src_id) {
+	case VISLANDS30_IV_SRCID_D1_VBLANK:
+		return DC_IRQ_SOURCE_VBLANK1;
+	case VISLANDS30_IV_SRCID_D2_VBLANK:
+		return DC_IRQ_SOURCE_VBLANK2;
+	case VISLANDS30_IV_SRCID_D3_VBLANK:
+		return DC_IRQ_SOURCE_VBLANK3;
+	case VISLANDS30_IV_SRCID_D4_VBLANK:
+		return DC_IRQ_SOURCE_VBLANK4;
+	case VISLANDS30_IV_SRCID_D5_VBLANK:
+		return DC_IRQ_SOURCE_VBLANK5;
+	case VISLANDS30_IV_SRCID_D6_VBLANK:
+		return DC_IRQ_SOURCE_VBLANK6;
+	case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
+		return DC_IRQ_SOURCE_VUPDATE1;
+	case VISLANDS30_IV_SRCID_D2_V_UPDATE_INT:
+		return DC_IRQ_SOURCE_VUPDATE2;
+	case VISLANDS30_IV_SRCID_D3_V_UPDATE_INT:
+		return DC_IRQ_SOURCE_VUPDATE3;
+	case VISLANDS30_IV_SRCID_D4_V_UPDATE_INT:
+		return DC_IRQ_SOURCE_VUPDATE4;
+	case VISLANDS30_IV_SRCID_D5_V_UPDATE_INT:
+		return DC_IRQ_SOURCE_VUPDATE5;
+	case VISLANDS30_IV_SRCID_D6_V_UPDATE_INT:
+		return DC_IRQ_SOURCE_VUPDATE6;
+	case VISLANDS30_IV_SRCID_D1_GRPH_PFLIP:
+		return DC_IRQ_SOURCE_PFLIP1;
+	case VISLANDS30_IV_SRCID_D2_GRPH_PFLIP:
+		return DC_IRQ_SOURCE_PFLIP2;
+	case VISLANDS30_IV_SRCID_D3_GRPH_PFLIP:
+		return DC_IRQ_SOURCE_PFLIP3;
+	case VISLANDS30_IV_SRCID_D4_GRPH_PFLIP:
+		return DC_IRQ_SOURCE_PFLIP4;
+	case VISLANDS30_IV_SRCID_D5_GRPH_PFLIP:
+		return DC_IRQ_SOURCE_PFLIP5;
+	case VISLANDS30_IV_SRCID_D6_GRPH_PFLIP:
+		return DC_IRQ_SOURCE_PFLIP6;
+
+	case VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A:
+		/* generic src_id for all HPD and HPDRX interrupts */
+		switch (ext_id) {
+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A:
+			return DC_IRQ_SOURCE_HPD1;
+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B:
+			return DC_IRQ_SOURCE_HPD2;
+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C:
+			return DC_IRQ_SOURCE_HPD3;
+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D:
+			return DC_IRQ_SOURCE_HPD4;
+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E:
+			return DC_IRQ_SOURCE_HPD5;
+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F:
+			return DC_IRQ_SOURCE_HPD6;
+		case VISLANDS30_IV_EXTID_HPD_RX_A:
+			return DC_IRQ_SOURCE_HPD1RX;
+		case VISLANDS30_IV_EXTID_HPD_RX_B:
+			return DC_IRQ_SOURCE_HPD2RX;
+		case VISLANDS30_IV_EXTID_HPD_RX_C:
+			return DC_IRQ_SOURCE_HPD3RX;
+		case VISLANDS30_IV_EXTID_HPD_RX_D:
+			return DC_IRQ_SOURCE_HPD4RX;
+		case VISLANDS30_IV_EXTID_HPD_RX_E:
+			return DC_IRQ_SOURCE_HPD5RX;
+		case VISLANDS30_IV_EXTID_HPD_RX_F:
+			return DC_IRQ_SOURCE_HPD6RX;
+		default:
+			return DC_IRQ_SOURCE_INVALID;
+		}
+		break;
+
+	default:
+		return DC_IRQ_SOURCE_INVALID;
+	}
+}
+
 static const struct irq_service_funcs irq_service_funcs_dce60 = {
-		.to_dal_irq_source = to_dal_irq_source_dce110
+		.to_dal_irq_source = to_dal_irq_source_dce60
 };
 
 static void construct(
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
index 7314268c739c..d9224b158fc2 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
@@ -28,6 +28,11 @@
 
 #include "../irq_service.h"
 
+enum dc_irq_source to_dal_irq_source_dce60(
+		struct irq_service *irq_service,
+		uint32_t src_id,
+		uint32_t ext_id);
+
 struct irq_service *dal_irq_service_dce60_create(
 	struct irq_service_init_data *init_data);
 
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
index ae798f768853..5f16097d9044 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
@@ -3879,6 +3879,7 @@
 #define mmKEY_RANGE_GREEN 0x1A56
 #define mmKEY_RANGE_RED 0x1A55
 #define mmLB0_DC_MVP_LB_CONTROL 0x1ADB
+#define mmLB0_INT_MASK 0x1AD0
 #define mmLB0_LB_DEBUG 0x1AFC
 #define mmLB0_LB_DEBUG2 0x1AC9
 #define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1AC8
@@ -3888,7 +3889,9 @@
 #define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1AD9
 #define mmLB0_MVP_AFR_FLIP_MODE 0x1AD8
 #define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ADA
+#define mmLB0_VBLANK_STATUS 0x1AEF
 #define mmLB1_DC_MVP_LB_CONTROL 0x1DDB
+#define mmLB1_INT_MASK 0x1DD0
 #define mmLB1_LB_DEBUG 0x1DFC
 #define mmLB1_LB_DEBUG2 0x1DC9
 #define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1DC8
@@ -3898,7 +3901,9 @@
 #define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1DD9
 #define mmLB1_MVP_AFR_FLIP_MODE 0x1DD8
 #define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1DDA
+#define mmLB1_VBLANK_STATUS 0x1DEF
 #define mmLB2_DC_MVP_LB_CONTROL 0x40DB
+#define mmLB2_INT_MASK 0x40D0
 #define mmLB2_LB_DEBUG 0x40FC
 #define mmLB2_LB_DEBUG2 0x40C9
 #define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40C8
@@ -3908,7 +3913,9 @@
 #define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40D9
 #define mmLB2_MVP_AFR_FLIP_MODE 0x40D8
 #define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40DA
+#define mmLB2_VBLANK_STATUS 0x40EF
 #define mmLB3_DC_MVP_LB_CONTROL 0x43DB
+#define mmLB3_INT_MASK 0x43D0
 #define mmLB3_LB_DEBUG 0x43FC
 #define mmLB3_LB_DEBUG2 0x43C9
 #define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43C8
@@ -3918,7 +3925,9 @@
 #define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43D9
 #define mmLB3_MVP_AFR_FLIP_MODE 0x43D8
 #define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43DA
+#define mmLB3_VBLANK_STATUS 0x43EF
 #define mmLB4_DC_MVP_LB_CONTROL 0x46DB
+#define mmLB4_INT_MASK 0x46D0
 #define mmLB4_LB_DEBUG 0x46FC
 #define mmLB4_LB_DEBUG2 0x46C9
 #define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46C8
@@ -3928,7 +3937,9 @@
 #define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46D9
 #define mmLB4_MVP_AFR_FLIP_MODE 0x46D8
 #define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46DA
+#define mmLB4_VBLANK_STATUS 0x46EF
 #define mmLB5_DC_MVP_LB_CONTROL 0x49DB
+#define mmLB5_INT_MASK 0x49D0
 #define mmLB5_LB_DEBUG 0x49FC
 #define mmLB5_LB_DEBUG2 0x49C9
 #define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49C8
@@ -3938,12 +3949,15 @@
 #define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49D9
 #define mmLB5_MVP_AFR_FLIP_MODE 0x49D8
 #define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49DA
+#define mmLB5_VBLANK_STATUS 0x49EF
 #define mmLB_DEBUG 0x1AFC
 #define mmLB_DEBUG2 0x1AC9
+#define mmLB_INT_MASK 0x1AD0
 #define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1AC8
 #define mmLB_SYNC_RESET_SEL 0x1ACA
 #define mmLB_TEST_DEBUG_DATA 0x1AFF
 #define mmLB_TEST_DEBUG_INDEX 0x1AFE
+#define mmLB_VBLANK_STATUS 0x1AEF
 #define mmLIGHT_SLEEP_CNTL 0x0132
 #define mmLOW_POWER_TILING_CONTROL 0x0325
 #define mmLVDS_DATA_CNTL 0x1C8C
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
index 5492c6b98525..53e13943eef2 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
@@ -7524,6 +7524,10 @@
 #define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x00000000
 #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x00000030L
 #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x00000004
+#define INT_MASK__VBLANK_INT_MASK 0x00000001L
+#define INT_MASK__VBLANK_INT__SHIFT 0x00000000
+#define INT_MASK__VLINE_INT_MASK 0x00000010L
+#define INT_MASK__VLINE_INT__SHIFT 0x00000004
 #define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000L
 #define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x0000001c
 #define KEY_CONTROL__KEY_MODE_MASK 0x00000006L
@@ -9372,6 +9376,26 @@
 #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0x0000000c
 #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x003e0000L
 #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x00000011
+#define VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+#define VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x00000000
+#define VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+#define VBLANK_STATUS__VBLANK_ACK__SHIFT 0x00000004
+#define VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+#define VBLANK_STATUS__VBLANK_STAT__SHIFT 0x0000000c
+#define VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+#define VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x00000010
+#define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+#define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x00000011
+#define VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+#define VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x00000000
+#define VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+#define VLINE_STATUS__VLINE_ACK__SHIFT 0x00000004
+#define VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+#define VLINE_STATUS__VLINE_STAT__SHIFT 0x0000000c
+#define VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+#define VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x00000010
+#define VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+#define VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x00000011
 #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x0000001fL
 #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x00000000
 #define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0x00000f00L
-- 
2.19.1

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Re: [PATCH] WIP: drm/amd/display: dc/irq: use dce_6_0_{d,sh_mask}.h

[Mauro Rossi]

Ah-ha! (Meaning self-checking and trying to self-correct myself)

I've seen that commit b10d51f8 ("drm/amd/display: Add interrupt
entries for VBLANK isr.")
required to be complemented by b57de80a ("drm/amd/display: Register on
VLBLANK ISR.")
which changed vblank irq control in dce110_register_irq_handlers() in file
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

In this WIP I did not applied changes in amdgpu_dm_irq.c accordingly
and this is the most probable root cause for screen being always blank

I will specialize a dce60_register_irq_handlers()
within braces #if defined(CONFIG_DRM_AMD_DC_SI)/#endif
and replicate the behavior of  b57de80a ("drm/amd/display: Register on
VLBLANK ISR.")

Please let me know if I'm at least going in the right direction
and confirm that there is no other VBLANK Interrupt Register to be used in DCE6,
if there is some other VBLANK Interrupt Register better than the one I found
I'd like to know to implement directly the best solution.

Mauro

On Wed, Jan 2, 2019 at 1:12 AM Mauro Rossi <issor.oruam@gmail.com> wrote:
>
> Work In Progress for using DCE6 headers
> vblank registers and masks where identified,
> but using them gives a glipse with monitor screen active,
> followed by monitor screen in standby
>
> Please review to identify the problem
> as the DCE6 vblank irq do not map exactlyto DC irq code,
> it's not clear how to_dal_irq_source_dce60 should be defined and used
> and it's not clear how to manage the DCE6 registers
> in the following struct:
>
> static const struct irq_source_info_funcs vblank_irq_info_funcs = {
>         .set = dce110_vblank_set,
>         .ack = NULL
> };
> ---
>  .../display/dc/irq/dce60/irq_service_dce60.c  | 116 +++++++++++++++---
>  .../display/dc/irq/dce60/irq_service_dce60.h  |   5 +
>  .../drm/amd/include/asic_reg/dce/dce_6_0_d.h  |  14 +++
>  .../include/asic_reg/dce/dce_6_0_sh_mask.h    |  24 ++++
>  4 files changed, 145 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> index 107e0dcb5f80..c3befab49374 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> @@ -30,10 +30,17 @@
>  #include "irq_service_dce60.h"
>  #include "../dce110/irq_service_dce110.h"
>
> -#include "dce/dce_8_0_d.h"
> -#include "dce/dce_8_0_sh_mask.h"
> -
> +#include "dce/dce_6_0_d.h"
> +#include "dce/dce_6_0_sh_mask.h"
> +/* Q1: Are the DCE8 Interrupt Vector tables applicable to DCE6? */
>  #include "ivsrcid/ivsrcid_vislands30.h"
> +/* See b10d51f8 ("drm/amd/display: Add interrupt entries for VBLANK isr.") */
> +#define VISLANDS30_IV_SRCID_D1_VBLANK                        1
> +#define VISLANDS30_IV_SRCID_D2_VBLANK                        2
> +#define VISLANDS30_IV_SRCID_D3_VBLANK                        3
> +#define VISLANDS30_IV_SRCID_D4_VBLANK                        4
> +#define VISLANDS30_IV_SRCID_D5_VBLANK                        5
> +#define VISLANDS30_IV_SRCID_D6_VBLANK                        6
>
>  #include "dc_types.h"
>
> @@ -78,7 +85,7 @@ static const struct irq_source_info_funcs pflip_irq_info_funcs = {
>         .set = NULL,
>         .ack = NULL
>  };
> -
> + /* NOTE: .set = NULL in commit b10d51f8 Q2: Can dce110_vblank_set be used here? */
>  static const struct irq_source_info_funcs vblank_irq_info_funcs = {
>         .set = dce110_vblank_set,
>         .ack = NULL
> @@ -145,21 +152,21 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
>                 .funcs = &vblank_irq_info_funcs\
>         }
>
> +/* NOTE: vblank_irq_info_funcs.set = dce110_vblank instead of NULL (see b10d51f8) */
>  #define vblank_int_entry(reg_num)\
>         [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
> -               .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
> +               .enable_reg = mmLB ## reg_num ## _INT_MASK,\
>                 .enable_mask =\
> -               CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
> +                       INT_MASK__VBLANK_INT_MASK,\
>                 .enable_value = {\
> -                       CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
> -                       ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
> -               .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
> +                       INT_MASK__VBLANK_INT_MASK,\
> +                       ~INT_MASK__VBLANK_INT_MASK},\
> +               .ack_reg = mmLB ## reg_num ## _VBLANK_STATUS,\
>                 .ack_mask =\
> -               CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
> +               VBLANK_STATUS__VBLANK_ACK_MASK,\
>                 .ack_value =\
> -               CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
> -               .funcs = &vblank_irq_info_funcs,\
> -               .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
> +               VBLANK_STATUS__VBLANK_ACK_MASK,\
> +               .funcs = &vblank_irq_info_funcs\
>         }
>
>  #define dummy_irq_entry() \
> @@ -273,8 +280,89 @@ irq_source_info_dce60[DAL_IRQ_SOURCES_NUMBER] = {
>         vblank_int_entry(5),
>  };
>
> +/* to_dal_irq_source_dce60 treats VBLANK differently from common dce110 one */
> +enum dc_irq_source to_dal_irq_source_dce60(
> +               struct irq_service *irq_service,
> +               uint32_t src_id,
> +               uint32_t ext_id)
> +{
> +       switch (src_id) {
> +       case VISLANDS30_IV_SRCID_D1_VBLANK:
> +               return DC_IRQ_SOURCE_VBLANK1;
> +       case VISLANDS30_IV_SRCID_D2_VBLANK:
> +               return DC_IRQ_SOURCE_VBLANK2;
> +       case VISLANDS30_IV_SRCID_D3_VBLANK:
> +               return DC_IRQ_SOURCE_VBLANK3;
> +       case VISLANDS30_IV_SRCID_D4_VBLANK:
> +               return DC_IRQ_SOURCE_VBLANK4;
> +       case VISLANDS30_IV_SRCID_D5_VBLANK:
> +               return DC_IRQ_SOURCE_VBLANK5;
> +       case VISLANDS30_IV_SRCID_D6_VBLANK:
> +               return DC_IRQ_SOURCE_VBLANK6;
> +       case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
> +               return DC_IRQ_SOURCE_VUPDATE1;
> +       case VISLANDS30_IV_SRCID_D2_V_UPDATE_INT:
> +               return DC_IRQ_SOURCE_VUPDATE2;
> +       case VISLANDS30_IV_SRCID_D3_V_UPDATE_INT:
> +               return DC_IRQ_SOURCE_VUPDATE3;
> +       case VISLANDS30_IV_SRCID_D4_V_UPDATE_INT:
> +               return DC_IRQ_SOURCE_VUPDATE4;
> +       case VISLANDS30_IV_SRCID_D5_V_UPDATE_INT:
> +               return DC_IRQ_SOURCE_VUPDATE5;
> +       case VISLANDS30_IV_SRCID_D6_V_UPDATE_INT:
> +               return DC_IRQ_SOURCE_VUPDATE6;
> +       case VISLANDS30_IV_SRCID_D1_GRPH_PFLIP:
> +               return DC_IRQ_SOURCE_PFLIP1;
> +       case VISLANDS30_IV_SRCID_D2_GRPH_PFLIP:
> +               return DC_IRQ_SOURCE_PFLIP2;
> +       case VISLANDS30_IV_SRCID_D3_GRPH_PFLIP:
> +               return DC_IRQ_SOURCE_PFLIP3;
> +       case VISLANDS30_IV_SRCID_D4_GRPH_PFLIP:
> +               return DC_IRQ_SOURCE_PFLIP4;
> +       case VISLANDS30_IV_SRCID_D5_GRPH_PFLIP:
> +               return DC_IRQ_SOURCE_PFLIP5;
> +       case VISLANDS30_IV_SRCID_D6_GRPH_PFLIP:
> +               return DC_IRQ_SOURCE_PFLIP6;
> +
> +       case VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A:
> +               /* generic src_id for all HPD and HPDRX interrupts */
> +               switch (ext_id) {
> +               case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A:
> +                       return DC_IRQ_SOURCE_HPD1;
> +               case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B:
> +                       return DC_IRQ_SOURCE_HPD2;
> +               case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C:
> +                       return DC_IRQ_SOURCE_HPD3;
> +               case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D:
> +                       return DC_IRQ_SOURCE_HPD4;
> +               case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E:
> +                       return DC_IRQ_SOURCE_HPD5;
> +               case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F:
> +                       return DC_IRQ_SOURCE_HPD6;
> +               case VISLANDS30_IV_EXTID_HPD_RX_A:
> +                       return DC_IRQ_SOURCE_HPD1RX;
> +               case VISLANDS30_IV_EXTID_HPD_RX_B:
> +                       return DC_IRQ_SOURCE_HPD2RX;
> +               case VISLANDS30_IV_EXTID_HPD_RX_C:
> +                       return DC_IRQ_SOURCE_HPD3RX;
> +               case VISLANDS30_IV_EXTID_HPD_RX_D:
> +                       return DC_IRQ_SOURCE_HPD4RX;
> +               case VISLANDS30_IV_EXTID_HPD_RX_E:
> +                       return DC_IRQ_SOURCE_HPD5RX;
> +               case VISLANDS30_IV_EXTID_HPD_RX_F:
> +                       return DC_IRQ_SOURCE_HPD6RX;
> +               default:
> +                       return DC_IRQ_SOURCE_INVALID;
> +               }
> +               break;
> +
> +       default:
> +               return DC_IRQ_SOURCE_INVALID;
> +       }
> +}
> +
>  static const struct irq_service_funcs irq_service_funcs_dce60 = {
> -               .to_dal_irq_source = to_dal_irq_source_dce110
> +               .to_dal_irq_source = to_dal_irq_source_dce60
>  };
>
>  static void construct(
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
> index 7314268c739c..d9224b158fc2 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
> @@ -28,6 +28,11 @@
>
>  #include "../irq_service.h"
>
> +enum dc_irq_source to_dal_irq_source_dce60(
> +               struct irq_service *irq_service,
> +               uint32_t src_id,
> +               uint32_t ext_id);
> +
>  struct irq_service *dal_irq_service_dce60_create(
>         struct irq_service_init_data *init_data);
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
> index ae798f768853..5f16097d9044 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
> @@ -3879,6 +3879,7 @@
>  #define mmKEY_RANGE_GREEN 0x1A56
>  #define mmKEY_RANGE_RED 0x1A55
>  #define mmLB0_DC_MVP_LB_CONTROL 0x1ADB
> +#define mmLB0_INT_MASK 0x1AD0
>  #define mmLB0_LB_DEBUG 0x1AFC
>  #define mmLB0_LB_DEBUG2 0x1AC9
>  #define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1AC8
> @@ -3888,7 +3889,9 @@
>  #define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1AD9
>  #define mmLB0_MVP_AFR_FLIP_MODE 0x1AD8
>  #define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ADA
> +#define mmLB0_VBLANK_STATUS 0x1AEF
>  #define mmLB1_DC_MVP_LB_CONTROL 0x1DDB
> +#define mmLB1_INT_MASK 0x1DD0
>  #define mmLB1_LB_DEBUG 0x1DFC
>  #define mmLB1_LB_DEBUG2 0x1DC9
>  #define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1DC8
> @@ -3898,7 +3901,9 @@
>  #define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1DD9
>  #define mmLB1_MVP_AFR_FLIP_MODE 0x1DD8
>  #define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1DDA
> +#define mmLB1_VBLANK_STATUS 0x1DEF
>  #define mmLB2_DC_MVP_LB_CONTROL 0x40DB
> +#define mmLB2_INT_MASK 0x40D0
>  #define mmLB2_LB_DEBUG 0x40FC
>  #define mmLB2_LB_DEBUG2 0x40C9
>  #define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40C8
> @@ -3908,7 +3913,9 @@
>  #define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40D9
>  #define mmLB2_MVP_AFR_FLIP_MODE 0x40D8
>  #define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40DA
> +#define mmLB2_VBLANK_STATUS 0x40EF
>  #define mmLB3_DC_MVP_LB_CONTROL 0x43DB
> +#define mmLB3_INT_MASK 0x43D0
>  #define mmLB3_LB_DEBUG 0x43FC
>  #define mmLB3_LB_DEBUG2 0x43C9
>  #define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43C8
> @@ -3918,7 +3925,9 @@
>  #define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43D9
>  #define mmLB3_MVP_AFR_FLIP_MODE 0x43D8
>  #define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43DA
> +#define mmLB3_VBLANK_STATUS 0x43EF
>  #define mmLB4_DC_MVP_LB_CONTROL 0x46DB
> +#define mmLB4_INT_MASK 0x46D0
>  #define mmLB4_LB_DEBUG 0x46FC
>  #define mmLB4_LB_DEBUG2 0x46C9
>  #define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46C8
> @@ -3928,7 +3937,9 @@
>  #define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46D9
>  #define mmLB4_MVP_AFR_FLIP_MODE 0x46D8
>  #define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46DA
> +#define mmLB4_VBLANK_STATUS 0x46EF
>  #define mmLB5_DC_MVP_LB_CONTROL 0x49DB
> +#define mmLB5_INT_MASK 0x49D0
>  #define mmLB5_LB_DEBUG 0x49FC
>  #define mmLB5_LB_DEBUG2 0x49C9
>  #define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49C8
> @@ -3938,12 +3949,15 @@
>  #define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49D9
>  #define mmLB5_MVP_AFR_FLIP_MODE 0x49D8
>  #define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49DA
> +#define mmLB5_VBLANK_STATUS 0x49EF
>  #define mmLB_DEBUG 0x1AFC
>  #define mmLB_DEBUG2 0x1AC9
> +#define mmLB_INT_MASK 0x1AD0
>  #define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1AC8
>  #define mmLB_SYNC_RESET_SEL 0x1ACA
>  #define mmLB_TEST_DEBUG_DATA 0x1AFF
>  #define mmLB_TEST_DEBUG_INDEX 0x1AFE
> +#define mmLB_VBLANK_STATUS 0x1AEF
>  #define mmLIGHT_SLEEP_CNTL 0x0132
>  #define mmLOW_POWER_TILING_CONTROL 0x0325
>  #define mmLVDS_DATA_CNTL 0x1C8C
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
> index 5492c6b98525..53e13943eef2 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
> @@ -7524,6 +7524,10 @@
>  #define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x00000000
>  #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x00000030L
>  #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x00000004
> +#define INT_MASK__VBLANK_INT_MASK 0x00000001L
> +#define INT_MASK__VBLANK_INT__SHIFT 0x00000000
> +#define INT_MASK__VLINE_INT_MASK 0x00000010L
> +#define INT_MASK__VLINE_INT__SHIFT 0x00000004
>  #define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000L
>  #define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x0000001c
>  #define KEY_CONTROL__KEY_MODE_MASK 0x00000006L
> @@ -9372,6 +9376,26 @@
>  #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0x0000000c
>  #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x003e0000L
>  #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x00000011
> +#define VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
> +#define VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x00000000
> +#define VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
> +#define VBLANK_STATUS__VBLANK_ACK__SHIFT 0x00000004
> +#define VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
> +#define VBLANK_STATUS__VBLANK_STAT__SHIFT 0x0000000c
> +#define VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
> +#define VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x00000010
> +#define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
> +#define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x00000011
> +#define VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
> +#define VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x00000000
> +#define VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
> +#define VLINE_STATUS__VLINE_ACK__SHIFT 0x00000004
> +#define VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
> +#define VLINE_STATUS__VLINE_STAT__SHIFT 0x0000000c
> +#define VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
> +#define VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x00000010
> +#define VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
> +#define VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x00000011
>  #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x0000001fL
>  #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x00000000
>  #define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0x00000f00L
> --
> 2.19.1
>
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Re: [PATCH] WIP: drm/amd/display: dc/irq: use dce_6_0_{d,sh_mask}.h

[Mauro Rossi]

Hi,
just not to keep you engaged on this,
I've got the vblank irq handling working now.

I had exactly to replicate in dce60_irq_service.c the behavior of commit
b10d51f8 ("drm/amd/display: Add interrupt entries for VBLANK isr.")
and behavior of b57de80a ("drm/amd/display: Register on VLBLANK ISR.")
in amdgpu_dm.c

From functional point of view IRQ handling for DCE6 is complete,
I can proceed with other improvements, like Line Buffer/Watermark programming,
and VGA support for Kaveri and older.

Some suggestion those two areas by AMD developers would be very much
appreciated.

Kind regards
Mauro

On Wed, Jan 9, 2019 at 8:07 PM Mauro Rossi <issor.oruam@gmail.com> wrote:
>
> Ah-ha! (Meaning self-checking and trying to self-correct myself)
>
> I've seen that commit b10d51f8 ("drm/amd/display: Add interrupt
> entries for VBLANK isr.")
> required to be complemented by b57de80a ("drm/amd/display: Register on
> VLBLANK ISR.")
> which changed vblank irq control in dce110_register_irq_handlers() in file
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
>
> In this WIP I did not applied changes in amdgpu_dm_irq.c accordingly
> and this is the most probable root cause for screen being always blank
>
> I will specialize a dce60_register_irq_handlers()
> within braces #if defined(CONFIG_DRM_AMD_DC_SI)/#endif
> and replicate the behavior of  b57de80a ("drm/amd/display: Register on
> VLBLANK ISR.")
>
> Please let me know if I'm at least going in the right direction
> and confirm that there is no other VBLANK Interrupt Register to be used in DCE6,
> if there is some other VBLANK Interrupt Register better than the one I found
> I'd like to know to implement directly the best solution.
>
> Mauro
>
> On Wed, Jan 2, 2019 at 1:12 AM Mauro Rossi <issor.oruam@gmail.com> wrote:
> >
> > Work In Progress for using DCE6 headers
> > vblank registers and masks where identified,
> > but using them gives a glipse with monitor screen active,
> > followed by monitor screen in standby
> >
> > Please review to identify the problem
> > as the DCE6 vblank irq do not map exactlyto DC irq code,
> > it's not clear how to_dal_irq_source_dce60 should be defined and used
> > and it's not clear how to manage the DCE6 registers
> > in the following struct:
> >
> > static const struct irq_source_info_funcs vblank_irq_info_funcs = {
> >         .set = dce110_vblank_set,
> >         .ack = NULL
> > };
> > ---
> >  .../display/dc/irq/dce60/irq_service_dce60.c  | 116 +++++++++++++++---
> >  .../display/dc/irq/dce60/irq_service_dce60.h  |   5 +
> >  .../drm/amd/include/asic_reg/dce/dce_6_0_d.h  |  14 +++
> >  .../include/asic_reg/dce/dce_6_0_sh_mask.h    |  24 ++++
> >  4 files changed, 145 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> > index 107e0dcb5f80..c3befab49374 100644
> > --- a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> > +++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> > @@ -30,10 +30,17 @@
> >  #include "irq_service_dce60.h"
> >  #include "../dce110/irq_service_dce110.h"
> >
> > -#include "dce/dce_8_0_d.h"
> > -#include "dce/dce_8_0_sh_mask.h"
> > -
> > +#include "dce/dce_6_0_d.h"
> > +#include "dce/dce_6_0_sh_mask.h"
> > +/* Q1: Are the DCE8 Interrupt Vector tables applicable to DCE6? */
> >  #include "ivsrcid/ivsrcid_vislands30.h"
> > +/* See b10d51f8 ("drm/amd/display: Add interrupt entries for VBLANK isr.") */
> > +#define VISLANDS30_IV_SRCID_D1_VBLANK                        1
> > +#define VISLANDS30_IV_SRCID_D2_VBLANK                        2
> > +#define VISLANDS30_IV_SRCID_D3_VBLANK                        3
> > +#define VISLANDS30_IV_SRCID_D4_VBLANK                        4
> > +#define VISLANDS30_IV_SRCID_D5_VBLANK                        5
> > +#define VISLANDS30_IV_SRCID_D6_VBLANK                        6
> >
> >  #include "dc_types.h"
> >
> > @@ -78,7 +85,7 @@ static const struct irq_source_info_funcs pflip_irq_info_funcs = {
> >         .set = NULL,
> >         .ack = NULL
> >  };
> > -
> > + /* NOTE: .set = NULL in commit b10d51f8 Q2: Can dce110_vblank_set be used here? */
> >  static const struct irq_source_info_funcs vblank_irq_info_funcs = {
> >         .set = dce110_vblank_set,
> >         .ack = NULL
> > @@ -145,21 +152,21 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
> >                 .funcs = &vblank_irq_info_funcs\
> >         }
> >
> > +/* NOTE: vblank_irq_info_funcs.set = dce110_vblank instead of NULL (see b10d51f8) */
> >  #define vblank_int_entry(reg_num)\
> >         [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
> > -               .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
> > +               .enable_reg = mmLB ## reg_num ## _INT_MASK,\
> >                 .enable_mask =\
> > -               CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
> > +                       INT_MASK__VBLANK_INT_MASK,\
> >                 .enable_value = {\
> > -                       CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
> > -                       ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
> > -               .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
> > +                       INT_MASK__VBLANK_INT_MASK,\
> > +                       ~INT_MASK__VBLANK_INT_MASK},\
> > +               .ack_reg = mmLB ## reg_num ## _VBLANK_STATUS,\
> >                 .ack_mask =\
> > -               CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
> > +               VBLANK_STATUS__VBLANK_ACK_MASK,\
> >                 .ack_value =\
> > -               CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
> > -               .funcs = &vblank_irq_info_funcs,\
> > -               .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
> > +               VBLANK_STATUS__VBLANK_ACK_MASK,\
> > +               .funcs = &vblank_irq_info_funcs\
> >         }
> >
> >  #define dummy_irq_entry() \
> > @@ -273,8 +280,89 @@ irq_source_info_dce60[DAL_IRQ_SOURCES_NUMBER] = {
> >         vblank_int_entry(5),
> >  };
> >
> > +/* to_dal_irq_source_dce60 treats VBLANK differently from common dce110 one */
> > +enum dc_irq_source to_dal_irq_source_dce60(
> > +               struct irq_service *irq_service,
> > +               uint32_t src_id,
> > +               uint32_t ext_id)
> > +{
> > +       switch (src_id) {
> > +       case VISLANDS30_IV_SRCID_D1_VBLANK:
> > +               return DC_IRQ_SOURCE_VBLANK1;
> > +       case VISLANDS30_IV_SRCID_D2_VBLANK:
> > +               return DC_IRQ_SOURCE_VBLANK2;
> > +       case VISLANDS30_IV_SRCID_D3_VBLANK:
> > +               return DC_IRQ_SOURCE_VBLANK3;
> > +       case VISLANDS30_IV_SRCID_D4_VBLANK:
> > +               return DC_IRQ_SOURCE_VBLANK4;
> > +       case VISLANDS30_IV_SRCID_D5_VBLANK:
> > +               return DC_IRQ_SOURCE_VBLANK5;
> > +       case VISLANDS30_IV_SRCID_D6_VBLANK:
> > +               return DC_IRQ_SOURCE_VBLANK6;
> > +       case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
> > +               return DC_IRQ_SOURCE_VUPDATE1;
> > +       case VISLANDS30_IV_SRCID_D2_V_UPDATE_INT:
> > +               return DC_IRQ_SOURCE_VUPDATE2;
> > +       case VISLANDS30_IV_SRCID_D3_V_UPDATE_INT:
> > +               return DC_IRQ_SOURCE_VUPDATE3;
> > +       case VISLANDS30_IV_SRCID_D4_V_UPDATE_INT:
> > +               return DC_IRQ_SOURCE_VUPDATE4;
> > +       case VISLANDS30_IV_SRCID_D5_V_UPDATE_INT:
> > +               return DC_IRQ_SOURCE_VUPDATE5;
> > +       case VISLANDS30_IV_SRCID_D6_V_UPDATE_INT:
> > +               return DC_IRQ_SOURCE_VUPDATE6;
> > +       case VISLANDS30_IV_SRCID_D1_GRPH_PFLIP:
> > +               return DC_IRQ_SOURCE_PFLIP1;
> > +       case VISLANDS30_IV_SRCID_D2_GRPH_PFLIP:
> > +               return DC_IRQ_SOURCE_PFLIP2;
> > +       case VISLANDS30_IV_SRCID_D3_GRPH_PFLIP:
> > +               return DC_IRQ_SOURCE_PFLIP3;
> > +       case VISLANDS30_IV_SRCID_D4_GRPH_PFLIP:
> > +               return DC_IRQ_SOURCE_PFLIP4;
> > +       case VISLANDS30_IV_SRCID_D5_GRPH_PFLIP:
> > +               return DC_IRQ_SOURCE_PFLIP5;
> > +       case VISLANDS30_IV_SRCID_D6_GRPH_PFLIP:
> > +               return DC_IRQ_SOURCE_PFLIP6;
> > +
> > +       case VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A:
> > +               /* generic src_id for all HPD and HPDRX interrupts */
> > +               switch (ext_id) {
> > +               case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A:
> > +                       return DC_IRQ_SOURCE_HPD1;
> > +               case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B:
> > +                       return DC_IRQ_SOURCE_HPD2;
> > +               case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C:
> > +                       return DC_IRQ_SOURCE_HPD3;
> > +               case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D:
> > +                       return DC_IRQ_SOURCE_HPD4;
> > +               case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E:
> > +                       return DC_IRQ_SOURCE_HPD5;
> > +               case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F:
> > +                       return DC_IRQ_SOURCE_HPD6;
> > +               case VISLANDS30_IV_EXTID_HPD_RX_A:
> > +                       return DC_IRQ_SOURCE_HPD1RX;
> > +               case VISLANDS30_IV_EXTID_HPD_RX_B:
> > +                       return DC_IRQ_SOURCE_HPD2RX;
> > +               case VISLANDS30_IV_EXTID_HPD_RX_C:
> > +                       return DC_IRQ_SOURCE_HPD3RX;
> > +               case VISLANDS30_IV_EXTID_HPD_RX_D:
> > +                       return DC_IRQ_SOURCE_HPD4RX;
> > +               case VISLANDS30_IV_EXTID_HPD_RX_E:
> > +                       return DC_IRQ_SOURCE_HPD5RX;
> > +               case VISLANDS30_IV_EXTID_HPD_RX_F:
> > +                       return DC_IRQ_SOURCE_HPD6RX;
> > +               default:
> > +                       return DC_IRQ_SOURCE_INVALID;
> > +               }
> > +               break;
> > +
> > +       default:
> > +               return DC_IRQ_SOURCE_INVALID;
> > +       }
> > +}
> > +
> >  static const struct irq_service_funcs irq_service_funcs_dce60 = {
> > -               .to_dal_irq_source = to_dal_irq_source_dce110
> > +               .to_dal_irq_source = to_dal_irq_source_dce60
> >  };
> >
> >  static void construct(
> > diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
> > index 7314268c739c..d9224b158fc2 100644
> > --- a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
> > +++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
> > @@ -28,6 +28,11 @@
> >
> >  #include "../irq_service.h"
> >
> > +enum dc_irq_source to_dal_irq_source_dce60(
> > +               struct irq_service *irq_service,
> > +               uint32_t src_id,
> > +               uint32_t ext_id);
> > +
> >  struct irq_service *dal_irq_service_dce60_create(
> >         struct irq_service_init_data *init_data);
> >
> > diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
> > index ae798f768853..5f16097d9044 100644
> > --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
> > +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
> > @@ -3879,6 +3879,7 @@
> >  #define mmKEY_RANGE_GREEN 0x1A56
> >  #define mmKEY_RANGE_RED 0x1A55
> >  #define mmLB0_DC_MVP_LB_CONTROL 0x1ADB
> > +#define mmLB0_INT_MASK 0x1AD0
> >  #define mmLB0_LB_DEBUG 0x1AFC
> >  #define mmLB0_LB_DEBUG2 0x1AC9
> >  #define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1AC8
> > @@ -3888,7 +3889,9 @@
> >  #define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1AD9
> >  #define mmLB0_MVP_AFR_FLIP_MODE 0x1AD8
> >  #define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ADA
> > +#define mmLB0_VBLANK_STATUS 0x1AEF
> >  #define mmLB1_DC_MVP_LB_CONTROL 0x1DDB
> > +#define mmLB1_INT_MASK 0x1DD0
> >  #define mmLB1_LB_DEBUG 0x1DFC
> >  #define mmLB1_LB_DEBUG2 0x1DC9
> >  #define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1DC8
> > @@ -3898,7 +3901,9 @@
> >  #define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1DD9
> >  #define mmLB1_MVP_AFR_FLIP_MODE 0x1DD8
> >  #define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1DDA
> > +#define mmLB1_VBLANK_STATUS 0x1DEF
> >  #define mmLB2_DC_MVP_LB_CONTROL 0x40DB
> > +#define mmLB2_INT_MASK 0x40D0
> >  #define mmLB2_LB_DEBUG 0x40FC
> >  #define mmLB2_LB_DEBUG2 0x40C9
> >  #define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40C8
> > @@ -3908,7 +3913,9 @@
> >  #define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40D9
> >  #define mmLB2_MVP_AFR_FLIP_MODE 0x40D8
> >  #define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40DA
> > +#define mmLB2_VBLANK_STATUS 0x40EF
> >  #define mmLB3_DC_MVP_LB_CONTROL 0x43DB
> > +#define mmLB3_INT_MASK 0x43D0
> >  #define mmLB3_LB_DEBUG 0x43FC
> >  #define mmLB3_LB_DEBUG2 0x43C9
> >  #define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43C8
> > @@ -3918,7 +3925,9 @@
> >  #define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43D9
> >  #define mmLB3_MVP_AFR_FLIP_MODE 0x43D8
> >  #define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43DA
> > +#define mmLB3_VBLANK_STATUS 0x43EF
> >  #define mmLB4_DC_MVP_LB_CONTROL 0x46DB
> > +#define mmLB4_INT_MASK 0x46D0
> >  #define mmLB4_LB_DEBUG 0x46FC
> >  #define mmLB4_LB_DEBUG2 0x46C9
> >  #define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46C8
> > @@ -3928,7 +3937,9 @@
> >  #define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46D9
> >  #define mmLB4_MVP_AFR_FLIP_MODE 0x46D8
> >  #define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46DA
> > +#define mmLB4_VBLANK_STATUS 0x46EF
> >  #define mmLB5_DC_MVP_LB_CONTROL 0x49DB
> > +#define mmLB5_INT_MASK 0x49D0
> >  #define mmLB5_LB_DEBUG 0x49FC
> >  #define mmLB5_LB_DEBUG2 0x49C9
> >  #define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49C8
> > @@ -3938,12 +3949,15 @@
> >  #define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49D9
> >  #define mmLB5_MVP_AFR_FLIP_MODE 0x49D8
> >  #define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49DA
> > +#define mmLB5_VBLANK_STATUS 0x49EF
> >  #define mmLB_DEBUG 0x1AFC
> >  #define mmLB_DEBUG2 0x1AC9
> > +#define mmLB_INT_MASK 0x1AD0
> >  #define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1AC8
> >  #define mmLB_SYNC_RESET_SEL 0x1ACA
> >  #define mmLB_TEST_DEBUG_DATA 0x1AFF
> >  #define mmLB_TEST_DEBUG_INDEX 0x1AFE
> > +#define mmLB_VBLANK_STATUS 0x1AEF
> >  #define mmLIGHT_SLEEP_CNTL 0x0132
> >  #define mmLOW_POWER_TILING_CONTROL 0x0325
> >  #define mmLVDS_DATA_CNTL 0x1C8C
> > diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
> > index 5492c6b98525..53e13943eef2 100644
> > --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
> > +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
> > @@ -7524,6 +7524,10 @@
> >  #define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x00000000
> >  #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x00000030L
> >  #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x00000004
> > +#define INT_MASK__VBLANK_INT_MASK 0x00000001L
> > +#define INT_MASK__VBLANK_INT__SHIFT 0x00000000
> > +#define INT_MASK__VLINE_INT_MASK 0x00000010L
> > +#define INT_MASK__VLINE_INT__SHIFT 0x00000004
> >  #define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000L
> >  #define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x0000001c
> >  #define KEY_CONTROL__KEY_MODE_MASK 0x00000006L
> > @@ -9372,6 +9376,26 @@
> >  #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0x0000000c
> >  #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x003e0000L
> >  #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x00000011
> > +#define VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
> > +#define VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x00000000
> > +#define VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
> > +#define VBLANK_STATUS__VBLANK_ACK__SHIFT 0x00000004
> > +#define VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
> > +#define VBLANK_STATUS__VBLANK_STAT__SHIFT 0x0000000c
> > +#define VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
> > +#define VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x00000010
> > +#define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
> > +#define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x00000011
> > +#define VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
> > +#define VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x00000000
> > +#define VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
> > +#define VLINE_STATUS__VLINE_ACK__SHIFT 0x00000004
> > +#define VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
> > +#define VLINE_STATUS__VLINE_STAT__SHIFT 0x0000000c
> > +#define VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
> > +#define VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x00000010
> > +#define VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
> > +#define VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x00000011
> >  #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x0000001fL
> >  #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x00000000
> >  #define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0x00000f00L
> > --
> > 2.19.1
> >
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[PATCH v2 08/10] drm/amd/display: amdgpu_dm: add SI support (v2)

[Mauro Rossi]

This commit adds Display Manager early initialization for SI parts
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration

(v2) remove CHIP_HAINAN support since it does not have physical DCE6 module
     add SI families except CHIP_HAINAN in load_dmcu_fw() new function
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 492230c41b4a..7dedb363a476 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -514,6 +514,12 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
 	const struct dmcu_firmware_header_v1_0 *hdr;
 
 	switch(adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+	case CHIP_TAHITI:
+	case CHIP_PITCAIRN:
+	case CHIP_VERDE:
+	case CHIP_OLAND:
+#endif
 	case CHIP_BONAIRE:
 	case CHIP_HAWAII:
 	case CHIP_KAVERI:
@@ -1728,6 +1734,12 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 
 	/* Software is initialized. Now we can register interrupt handlers. */
 	switch (adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+	case CHIP_TAHITI:
+	case CHIP_PITCAIRN:
+	case CHIP_VERDE:
+	case CHIP_OLAND:
+#endif
 	case CHIP_BONAIRE:
 	case CHIP_HAWAII:
 	case CHIP_KAVERI:
@@ -1918,6 +1930,22 @@ static int dm_early_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	switch (adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+	case CHIP_TAHITI:
+	case CHIP_PITCAIRN:
+	case CHIP_VERDE:
+		adev->mode_info.num_crtc = 6;
+		adev->mode_info.num_hpd = 6;
+		adev->mode_info.num_dig = 6;
+		adev->mode_info.plane_type = dm_plane_type_default;
+		break;
+	case CHIP_OLAND:
+		adev->mode_info.num_crtc = 2;
+		adev->mode_info.num_hpd = 2;
+		adev->mode_info.num_dig = 2;
+		adev->mode_info.plane_type = dm_plane_type_default;
+		break;
+#endif
 	case CHIP_BONAIRE:
 	case CHIP_HAWAII:
 		adev->mode_info.num_crtc = 6;
-- 
2.17.1

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[PATCH v2 09/10] drm/amdgpu: enable DC support for SI parts (v2)

[Mauro Rossi]

This commit enables DC support and Display Manager IP block
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration

(v1) pre-requisite to have Kaveri and Hawaii is revert of d9fda24804
     ("drm/amdgpu: Don't default to DC support for Kaveri and older")

(v2) fix for bc011f9350 ("drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence")
     remove CHIP_HAINAN support since it does not have physical DCE6 module
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  6 ++++++
 drivers/gpu/drm/amd/amdgpu/si.c            | 10 ++++++++++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 27de8442e808..2d17d760af64 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2290,6 +2290,12 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
 {
 	switch (asic_type) {
 #if defined(CONFIG_DRM_AMD_DC)
+#if defined(CONFIG_DRM_AMD_DC_SI)
+	case CHIP_TAHITI:
+	case CHIP_PITCAIRN:
+	case CHIP_VERDE:
+	case CHIP_OLAND:
+#endif
 	case CHIP_BONAIRE:
 	case CHIP_HAWAII:
 	case CHIP_KAVERI:
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index f8408f88cd37..700d6a914b30 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -48,6 +48,8 @@
 #include "uvd/uvd_4_0_d.h"
 #include "bif/bif_3_0_d.h"
 
+#include "amdgpu_dm.h"
+
 static const u32 tahiti_golden_registers[] =
 {
 	mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
@@ -2062,6 +2064,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
 		amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
 		if (adev->enable_virtual_display)
 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+		else if (amdgpu_device_has_dc_support(adev))
+			amdgpu_device_ip_block_add(adev, &dm_ip_block);
+#endif
 		else
 			amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block);
 		/* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */
@@ -2076,6 +2082,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
 		amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
 		if (adev->enable_virtual_display)
 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+		else if (amdgpu_device_has_dc_support(adev))
+			amdgpu_device_ip_block_add(adev, &dm_ip_block);
+#endif
 		else
 			amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block);
 
-- 
2.17.1

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[PATCH v2 10/10] drm/amd/display: enable SI support in the Kconfig (v2)

[Mauro Rossi]

CONFIG_DRM_AMD_DC_SI configuration option is added, default setting is disabled

(v2) Hainan is not supported, description updated accordingly
---
 drivers/gpu/drm/amd/display/Kconfig | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
index 13a6ce9c8e94..32cdb2da603e 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -21,6 +21,14 @@ config DRM_AMD_DC_DCN1_01
 	help
 	  RV2 family for display engine
 
+config DRM_AMD_DC_SI
+	bool "AMD DC support for Southern Islands ASICs"
+	default n
+	help
+	  Choose this option to enable new AMD DC support for SI asics
+	  by default. This includes Tahiti, Pitcairn, Cape Verde, Oland.
+	  Hainan is not supported by AMD DC and it has no physical DCE6.
+
 config DEBUG_KERNEL_DC
 	bool "Enable kgdb break in DC"
 	depends on DRM_AMD_DC
-- 
2.17.1

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