From: <sunpeng.li-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Leo Li <sunpeng.li-5C7GfCeVMHo@public.gmane.org>,
Charlene Liu <Charlene.Liu-5C7GfCeVMHo@public.gmane.org>,
Dmytro Laktyushkin
<Dmytro.Laktyushkin-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 27/49] drm/amd/display: update optc odm interface for more than 2 opps
Date: Fri, 9 Aug 2019 17:37:20 -0400 [thread overview]
Message-ID: <20190809213742.30301-28-sunpeng.li@amd.com> (raw)
In-Reply-To: <20190809213742.30301-1-sunpeng.li-5C7GfCeVMHo@public.gmane.org>
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Current optc odm interface only accepts 2 opps, we need to
expand this to allow 4 to 1 odm combine.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 3 +--
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 2 +-
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 22 +++++++++++--------
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 20 +++++++++--------
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 4 ++--
.../amd/display/dc/inc/hw/timing_generator.h | 6 ++---
6 files changed, 31 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index a546c2bc9129..b631786a4a34 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -287,7 +287,7 @@ void optc1_program_timing(
h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing);
REG_UPDATE(OTG_H_TIMING_CNTL,
- OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->comb_opp_id != 0xf);
+ OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->opp_count == 2);
}
@@ -1513,7 +1513,6 @@ void dcn10_timing_generator_init(struct optc *optc1)
optc1->min_v_blank_interlace = 5;
optc1->min_h_sync_width = 8;
optc1->min_v_sync_width = 1;
- optc1->comb_opp_id = 0xf;
}
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index 66c08d05da0e..82d91ab54ba5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -494,7 +494,7 @@ struct optc {
const struct dcn_optc_shift *tg_shift;
const struct dcn_optc_mask *tg_mask;
- int comb_opp_id;
+ int opp_count;
uint32_t max_h_total;
uint32_t max_v_total;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index c3635f5cd990..5904d4d329df 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -545,12 +545,14 @@ enum dc_status dcn20_enable_stream_timing(
/* TODO check if timing_changed, disable stream if timing changed */
- if (odm_pipe)
+ if (odm_pipe) {
+ int opp_inst[2] = { pipe_ctx->stream_res.opp->inst, odm_pipe->stream_res.opp->inst };
+
pipe_ctx->stream_res.tg->funcs->set_odm_combine(
pipe_ctx->stream_res.tg,
- odm_pipe->stream_res.opp->inst,
- pipe_ctx->stream->timing.h_addressable/2,
- pipe_ctx->stream->timing.pixel_encoding);
+ opp_inst, 2,
+ &pipe_ctx->stream->timing);
+ }
/* HW program guide assume display already disable
* by unplug sequence. OTG assume stop.
*/
@@ -822,13 +824,15 @@ static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pip
{
struct pipe_ctx *combine_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
- if (combine_pipe)
+ if (combine_pipe) {
+ int opp_inst[2] = { pipe_ctx->stream_res.opp->inst,
+ combine_pipe->stream_res.opp->inst };
+
pipe_ctx->stream_res.tg->funcs->set_odm_combine(
pipe_ctx->stream_res.tg,
- combine_pipe->stream_res.opp->inst,
- pipe_ctx->plane_res.scl_data.h_active,
- pipe_ctx->stream->timing.pixel_encoding);
- else
+ opp_inst, 2,
+ &pipe_ctx->stream->timing);
+ } else
pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 6dede495d0fd..aedf9de1c947 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -224,7 +224,6 @@ void optc2_set_odm_bypass(struct timing_generator *optc,
struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t h_div_2 = 0;
- optc1->comb_opp_id = 0xf;
REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
OPTC_NUM_OF_INPUT_SEGMENT, 0,
OPTC_SEG0_SRC_SEL, optc->inst,
@@ -236,13 +235,16 @@ void optc2_set_odm_bypass(struct timing_generator *optc,
OTG_H_TIMING_DIV_BY2, h_div_2);
REG_SET(OPTC_MEMORY_CONFIG, 0,
OPTC_MEM_SEL, 0);
+ optc1->opp_count = 1;
}
-void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id,
- int mpcc_hactive, enum dc_pixel_encoding pixel_encoding)
+void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
+ struct dc_crtc_timing *timing)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
/* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192 */
+ int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
+ / opp_cnt;
int memory_mask = mpcc_hactive <= 2560 ? 0x3 : 0xf;
uint32_t data_fmt = 0;
@@ -257,23 +259,24 @@ void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id,
REG_SET(OPTC_MEMORY_CONFIG, 0,
OPTC_MEM_SEL, memory_mask << (optc->inst * 4));
- if (pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
data_fmt = 1;
- else if (pixel_encoding == PIXEL_ENCODING_YCBCR420)
+ else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
data_fmt = 2;
REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
+ ASSERT(opp_cnt == 2);
REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
OPTC_NUM_OF_INPUT_SEGMENT, 1,
- OPTC_SEG0_SRC_SEL, optc->inst,
- OPTC_SEG1_SRC_SEL, combine_opp_id);
+ OPTC_SEG0_SRC_SEL, opp_id[0],
+ OPTC_SEG1_SRC_SEL, opp_id[1]);
REG_UPDATE(OPTC_WIDTH_CONTROL,
OPTC_SEGMENT_WIDTH, mpcc_hactive);
REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
- optc1->comb_opp_id = combine_opp_id;
+ optc1->opp_count = opp_cnt;
}
void optc2_get_optc_source(struct timing_generator *optc,
@@ -538,6 +541,5 @@ void dcn20_timing_generator_init(struct optc *optc1)
optc1->min_v_blank_interlace = 5;
optc1->min_h_sync_width = 4;// Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
optc1->min_v_sync_width = 1;
- optc1->comb_opp_id = 0xf;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
index ebf07c582da2..47cb4de1564c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
@@ -96,8 +96,8 @@ void optc2_set_dsc_config(struct timing_generator *optc,
void optc2_set_odm_bypass(struct timing_generator *optc,
const struct dc_crtc_timing *dc_crtc_timing);
-void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id,
- int mpcc_hactive, enum dc_pixel_encoding pixel_encoding);
+void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
+ struct dc_crtc_timing *timing);
void optc2_get_optc_source(struct timing_generator *optc,
uint32_t *num_of_src_opp,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 5e93bc0e8ff9..1f83cb7c7dd4 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -267,9 +267,9 @@ struct timing_generator_funcs {
uint32_t dsc_bytes_per_pixel,
uint32_t dsc_slice_width);
#endif
- void (*set_odm_bypass)(struct timing_generator *tg, const struct dc_crtc_timing *dc_crtc_timing);
- void (*set_odm_combine)(struct timing_generator *tg, int combine_opp_id,
- int mpcc_hactive, enum dc_pixel_encoding pixel_encoding);
+ void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
+ void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
+ struct dc_crtc_timing *timing);
void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
void (*set_gsl_source_select)(struct timing_generator *optc,
int group_idx,
--
2.22.0
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next prev parent reply other threads:[~2019-08-09 21:37 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-09 21:36 [PATCH 00/49] DC Patches 09 Aug, 2019 sunpeng.li-5C7GfCeVMHo
[not found] ` <20190809213742.30301-1-sunpeng.li-5C7GfCeVMHo@public.gmane.org>
2019-08-09 21:36 ` [PATCH 01/49] drm/amd/display: Add PIXEL_RATE control regs for more instances sunpeng.li-5C7GfCeVMHo
2019-08-09 21:36 ` [PATCH 02/49] drm/amd/display: Add DFS reference clock field sunpeng.li-5C7GfCeVMHo
2019-08-09 21:36 ` [PATCH 03/49] drm/amd/display: reset drr programming on pipe reset sunpeng.li-5C7GfCeVMHo
2019-08-09 21:36 ` [PATCH 04/49] drm/amd/display: reset hdmi tmds rate and data scramble " sunpeng.li-5C7GfCeVMHo
2019-08-09 21:36 ` [PATCH 05/49] drm/amd/display: fix issue where 252-255 values are clipped sunpeng.li-5C7GfCeVMHo
2019-08-09 21:36 ` [PATCH 06/49] drm/amd/display: Fix frames_to_insert math sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 07/49] drm/amd/display: Add 22, 24, and 26 degamma sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 08/49] drm/amd/display: Improve sharing of HUBBUB register lists sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 09/49] drm/amd/display: Synchronous DisplayPort Link Training sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 10/49] drm/amd/display: make firmware info only load once during dc_bios create sunpeng.li-5C7GfCeVMHo
[not found] ` <20190809213742.30301-11-sunpeng.li-5C7GfCeVMHo@public.gmane.org>
2019-08-20 13:59 ` Mike Lothian
2019-08-09 21:37 ` [PATCH 11/49] drm/amd/display: fixup DPP programming sequence sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 12/49] drm/amd/display: Add work-around option to skip DCN20 clock updates sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 13/49] drm/amd/display: refactor gpio to allocate hw_container in constructor sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 14/49] drm/amd/display: wait for pending complete when enabling a plane sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 15/49] drm/amd/display: 3.2.43 sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 16/49] drm/amd/display: Make init_hw and init_pipes generic for seamless boot sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 17/49] drm/amd/display: fix dcn-specific clk_mgr init_clocks sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 18/49] drm/amd/display: enabling seamless boot sequence for dcn2 sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 19/49] drm/amd/display: clean up DML for DCN2x sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 20/49] drm/amd/display: Add HLG support in color module sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 21/49] drm/amd/display: Change DSC policy from slices per column to minimum slice height sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 22/49] drm/amd/display: Set DSC before DIG front-end is connected to its back-end sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 23/49] drm/amd/display: 3.2.44 sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 24/49] drm/amd/display: fix pipe selection logic in validate sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 25/49] drm/amd/display: Remove duplicate interface for programming FB sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 26/49] drm/amd/display: Update DML parameters sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` sunpeng.li-5C7GfCeVMHo [this message]
2019-08-09 21:37 ` [PATCH 28/49] drm/amd/display: HUBP/HUBBUB register programming fixes sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 29/49] drm/amd/display: Enable type C hotplug sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 30/49] drm/amd/display: reprogram VM config when system resume sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 31/49] drm/amd/display: Remove 4:2:2 DSC support sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 32/49] drm/amd/display: Add Logging for Gamma Related information (1/2) sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 33/49] drm/amd/display: Fix type of ODMCombineType field sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 34/49] drm/amd/display: Check if set_blank_data_double_buffer exists before call sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 35/49] drm/amd/display: Correct DSC PPS log sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 36/49] drm/amd/display: wake up ogam mem pwr before programming ocsc sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 37/49] drm/amd/display: Register VUPDATE_NO_LOCK interrupts for DCN2 sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 38/49] drm/amd/display: Add enum for H-timing divider mode sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 39/49] drm/amd/display: Remove redundant definition of dwb_source enums sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 40/49] drm/amd/display: Add Logging for Gamma Related information (2/2) sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 41/49] drm/amd/display: Add and refine DSC logs in enable sequence sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 42/49] drm/amd/display: 3.2.45 sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 43/49] drm/amd/display: fix dcn20 global sync dml param extraction sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 44/49] drm/amd/display: 3.2.46 sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 45/49] drm/amd/display: enable dcn_mem_pwr as golden setting updates sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 46/49] drm/amd/display: check hpd before retry verify link cap sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 47/49] drm/amd/display: audio cannot switch to internal when display turns off sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 48/49] drm/amd/display: Enable MPO with pre-blend color processing (RGB) sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 49/49] drm/amd/display: Load NV12 SOC BB from firmware sunpeng.li-5C7GfCeVMHo
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