From: <sunpeng.li-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Leo Li <sunpeng.li-5C7GfCeVMHo@public.gmane.org>,
David Francis <David.Francis-5C7GfCeVMHo@public.gmane.org>,
Nicholas Kazlauskas
<nicholas.kazlauskas-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 37/49] drm/amd/display: Register VUPDATE_NO_LOCK interrupts for DCN2
Date: Fri, 9 Aug 2019 17:37:30 -0400 [thread overview]
Message-ID: <20190809213742.30301-38-sunpeng.li@amd.com> (raw)
In-Reply-To: <20190809213742.30301-1-sunpeng.li-5C7GfCeVMHo@public.gmane.org>
From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
[Why]
These are needed to send back DRM vblank events in the case where VRR
is on. Without the interrupt enabled we're deferring the events into the
vblank queue and userspace is left waiting forever to get back the
events they need.
Found using igt@kms_vrr - the test fails immediately due to vblank
timeout.
[How]
Register them the same way we're handling it for DCN1.
This fixes igt@kms_vrr for DCN2.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <David.Francis@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
.../display/dc/irq/dcn20/irq_service_dcn20.c | 28 ++++++++++++-------
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
index 65866d620759..1fdbc9e5f7bc 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
@@ -165,6 +165,11 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
.ack = NULL
};
+static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
#undef BASE_INNER
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
@@ -219,12 +224,15 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
.funcs = &pflip_irq_info_funcs\
}
-#define vupdate_int_entry(reg_num)\
+/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
+ * of DCE's DC_IRQ_SOURCE_VUPDATEx.
+ */
+#define vupdate_no_lock_int_entry(reg_num)\
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
IRQ_REG_ENTRY(OTG, reg_num,\
- OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
- OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
- .funcs = &vblank_irq_info_funcs\
+ OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
+ OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
+ .funcs = &vupdate_no_lock_irq_info_funcs\
}
#define vblank_int_entry(reg_num)\
@@ -331,12 +339,12 @@ irq_source_info_dcn20[DAL_IRQ_SOURCES_NUMBER] = {
dc_underflow_int_entry(6),
[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
- vupdate_int_entry(0),
- vupdate_int_entry(1),
- vupdate_int_entry(2),
- vupdate_int_entry(3),
- vupdate_int_entry(4),
- vupdate_int_entry(5),
+ vupdate_no_lock_int_entry(0),
+ vupdate_no_lock_int_entry(1),
+ vupdate_no_lock_int_entry(2),
+ vupdate_no_lock_int_entry(3),
+ vupdate_no_lock_int_entry(4),
+ vupdate_no_lock_int_entry(5),
vblank_int_entry(0),
vblank_int_entry(1),
vblank_int_entry(2),
--
2.22.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
next prev parent reply other threads:[~2019-08-09 21:37 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-09 21:36 [PATCH 00/49] DC Patches 09 Aug, 2019 sunpeng.li-5C7GfCeVMHo
[not found] ` <20190809213742.30301-1-sunpeng.li-5C7GfCeVMHo@public.gmane.org>
2019-08-09 21:36 ` [PATCH 01/49] drm/amd/display: Add PIXEL_RATE control regs for more instances sunpeng.li-5C7GfCeVMHo
2019-08-09 21:36 ` [PATCH 02/49] drm/amd/display: Add DFS reference clock field sunpeng.li-5C7GfCeVMHo
2019-08-09 21:36 ` [PATCH 03/49] drm/amd/display: reset drr programming on pipe reset sunpeng.li-5C7GfCeVMHo
2019-08-09 21:36 ` [PATCH 04/49] drm/amd/display: reset hdmi tmds rate and data scramble " sunpeng.li-5C7GfCeVMHo
2019-08-09 21:36 ` [PATCH 05/49] drm/amd/display: fix issue where 252-255 values are clipped sunpeng.li-5C7GfCeVMHo
2019-08-09 21:36 ` [PATCH 06/49] drm/amd/display: Fix frames_to_insert math sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 07/49] drm/amd/display: Add 22, 24, and 26 degamma sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 08/49] drm/amd/display: Improve sharing of HUBBUB register lists sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 09/49] drm/amd/display: Synchronous DisplayPort Link Training sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 10/49] drm/amd/display: make firmware info only load once during dc_bios create sunpeng.li-5C7GfCeVMHo
[not found] ` <20190809213742.30301-11-sunpeng.li-5C7GfCeVMHo@public.gmane.org>
2019-08-20 13:59 ` Mike Lothian
2019-08-09 21:37 ` [PATCH 11/49] drm/amd/display: fixup DPP programming sequence sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 12/49] drm/amd/display: Add work-around option to skip DCN20 clock updates sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 13/49] drm/amd/display: refactor gpio to allocate hw_container in constructor sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 14/49] drm/amd/display: wait for pending complete when enabling a plane sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 15/49] drm/amd/display: 3.2.43 sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 16/49] drm/amd/display: Make init_hw and init_pipes generic for seamless boot sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 17/49] drm/amd/display: fix dcn-specific clk_mgr init_clocks sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 18/49] drm/amd/display: enabling seamless boot sequence for dcn2 sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 19/49] drm/amd/display: clean up DML for DCN2x sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 20/49] drm/amd/display: Add HLG support in color module sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 21/49] drm/amd/display: Change DSC policy from slices per column to minimum slice height sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 22/49] drm/amd/display: Set DSC before DIG front-end is connected to its back-end sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 23/49] drm/amd/display: 3.2.44 sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 24/49] drm/amd/display: fix pipe selection logic in validate sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 25/49] drm/amd/display: Remove duplicate interface for programming FB sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 26/49] drm/amd/display: Update DML parameters sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 27/49] drm/amd/display: update optc odm interface for more than 2 opps sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 28/49] drm/amd/display: HUBP/HUBBUB register programming fixes sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 29/49] drm/amd/display: Enable type C hotplug sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 30/49] drm/amd/display: reprogram VM config when system resume sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 31/49] drm/amd/display: Remove 4:2:2 DSC support sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 32/49] drm/amd/display: Add Logging for Gamma Related information (1/2) sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 33/49] drm/amd/display: Fix type of ODMCombineType field sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 34/49] drm/amd/display: Check if set_blank_data_double_buffer exists before call sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 35/49] drm/amd/display: Correct DSC PPS log sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 36/49] drm/amd/display: wake up ogam mem pwr before programming ocsc sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` sunpeng.li-5C7GfCeVMHo [this message]
2019-08-09 21:37 ` [PATCH 38/49] drm/amd/display: Add enum for H-timing divider mode sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 39/49] drm/amd/display: Remove redundant definition of dwb_source enums sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 40/49] drm/amd/display: Add Logging for Gamma Related information (2/2) sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 41/49] drm/amd/display: Add and refine DSC logs in enable sequence sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 42/49] drm/amd/display: 3.2.45 sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 43/49] drm/amd/display: fix dcn20 global sync dml param extraction sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 44/49] drm/amd/display: 3.2.46 sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 45/49] drm/amd/display: enable dcn_mem_pwr as golden setting updates sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 46/49] drm/amd/display: check hpd before retry verify link cap sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 47/49] drm/amd/display: audio cannot switch to internal when display turns off sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 48/49] drm/amd/display: Enable MPO with pre-blend color processing (RGB) sunpeng.li-5C7GfCeVMHo
2019-08-09 21:37 ` [PATCH 49/49] drm/amd/display: Load NV12 SOC BB from firmware sunpeng.li-5C7GfCeVMHo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190809213742.30301-38-sunpeng.li@amd.com \
--to=sunpeng.li-5c7gfcevmho@public.gmane.org \
--cc=David.Francis-5C7GfCeVMHo@public.gmane.org \
--cc=amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org \
--cc=nicholas.kazlauskas-5C7GfCeVMHo@public.gmane.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox