AMD-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Anthony Koo <Anthony.Koo@amd.com>,
	Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com, Aurabindo.Pillai@amd.com,
	Bhawanpreet.Lakha@amd.com, Camille Cho <Camille.Cho@amd.com>,
	bindu.r@amd.com
Subject: [PATCH 17/18] drm/amd/display: To update backlight restore mechanism
Date: Fri, 20 Nov 2020 15:19:57 -0500	[thread overview]
Message-ID: <20201120201958.2455002-18-Rodrigo.Siqueira@amd.com> (raw)
In-Reply-To: <20201120201958.2455002-1-Rodrigo.Siqueira@amd.com>

From: Camille Cho <Camille.Cho@amd.com>

[Why]
Cached backlight is never being updated since panel_cntl specific
registers were moved from abm to panel_cntl.

[How]
Update cached backlight in set_abm_immediate_disable as what we used to
do. Also, update the priority of backlight restore mechanism so that
cached backlight has the highest priority since it is always correct.

Signed-off-by: Camille Cho <Camille.Cho@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../drm/amd/display/dc/dce/dce_panel_cntl.c   | 36 +++++++++----------
 .../drm/amd/display/dc/dcn21/dcn21_hwseq.c    |  4 ++-
 2 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
index 74f7619d4154..761fdfc1f5bd 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
@@ -108,25 +108,17 @@ static uint32_t dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
 	 */
 	REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
 
-	if (value == 0 || value == 1) {
-		if (panel_cntl->stored_backlight_registers.BL_PWM_CNTL != 0) {
-			REG_WRITE(BL_PWM_CNTL,
-					panel_cntl->stored_backlight_registers.BL_PWM_CNTL);
-			REG_WRITE(BL_PWM_CNTL2,
-					panel_cntl->stored_backlight_registers.BL_PWM_CNTL2);
-			REG_WRITE(BL_PWM_PERIOD_CNTL,
-					panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
-			REG_UPDATE(PWRSEQ_REF_DIV,
-				BL_PWM_REF_DIV,
-				panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
-		} else {
-			/* TODO: Note: This should not really happen since VBIOS
-			 * should have initialized PWM registers on boot.
-			 */
-			REG_WRITE(BL_PWM_CNTL, 0xC000FA00);
-			REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
-		}
-	} else {
+	if (panel_cntl->stored_backlight_registers.BL_PWM_CNTL != 0) {
+		REG_WRITE(BL_PWM_CNTL,
+				panel_cntl->stored_backlight_registers.BL_PWM_CNTL);
+		REG_WRITE(BL_PWM_CNTL2,
+				panel_cntl->stored_backlight_registers.BL_PWM_CNTL2);
+		REG_WRITE(BL_PWM_PERIOD_CNTL,
+				panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
+		REG_UPDATE(PWRSEQ_REF_DIV,
+			BL_PWM_REF_DIV,
+			panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
+	} else if ((value != 0) && (value != 1)) {
 		panel_cntl->stored_backlight_registers.BL_PWM_CNTL =
 				REG_READ(BL_PWM_CNTL);
 		panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 =
@@ -136,6 +128,12 @@ static uint32_t dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
 
 		REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
 				&panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
+	} else {
+		/* TODO: Note: This should not really happen since VBIOS
+		 * should have initialized PWM registers on boot.
+		 */
+		REG_WRITE(BL_PWM_CNTL, 0x8000FA00);
+		REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
 	}
 
 	// Have driver take backlight control
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
index 1fa193078803..96ee0b82f458 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
@@ -171,9 +171,11 @@ void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
 		return;
 	}
 
-	if (abm && panel_cntl)
+	if (abm && panel_cntl) {
 		dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_IMMEDIATELY_DISABLE,
 				panel_cntl->inst);
+		panel_cntl->funcs->store_backlight_level(panel_cntl);
+	}
 }
 
 void dcn21_set_pipe(struct pipe_ctx *pipe_ctx)
-- 
2.29.2

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

  parent reply	other threads:[~2020-11-20 20:20 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-20 20:19 [PATCH 00/18] DC 3.2.113 Patches, November 20, 2020 Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 01/18] drm/amd/display: add i2c speed arbitration for dc_i2c and hdcp_i2c Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 02/18] drm/amd/display: Source minimum HBlank support Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 03/18] drm/amd/display: Update panel register Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 04/18] drm/amd/display: Enable stutter for dcn3.01 Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 05/18] drm/amd/display: Add DMCU memory low power support Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 06/18] drm/amd/display: intermittent underflow observed when PIP is toggled in Full screen Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 07/18] drm/amd/display: expose clk_mgr functions for reuse Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 08/18] drm/amd/display: change hw sequence Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 09/18] drm/amd/display: Clear sticky vsc sdp error bit Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 10/18] drm/amd/display: Add BLNDGAM memory shutdown support Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 11/18] drm/amd/display: Add internal display info Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 12/18] drm/amd/display: Check multiple internal displays for power optimization Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 13/18] drm/amd/display: remove macro which is in header already Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 14/18] drm/amd/display: Add GAMCOR memory shutdown support Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 15/18] drm/amd/display: enable pipe power gating by default Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 16/18] drm/amd/display: 3.2.113 Rodrigo Siqueira
2020-11-20 20:19 ` Rodrigo Siqueira [this message]
2020-11-20 20:19 ` [PATCH 18/18] drm/amd/display: init soc bounding box for dcn3.01 Rodrigo Siqueira

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201120201958.2455002-18-Rodrigo.Siqueira@amd.com \
    --to=rodrigo.siqueira@amd.com \
    --cc=Anthony.Koo@amd.com \
    --cc=Aurabindo.Pillai@amd.com \
    --cc=Bhawanpreet.Lakha@amd.com \
    --cc=Camille.Cho@amd.com \
    --cc=Eryk.Brol@amd.com \
    --cc=Harry.Wentland@amd.com \
    --cc=Sunpeng.Li@amd.com \
    --cc=amd-gfx@lists.freedesktop.org \
    --cc=bindu.r@amd.com \
    --cc=qingqing.zhuo@amd.com \
    --cc=roman.li@amd.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox