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From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Eric Yang <eric.yang2@amd.com>,
	Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com, Aurabindo.Pillai@amd.com,
	Jacky Liao <ziyu.liao@amd.com>,
	Bhawanpreet.Lakha@amd.com, bindu.r@amd.com
Subject: [PATCH 05/18] drm/amd/display: Add DMCU memory low power support
Date: Fri, 20 Nov 2020 15:19:45 -0500	[thread overview]
Message-ID: <20201120201958.2455002-6-Rodrigo.Siqueira@amd.com> (raw)
In-Reply-To: <20201120201958.2455002-1-Rodrigo.Siqueira@amd.com>

From: Jacky Liao <ziyu.liao@amd.com>

[Why]
On some platforms, DMCU is no longer used. In these cases, some DMCU
memory should be completely powered off to save power.

[How]
1. Set DMCU_ERAM_MEM_PWR_FORCE to shutdown memory when DMCU is not in
   use
2. Added a debug option to allow this behaviour to be turned off
3. Set all memory low power debug options to off first, to not
   immediately cause problems

Signed-off-by: Jacky Liao <ziyu.liao@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h                | 2 ++
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h     | 7 +++++--
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 7 +++++++
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 443b1f1ad546..b170e653febc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -420,6 +420,8 @@ struct dc_bw_validation_profile {
 union mem_low_power_enable_options {
 	struct {
 		bool i2c: 1;
+		bool dmcu: 1;
+		bool cm: 1;
 		bool mpc: 1;
 		bool optc: 1;
 	} bits;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index ad0ae1f7b513..fe31abfa6c85 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -597,6 +597,7 @@ struct dce_hwseq_registers {
 	uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
 	uint32_t HPO_TOP_CLOCK_CONTROL;
 	uint32_t ODM_MEM_PWR_CTRL3;
+	uint32_t DMU_MEM_PWR_CNTL;
 };
  /* set field name */
 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\
@@ -836,7 +837,8 @@ struct dce_hwseq_registers {
 	HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \
 	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
-	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh)
+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
+	HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh)
 
 #define HWSEQ_DCN301_MASK_SH_LIST(mask_sh)\
 	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
@@ -1046,7 +1048,8 @@ struct dce_hwseq_registers {
 	type D4VGA_MODE_ENABLE; \
 	type AZALIA_AUDIO_DTO_MODULE; \
 	type ODM_MEM_UNASSIGNED_PWR_MODE; \
-	type ODM_MEM_VBLANK_PWR_MODE;
+	type ODM_MEM_VBLANK_PWR_MODE; \
+	type DMCU_ERAM_MEM_PWR_FORCE;
 
 #define HWSEQ_DCN3_REG_FIELD_LIST(type) \
 	type HPO_HDMISTREAMCLK_GATE_DIS;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index e76d6ab8d93a..7a7efe9ea961 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -462,6 +462,13 @@ void dcn30_init_hw(struct dc *dc)
 		hws->funcs.disable_vga(dc->hwseq);
 	}
 
+	if (dc->debug.enable_mem_low_power.bits.dmcu) {
+		// Force ERAM to shutdown if DMCU is not enabled
+		if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
+			REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
+		}
+	}
+
 	// Set default OPTC memory power states
 	if (dc->debug.enable_mem_low_power.bits.optc) {
 		// Shutdown when unassigned and light sleep in VBLANK
-- 
2.29.2

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  parent reply	other threads:[~2020-11-20 20:20 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-20 20:19 [PATCH 00/18] DC 3.2.113 Patches, November 20, 2020 Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 01/18] drm/amd/display: add i2c speed arbitration for dc_i2c and hdcp_i2c Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 02/18] drm/amd/display: Source minimum HBlank support Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 03/18] drm/amd/display: Update panel register Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 04/18] drm/amd/display: Enable stutter for dcn3.01 Rodrigo Siqueira
2020-11-20 20:19 ` Rodrigo Siqueira [this message]
2020-11-20 20:19 ` [PATCH 06/18] drm/amd/display: intermittent underflow observed when PIP is toggled in Full screen Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 07/18] drm/amd/display: expose clk_mgr functions for reuse Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 08/18] drm/amd/display: change hw sequence Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 09/18] drm/amd/display: Clear sticky vsc sdp error bit Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 10/18] drm/amd/display: Add BLNDGAM memory shutdown support Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 11/18] drm/amd/display: Add internal display info Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 12/18] drm/amd/display: Check multiple internal displays for power optimization Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 13/18] drm/amd/display: remove macro which is in header already Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 14/18] drm/amd/display: Add GAMCOR memory shutdown support Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 15/18] drm/amd/display: enable pipe power gating by default Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 16/18] drm/amd/display: 3.2.113 Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 17/18] drm/amd/display: To update backlight restore mechanism Rodrigo Siqueira
2020-11-20 20:19 ` [PATCH 18/18] drm/amd/display: init soc bounding box for dcn3.01 Rodrigo Siqueira

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