* [PATCH 01/14] drm/amd/display: Prevent using DMUB rptr that is out-of-bounds
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
@ 2021-10-01 14:36 ` Solomon Chiu
2021-10-01 14:36 ` [PATCH 02/14] drm/amd/display: update irq_service and other required change part 2 Solomon Chiu
` (13 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Solomon Chiu @ 2021-10-01 14:36 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Wyatt Wood,
Nicholas Kazlauskas
From: Wyatt Wood <wyatt.wood@amd.com>
[Why]
Running into bugchecks during stress test where rptr is 0xFFFFFFFF.
Typically this is caused by a hard hang, and can come from HW outside
of DCN.
[How]
To prevent bugchecks when writing the DMUB rptr, fist check that the
rptr is valid.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 +
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 10 ++++++++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index ef324fc39315..efb667cf6c98 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -84,6 +84,7 @@ enum dmub_status {
DMUB_STATUS_QUEUE_FULL,
DMUB_STATUS_TIMEOUT,
DMUB_STATUS_INVALID,
+ DMUB_STATUS_HW_FAILURE,
};
/* enum dmub_asic - dmub asic identifier */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index a6188d067d65..77c67222cabd 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -655,13 +655,19 @@ enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
uint32_t timeout_us)
{
- uint32_t i;
+ uint32_t i, rptr;
if (!dmub->hw_init)
return DMUB_STATUS_INVALID;
for (i = 0; i <= timeout_us; ++i) {
- dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
+ rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
+
+ if (rptr > dmub->inbox1_rb.capacity)
+ return DMUB_STATUS_HW_FAILURE;
+
+ dmub->inbox1_rb.rptr = rptr;
+
if (dmub_rb_empty(&dmub->inbox1_rb))
return DMUB_STATUS_OK;
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 02/14] drm/amd/display: update irq_service and other required change part 2.
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
2021-10-01 14:36 ` [PATCH 01/14] drm/amd/display: Prevent using DMUB rptr that is out-of-bounds Solomon Chiu
@ 2021-10-01 14:36 ` Solomon Chiu
2021-10-01 14:36 ` [PATCH 03/14] drm/amd/display: Skip override for preferred link settings during link training Solomon Chiu
` (12 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Solomon Chiu @ 2021-10-01 14:36 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Charlene Liu,
sungjoon.kim
From: Charlene Liu <Charlene.Liu@amd.com>
[why]
fix NULL pointer in irq_service_dcn201
[how]
initialize proper num of irq source for linu
Reviewed-by: Sung joon Kim <USER DID NOT SET AN EMAIL>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 9 +++++----
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 17 ++++++++++-------
4 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 8cc9626fc111..c5a091d0bbfc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -899,6 +899,7 @@ union surface_update_flags {
uint32_t bandwidth_change:1;
uint32_t clock_change:1;
uint32_t stereo_format_change:1;
+ uint32_t lut_3d:1;
uint32_t full_update:1;
} bits;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 296b2f80a1ec..307369b52b42 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -663,14 +663,15 @@ struct dce_hwseq_registers {
uint32_t MC_VM_XGMI_LFB_CNTL;
uint32_t AZALIA_AUDIO_DTO;
uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
+ /* MMHUB VM */
+ uint32_t MC_VM_FB_LOCATION_BASE;
+ uint32_t MC_VM_FB_LOCATION_TOP;
+ uint32_t MC_VM_FB_OFFSET;
+ uint32_t MMHUBBUB_MEM_PWR_CNTL;
uint32_t HPO_TOP_CLOCK_CONTROL;
uint32_t ODM_MEM_PWR_CTRL3;
uint32_t DMU_MEM_PWR_CNTL;
- uint32_t MMHUBBUB_MEM_PWR_CNTL;
uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
- uint32_t MC_VM_FB_LOCATION_BASE;
- uint32_t MC_VM_FB_LOCATION_TOP;
- uint32_t MC_VM_FB_OFFSET;
};
/* set field name */
#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
index bf1ffc3629c7..3d9be87aae45 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
@@ -111,6 +111,7 @@ enum dce110_opp_reg_type {
OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
+ OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index fb0dec4ed3a6..0f273ac0c83f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -256,16 +256,19 @@ struct abm *dmub_abm_create(
const struct dce_abm_shift *abm_shift,
const struct dce_abm_mask *abm_mask)
{
- struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
+ if (!ctx->dc->config.disable_dmcu) {
+ struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
- if (abm_dce == NULL) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
+ if (abm_dce == NULL) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
- dmub_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask);
+ dmub_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask);
- return &abm_dce->base;
+ return &abm_dce->base;
+ }
+ return NULL;
}
void dmub_abm_destroy(struct abm **abm)
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 03/14] drm/amd/display: Skip override for preferred link settings during link training
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
2021-10-01 14:36 ` [PATCH 01/14] drm/amd/display: Prevent using DMUB rptr that is out-of-bounds Solomon Chiu
2021-10-01 14:36 ` [PATCH 02/14] drm/amd/display: update irq_service and other required change part 2 Solomon Chiu
@ 2021-10-01 14:36 ` Solomon Chiu
2021-10-01 14:36 ` [PATCH 04/14] drm/amd/display: Re-arrange FPU code structure for dcn2x Solomon Chiu
` (11 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Solomon Chiu @ 2021-10-01 14:36 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, George Shen,
Wenjing Liu
From: George Shen <george.shen@amd.com>
[Why]
Overriding link setting inside override_training_settings
result in fallback link settings being ignored. This can
potentially cause link training to always fail and consequently
result in an infinite loop of link training to occur in
dp_verify_link_cap during detection.
[How]
Since preferred link settings are already considered inside
decide_link_settings, skip the check in override_training_settings
to avoid infinite link training loops.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 029cc78bc9e9..649a9da338a7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1645,12 +1645,6 @@ static void override_training_settings(
{
uint32_t lane;
- /* Override link settings */
- if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
- lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
- if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
- lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
-
/* Override link spread */
if (!link->dp_ss_off && overrides->downspread != NULL)
lt_settings->link_settings.link_spread = *overrides->downspread ?
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 04/14] drm/amd/display: Re-arrange FPU code structure for dcn2x
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
` (2 preceding siblings ...)
2021-10-01 14:36 ` [PATCH 03/14] drm/amd/display: Skip override for preferred link settings during link training Solomon Chiu
@ 2021-10-01 14:36 ` Solomon Chiu
2021-10-01 14:36 ` [PATCH 05/14] drm/amd/display: Fix 3DLUT skipped programming Solomon Chiu
` (10 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Solomon Chiu @ 2021-10-01 14:36 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu
From: Qingqing Zhuo <qingqing.zhuo@amd.com>
[Why]
Current FPU code for DCN2x is located under dml/dcn2x.
This is not aligned with DC's general source tree
structure.
[How]
Move FPU code for DCN2x to dml/dcn20.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dml/Makefile | 4 ++--
.../amd/display/dc/dml/{dcn2x/dcn2x.c => dcn20/dcn20_fpu.c} | 2 +-
.../amd/display/dc/dml/{dcn2x/dcn2x.h => dcn20/dcn20_fpu.h} | 6 +++---
7 files changed, 10 insertions(+), 10 deletions(-)
rename drivers/gpu/drm/amd/display/dc/dml/{dcn2x/dcn2x.c => dcn20/dcn20_fpu.c} (99%)
rename drivers/gpu/drm/amd/display/dc/dml/{dcn2x/dcn2x.h => dcn20/dcn20_fpu.h} (94%)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
index b1bf80da3a55..ab0c6d191038 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
@@ -52,7 +52,7 @@ static DEFINE_PER_CPU(int, fpu_recursion_depth);
* This function tells if the code is already under FPU protection or not. A
* function that works as an API for a set of FPU operations can use this
* function for checking if the caller invoked it after DC_FP_START(). For
- * example, take a look at dcn2x.c file.
+ * example, take a look at dcn20_fpu.c file.
*/
inline void dc_assert_fp_enabled(void)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 899d0086ffbe..756f5d411d9a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -35,7 +35,7 @@
#include "include/irq_service_interface.h"
#include "dcn20/dcn20_resource.h"
-#include "dml/dcn2x/dcn2x.h"
+#include "dml/dcn20/dcn20_fpu.h"
#include "dcn10/dcn10_hubp.h"
#include "dcn10/dcn10_ipp.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
index aec276e1db65..5881dc49f7c5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
@@ -27,7 +27,7 @@
#include "dc.h"
#include "dcn201_init.h"
-#include "dml/dcn2x/dcn2x.h"
+#include "dml/dcn20/dcn20_fpu.h"
#include "resource.h"
#include "include/irq_service_interface.h"
#include "dcn201_resource.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index fbbdf9976183..d452a0d1777e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -35,7 +35,7 @@
#include "include/irq_service_interface.h"
#include "dcn20/dcn20_resource.h"
-#include "dml/dcn2x/dcn2x.h"
+#include "dml/dcn20/dcn20_fpu.h"
#include "clk_mgr.h"
#include "dcn10/dcn10_hubp.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index 56055df2e8d2..169a4e68f86e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -58,7 +58,7 @@ CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
ifdef CONFIG_DRM_AMD_DC_DCN
CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
-CFLAGS_$(AMDDALPATH)/dc/dml/dcn2x/dcn2x.o := $(dml_ccflags)
+CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
@@ -93,8 +93,8 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_rq_dlg_helpers.o := $(dml_rcflags)
DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
ifdef CONFIG_DRM_AMD_DC_DCN
+DML += dcn20/dcn20_fpu.o
DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_20.o
-DML += dcn2x/dcn2x.o
DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o
DML += dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn2x/dcn2x.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
similarity index 99%
rename from drivers/gpu/drm/amd/display/dc/dml/dcn2x/dcn2x.c
rename to drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index c58522436291..d590dc917363 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn2x/dcn2x.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -26,7 +26,7 @@
#include "resource.h"
-#include "dcn2x.h"
+#include "dcn20_fpu.h"
/**
* DOC: DCN2x FPU manipulation Overview
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn2x/dcn2x.h b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
similarity index 94%
rename from drivers/gpu/drm/amd/display/dc/dml/dcn2x/dcn2x.h
rename to drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
index 331547ba0713..36f26126d574 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn2x/dcn2x.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
@@ -24,11 +24,11 @@
*
*/
-#ifndef __DCN2X_H__
-#define __DCN2X_H__
+#ifndef __DCN20_FPU_H__
+#define __DCN20_FPU_H__
void dcn20_populate_dml_writeback_from_context(struct dc *dc,
struct resource_context *res_ctx,
display_e2e_pipe_params_st *pipes);
-#endif /* __DCN2X_H__ */
+#endif /* __DCN20_FPU_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 05/14] drm/amd/display: Fix 3DLUT skipped programming
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
` (3 preceding siblings ...)
2021-10-01 14:36 ` [PATCH 04/14] drm/amd/display: Re-arrange FPU code structure for dcn2x Solomon Chiu
@ 2021-10-01 14:36 ` Solomon Chiu
2021-10-01 14:36 ` [PATCH 06/14] drm/amd/display: dcn3 failed due to dmcbu_abm not created Solomon Chiu
` (9 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Solomon Chiu @ 2021-10-01 14:36 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Aric Cyr,
Anthony Koo
From: Aric Cyr <aric.cyr@amd.com>
[Why]
3DLUT not updated due to missing condition
[How]
Check if 3DLUT update is needed
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0f0440408a16..8e0bcd4fd000 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2187,6 +2187,9 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
update_flags->bits.gamma_change = 1;
}
+ if (u->lut3d_func || u->func_shaper)
+ update_flags->bits.lut_3d = 1;
+
if (u->hdr_mult.value)
if (u->hdr_mult.value != u->surface->hdr_mult.value) {
update_flags->bits.hdr_mult = 1;
@@ -2200,6 +2203,7 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
if (update_flags->bits.input_csc_change
|| update_flags->bits.coeff_reduction_change
+ || update_flags->bits.lut_3d
|| update_flags->bits.gamma_change
|| update_flags->bits.gamut_remap_change) {
type = UPDATE_TYPE_FULL;
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 06/14] drm/amd/display: dcn3 failed due to dmcbu_abm not created
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
` (4 preceding siblings ...)
2021-10-01 14:36 ` [PATCH 05/14] drm/amd/display: Fix 3DLUT skipped programming Solomon Chiu
@ 2021-10-01 14:36 ` Solomon Chiu
2021-10-01 14:36 ` [PATCH 07/14] drm/amd/display: Added root clock optimization flags Solomon Chiu
` (8 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Solomon Chiu @ 2021-10-01 14:36 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Charlene Liu,
Aric Cyr
From: Charlene Liu <Charlene.Liu@amd.com>
[why]
dc->config.disable_dmcu set to true, but it still need create
dmcub based abm.
[how]
check to dc->caps.dmcub_support check.
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index 0f273ac0c83f..6ab81d609c97 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -256,7 +256,7 @@ struct abm *dmub_abm_create(
const struct dce_abm_shift *abm_shift,
const struct dce_abm_mask *abm_mask)
{
- if (!ctx->dc->config.disable_dmcu) {
+ if (ctx->dc->caps.dmcub_support) {
struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
if (abm_dce == NULL) {
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 07/14] drm/amd/display: Added root clock optimization flags
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
` (5 preceding siblings ...)
2021-10-01 14:36 ` [PATCH 06/14] drm/amd/display: dcn3 failed due to dmcbu_abm not created Solomon Chiu
@ 2021-10-01 14:36 ` Solomon Chiu
2021-10-01 14:36 ` [PATCH 08/14] drm/amd/display: Limit display scaling to up to 4k for DCN 3.1 Solomon Chiu
` (7 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Solomon Chiu @ 2021-10-01 14:36 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Jake Wang,
Nicholas Kazlauskas
From: Jake Wang <haonan.wang2@amd.com>
[Why & How]
Added root clock optimization debug flags for future debugging.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index c5a091d0bbfc..5ffe2a41258f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -477,6 +477,23 @@ union mem_low_power_enable_options {
uint32_t u32All;
};
+union root_clock_optimization_options {
+ struct {
+ bool dpp: 1;
+ bool dsc: 1;
+ bool hdmistream: 1;
+ bool hdmichar: 1;
+ bool dpstream: 1;
+ bool symclk32_se: 1;
+ bool symclk32_le: 1;
+ bool symclk_fe: 1;
+ bool physymclk: 1;
+ bool dpiasymclk: 1;
+ uint32_t reserved: 22;
+ } bits;
+ uint32_t u32All;
+};
+
struct dc_debug_data {
uint32_t ltFailCount;
uint32_t i2cErrorCount;
@@ -637,6 +654,7 @@ struct dc_debug_options {
bool legacy_dp2_lt;
#endif
union mem_low_power_enable_options enable_mem_low_power;
+ union root_clock_optimization_options root_clock_optimization;
bool force_vblank_alignment;
/* Enable dmub aux for legacy ddc */
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 08/14] drm/amd/display: Limit display scaling to up to 4k for DCN 3.1
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
` (6 preceding siblings ...)
2021-10-01 14:36 ` [PATCH 07/14] drm/amd/display: Added root clock optimization flags Solomon Chiu
@ 2021-10-01 14:36 ` Solomon Chiu
2021-10-01 14:36 ` [PATCH 09/14] drm/amd/display: Fix detection of 4 lane for DPALT Solomon Chiu
` (6 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Solomon Chiu @ 2021-10-01 14:36 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Nikola Cornij,
Zhan Liu
From: Nikola Cornij <nikola.cornij@amd.com>
[why]
The existing limit was mistakenly bigger than 4k for DCN 3.1
Reviewed-by: Zhan Liu <Zhan.Liu@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 613d34bde7dd..d5b58025f0cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -998,7 +998,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_dcc = DCC_ENABLE,
.vsr_support = true,
.performance_trace = false,
- .max_downscale_src_width = 7680,/*upto 8K*/
+ .max_downscale_src_width = 3840,/*upto 4K*/
.disable_pplib_wm_range = false,
.scl_reset_length10 = true,
.sanity_checks = false,
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 09/14] drm/amd/display: Fix detection of 4 lane for DPALT
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
` (7 preceding siblings ...)
2021-10-01 14:36 ` [PATCH 08/14] drm/amd/display: Limit display scaling to up to 4k for DCN 3.1 Solomon Chiu
@ 2021-10-01 14:36 ` Solomon Chiu
2021-10-01 14:36 ` [PATCH 10/14] drm/amd/display: [FW Promotion] Release 0.0.87 Solomon Chiu
` (5 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Solomon Chiu @ 2021-10-01 14:36 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Hansen,
Charlene Liu
From: Hansen <Hansen.Dsouza@amd.com>
[Why]
DPALT detection for B0 PHY has its own set of RDPCSPIPE registers
[How]
Use RDPCSPIPE registers to detect if DPALT lane is 4 lane
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Hansen <Hansen.Dsouza@amd.com>
---
.../display/dc/dcn31/dcn31_dio_link_encoder.c | 33 ++++++++++++++++++-
.../display/dc/dcn31/dcn31_dio_link_encoder.h | 3 ++
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
index 4f0a0803db6c..616a48d72afa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
@@ -63,6 +63,10 @@
#define AUX_REG_WRITE(reg_name, val) \
dm_write_reg(CTX, AUX_REG(reg_name), val)
+#ifndef MIN
+#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
+#endif
+
void dcn31_link_encoder_set_dio_phy_mux(
struct link_encoder *enc,
enum encoder_type_select sel,
@@ -217,7 +221,7 @@ static const struct link_encoder_funcs dcn31_link_enc_funcs = {
.get_dig_frontend = dcn10_get_dig_frontend,
.get_dig_mode = dcn10_get_dig_mode,
.is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,
- .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
+ .get_max_link_cap = dcn31_link_encoder_get_max_link_cap,
.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
};
@@ -439,3 +443,30 @@ bool dcn31_link_encoder_is_in_alt_mode(struct link_encoder *enc)
return is_usb_c_alt_mode;
}
+
+void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,
+ struct dc_link_settings *link_settings)
+{
+ struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+ uint32_t is_in_usb_c_dp4_mode = 0;
+
+ dcn10_link_encoder_get_max_link_cap(enc, link_settings);
+
+ /* in usb c dp2 mode, max lane count is 2 */
+ if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
+ if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
+ // [Note] no need to check hw_internal_rev once phy mux selection is ready
+ REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
+ } else {
+ if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A)
+ || (enc10->base.transmitter == TRANSMITTER_UNIPHY_B)
+ || (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
+ REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
+ } else {
+ REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
+ }
+ }
+ if (!is_in_usb_c_dp4_mode)
+ link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
+ }
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
index bec50e4402ff..3454f1e7c1f1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
@@ -252,4 +252,7 @@ void dcn31_link_encoder_disable_output(
bool dcn31_link_encoder_is_in_alt_mode(
struct link_encoder *enc);
+void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,
+ struct dc_link_settings *link_settings);
+
#endif /* __DC_LINK_ENCODER__DCN31_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 10/14] drm/amd/display: [FW Promotion] Release 0.0.87
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
` (8 preceding siblings ...)
2021-10-01 14:36 ` [PATCH 09/14] drm/amd/display: Fix detection of 4 lane for DPALT Solomon Chiu
@ 2021-10-01 14:36 ` Solomon Chiu
2021-10-01 14:36 ` [PATCH 11/14] drm/amd/display: 3.2.156 Solomon Chiu
` (4 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Solomon Chiu @ 2021-10-01 14:36 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index f5974562aa23..42956dd398f3 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x42c0e74b
+#define DMUB_FW_VERSION_GIT_HASH 0xf0c64c97
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 86
+#define DMUB_FW_VERSION_REVISION 87
#define DMUB_FW_VERSION_TEST 0
#define DMUB_FW_VERSION_VBIOS 0
#define DMUB_FW_VERSION_HOTFIX 0
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 11/14] drm/amd/display: 3.2.156
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
` (9 preceding siblings ...)
2021-10-01 14:36 ` [PATCH 10/14] drm/amd/display: [FW Promotion] Release 0.0.87 Solomon Chiu
@ 2021-10-01 14:36 ` Solomon Chiu
2021-10-01 14:36 ` [PATCH 12/14] drm/amd/display: Add helper for blanking all dp displays Solomon Chiu
` (3 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Solomon Chiu @ 2021-10-01 14:36 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Aric Cyr
From: Aric Cyr <aric.cyr@amd.com>
This version brings along following fixes:
- New firmware version
- Fix DMUB problems on stress test.
- Improve link training by skip overrride for preferred link
- Refinement of FPU code structure for DCN2
- Fix 3DLUT skipped programming
- Fix detection of 4 lane for DPALT
- Fix dcn3 failure due to dmcbu_abm not created
- Limit display scaling to up to 4k for DCN 3.1
- Add helper for blanking all dp displays
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 5ffe2a41258f..204bab6f82ef 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -45,7 +45,7 @@
/* forward declaration */
struct aux_payload;
-#define DC_VER "3.2.155"
+#define DC_VER "3.2.156"
#define MAX_SURFACES 3
#define MAX_PLANES 6
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 12/14] drm/amd/display: Add helper for blanking all dp displays
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
` (10 preceding siblings ...)
2021-10-01 14:36 ` [PATCH 11/14] drm/amd/display: 3.2.156 Solomon Chiu
@ 2021-10-01 14:36 ` Solomon Chiu
2021-10-01 14:36 ` [PATCH 13/14] drm/amd/display: Fix concurrent dynamic encoder assignment Solomon Chiu
` (2 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Solomon Chiu @ 2021-10-01 14:36 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu,
Leo (Hanghong) Ma, Aric Cyr
From: "Leo (Hanghong) Ma" <hanghong.ma@amd.com>
[Why & How]
The codes to blank all dp display have been called many times,
so add a helper in dc_link to make it more concise.
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 45 +++++++++++++++++++
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
.../display/dc/dce110/dce110_hw_sequencer.c | 24 ++--------
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 41 ++---------------
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 39 ++--------------
.../drm/amd/display/dc/dcn31/dcn31_hwseq.c | 39 ++--------------
6 files changed, 59 insertions(+), 130 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 02c7a18c095f..74da226efffe 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1906,6 +1906,51 @@ static enum dc_status enable_link_dp_mst(
return enable_link_dp(state, pipe_ctx);
}
+void blank_all_dp_displays(struct dc *dc, bool hw_init)
+{
+ unsigned int i, j, fe;
+ uint8_t dpcd_power_state = '\0';
+ enum dc_status status = DC_ERROR_UNEXPECTED;
+
+ for (i = 0; i < dc->link_count; i++) {
+ enum signal_type signal = dc->links[i]->connector_signal;
+
+ if ((signal == SIGNAL_TYPE_EDP) ||
+ (signal == SIGNAL_TYPE_DISPLAY_PORT)) {
+ if (hw_init && signal != SIGNAL_TYPE_EDP) {
+ /* DP 2.0 spec requires that we read LTTPR caps first */
+ dp_retrieve_lttpr_cap(dc->links[i]);
+ /* if any of the displays are lit up turn them off */
+ status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
+ &dpcd_power_state, sizeof(dpcd_power_state));
+ }
+
+ if ((signal != SIGNAL_TYPE_EDP && status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) ||
+ (!hw_init && dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc))) {
+ if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY &&
+ dc->links[i]->link_enc->funcs->get_dig_frontend) {
+ fe = dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
+ if (fe == ENGINE_ID_UNKNOWN)
+ continue;
+
+ for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
+ if (fe == dc->res_pool->stream_enc[j]->id) {
+ dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
+ dc->res_pool->stream_enc[j]);
+ break;
+ }
+ }
+ }
+
+ if (!dc->links[i]->wa_flags.dp_keep_receiver_powered ||
+ (hw_init && signal != SIGNAL_TYPE_EDP))
+ dp_receiver_power_ctrl(dc->links[i], false);
+ }
+ }
+ }
+
+}
+
static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
enum engine_id eng_id,
struct ext_hdmi_settings *settings)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index a73d64b1fd33..69b008bafbbc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -277,6 +277,7 @@ bool dc_link_setup_psr(struct dc_link *dc_link,
struct psr_context *psr_context);
void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency);
+void blank_all_dp_displays(struct dc *dc, bool hw_init);
/* Request DC to detect if there is a Panel connected.
* boot - If this call is during initial boot.
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index af3e68d3e747..8108f9ae2638 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1649,31 +1649,13 @@ static enum dc_status apply_single_controller_ctx_to_hw(
static void power_down_encoders(struct dc *dc)
{
- int i, j;
+ int i;
+
+ blank_all_dp_displays(dc, false);
for (i = 0; i < dc->link_count; i++) {
enum signal_type signal = dc->links[i]->connector_signal;
- if ((signal == SIGNAL_TYPE_EDP) ||
- (signal == SIGNAL_TYPE_DISPLAY_PORT)) {
- if (dc->links[i]->link_enc->funcs->get_dig_frontend &&
- dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc)) {
- unsigned int fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
- dc->links[i]->link_enc);
-
- for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
- if (fe == dc->res_pool->stream_enc[j]->id) {
- dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
- dc->res_pool->stream_enc[j]);
- break;
- }
- }
- }
-
- if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
- dp_receiver_power_ctrl(dc->links[i], false);
- }
-
if (signal != SIGNAL_TYPE_EDP)
signal = SIGNAL_TYPE_NONE;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index c5e2b4f138fd..bc3ec05bf34b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1366,7 +1366,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
void dcn10_init_hw(struct dc *dc)
{
- int i, j;
+ int i;
struct abm *abm = dc->res_pool->abm;
struct dmcu *dmcu = dc->res_pool->dmcu;
struct dce_hwseq *hws = dc->hwseq;
@@ -1462,43 +1462,8 @@ void dcn10_init_hw(struct dc *dc)
dmub_enable_outbox_notification(dc);
/* we want to turn off all dp displays before doing detection */
- if (dc->config.power_down_display_on_boot) {
- uint8_t dpcd_power_state = '\0';
- enum dc_status status = DC_ERROR_UNEXPECTED;
-
- for (i = 0; i < dc->link_count; i++) {
- if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
- continue;
-
- /* DP 2.0 requires that LTTPR Caps be read first */
- dp_retrieve_lttpr_cap(dc->links[i]);
-
- /*
- * If any of the displays are lit up turn them off.
- * The reason is that some MST hubs cannot be turned off
- * completely until we tell them to do so.
- * If not turned off, then displays connected to MST hub
- * won't light up.
- */
- status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
- &dpcd_power_state, sizeof(dpcd_power_state));
- if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) {
- /* blank dp stream before power off receiver*/
- if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
- unsigned int fe = dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
-
- for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
- if (fe == dc->res_pool->stream_enc[j]->id) {
- dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
- dc->res_pool->stream_enc[j]);
- break;
- }
- }
- }
- dp_receiver_power_ctrl(dc->links[i], false);
- }
- }
- }
+ if (dc->config.power_down_display_on_boot)
+ blank_all_dp_displays(dc, true);
/* If taking control over from VBIOS, we may want to optimize our first
* mode set, so we need to skip powering down pipes until we know which
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index b132ebed09d4..01a90badd173 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -437,7 +437,7 @@ void dcn30_init_hw(struct dc *dc)
struct dce_hwseq *hws = dc->hwseq;
struct dc_bios *dcb = dc->ctx->dc_bios;
struct resource_pool *res_pool = dc->res_pool;
- int i, j;
+ int i;
int edp_num;
uint32_t backlight = MAX_BACKLIGHT_LEVEL;
@@ -534,41 +534,8 @@ void dcn30_init_hw(struct dc *dc)
hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
/* we want to turn off all dp displays before doing detection */
- if (dc->config.power_down_display_on_boot) {
- uint8_t dpcd_power_state = '\0';
- enum dc_status status = DC_ERROR_UNEXPECTED;
-
- for (i = 0; i < dc->link_count; i++) {
- if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
- continue;
- /* DP 2.0 states that LTTPR regs must be read first */
- dp_retrieve_lttpr_cap(dc->links[i]);
-
- /* if any of the displays are lit up turn them off */
- status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
- &dpcd_power_state, sizeof(dpcd_power_state));
- if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) {
- /* blank dp stream before power off receiver*/
- if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
- unsigned int fe;
-
- fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
- dc->links[i]->link_enc);
- if (fe == ENGINE_ID_UNKNOWN)
- continue;
-
- for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
- if (fe == dc->res_pool->stream_enc[j]->id) {
- dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
- dc->res_pool->stream_enc[j]);
- break;
- }
- }
- }
- dp_receiver_power_ctrl(dc->links[i], false);
- }
- }
- }
+ if (dc->config.power_down_display_on_boot)
+ blank_all_dp_displays(dc, true);
/* If taking control over from VBIOS, we may want to optimize our first
* mode set, so we need to skip powering down pipes until we know which
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 0713910a3aa9..80f06ceccea8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -71,7 +71,7 @@ void dcn31_init_hw(struct dc *dc)
struct dc_bios *dcb = dc->ctx->dc_bios;
struct resource_pool *res_pool = dc->res_pool;
uint32_t backlight = MAX_BACKLIGHT_LEVEL;
- int i, j;
+ int i;
int edp_num;
if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
@@ -175,40 +175,9 @@ void dcn31_init_hw(struct dc *dc)
hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
/* we want to turn off all dp displays before doing detection */
- if (dc->config.power_down_display_on_boot) {
- uint8_t dpcd_power_state = '\0';
- enum dc_status status = DC_ERROR_UNEXPECTED;
-
- for (i = 0; i < dc->link_count; i++) {
- if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
- continue;
-
- /* if any of the displays are lit up turn them off */
- status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
- &dpcd_power_state, sizeof(dpcd_power_state));
- if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) {
- /* blank dp stream before power off receiver*/
- if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY &&
- dc->links[i]->link_enc->funcs->get_dig_frontend) {
- unsigned int fe;
-
- fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
- dc->links[i]->link_enc);
- if (fe == ENGINE_ID_UNKNOWN)
- continue;
-
- for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
- if (fe == dc->res_pool->stream_enc[j]->id) {
- dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
- dc->res_pool->stream_enc[j]);
- break;
- }
- }
- }
- dp_receiver_power_ctrl(dc->links[i], false);
- }
- }
- }
+ if (dc->config.power_down_display_on_boot)
+ blank_all_dp_displays(dc, true);
+
/* If taking control over from VBIOS, we may want to optimize our first
* mode set, so we need to skip powering down pipes until we know which
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 13/14] drm/amd/display: Fix concurrent dynamic encoder assignment.
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
` (11 preceding siblings ...)
2021-10-01 14:36 ` [PATCH 12/14] drm/amd/display: Add helper for blanking all dp displays Solomon Chiu
@ 2021-10-01 14:36 ` Solomon Chiu
2021-10-01 14:36 ` [PATCH 14/14] drm/amd/display: Fix error in dmesg at boot Solomon Chiu
2021-10-04 13:27 ` [PATCH 00/14] DC Patches October 1, 2021 Wheeler, Daniel
14 siblings, 0 replies; 16+ messages in thread
From: Solomon Chiu @ 2021-10-01 14:36 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu, Jimmy Kizito,
Jun Lei
From: Jimmy Kizito <Jimmy.Kizito@amd.com>
[Why]
Trying to enable multiple displays simultaneously exposed shortcomings
with the algorithm for dynamic link encoder assignment.
The main problems were:
- Assuming stream order remained constant across states would
sometimes lead to invalid DIG encoder assignment.
- Incorrect logic for deciding whether or not a DIG could support a
stream would also sometimes lead to invalid DIG encoder assignment.
- Changes in encoder assignment were wholesale while updating of the
pipe backend is incremental. This would lead to the hardware state
not matching the software state even with valid encoder assignments.
[How]
The following changes fix the identified problems.
- Use stream pointer rather than stream index to track streams across
states.
- Fix DIG compatibility check by examining the link signal type
rather than the stream signal type.
- Modify assignment algorithm to make incremental updates so software
and hardware states remain coherent.
Additionally:
- Add assertions and an encoder assignment validation
function link_enc_cfg_validate() to detect potential problems with
encoder assignment closer to their root cause.
- Reduce the frequency with which the assignment algorithm is
executed. It should not be necessary for fast state validation.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 74da226efffe..81bf1e5a64c8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1926,9 +1926,9 @@ void blank_all_dp_displays(struct dc *dc, bool hw_init)
}
if ((signal != SIGNAL_TYPE_EDP && status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) ||
- (!hw_init && dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc))) {
- if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY &&
- dc->links[i]->link_enc->funcs->get_dig_frontend) {
+ (!hw_init && dc->links[i]->link_enc &&
+ dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc))) {
+ if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
fe = dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
if (fe == ENGINE_ID_UNKNOWN)
continue;
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 14/14] drm/amd/display: Fix error in dmesg at boot
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
` (12 preceding siblings ...)
2021-10-01 14:36 ` [PATCH 13/14] drm/amd/display: Fix concurrent dynamic encoder assignment Solomon Chiu
@ 2021-10-01 14:36 ` Solomon Chiu
2021-10-04 13:27 ` [PATCH 00/14] DC Patches October 1, 2021 Wheeler, Daniel
14 siblings, 0 replies; 16+ messages in thread
From: Solomon Chiu @ 2021-10-01 14:36 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, Sunpeng.Li, Bhawanpreet.Lakha, Rodrigo.Siqueira,
Aurabindo.Pillai, qingqing.zhuo, mikita.lipski, roman.li,
Anson.Jacob, wayne.lin, stylon.wang, solomon.chiu,
Leo (Hanghong) Ma, Nicholas Kazlauskas
From: "Leo (Hanghong) Ma" <hanghong.ma@amd.com>
[Why]
During DQE's promotion test, error appears in dmesg at boot
on dcn3.1;
[How]
Add NULL pointor check for the pointor to the amdgpu_dm_connector;
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 81bf1e5a64c8..64b9c493dce2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1917,7 +1917,7 @@ void blank_all_dp_displays(struct dc *dc, bool hw_init)
if ((signal == SIGNAL_TYPE_EDP) ||
(signal == SIGNAL_TYPE_DISPLAY_PORT)) {
- if (hw_init && signal != SIGNAL_TYPE_EDP) {
+ if (hw_init && signal != SIGNAL_TYPE_EDP && dc->links[i]->priv != NULL) {
/* DP 2.0 spec requires that we read LTTPR caps first */
dp_retrieve_lttpr_cap(dc->links[i]);
/* if any of the displays are lit up turn them off */
@@ -1943,7 +1943,7 @@ void blank_all_dp_displays(struct dc *dc, bool hw_init)
}
if (!dc->links[i]->wa_flags.dp_keep_receiver_powered ||
- (hw_init && signal != SIGNAL_TYPE_EDP))
+ (hw_init && signal != SIGNAL_TYPE_EDP && dc->links[i]->priv != NULL))
dp_receiver_power_ctrl(dc->links[i], false);
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* RE: [PATCH 00/14] DC Patches October 1, 2021
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
` (13 preceding siblings ...)
2021-10-01 14:36 ` [PATCH 14/14] drm/amd/display: Fix error in dmesg at boot Solomon Chiu
@ 2021-10-04 13:27 ` Wheeler, Daniel
14 siblings, 0 replies; 16+ messages in thread
From: Wheeler, Daniel @ 2021-10-04 13:27 UTC (permalink / raw)
To: Chiu, Solomon, amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry, Li, Sun peng (Leo), Lakha, Bhawanpreet,
Siqueira, Rodrigo, Pillai, Aurabindo, Zhuo, Qingqing,
Lipski, Mikita, Li, Roman, Jacob, Anson, Lin, Wayne,
Wang, Chao-kai (Stylon), Chiu, Solomon
[Public]
Hi all,
This week this patchset was tested on the following systems:
HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
AMD Ryzen 9 5900H, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
Sapphire Pulse RX5700XT with the following display types:
4k 60hz (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Reference AMD RX6800 with the following display types:
4k 60hz (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz, and 3x 1080p 60hz on all systems.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Thank you,
Dan Wheeler
Technologist | AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
Facebook | Twitter | amd.com
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Solomon Chiu
Sent: October 1, 2021 10:36 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry <Harry.Wentland@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Zhuo, Qingqing <Qingqing.Zhuo@amd.com>; Lipski, Mikita <Mikita.Lipski@amd.com>; Li, Roman <Roman.Li@amd.com>; Jacob, Anson <Anson.Jacob@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>; Chiu, Solomon <Solomon.Chiu@amd.com>
Subject: [PATCH 00/14] DC Patches October 1, 2021
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- New firmware version
- Fix DMUB problems on stress test.
- Improve link training by skip overrride for preferred link
- Refinement of FPU code structure for DCN2
- Fix 3DLUT skipped programming
- Fix detection of 4 lane for DPALT
- Fix dcn3 failure due to dmcbu_abm not created
- Limit display scaling to up to 4k for DCN 3.1
- Add helper for blanking all dp displays
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.87
Aric Cyr (2):
drm/amd/display: Fix 3DLUT skipped programming
drm/amd/display: 3.2.156
Charlene Liu (2):
drm/amd/display: update irq_service and other required change part 2.
drm/amd/display: dcn3 failed due to dmcbu_abm not created
George Shen (1):
drm/amd/display: Skip override for preferred link settings during link
training
Hansen (1):
drm/amd/display: Fix detection of 4 lane for DPALT
Jake Wang (1):
drm/amd/display: Added root clock optimization flags
Jimmy Kizito (1):
drm/amd/display: Fix concurrent dynamic encoder assignment.
Leo (Hanghong) Ma (2):
drm/amd/display: Add helper for blanking all dp displays
drm/amd/display: Fix error in dmesg at boot
Nikola Cornij (1):
drm/amd/display: Limit display scaling to up to 4k for DCN 3.1
Qingqing Zhuo (1):
drm/amd/display: Re-arrange FPU code structure for dcn2x
Wyatt Wood (1):
drm/amd/display: Prevent using DMUB rptr that is out-of-bounds
.../gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 45 +++++++++++++++++++ .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 6 ---
drivers/gpu/drm/amd/display/dc/dc.h | 21 ++++++++-
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 9 ++--
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 1 + drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 17 ++++---
.../display/dc/dce110/dce110_hw_sequencer.c | 24 ++--------
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 41 ++--------------- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
.../amd/display/dc/dcn201/dcn201_resource.c | 2 +-
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 39 ++--------------
.../display/dc/dcn31/dcn31_dio_link_encoder.c | 33 +++++++++++++- .../display/dc/dcn31/dcn31_dio_link_encoder.h | 3 ++
.../drm/amd/display/dc/dcn31/dcn31_hwseq.c | 39 ++--------------
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dml/Makefile | 4 +-
.../dml/{dcn2x/dcn2x.c => dcn20/dcn20_fpu.c} | 2 +- .../dml/{dcn2x/dcn2x.h => dcn20/dcn20_fpu.h} | 6 +--
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 +
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 +-
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 10 ++++-
25 files changed, 156 insertions(+), 164 deletions(-) rename drivers/gpu/drm/amd/display/dc/dml/{dcn2x/dcn2x.c => dcn20/dcn20_fpu.c} (99%) rename drivers/gpu/drm/amd/display/dc/dml/{dcn2x/dcn2x.h => dcn20/dcn20_fpu.h} (94%)
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread