[PATCH 00/33] DC Patches August 27 ,2022

[PATCH 00/33] DC Patches August 27 ,2022

[brichang]

This DC patchset brings improvements in multiple areas. In summary, we have:

* Correct cursor position on horizontal mirror;
* Fix black flash when switching from ODM2to1 to ODMBypass;
* Fix plane and stream check;
* Fix viewport after pipe merge;
* Correct plane for CAB cursor;
* Fix comment to correct visual confirm option;
* Fix SubVP related regression;
* Fix primary EDP link detection;
* Fix wrong register access;
* Fix cursor size allocation for DCN32/321;
* Fix display fresh edge case from MALL for DCN321;
* Add HPO instance;
* Refactor EDP codes;
* Add SubVP scaling case;
* Add support for visual confirm color;
* Fix PHY state update;
* Cleanup PSR flag;
* Fix cursor lag with PSR1 eDP;
* Add DC debug optioon for LTTPR mode;
* Add override flag for some dongle;
* Fix SubVP state after pipe programming;
* Remove assert from PHY state update;
* Fix dig fifo read level before reset;
* Add dcn35 basic suppoet;
* Fix OTG H timming for dcn314;
* Fix aux transaction;
* Fix DCN32 DPSTREAMCLK_CNTL programming;
* Fix SubVP scheduling issues;
* Set ODM policy.


Alvin Lee (3):
  drm/amd/display: Don't choose SubVP display if ActiveMargin > 0
  drm/amd/display: Only commit SubVP state after pipe programming
  drm/amd/display: SubVP missing scaling case

Anthony Koo (1):
  drm/amd/display: [FW Promotion] Release 0.0.132.0

Aric Cyr (1):
  drm/amd/display: 3.2.201

Aurabindo Pillai (5):
  drm/amd/display: Fix CAB cursor size allocation for DCN32/321
  drm/amd/display: disable display fresh from MALL on an edge case for
    DCN321
  drm/amd/display: use actual cursor size instead of max for CAB
    allocation
  drm/amd/display: Revert "program k1/k2 divider for virtual signal for
    DCN32"
  drm/amd/display: Use correct plane for CAB cursor size allocation

Charlene Liu (2):
  drm/amd/display: add dcn35 basic support
  drm/amd/display: fix wrong register access

Chen, Leo (1):
  drm/amd/display: add a override flag as wa for some specific dongle

Duncan Ma (1):
  drm/amd/display: Fix OTG H timing reset for dcn314

Ethan Wellenreiter (2):
  drm/amd/display: Re-initialize viewport after pipe merge
  drm/amd/display: Fix check for stream and plane

Gabe Teeger (2):
  drm/amd/display: Cursor lag with PSR1 eDP
  drm/amd/display: Cleanup PSR flag

George Shen (1):
  drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming

Ian Chen (2):
  drm/amd/display: Refactor edp dsc codes.
  drm/amd/display: Add comments.

Iswara Nagulendran (1):
  drm/amd/display: Fix primary EDP link detection

Leo (Hanghong) Ma (2):
  drm/amd/display: Add visual confirm color support for SubVP
  drm/amd/display: Add support for visual confirm color

Leo Chen (1):
  drm/amd/display: Missing HPO instance added

Lewis Huang (1):
  drm/amd/display: Refine aux transaction before retrieve caps

Martin Tsai (1):
  drm/amd/display: Correct cursor position on horizontal mirror

Michael Strauss (1):
  drm/amd/display: Add DC debug option to force LTTPR mode

Taimur Hassan (3):
  drm/amd/display: Set ODM policy based on number of DSC slices
  drm/amd/display: Remove assert from PHY state update
  drm/amd/display: Allow PHY state update between same states

Vladimir Stempen (1):
  drm/amd/display: Fix black flash when switching from ODM2to1 to
    ODMBypass

Wang Fudong (1):
  drm/amd/display: set dig fifo read start level to 7 before dig fifo
    reset

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  4 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 +++++
 .../drm/amd/display/dc/clk_mgr/Makefile.rej   | 17 ++++
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 26 +++---
 .../drm/amd/display/dc/core/dc_hw_sequencer.c | 38 +++++++++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 ++---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 53 +++++++++---
 drivers/gpu/drm/amd/display/dc/dc.h           |  8 +-
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  | 41 ++++++++-
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h  |  1 +
 drivers/gpu/drm/amd/display/dc/dc_link.h      | 12 +++
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h  |  9 +-
 .../display/dc/dce110/dce110_hw_sequencer.c   | 13 +++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c  |  5 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |  9 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 83 +++++++++++++------
 .../display/dc/dcn10/dcn10_stream_encoder.h   |  1 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c |  9 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  6 +-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h  |  3 +-
 .../display/dc/dcn31/dcn31_dio_link_encoder.c |  3 +
 .../dc/dcn31/dcn31_hpo_dp_link_encoder.h      | 10 ++-
 .../drm/amd/display/dc/dcn31/dcn31_resource.c |  1 -
 .../dc/dcn314/dcn314_dio_stream_encoder.c     |  1 +
 .../drm/amd/display/dc/dcn314/dcn314_optc.c   |  3 +-
 .../amd/display/dc/dcn314/dcn314_resource.c   |  2 +-
 .../amd/display/dc/dcn315/dcn315_resource.c   |  1 -
 .../amd/display/dc/dcn316/dcn316_resource.c   |  1 -
 .../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c |  8 +-
 .../dc/dcn32/dcn32_dio_stream_encoder.c       |  5 ++
 .../drm/amd/display/dc/dcn32/dcn32_hwseq.c    | 75 ++++++++++++-----
 .../display/dc/dcn32/dcn32_resource_helpers.c |  2 +-
 drivers/gpu/drm/amd/display/dc/dm_helpers.h   |  7 +-
 .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c  | 36 +++++++-
 .../dc/dml/dcn32/display_mode_vba_32.c        |  4 +-
 .../dc/dml/dcn32/display_mode_vba_util_32.c   |  7 +-
 .../dc/dml/dcn32/display_mode_vba_util_32.h   |  1 +
 .../drm/amd/display/dc/dml/display_mode_vba.h |  1 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  5 ++
 .../amd/display/dc/link/link_hwss_hpo_dp.c    |  4 +-
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h   |  4 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 47 ++++++++++-
 .../gpu/drm/amd/display/include/dal_types.h   |  1 +
 43 files changed, 469 insertions(+), 139 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej

-- 
2.25.1

[PATCH 01/33] drm/amd/display: Set ODM policy based on number of DSC slices

[brichang]

From: Taimur Hassan <Syed.Hassan@amd.com>

[Why & How]
Add addtional check in CalculateODMMode for cases where the ODM combine
is needed due to number of DSC slices.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
---
 .../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 ++
 .../amd/display/dc/dml/dcn32/display_mode_vba_util_32.c    | 7 +++++--
 .../amd/display/dc/dml/dcn32/display_mode_vba_util_32.h    | 1 +
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index cb2025771646..f831855db022 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -2045,6 +2045,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 						mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
 						mode_lib->vba.DISPCLKRampingMargin,
 						mode_lib->vba.DISPCLKDPPCLKVCOSpeed,
+						mode_lib->vba.NumberOfDSCSlices[k],
 
 						/* Output */
 						&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalAvailablePipesSupportNoDSC,
@@ -2066,6 +2067,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 						mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
 						mode_lib->vba.DISPCLKRampingMargin,
 						mode_lib->vba.DISPCLKDPPCLKVCOSpeed,
+						mode_lib->vba.NumberOfDSCSlices[k],
 
 						/* Output */
 						&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalAvailablePipesSupportDSC,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 05fc14a47fba..6b3c4dbb140b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -1193,6 +1193,7 @@ void dml32_CalculateODMMode(
 		double DISPCLKDPPCLKDSCCLKDownSpreading,
 		double DISPCLKRampingMargin,
 		double DISPCLKDPPCLKVCOSpeed,
+		unsigned int NumberOfDSCSlices,
 
 		/* Output */
 		bool *TotalAvailablePipesSupport,
@@ -1228,7 +1229,8 @@ void dml32_CalculateODMMode(
 
 	if (!(Output == dm_hdmi || Output == dm_dp || Output == dm_edp) && (ODMUse == dm_odm_combine_policy_4to1 ||
 			((SurfaceRequiredDISPCLKWithODMCombineTwoToOne > StateDispclk ||
-					(DSCEnable && (HActive > 2 * MaximumPixelsPerLinePerDSCUnit)))))) {
+					(DSCEnable && (HActive > 2 * MaximumPixelsPerLinePerDSCUnit))
+					|| NumberOfDSCSlices > 8)))) {
 		if (TotalNumberOfActiveDPP + 4 <= MaxNumDPP) {
 			*ODMMode = dm_odm_combine_mode_4to1;
 			*RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineFourToOne;
@@ -1239,7 +1241,8 @@ void dml32_CalculateODMMode(
 	} else if (Output != dm_hdmi && (ODMUse == dm_odm_combine_policy_2to1 ||
 			(((SurfaceRequiredDISPCLKWithoutODMCombine > StateDispclk &&
 					SurfaceRequiredDISPCLKWithODMCombineTwoToOne <= StateDispclk) ||
-					(DSCEnable && (HActive > MaximumPixelsPerLinePerDSCUnit)))))) {
+					(DSCEnable && (HActive > MaximumPixelsPerLinePerDSCUnit))
+					|| (NumberOfDSCSlices <= 8 && NumberOfDSCSlices > 4))))) {
 		if (TotalNumberOfActiveDPP + 2 <= MaxNumDPP) {
 			*ODMMode = dm_odm_combine_mode_2to1;
 			*RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineTwoToOne;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
index d293856ba906..626f6605e2d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
@@ -226,6 +226,7 @@ void dml32_CalculateODMMode(
 		double DISPCLKDPPCLKDSCCLKDownSpreading,
 		double DISPCLKRampingMargin,
 		double DISPCLKDPPCLKVCOSpeed,
+		unsigned int NumberOfDSCSlices,
 
 		/* Output */
 		bool *TotalAvailablePipesSupport,
-- 
2.25.1

[PATCH 02/33] drm/amd/display: Don't choose SubVP display if ActiveMargin > 0

[brichang]

From: Alvin Lee <Alvin.Lee2@amd.com>

[Description]
There can be SubVP scheduling issues if a SubVP
display is chosen has ActiveDramClockChangeLatency > 0.
Block this case for now, and enable Vactive case
(later) to handle this.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
---
 .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c  | 21 ++++++++++++++++---
 .../dc/dml/dcn32/display_mode_vba_32.c        |  2 +-
 .../drm/amd/display/dc/dml/display_mode_vba.h |  1 +
 3 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index edefb3fc1c3c..e72213a20e75 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -560,6 +560,7 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,
 	bool valid_assignment_found = false;
 	unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
 	bool current_assignment_freesync = false;
+	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 
 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
@@ -573,8 +574,15 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,
 		refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
 				pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
 				/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
+		/* SubVP pipe candidate requirements:
+		 * - Refresh rate < 120hz
+		 * - Not able to switch in vactive naturally (switching in active means the
+		 *   DET provides enough buffer to hide the P-State switch latency -- trying
+		 *   to combine this with SubVP can cause issues with the scheduling).
+		 */
 		if (pipe->plane_state && !pipe->top_pipe &&
-				pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120) {
+				pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120 &&
+				vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) {
 			while (pipe) {
 				num_pipes++;
 				pipe = pipe->bottom_pipe;
@@ -998,8 +1006,10 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
 
 	*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
 	/* This may adjust vlevel and maxMpcComb */
-	if (*vlevel < context->bw_ctx.dml.soc.num_states)
+	if (*vlevel < context->bw_ctx.dml.soc.num_states) {
 		*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
+		vba->VoltageLevel = *vlevel;
+	}
 
 	/* Conditions for setting up phantom pipes for SubVP:
 	 * 1. Not force disable SubVP
@@ -1085,13 +1095,16 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
 
 			*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
 			/* This may adjust vlevel and maxMpcComb */
-			if (*vlevel < context->bw_ctx.dml.soc.num_states)
+			if (*vlevel < context->bw_ctx.dml.soc.num_states) {
 				*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
+				vba->VoltageLevel = *vlevel;
+			}
 		} else {
 			// only call dcn20_validate_apply_pipe_split_flags if we found a supported config
 			memset(split, 0, MAX_PIPES * sizeof(int));
 			memset(merge, 0, MAX_PIPES * sizeof(bool));
 			*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
+			vba->VoltageLevel = *vlevel;
 
 			// Most populate phantom DLG params before programming hardware / timing for phantom pipe
 			DC_FP_START();
@@ -1421,6 +1434,8 @@ bool dcn32_internal_validate_bw(struct dc *dc,
 			memset(split, 0, sizeof(split));
 			memset(merge, 0, sizeof(merge));
 			vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
+			// dcn20_validate_apply_pipe_split_flags can modify voltage level outside of DML
+			vba->VoltageLevel = vlevel;
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index f831855db022..3040428a7304 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -3617,7 +3617,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 						&mode_lib->vba.FCLKChangeSupport[i][j],
 						&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single2[1], // double *MinActiveFCLKChangeLatencySupported
 						&mode_lib->vba.USRRetrainingSupport[i][j],
-						mode_lib->vba.ActiveDRAMClockChangeLatencyMargin);
+						mode_lib->vba.ActiveDRAMClockChangeLatencyMarginPerState[i][j]);
 			}
 		}
 	} // End of Prefetch Check
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 492aec634b68..da8acf59ccac 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -312,6 +312,7 @@ struct vba_vars_st {
 	unsigned int ActiveDPPs;
 	unsigned int LBLatencyHidingSourceLinesY;
 	unsigned int LBLatencyHidingSourceLinesC;
+	double ActiveDRAMClockChangeLatencyMarginPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];// DML doesn't save active margin per state
 	double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
 	double CachedActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; // Cache in dml_get_voltage_level for debug purposes only
 	double MinActiveDRAMClockChangeMargin;
-- 
2.25.1

[PATCH 03/33] drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming

[brichang]

From: George Shen <george.shen@amd.com>

[Why]
Each index in the DPSTREAMCLK_CNTL register
phyiscally maps 1-to-1 with HPO stream encoder
instance. On the other hand, each index in
DTBCLK_P_CNTL physically maps 1-to-1 with OTG
instance.

Current DCN32 DPSTREAMCLK_CLK programing assumes
that OTG instance always maps 1-to-1 with
HPO stream encoder instance. This is not always
guaranteed and can result in blackscreen.

[How]
Program the correct dpstreamclk instance with
the correct dtbclk_p source.

Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c      | 8 ++++----
 drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index a31c64b50410..0d5e8a441512 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -225,19 +225,19 @@ void dccg32_set_dpstreamclk(
 	case 0:
 		REG_UPDATE_2(DPSTREAMCLK_CNTL,
 			     DPSTREAMCLK0_EN,
-			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, 0);
+			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst);
 		break;
 	case 1:
 		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,
-			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, 1);
+			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst);
 		break;
 	case 2:
 		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,
-			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, 2);
+			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst);
 		break;
 	case 3:
 		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,
-			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, 3);
+			     (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst);
 		break;
 	default:
 		BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c b/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c
index db7b0b155374..226af06278ce 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c
@@ -116,7 +116,7 @@ static void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx)
 	dto_params.timing = &pipe_ctx->stream->timing;
 	dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
 
-	dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, link_enc->inst);
+	dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, stream_enc->inst);
 	dccg->funcs->enable_symclk32_se(dccg, stream_enc->inst, phyd32clk);
 	dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
 	stream_enc->funcs->enable_stream(stream_enc);
@@ -137,7 +137,7 @@ static void reset_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx)
 	stream_enc->funcs->disable(stream_enc);
 	dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
 	dccg->funcs->disable_symclk32_se(dccg, stream_enc->inst);
-	dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst,  pipe_ctx->link_res.hpo_dp_link_enc->inst);
+	dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, stream_enc->inst);
 }
 
 static void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx)
-- 
2.25.1

[PATCH 04/33] drm/amd/display: Refine aux transaction before retrieve caps

[brichang]

From: Lewis Huang <Lewis.Huang@amd.com>

[Why]
LTTPR caps will read fail if aux channel is not active.

[How]
1.Perform 600 read upto 10 retry with 1ms delay in between.
2.If fail, return false and trigger another retry detection.
3.If pass, read LTTPR caps in retrieve link caps.

Reviewed-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 45 ++++++++++++++-----
 1 file changed, 34 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 2b7bb3a796e8..8617de559174 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5275,6 +5275,7 @@ static bool retrieve_link_cap(struct dc_link *link)
 	union dp_downstream_port_present ds_port = { 0 };
 	enum dc_status status = DC_ERROR_UNEXPECTED;
 	uint32_t read_dpcd_retry_cnt = 3;
+	uint32_t aux_channel_retry_cnt = 0;
 	int i;
 	struct dp_sink_hw_fw_revision dp_hw_fw_revision;
 	const uint32_t post_oui_delay = 30; // 30ms
@@ -5302,21 +5303,43 @@ static bool retrieve_link_cap(struct dc_link *link)
 		status = wa_try_to_wake_dprx(link, timeout_ms);
 	}
 
+	while (status != DC_OK && aux_channel_retry_cnt < 10) {
+		status = core_link_read_dpcd(link, DP_SET_POWER,
+				&dpcd_power_state, sizeof(dpcd_power_state));
+
+		/* Delay 1 ms if AUX CH is in power down state. Based on spec
+		 * section 2.3.1.2, if AUX CH may be powered down due to
+		 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
+		 * signal and may need up to 1 ms before being able to reply.
+		 */
+		if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) {
+			udelay(1000);
+			aux_channel_retry_cnt++;
+		}
+	}
+
+	/* If aux channel is not active, return false and trigger another detect*/
+	if (status != DC_OK) {
+		dpcd_power_state = DP_SET_POWER_D0;
+		status = core_link_write_dpcd(
+				link,
+				DP_SET_POWER,
+				&dpcd_power_state,
+				sizeof(dpcd_power_state));
+
+		dpcd_power_state = DP_SET_POWER_D3;
+		status = core_link_write_dpcd(
+				link,
+				DP_SET_POWER,
+				&dpcd_power_state,
+				sizeof(dpcd_power_state));
+		return false;
+	}
+
 	is_lttpr_present = dp_retrieve_lttpr_cap(link);
 	/* Read DP tunneling information. */
 	status = dpcd_get_tunneling_device_data(link);
 
-	status = core_link_read_dpcd(link, DP_SET_POWER,
-			&dpcd_power_state, sizeof(dpcd_power_state));
-
-	/* Delay 1 ms if AUX CH is in power down state. Based on spec
-	 * section 2.3.1.2, if AUX CH may be powered down due to
-	 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
-	 * signal and may need up to 1 ms before being able to reply.
-	 */
-	if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
-		udelay(1000);
-
 	dpcd_set_source_specific_data(link);
 	/* Sink may need to configure internals based on vendor, so allow some
 	 * time before proceeding with possibly vendor specific transactions
-- 
2.25.1

[PATCH 05/33] drm/amd/display: Fix OTG H timing reset for dcn314

[brichang]

From: Duncan Ma <duncan.ma@amd.com>

[Why]
When ODM is enabled, H timing control register reset
to 0. Div mode manual field get overwritten causing
no display on certain modes for dcn314.

[How]
Use REG_UPDATE instead of REG_SET to set div_mode
field.

Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
index 0c7980266b85..38aa28ec6b13 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
@@ -98,7 +98,8 @@ static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id,
 	REG_UPDATE(OPTC_WIDTH_CONTROL,
 			OPTC_SEGMENT_WIDTH, mpcc_hactive);
 
-	REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
+	REG_UPDATE(OTG_H_TIMING_CNTL,
+			OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
 	optc1->opp_count = opp_cnt;
 }
 
-- 
2.25.1

[PATCH 06/33] drm/amd/display: add dcn35 basic support

[brichang]

From: Charlene Liu <Charlene.Liu@amd.com>

[why]
this is to add new dcn frame work

Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/Makefile.rej | 17 +++++++++++++++++
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h    |  9 ++++++---
 .../amd/display/dc/dcn10/dcn10_stream_encoder.h |  1 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h    |  3 ++-
 .../dc/dcn31/dcn31_hpo_dp_link_encoder.h        | 10 ++++++++--
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h     |  3 ++-
 drivers/gpu/drm/amd/display/include/dal_types.h |  1 +
 7 files changed, 37 insertions(+), 7 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej
new file mode 100644
index 000000000000..bfbfd67a7451
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej
@@ -0,0 +1,17 @@
+diff a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile	(rejected hunks)
+@@ -160,6 +160,15 @@ AMD_DAL_CLK_MGR_DCN32 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn32/,$(CLK_MGR_DC
+ 
+ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN32)
+ 
++
++###############################################################################
++# DCN35
++###############################################################################
++CLK_MGR_DCN35 = dcn35_smu.o dcn35_clk_mgr.o
++
++AMD_DAL_CLK_MGR_DCN35 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn35/,$(CLK_MGR_DCN35))
++
++AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN35)
+ ###############################################################################
+ # DCN3AG
+ ###############################################################################
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index e6c06325742a..a3c27cbb77c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -183,8 +183,7 @@
 	ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
 			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
 
-#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
-	ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
+#define ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh) \
 	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
 			ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
 	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
@@ -214,9 +213,13 @@
 	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
 			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
 
-#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
+#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
+	ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
+	ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh)
 
+#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
 #define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
+#define ABM_MASK_SH_LIST_DCN35(mask_sh) ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh)
 
 #define ABM_MASK_SH_LIST_DCN32(mask_sh) \
 	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 9d5e2a7848dd..3f9582b4cc79 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -188,6 +188,7 @@ struct dcn10_stream_enc_registers {
 	uint32_t HDMI_GENERIC_PACKET_CONTROL10;
 	uint32_t DIG_CLOCK_PATTERN;
 	uint32_t DIG_FIFO_CTRL0;
+	uint32_t DIG_FE_CLK_CNTL;
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
index 6263408d71fc..815169e08e5b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
@@ -172,7 +172,8 @@
 	SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM, id),\
 	SRI(CM_BLNDGAM_LUT_CONTROL, CM, id)
 
-
+#define DPP_REG_LIST_DCN35(id)\
+	DPP_REG_LIST_DCN30_COMMON(id)
 
 #define DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh)\
 	TF_SF(CM0_CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
index e324e9b83136..51f5781325e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
@@ -104,7 +104,10 @@ struct dcn31_hpo_dp_link_encoder_registers {
 	uint32_t RDPCSTX_PHY_CNTL6[5];
 };
 
-#define DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\
+#define DCN3_1_HPO_DP_LINK_ENC_RDPCSTX_MASK_SH_LIST(mask_sh)\
+	SE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
+
+#define DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(mask_sh)\
 	SE_SF(DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, mask_sh),\
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_RESET, mask_sh),\
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_ENABLE, mask_sh),\
@@ -126,11 +129,14 @@ struct dcn31_hpo_dp_link_encoder_registers {
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE, TP_SQ_PULSE_WIDTH, mask_sh),\
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_STREAM_SOURCE, mask_sh),\
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_SLOT_COUNT, mask_sh),\
-	SE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_X, mask_sh),\
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_Y, mask_sh),\
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE, SAT_UPDATE, mask_sh)
 
+#define DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\
+	DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(mask_sh),\
+	DCN3_1_HPO_DP_LINK_ENC_RDPCSTX_MASK_SH_LIST(mask_sh)\
+
 #define DCN3_1_HPO_DP_LINK_ENC_REG_FIELD_LIST(type) \
 	type DP_LINK_ENC_CLOCK_EN;\
 	type DPHY_RESET;\
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index ced176d17bae..840460ad0bf8 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -103,6 +103,7 @@ enum dmub_asic {
 	DMUB_ASIC_DCN316,
 	DMUB_ASIC_DCN32,
 	DMUB_ASIC_DCN321,
+
 	DMUB_ASIC_MAX,
 };
 
@@ -419,7 +420,7 @@ struct dmub_srv {
 	const struct dmub_srv_common_regs *regs;
 	const struct dmub_srv_dcn31_regs *regs_dcn31;
 	const struct dmub_srv_dcn32_regs *regs_dcn32;
-
+    const struct dmub_srv_dcn35_regs *regs_dcn35;
 	struct dmub_srv_base_funcs funcs;
 	struct dmub_srv_hw_funcs hw_funcs;
 	struct dmub_rb inbox1_rb;
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index d2427cf1155f..97084958d845 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -62,6 +62,7 @@ enum dce_version {
 	DCN_VERSION_3_16,
 	DCN_VERSION_3_2,
 	DCN_VERSION_3_21,
+
 	DCN_VERSION_MAX
 };
 
-- 
2.25.1

[PATCH 07/33] drm/amd/display: set dig fifo read start level to 7 before dig fifo reset

[brichang]

From: Wang Fudong <Fudong.Wang@amd.com>

[Why]
DIG_FIFO_ERROR = 1 caused mst daisy chain 2nd monitor black.

[How]
We need to set dig fifo read start level = 7 before dig fifo reset during dig
fifo enable according to hardware designer's suggestion. If it is zero, it will
cause underflow or overflow and DIG_FIFO_ERROR = 1.

Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Wang Fudong <Fudong.Wang@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c  | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
index 26648ce772da..38a48983f663 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c
@@ -310,6 +310,11 @@ static void enc32_stream_encoder_dp_unblank(
 	// TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON
 	REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000);
 
+	/* read start level = 0 will bring underflow / overflow and DIG_FIFO_ERROR = 1
+	 * so set it to 1/2 full = 7 before reset as suggested by hardware team.
+	 */
+	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);
+
 	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);
 
 	REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);
-- 
2.25.1

[PATCH 08/33] drm/amd/display: Remove assert from PHY state update

[brichang]

From: Taimur Hassan <Syed.Hassan@amd.com>

[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON. This is
expected, so do not assert. However, these are redundant, so return
prematurely.

Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 3b1c6603ae0c..b7556111ee44 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1224,10 +1224,8 @@ void dcn32_update_phy_state(struct dc_state *state, struct pipe_ctx *pipe_ctx,
 {
 	enum phy_state current_state = pipe_ctx->stream->link->phy_state;
 
-	if (current_state == target_state) {
-		BREAK_TO_DEBUGGER();
+	if (current_state == target_state)
 		return;
-	}
 
 	if (target_state == TX_OFF_SYMCLK_OFF) {
 		core_link_disable_stream(pipe_ctx);
-- 
2.25.1

[PATCH 09/33] drm/amd/display: Only commit SubVP state after pipe programming

[brichang]

From: Alvin Lee <Alvin.Lee2@amd.com>

[Description]
We only want to commit the SubVP config to DMCUB
after the main and phantom pipe programming has
completed. Commiting the state early can cause
issues such as P-State being allowed by the HW
early which causes the SubVP state machine to
go into a bad state

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ced09f875e58..95daee11a445 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3333,10 +3333,6 @@ static void commit_planes_for_stream(struct dc *dc,
 		if (dc->hwss.program_front_end_for_ctx)
 			dc->hwss.program_front_end_for_ctx(dc, context);
 
-		if (update_type != UPDATE_TYPE_FAST)
-			if (dc->hwss.commit_subvp_config)
-				dc->hwss.commit_subvp_config(dc, context);
-
 		if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
 			dc->hwss.interdependent_update_lock(dc, context, false);
 		} else {
@@ -3344,6 +3340,10 @@ static void commit_planes_for_stream(struct dc *dc,
 		}
 		dc->hwss.post_unlock_program_front_end(dc, context);
 
+		if (update_type != UPDATE_TYPE_FAST)
+			if (dc->hwss.commit_subvp_config)
+				dc->hwss.commit_subvp_config(dc, context);
+
 		/* Since phantom pipe programming is moved to post_unlock_program_front_end,
 		 * move the SubVP lock to after the phantom pipes have been setup
 		 */
@@ -3477,10 +3477,6 @@ static void commit_planes_for_stream(struct dc *dc,
 
 	}
 
-	if (update_type != UPDATE_TYPE_FAST)
-		if (dc->hwss.commit_subvp_config)
-			dc->hwss.commit_subvp_config(dc, context);
-
 	if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
 		dc->hwss.interdependent_update_lock(dc, context, false);
 	} else {
@@ -3517,6 +3513,9 @@ static void commit_planes_for_stream(struct dc *dc,
 
 	if (update_type != UPDATE_TYPE_FAST)
 		dc->hwss.post_unlock_program_front_end(dc, context);
+		if (update_type != UPDATE_TYPE_FAST)
+			if (dc->hwss.commit_subvp_config)
+				dc->hwss.commit_subvp_config(dc, context);
 
 	/* Since phantom pipe programming is moved to post_unlock_program_front_end,
 	 * move the SubVP lock to after the phantom pipes have been setup
-- 
2.25.1

[PATCH 10/33] drm/amd/display: add a override flag as wa for some specific dongle

[brichang]

From: "Chen, Leo" <SanChuan.Chen@amd.com>

[Why & How]
Add a override flag as wa for some specific dongle

Co-authored-by: Leo Chen <sancchen@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Leo Chen <sancchen@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index b18efe988830..d1214944839f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -224,6 +224,7 @@ struct dc_link {
 		bool dpia_mst_dsc_always_on;
 		/* Forced DPIA into TBT3 compatibility mode. */
 		bool dpia_forced_tbt3_mode;
+		bool dongle_mode_timing_override;
 	} wa_flags;
 	struct link_mst_stream_allocation_table mst_stream_alloc_table;
 
-- 
2.25.1

[PATCH 11/33] drm/amd/display: Add DC debug option to force LTTPR mode

[brichang]

From: Michael Strauss <michael.strauss@amd.com>

[WHY]
Useful for external teams debugging LTTPR issues

Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++++
 drivers/gpu/drm/amd/display/dc/dc.h              | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 8617de559174..7e97265b76e8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5032,6 +5032,10 @@ static void determine_lttpr_mode(struct dc_link *link)
 	bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable;
 	bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
 
+	if (link->ctx->dc->debug.lttpr_mode_override != 0) {
+		link->lttpr_mode = link->ctx->dc->debug.lttpr_mode_override;
+		return;
+	}
 
 	if ((link->dc->config.allow_lttpr_non_transparent_mode.bits.DP2_0 &&
 			link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)) {
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 2362d5ee2401..473e6a0c3310 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -846,6 +846,7 @@ struct dc_debug_options {
 	bool exit_idle_opt_for_cursor_updates;
 	bool enable_single_display_2to1_odm_policy;
 	bool enable_dp_dig_pixel_rate_div_policy;
+	enum lttpr_mode lttpr_mode_override;
 };
 
 struct gpu_info_soc_bounding_box_v1_0;
-- 
2.25.1

[PATCH 06/33] drm/amd/display: add dcn35 basic support

[brichang]

From: Charlene Liu <Charlene.Liu@amd.com>

[why]
this is to add new dcn frame work

Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/Makefile.rej | 17 +++++++++++++++++
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h    |  9 ++++++---
 .../amd/display/dc/dcn10/dcn10_stream_encoder.h |  1 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h    |  3 ++-
 .../dc/dcn31/dcn31_hpo_dp_link_encoder.h        | 10 ++++++++--
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h     |  3 ++-
 drivers/gpu/drm/amd/display/include/dal_types.h |  1 +
 7 files changed, 37 insertions(+), 7 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej
new file mode 100644
index 000000000000..bfbfd67a7451
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej
@@ -0,0 +1,17 @@
+diff a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile	(rejected hunks)
+@@ -160,6 +160,15 @@ AMD_DAL_CLK_MGR_DCN32 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn32/,$(CLK_MGR_DC
+ 
+ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN32)
+ 
++
++###############################################################################
++# DCN35
++###############################################################################
++CLK_MGR_DCN35 = dcn35_smu.o dcn35_clk_mgr.o
++
++AMD_DAL_CLK_MGR_DCN35 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn35/,$(CLK_MGR_DCN35))
++
++AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN35)
+ ###############################################################################
+ # DCN3AG
+ ###############################################################################
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index e6c06325742a..a3c27cbb77c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -183,8 +183,7 @@
 	ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
 			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
 
-#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
-	ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
+#define ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh) \
 	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
 			ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
 	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
@@ -214,9 +213,13 @@
 	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
 			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
 
-#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
+#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
+	ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
+	ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh)
 
+#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
 #define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
+#define ABM_MASK_SH_LIST_DCN35(mask_sh) ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh)
 
 #define ABM_MASK_SH_LIST_DCN32(mask_sh) \
 	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 9d5e2a7848dd..3f9582b4cc79 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -188,6 +188,7 @@ struct dcn10_stream_enc_registers {
 	uint32_t HDMI_GENERIC_PACKET_CONTROL10;
 	uint32_t DIG_CLOCK_PATTERN;
 	uint32_t DIG_FIFO_CTRL0;
+	uint32_t DIG_FE_CLK_CNTL;
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
index 6263408d71fc..815169e08e5b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
@@ -172,7 +172,8 @@
 	SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM, id),\
 	SRI(CM_BLNDGAM_LUT_CONTROL, CM, id)
 
-
+#define DPP_REG_LIST_DCN35(id)\
+	DPP_REG_LIST_DCN30_COMMON(id)
 
 #define DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh)\
 	TF_SF(CM0_CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
index e324e9b83136..51f5781325e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
@@ -104,7 +104,10 @@ struct dcn31_hpo_dp_link_encoder_registers {
 	uint32_t RDPCSTX_PHY_CNTL6[5];
 };
 
-#define DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\
+#define DCN3_1_HPO_DP_LINK_ENC_RDPCSTX_MASK_SH_LIST(mask_sh)\
+	SE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
+
+#define DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(mask_sh)\
 	SE_SF(DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, mask_sh),\
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_RESET, mask_sh),\
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_ENABLE, mask_sh),\
@@ -126,11 +129,14 @@ struct dcn31_hpo_dp_link_encoder_registers {
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE, TP_SQ_PULSE_WIDTH, mask_sh),\
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_STREAM_SOURCE, mask_sh),\
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_SLOT_COUNT, mask_sh),\
-	SE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_X, mask_sh),\
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_Y, mask_sh),\
 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE, SAT_UPDATE, mask_sh)
 
+#define DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\
+	DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(mask_sh),\
+	DCN3_1_HPO_DP_LINK_ENC_RDPCSTX_MASK_SH_LIST(mask_sh)\
+
 #define DCN3_1_HPO_DP_LINK_ENC_REG_FIELD_LIST(type) \
 	type DP_LINK_ENC_CLOCK_EN;\
 	type DPHY_RESET;\
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index ced176d17bae..840460ad0bf8 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -103,6 +103,7 @@ enum dmub_asic {
 	DMUB_ASIC_DCN316,
 	DMUB_ASIC_DCN32,
 	DMUB_ASIC_DCN321,
+
 	DMUB_ASIC_MAX,
 };
 
@@ -419,7 +420,7 @@ struct dmub_srv {
 	const struct dmub_srv_common_regs *regs;
 	const struct dmub_srv_dcn31_regs *regs_dcn31;
 	const struct dmub_srv_dcn32_regs *regs_dcn32;
-
+    const struct dmub_srv_dcn35_regs *regs_dcn35;
 	struct dmub_srv_base_funcs funcs;
 	struct dmub_srv_hw_funcs hw_funcs;
 	struct dmub_rb inbox1_rb;
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index d2427cf1155f..97084958d845 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -62,6 +62,7 @@ enum dce_version {
 	DCN_VERSION_3_16,
 	DCN_VERSION_3_2,
 	DCN_VERSION_3_21,
+
 	DCN_VERSION_MAX
 };
 
-- 
2.25.1

RE: [PATCH 00/33] DC Patches August 27 ,2022

[Wheeler, Daniel]

[Public]

Hi all,
 
This week this patchset was tested on the following systems:
 
Sapphire Pulse RX5700XT 
Reference AMD RX6800
Engineering board with Ryzen 9 5900H
 
These systems were tested on the following display types: 
eDP, (1080p 60hz)
VGA and DVI (1680x1050 60HZ [DP to VGA/DVI, USB-C to DVI/VGA])
DP/HDMI/USB-C (1440p 170hz, 4k 60hz, 4k 144hz [Includes USB-C to DP/HDMI adapters])
 
MST tested with Startech MST14DP123DP and 2x 4k 60Hz displays
DSC tested with Cable Matters 101075 (DP to 3x DP), and 201375 (USB-C to 3x DP) with 3x 4k60 displays
 
The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to):
Changing display configurations and settings
Benchmark testing
Feature testing (Freesync, etc.)
 
Automated testing includes (but is not limited to):
Script testing (scripts to automate some of the manual checks)
IGT testing
 
The patchset consists of the amd-staging-drm-next branch (Head commit - afa4f339ec6175bdd2e9d12d771aef3cfedb5960) with new patches added on top of it. This branch is used for both Ubuntu and Chrome OS testing (ChromeOS on a bi-weekly basis).

 
Tested on Ubuntu 22.04
 
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
 
 
Thank you,
 
Dan Wheeler
Sr. Technologist | AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
amd.com

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of brichang
Sent: August 26, 2022 6:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>; Chang, Brian <Brian.Chang@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Li, Roman <Roman.Li@amd.com>; Chiu, Solomon <Solomon.Chiu@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>
Subject: [PATCH 00/33] DC Patches August 27 ,2022

This DC patchset brings improvements in multiple areas. In summary, we have:

* Correct cursor position on horizontal mirror;
* Fix black flash when switching from ODM2to1 to ODMBypass;
* Fix plane and stream check;
* Fix viewport after pipe merge;
* Correct plane for CAB cursor;
* Fix comment to correct visual confirm option;
* Fix SubVP related regression;
* Fix primary EDP link detection;
* Fix wrong register access;
* Fix cursor size allocation for DCN32/321;
* Fix display fresh edge case from MALL for DCN321;
* Add HPO instance;
* Refactor EDP codes;
* Add SubVP scaling case;
* Add support for visual confirm color;
* Fix PHY state update;
* Cleanup PSR flag;
* Fix cursor lag with PSR1 eDP;
* Add DC debug optioon for LTTPR mode;
* Add override flag for some dongle;
* Fix SubVP state after pipe programming;
* Remove assert from PHY state update;
* Fix dig fifo read level before reset;
* Add dcn35 basic suppoet;
* Fix OTG H timming for dcn314;
* Fix aux transaction;
* Fix DCN32 DPSTREAMCLK_CNTL programming;
* Fix SubVP scheduling issues;
* Set ODM policy.


Alvin Lee (3):
  drm/amd/display: Don't choose SubVP display if ActiveMargin > 0
  drm/amd/display: Only commit SubVP state after pipe programming
  drm/amd/display: SubVP missing scaling case

Anthony Koo (1):
  drm/amd/display: [FW Promotion] Release 0.0.132.0

Aric Cyr (1):
  drm/amd/display: 3.2.201

Aurabindo Pillai (5):
  drm/amd/display: Fix CAB cursor size allocation for DCN32/321
  drm/amd/display: disable display fresh from MALL on an edge case for
    DCN321
  drm/amd/display: use actual cursor size instead of max for CAB
    allocation
  drm/amd/display: Revert "program k1/k2 divider for virtual signal for
    DCN32"
  drm/amd/display: Use correct plane for CAB cursor size allocation

Charlene Liu (2):
  drm/amd/display: add dcn35 basic support
  drm/amd/display: fix wrong register access

Chen, Leo (1):
  drm/amd/display: add a override flag as wa for some specific dongle

Duncan Ma (1):
  drm/amd/display: Fix OTG H timing reset for dcn314

Ethan Wellenreiter (2):
  drm/amd/display: Re-initialize viewport after pipe merge
  drm/amd/display: Fix check for stream and plane

Gabe Teeger (2):
  drm/amd/display: Cursor lag with PSR1 eDP
  drm/amd/display: Cleanup PSR flag

George Shen (1):
  drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming

Ian Chen (2):
  drm/amd/display: Refactor edp dsc codes.
  drm/amd/display: Add comments.

Iswara Nagulendran (1):
  drm/amd/display: Fix primary EDP link detection

Leo (Hanghong) Ma (2):
  drm/amd/display: Add visual confirm color support for SubVP
  drm/amd/display: Add support for visual confirm color

Leo Chen (1):
  drm/amd/display: Missing HPO instance added

Lewis Huang (1):
  drm/amd/display: Refine aux transaction before retrieve caps

Martin Tsai (1):
  drm/amd/display: Correct cursor position on horizontal mirror

Michael Strauss (1):
  drm/amd/display: Add DC debug option to force LTTPR mode

Taimur Hassan (3):
  drm/amd/display: Set ODM policy based on number of DSC slices
  drm/amd/display: Remove assert from PHY state update
  drm/amd/display: Allow PHY state update between same states

Vladimir Stempen (1):
  drm/amd/display: Fix black flash when switching from ODM2to1 to
    ODMBypass

Wang Fudong (1):
  drm/amd/display: set dig fifo read start level to 7 before dig fifo
    reset

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  4 +-  .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 +++++
 .../drm/amd/display/dc/clk_mgr/Makefile.rej   | 17 ++++
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 26 +++---
 .../drm/amd/display/dc/core/dc_hw_sequencer.c | 38 +++++++++  drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 ++---  .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 53 +++++++++---
 drivers/gpu/drm/amd/display/dc/dc.h           |  8 +-
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  | 41 ++++++++-  drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h  |  1 +
 drivers/gpu/drm/amd/display/dc/dc_link.h      | 12 +++
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h  |  9 +-
 .../display/dc/dce110/dce110_hw_sequencer.c   | 13 +++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c  |  5 +-  .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |  9 +-  .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 83 +++++++++++++------
 .../display/dc/dcn10/dcn10_stream_encoder.h   |  1 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c |  9 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  6 +-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h  |  3 +-  .../display/dc/dcn31/dcn31_dio_link_encoder.c |  3 +
 .../dc/dcn31/dcn31_hpo_dp_link_encoder.h      | 10 ++-
 .../drm/amd/display/dc/dcn31/dcn31_resource.c |  1 -
 .../dc/dcn314/dcn314_dio_stream_encoder.c     |  1 +
 .../drm/amd/display/dc/dcn314/dcn314_optc.c   |  3 +-
 .../amd/display/dc/dcn314/dcn314_resource.c   |  2 +-
 .../amd/display/dc/dcn315/dcn315_resource.c   |  1 -
 .../amd/display/dc/dcn316/dcn316_resource.c   |  1 -
 .../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c |  8 +-
 .../dc/dcn32/dcn32_dio_stream_encoder.c       |  5 ++
 .../drm/amd/display/dc/dcn32/dcn32_hwseq.c    | 75 ++++++++++++-----
 .../display/dc/dcn32/dcn32_resource_helpers.c |  2 +-
 drivers/gpu/drm/amd/display/dc/dm_helpers.h   |  7 +-
 .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c  | 36 +++++++-
 .../dc/dml/dcn32/display_mode_vba_32.c        |  4 +-
 .../dc/dml/dcn32/display_mode_vba_util_32.c   |  7 +-
 .../dc/dml/dcn32/display_mode_vba_util_32.h   |  1 +
 .../drm/amd/display/dc/dml/display_mode_vba.h |  1 +  .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  5 ++
 .../amd/display/dc/link/link_hwss_hpo_dp.c    |  4 +-
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h   |  4 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 47 ++++++++++-
 .../gpu/drm/amd/display/include/dal_types.h   |  1 +
 43 files changed, 469 insertions(+), 139 deletions(-)  create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej

--
2.25.1