From: brichang <Brian.Chang@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Charlene Liu <Charlene.Liu@amd.com>,
Hansen Dsouza <hansen.dsouza@amd.com>,
Brian Chang <Brian.Chang@amd.com>,
Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com,
wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com,
agustin.gutierrez@amd.com, pavle.kotarac@amd.com
Subject: [PATCH 06/33] drm/amd/display: add dcn35 basic support
Date: Sat, 27 Aug 2022 06:50:26 +0800 [thread overview]
Message-ID: <20220826225053.1435588-7-Brian.Chang@amd.com> (raw)
In-Reply-To: <20220826225053.1435588-1-Brian.Chang@amd.com>
From: Charlene Liu <Charlene.Liu@amd.com>
[why]
this is to add new dcn frame work
Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile.rej | 17 +++++++++++++++++
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 9 ++++++---
.../amd/display/dc/dcn10/dcn10_stream_encoder.h | 1 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h | 3 ++-
.../dc/dcn31/dcn31_hpo_dp_link_encoder.h | 10 ++++++++--
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 3 ++-
drivers/gpu/drm/amd/display/include/dal_types.h | 1 +
7 files changed, 37 insertions(+), 7 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej
new file mode 100644
index 000000000000..bfbfd67a7451
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej
@@ -0,0 +1,17 @@
+diff a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile (rejected hunks)
+@@ -160,6 +160,15 @@ AMD_DAL_CLK_MGR_DCN32 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn32/,$(CLK_MGR_DC
+
+ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN32)
+
++
++###############################################################################
++# DCN35
++###############################################################################
++CLK_MGR_DCN35 = dcn35_smu.o dcn35_clk_mgr.o
++
++AMD_DAL_CLK_MGR_DCN35 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn35/,$(CLK_MGR_DCN35))
++
++AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN35)
+ ###############################################################################
+ # DCN3AG
+ ###############################################################################
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index e6c06325742a..a3c27cbb77c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -183,8 +183,7 @@
ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
-#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
- ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
+#define ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh) \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
@@ -214,9 +213,13 @@
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
-#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
+#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
+ ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
+ ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh)
+#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
#define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
+#define ABM_MASK_SH_LIST_DCN35(mask_sh) ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh)
#define ABM_MASK_SH_LIST_DCN32(mask_sh) \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 9d5e2a7848dd..3f9582b4cc79 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -188,6 +188,7 @@ struct dcn10_stream_enc_registers {
uint32_t HDMI_GENERIC_PACKET_CONTROL10;
uint32_t DIG_CLOCK_PATTERN;
uint32_t DIG_FIFO_CTRL0;
+ uint32_t DIG_FE_CLK_CNTL;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
index 6263408d71fc..815169e08e5b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
@@ -172,7 +172,8 @@
SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM, id),\
SRI(CM_BLNDGAM_LUT_CONTROL, CM, id)
-
+#define DPP_REG_LIST_DCN35(id)\
+ DPP_REG_LIST_DCN30_COMMON(id)
#define DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh)\
TF_SF(CM0_CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
index e324e9b83136..51f5781325e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
@@ -104,7 +104,10 @@ struct dcn31_hpo_dp_link_encoder_registers {
uint32_t RDPCSTX_PHY_CNTL6[5];
};
-#define DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\
+#define DCN3_1_HPO_DP_LINK_ENC_RDPCSTX_MASK_SH_LIST(mask_sh)\
+ SE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
+
+#define DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(mask_sh)\
SE_SF(DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, mask_sh),\
SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_RESET, mask_sh),\
SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_ENABLE, mask_sh),\
@@ -126,11 +129,14 @@ struct dcn31_hpo_dp_link_encoder_registers {
SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE, TP_SQ_PULSE_WIDTH, mask_sh),\
SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_STREAM_SOURCE, mask_sh),\
SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_SLOT_COUNT, mask_sh),\
- SE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_X, mask_sh),\
SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_Y, mask_sh),\
SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE, SAT_UPDATE, mask_sh)
+#define DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\
+ DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(mask_sh),\
+ DCN3_1_HPO_DP_LINK_ENC_RDPCSTX_MASK_SH_LIST(mask_sh)\
+
#define DCN3_1_HPO_DP_LINK_ENC_REG_FIELD_LIST(type) \
type DP_LINK_ENC_CLOCK_EN;\
type DPHY_RESET;\
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index ced176d17bae..840460ad0bf8 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -103,6 +103,7 @@ enum dmub_asic {
DMUB_ASIC_DCN316,
DMUB_ASIC_DCN32,
DMUB_ASIC_DCN321,
+
DMUB_ASIC_MAX,
};
@@ -419,7 +420,7 @@ struct dmub_srv {
const struct dmub_srv_common_regs *regs;
const struct dmub_srv_dcn31_regs *regs_dcn31;
const struct dmub_srv_dcn32_regs *regs_dcn32;
-
+ const struct dmub_srv_dcn35_regs *regs_dcn35;
struct dmub_srv_base_funcs funcs;
struct dmub_srv_hw_funcs hw_funcs;
struct dmub_rb inbox1_rb;
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index d2427cf1155f..97084958d845 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -62,6 +62,7 @@ enum dce_version {
DCN_VERSION_3_16,
DCN_VERSION_3_2,
DCN_VERSION_3_21,
+
DCN_VERSION_MAX
};
--
2.25.1
next prev parent reply other threads:[~2022-08-27 2:51 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-26 22:50 [PATCH 00/33] DC Patches August 27 ,2022 brichang
2022-08-26 22:50 ` [PATCH 01/33] drm/amd/display: Set ODM policy based on number of DSC slices brichang
2022-08-26 22:50 ` [PATCH 02/33] drm/amd/display: Don't choose SubVP display if ActiveMargin > 0 brichang
2022-08-26 22:50 ` [PATCH 03/33] drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming brichang
2022-08-26 22:50 ` [PATCH 04/33] drm/amd/display: Refine aux transaction before retrieve caps brichang
2022-08-26 22:50 ` [PATCH 05/33] drm/amd/display: Fix OTG H timing reset for dcn314 brichang
2022-08-26 22:50 ` brichang [this message]
2022-08-26 22:50 ` [PATCH 07/33] drm/amd/display: set dig fifo read start level to 7 before dig fifo reset brichang
2022-08-26 22:50 ` [PATCH 08/33] drm/amd/display: Remove assert from PHY state update brichang
2022-08-26 22:50 ` [PATCH 09/33] drm/amd/display: Only commit SubVP state after pipe programming brichang
2022-08-26 22:50 ` [PATCH 10/33] drm/amd/display: add a override flag as wa for some specific dongle brichang
2022-08-26 22:50 ` [PATCH 11/33] drm/amd/display: Add DC debug option to force LTTPR mode brichang
2022-08-26 22:50 ` [PATCH 12/33] drm/amd/display: Cursor lag with PSR1 eDP brichang
2022-08-26 22:50 ` [PATCH 13/33] drm/amd/display: Cleanup PSR flag brichang
2022-08-26 22:50 ` [PATCH 14/33] drm/amd/display: Allow PHY state update between same states brichang
2022-08-26 22:50 ` [PATCH 15/33] drm/amd/display: Add visual confirm color support for SubVP brichang
2022-08-26 22:50 ` [PATCH 16/33] drm/amd/display: Add support for visual confirm color brichang
2022-08-26 22:50 ` [PATCH 17/33] drm/amd/display: SubVP missing scaling case brichang
2022-08-26 22:50 ` [PATCH 18/33] drm/amd/display: Refactor edp dsc codes brichang
2022-08-26 22:50 ` [PATCH 19/33] drm/amd/display: Missing HPO instance added brichang
2022-08-26 22:50 ` [PATCH 20/33] drm/amd/display: Fix CAB cursor size allocation for DCN32/321 brichang
2022-08-26 22:50 ` [PATCH 21/33] drm/amd/display: disable display fresh from MALL on an edge case for DCN321 brichang
2022-08-26 22:50 ` [PATCH 22/33] drm/amd/display: use actual cursor size instead of max for CAB allocation brichang
2022-08-26 22:50 ` [PATCH 23/33] drm/amd/display: fix wrong register access brichang
2022-08-26 22:50 ` [PATCH 24/33] drm/amd/display: Fix primary EDP link detection brichang
2022-08-26 22:50 ` [PATCH 25/33] drm/amd/display: Revert "program k1/k2 divider for virtual signal for DCN32" brichang
2022-08-26 22:50 ` [PATCH 26/33] drm/amd/display: Add comments brichang
2022-08-26 22:50 ` [PATCH 27/33] drm/amd/display: [FW Promotion] Release 0.0.132.0 brichang
2022-08-26 22:50 ` [PATCH 28/33] drm/amd/display: 3.2.201 brichang
2022-08-26 22:50 ` [PATCH 29/33] drm/amd/display: Use correct plane for CAB cursor size allocation brichang
2022-08-26 22:50 ` [PATCH 30/33] drm/amd/display: Re-initialize viewport after pipe merge brichang
2022-08-26 22:50 ` [PATCH 31/33] drm/amd/display: Fix check for stream and plane brichang
2022-08-26 22:50 ` [PATCH 32/33] drm/amd/display: Fix black flash when switching from ODM2to1 to ODMBypass brichang
2022-08-26 22:50 ` [PATCH 33/33] drm/amd/display: Correct cursor position on horizontal mirror brichang
-- strict thread matches above, loose matches on Subject: below --
2022-08-26 22:26 [PATCH 00/33] DC Patches August 27 ,2022 brichang
2022-08-26 22:26 ` [PATCH 06/33] drm/amd/display: add dcn35 basic support brichang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220826225053.1435588-7-Brian.Chang@amd.com \
--to=brian.chang@amd.com \
--cc=Aurabindo.Pillai@amd.com \
--cc=Bhawanpreet.Lakha@amd.com \
--cc=Charlene.Liu@amd.com \
--cc=Harry.Wentland@amd.com \
--cc=Rodrigo.Siqueira@amd.com \
--cc=Sunpeng.Li@amd.com \
--cc=agustin.gutierrez@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=hansen.dsouza@amd.com \
--cc=pavle.kotarac@amd.com \
--cc=qingqing.zhuo@amd.com \
--cc=roman.li@amd.com \
--cc=solomon.chiu@amd.com \
--cc=stylon.wang@amd.com \
--cc=wayne.lin@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox