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From: brichang <Brian.Chang@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Brian Chang <Brian.Chang@amd.com>,
	Anthony Koo <Anthony.Koo@amd.com>,
	Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com, Gabe Teeger <gabe.teeger@amd.com>,
	solomon.chiu@amd.com, Aurabindo.Pillai@amd.com,
	wayne.lin@amd.com, Robin Chen <robin.chen@amd.com>,
	Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com,
	pavle.kotarac@amd.com
Subject: [PATCH 13/33] drm/amd/display: Cleanup PSR flag
Date: Sat, 27 Aug 2022 06:50:33 +0800	[thread overview]
Message-ID: <20220826225053.1435588-14-Brian.Chang@amd.com> (raw)
In-Reply-To: <20220826225053.1435588-1-Brian.Chang@amd.com>

From: Gabe Teeger <gabe.teeger@amd.com>

[Why]
enable_sw_cntl_psr flag is not needed.
For PSR1 and PSR2, we should be passing
dirty rectangle and cursor updates to FW
regardless of enable_sw_cntl_psr flag.

[How]
Remove enable_sw_cntl_psr flag from driver.
Send cursor info and dirty rectagle status to
dmub only in the case of dcn31 and above.

Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Robin Chen <robin.chen@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c                  | 8 +++-----
 drivers/gpu/drm/amd/display/dc/dc.h                       | 1 -
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++-
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c     | 1 -
 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c   | 1 -
 drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c   | 1 -
 drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c   | 1 -
 7 files changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 95daee11a445..1ca76708705b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3113,11 +3113,9 @@ static void commit_planes_do_stream_update(struct dc *dc,
 
 static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream)
 {
-	if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
-		return true;
-
-	if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1 &&
-	    dc->debug.enable_sw_cntl_psr)
+	if ((stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1
+			|| stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
+			&& stream->ctx->dce_version >= DCN_VERSION_3_1)
 		return true;
 
 	return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 473e6a0c3310..cffb91363b52 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -827,7 +827,6 @@ struct dc_debug_options {
 	int crb_alloc_policy_min_disp_count;
 	bool disable_z10;
 	bool enable_z9_disable_interface;
-	bool enable_sw_cntl_psr;
 	union dpia_debug_options dpia_debug;
 	bool disable_fixed_vs_aux_timeout_wa;
 	bool force_disable_subvp;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 1eb3957f52a3..2118ad3e37d0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3343,7 +3343,8 @@ static bool dcn10_dmub_should_update_cursor_data(
 	if (dcn10_can_pipe_disable_cursor(pipe_ctx))
 		return false;
 
-	if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 || pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
+	if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 || pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
+			&& pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1)
 		return true;
 
 	return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index aedff18aff56..8745132d6374 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -889,7 +889,6 @@ static const struct dc_debug_options debug_defaults_drv = {
 	},
 	.disable_z10 = true,
 	.optimize_edp_link_rate = true,
-	.enable_sw_cntl_psr = true,
 	.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
 	.dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 3a9e3870b3a9..5e62527d3ab9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -911,7 +911,6 @@ static const struct dc_debug_options debug_defaults_drv = {
 		}
 	},
 	.optimize_edp_link_rate = true,
-	.enable_sw_cntl_psr = true,
 	.seamless_boot_odm_combine = true
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index 7463b12ae4a3..eebb42c9ddd6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -886,7 +886,6 @@ static const struct dc_debug_options debug_defaults_drv = {
 		}
 	},
 	.optimize_edp_link_rate = true,
-	.enable_sw_cntl_psr = true,
 	.psr_power_use_phy_fsm = 0,
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
index d56a212e065c..f4b52a35ad84 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
@@ -886,7 +886,6 @@ static const struct dc_debug_options debug_defaults_drv = {
 		}
 	},
 	.optimize_edp_link_rate = true,
-	.enable_sw_cntl_psr = true,
 };
 
 static const struct dc_debug_options debug_defaults_diags = {
-- 
2.25.1


  parent reply	other threads:[~2022-08-27  2:51 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-26 22:50 [PATCH 00/33] DC Patches August 27 ,2022 brichang
2022-08-26 22:50 ` [PATCH 01/33] drm/amd/display: Set ODM policy based on number of DSC slices brichang
2022-08-26 22:50 ` [PATCH 02/33] drm/amd/display: Don't choose SubVP display if ActiveMargin > 0 brichang
2022-08-26 22:50 ` [PATCH 03/33] drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming brichang
2022-08-26 22:50 ` [PATCH 04/33] drm/amd/display: Refine aux transaction before retrieve caps brichang
2022-08-26 22:50 ` [PATCH 05/33] drm/amd/display: Fix OTG H timing reset for dcn314 brichang
2022-08-26 22:50 ` [PATCH 06/33] drm/amd/display: add dcn35 basic support brichang
2022-08-26 22:50 ` [PATCH 07/33] drm/amd/display: set dig fifo read start level to 7 before dig fifo reset brichang
2022-08-26 22:50 ` [PATCH 08/33] drm/amd/display: Remove assert from PHY state update brichang
2022-08-26 22:50 ` [PATCH 09/33] drm/amd/display: Only commit SubVP state after pipe programming brichang
2022-08-26 22:50 ` [PATCH 10/33] drm/amd/display: add a override flag as wa for some specific dongle brichang
2022-08-26 22:50 ` [PATCH 11/33] drm/amd/display: Add DC debug option to force LTTPR mode brichang
2022-08-26 22:50 ` [PATCH 12/33] drm/amd/display: Cursor lag with PSR1 eDP brichang
2022-08-26 22:50 ` brichang [this message]
2022-08-26 22:50 ` [PATCH 14/33] drm/amd/display: Allow PHY state update between same states brichang
2022-08-26 22:50 ` [PATCH 15/33] drm/amd/display: Add visual confirm color support for SubVP brichang
2022-08-26 22:50 ` [PATCH 16/33] drm/amd/display: Add support for visual confirm color brichang
2022-08-26 22:50 ` [PATCH 17/33] drm/amd/display: SubVP missing scaling case brichang
2022-08-26 22:50 ` [PATCH 18/33] drm/amd/display: Refactor edp dsc codes brichang
2022-08-26 22:50 ` [PATCH 19/33] drm/amd/display: Missing HPO instance added brichang
2022-08-26 22:50 ` [PATCH 20/33] drm/amd/display: Fix CAB cursor size allocation for DCN32/321 brichang
2022-08-26 22:50 ` [PATCH 21/33] drm/amd/display: disable display fresh from MALL on an edge case for DCN321 brichang
2022-08-26 22:50 ` [PATCH 22/33] drm/amd/display: use actual cursor size instead of max for CAB allocation brichang
2022-08-26 22:50 ` [PATCH 23/33] drm/amd/display: fix wrong register access brichang
2022-08-26 22:50 ` [PATCH 24/33] drm/amd/display: Fix primary EDP link detection brichang
2022-08-26 22:50 ` [PATCH 25/33] drm/amd/display: Revert "program k1/k2 divider for virtual signal for DCN32" brichang
2022-08-26 22:50 ` [PATCH 26/33] drm/amd/display: Add comments brichang
2022-08-26 22:50 ` [PATCH 27/33] drm/amd/display: [FW Promotion] Release 0.0.132.0 brichang
2022-08-26 22:50 ` [PATCH 28/33] drm/amd/display: 3.2.201 brichang
2022-08-26 22:50 ` [PATCH 29/33] drm/amd/display: Use correct plane for CAB cursor size allocation brichang
2022-08-26 22:50 ` [PATCH 30/33] drm/amd/display: Re-initialize viewport after pipe merge brichang
2022-08-26 22:50 ` [PATCH 31/33] drm/amd/display: Fix check for stream and plane brichang
2022-08-26 22:50 ` [PATCH 32/33] drm/amd/display: Fix black flash when switching from ODM2to1 to ODMBypass brichang
2022-08-26 22:50 ` [PATCH 33/33] drm/amd/display: Correct cursor position on horizontal mirror brichang

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