From: brichang <Brian.Chang@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Ian Chen <ian.chen@amd.com>,
Mike Hsieh <mike.hsieh@amd.com>,
Brian Chang <Brian.Chang@amd.com>,
Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com,
wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com,
agustin.gutierrez@amd.com, pavle.kotarac@amd.com
Subject: [PATCH 18/33] drm/amd/display: Refactor edp dsc codes.
Date: Sat, 27 Aug 2022 06:50:38 +0800 [thread overview]
Message-ID: <20220826225053.1435588-19-Brian.Chang@amd.com> (raw)
In-Reply-To: <20220826225053.1435588-1-Brian.Chang@amd.com>
From: Ian Chen <ian.chen@amd.com>
Refactor edp dsc codes.
We split out edp dsc config from "global" to "per-panel" config settings.
Reviewed-by: Mike Hsieh <mike.hsieh@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 +++++++++++++++++++
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 10 +++++++++-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dc.h | 2 --
drivers/gpu/drm/amd/display/dc/dc_link.h | 10 ++++++++++
drivers/gpu/drm/amd/display/dc/dm_helpers.h | 7 ++++++-
7 files changed, 48 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 35b0d6a28726..62378f8694c0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1527,7 +1527,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
adev->dm.dc->debug.disable_dsc = true;
- adev->dm.dc->debug.disable_dsc_edp = true;
}
if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
@@ -5627,7 +5626,8 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
dc_dsc_policy_set_enable_dsc_when_not_needed(
aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
- if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && !dc->debug.disable_dsc_edp &&
+ if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
+ !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index bd364d2cc4f7..0b7440b92c10 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -916,6 +916,25 @@ void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigne
//amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
}
+void dm_helpers_init_panel_settings(
+ struct dc_context *ctx,
+ struct dc_panel_config *panel_config)
+{
+ // Feature DSC
+ panel_config->dsc.disable_dsc_edp = false;
+ panel_config->dsc.force_dsc_edp_policy = 0;
+}
+
+void dm_helpers_override_panel_settings(
+ struct dc_context *ctx,
+ struct dc_panel_config *panel_config)
+{
+ // Feature DSC
+ if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
+ panel_config->dsc.disable_dsc_edp = true;
+ }
+}
+
void *dm_helpers_allocate_gpu_mem(
struct dc_context *ctx,
enum dc_gpu_mem_alloc_type type,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 66d2ae7aacf5..74db87f3dc6f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1311,6 +1311,14 @@ static bool detect_link_and_local_sink(struct dc_link *link,
sink->edid_caps.audio_modes[i].sample_rate,
sink->edid_caps.audio_modes[i].sample_size);
}
+
+ if (link->connector_signal == SIGNAL_TYPE_EDP) {
+ // Init dc_panel_config
+ dm_helpers_init_panel_settings(dc_ctx, &link->panel_config);
+ // Override dc_panel_config if system has specific settings
+ dm_helpers_override_panel_settings(dc_ctx, &link->panel_config);
+ }
+
} else {
/* From Connected-to-Disconnected. */
link->type = dc_connection_none;
@@ -4736,7 +4744,7 @@ bool dc_link_should_enable_fec(const struct dc_link *link)
else if (link->connector_signal == SIGNAL_TYPE_EDP
&& (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
dsc_support.DSC_SUPPORT == false
- || link->dc->debug.disable_dsc_edp
+ || link->panel_config.dsc.disable_dsc_edp
|| !link->dc->caps.edp_dsc_support))
force_disable = true;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 7e97265b76e8..11e13c45a338 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3743,7 +3743,7 @@ static bool decide_edp_link_settings_with_dsc(struct dc_link *link,
unsigned int policy = 0;
- policy = link->ctx->dc->debug.force_dsc_edp_policy;
+ policy = link->panel_config.dsc.force_dsc_edp_policy;
if (max_link_rate == LINK_RATE_UNKNOWN)
max_link_rate = link->verified_link_cap.link_rate;
/*
@@ -3909,7 +3909,7 @@ bool decide_link_settings(struct dc_stream_state *stream,
if (stream->timing.flags.DSC) {
enum dc_link_rate max_link_rate = LINK_RATE_UNKNOWN;
- if (link->ctx->dc->debug.force_dsc_edp_policy) {
+ if (link->panel_config.dsc.force_dsc_edp_policy) {
/* calculate link max link rate cap*/
struct dc_link_settings tmp_link_setting;
struct dc_crtc_timing tmp_timing = stream->timing;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index a53863bddee0..9cde9465f5ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -803,8 +803,6 @@ struct dc_debug_options {
bool validate_dml_output;
bool enable_dmcub_surface_flip;
bool usbc_combo_phy_reset_wa;
- bool disable_dsc_edp;
- unsigned int force_dsc_edp_policy;
bool enable_dram_clock_change_one_display_vactive;
/* TODO - remove once tested */
bool legacy_dp2_lt;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index d1214944839f..43d250918fd0 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -113,6 +113,15 @@ struct psr_settings {
unsigned int psr_power_opt;
};
+/* To split out "global" and "per-panel" config settings.
+ * Add a struct dc_panel_config under dc_link
+ */
+struct dc_panel_config {
+ struct dsc {
+ bool disable_dsc_edp;
+ unsigned int force_dsc_edp_policy;
+ } dsc;
+};
/*
* A link contains one or more sinks and their connected status.
* The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
@@ -233,6 +242,7 @@ struct dc_link {
struct gpio *hpd_gpio;
enum dc_link_fec_state fec_state;
+ struct dc_panel_config panel_config;
enum phy_state phy_state;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
index fb6a2d7b6470..6e4d3df0454e 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
@@ -171,7 +171,12 @@ void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigne
// 0x1 = Result_OK, 0xFE = Result_UnkmownCmd, 0x0 = Status_Busy
#define IS_SMU_TIMEOUT(result) \
(result == 0x0)
-
+void dm_helpers_init_panel_settings(
+ struct dc_context *ctx,
+ struct dc_panel_config *config);
+void dm_helpers_override_panel_settings(
+ struct dc_context *ctx,
+ struct dc_panel_config *config);
int dm_helper_dmub_aux_transfer_sync(
struct dc_context *ctx,
const struct dc_link *link,
--
2.25.1
next prev parent reply other threads:[~2022-08-27 2:51 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-26 22:50 [PATCH 00/33] DC Patches August 27 ,2022 brichang
2022-08-26 22:50 ` [PATCH 01/33] drm/amd/display: Set ODM policy based on number of DSC slices brichang
2022-08-26 22:50 ` [PATCH 02/33] drm/amd/display: Don't choose SubVP display if ActiveMargin > 0 brichang
2022-08-26 22:50 ` [PATCH 03/33] drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming brichang
2022-08-26 22:50 ` [PATCH 04/33] drm/amd/display: Refine aux transaction before retrieve caps brichang
2022-08-26 22:50 ` [PATCH 05/33] drm/amd/display: Fix OTG H timing reset for dcn314 brichang
2022-08-26 22:50 ` [PATCH 06/33] drm/amd/display: add dcn35 basic support brichang
2022-08-26 22:50 ` [PATCH 07/33] drm/amd/display: set dig fifo read start level to 7 before dig fifo reset brichang
2022-08-26 22:50 ` [PATCH 08/33] drm/amd/display: Remove assert from PHY state update brichang
2022-08-26 22:50 ` [PATCH 09/33] drm/amd/display: Only commit SubVP state after pipe programming brichang
2022-08-26 22:50 ` [PATCH 10/33] drm/amd/display: add a override flag as wa for some specific dongle brichang
2022-08-26 22:50 ` [PATCH 11/33] drm/amd/display: Add DC debug option to force LTTPR mode brichang
2022-08-26 22:50 ` [PATCH 12/33] drm/amd/display: Cursor lag with PSR1 eDP brichang
2022-08-26 22:50 ` [PATCH 13/33] drm/amd/display: Cleanup PSR flag brichang
2022-08-26 22:50 ` [PATCH 14/33] drm/amd/display: Allow PHY state update between same states brichang
2022-08-26 22:50 ` [PATCH 15/33] drm/amd/display: Add visual confirm color support for SubVP brichang
2022-08-26 22:50 ` [PATCH 16/33] drm/amd/display: Add support for visual confirm color brichang
2022-08-26 22:50 ` [PATCH 17/33] drm/amd/display: SubVP missing scaling case brichang
2022-08-26 22:50 ` brichang [this message]
2022-08-26 22:50 ` [PATCH 19/33] drm/amd/display: Missing HPO instance added brichang
2022-08-26 22:50 ` [PATCH 20/33] drm/amd/display: Fix CAB cursor size allocation for DCN32/321 brichang
2022-08-26 22:50 ` [PATCH 21/33] drm/amd/display: disable display fresh from MALL on an edge case for DCN321 brichang
2022-08-26 22:50 ` [PATCH 22/33] drm/amd/display: use actual cursor size instead of max for CAB allocation brichang
2022-08-26 22:50 ` [PATCH 23/33] drm/amd/display: fix wrong register access brichang
2022-08-26 22:50 ` [PATCH 24/33] drm/amd/display: Fix primary EDP link detection brichang
2022-08-26 22:50 ` [PATCH 25/33] drm/amd/display: Revert "program k1/k2 divider for virtual signal for DCN32" brichang
2022-08-26 22:50 ` [PATCH 26/33] drm/amd/display: Add comments brichang
2022-08-26 22:50 ` [PATCH 27/33] drm/amd/display: [FW Promotion] Release 0.0.132.0 brichang
2022-08-26 22:50 ` [PATCH 28/33] drm/amd/display: 3.2.201 brichang
2022-08-26 22:50 ` [PATCH 29/33] drm/amd/display: Use correct plane for CAB cursor size allocation brichang
2022-08-26 22:50 ` [PATCH 30/33] drm/amd/display: Re-initialize viewport after pipe merge brichang
2022-08-26 22:50 ` [PATCH 31/33] drm/amd/display: Fix check for stream and plane brichang
2022-08-26 22:50 ` [PATCH 32/33] drm/amd/display: Fix black flash when switching from ODM2to1 to ODMBypass brichang
2022-08-26 22:50 ` [PATCH 33/33] drm/amd/display: Correct cursor position on horizontal mirror brichang
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