From: brichang <Brian.Chang@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Brian Chang <Brian.Chang@amd.com>,
Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com,
Alvin Lee <Alvin.Lee2@amd.com>,
wayne.lin@amd.com, "Leo \(Hanghong\) Ma" <hanghong.ma@amd.com>,
Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com,
pavle.kotarac@amd.com
Subject: [PATCH 15/33] drm/amd/display: Add visual confirm color support for SubVP
Date: Sat, 27 Aug 2022 06:50:35 +0800 [thread overview]
Message-ID: <20220826225053.1435588-16-Brian.Chang@amd.com> (raw)
In-Reply-To: <20220826225053.1435588-1-Brian.Chang@amd.com>
From: "Leo (Hanghong) Ma" <hanghong.ma@amd.com>
[Why && How]
We would like to have visual confirm color support for SubVP.
1. Set visual confirm color to red: SubVP is enable on this
display;
2. Set visual confirm color to green: SubVP is enable on
other display and DRR is on this display;
3. Set visual confirm color to blue: SubVP is enable on
other display and DRR is off on this display;
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
---
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 38 +++++++++++++++++++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 5 +++
4 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 2a8007928210..9dd705b985b9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -402,6 +402,44 @@ void get_hdr_visual_confirm_color(
}
}
+void get_subvp_visual_confirm_color(
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct tg_color *color)
+{
+ uint32_t color_value = MAX_TG_COLOR_VALUE;
+ bool enable_subvp = false;
+ int i;
+
+ if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx)
+ return;
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+
+ if (pipe->stream && pipe->stream->mall_stream_config.paired_stream &&
+ pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
+ /* SubVP enable - red */
+ color->color_r_cr = color_value;
+ enable_subvp = true;
+
+ if (pipe_ctx->stream == pipe->stream)
+ return;
+ break;
+ }
+ }
+
+ if (enable_subvp && pipe_ctx->stream->mall_stream_config.type == SUBVP_NONE) {
+ color->color_r_cr = 0;
+ if (pipe_ctx->stream->ignore_msa_timing_param == 1)
+ /* SubVP enable and DRR on - green */
+ color->color_g_y = color_value;
+ else
+ /* SubVP enable and No DRR - blue */
+ color->color_b_cb = color_value;
+ }
+}
+
void get_surface_tile_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index cffb91363b52..eef38d2e4753 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -417,6 +417,7 @@ enum visual_confirm {
VISUAL_CONFIRM_SWAPCHAIN = 6,
VISUAL_CONFIRM_FAMS = 7,
VISUAL_CONFIRM_SWIZZLE = 9,
+ VISUAL_CONFIRM_SUBVP = 14,
};
enum dc_psr_power_opts {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index cf439ed270de..4b4368456477 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2465,6 +2465,8 @@ void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx,
get_mpctree_visual_confirm_color(pipe_ctx, color);
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
get_surface_tile_visual_confirm_color(pipe_ctx, color);
+ else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)
+ get_subvp_visual_confirm_color(dc, pipe_ctx, color);
if (mpc->funcs->set_bg_color)
mpc->funcs->set_bg_color(mpc, color, mpcc_id);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index a4e02b0ace24..8df493572a9a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -272,6 +272,11 @@ const uint16_t *find_color_matrix(
void get_surface_visual_confirm_color(
const struct pipe_ctx *pipe_ctx,
struct tg_color *color);
+
+void get_subvp_visual_confirm_color(
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct tg_color *color);
void get_hdr_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
--
2.25.1
next prev parent reply other threads:[~2022-08-27 2:51 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-26 22:50 [PATCH 00/33] DC Patches August 27 ,2022 brichang
2022-08-26 22:50 ` [PATCH 01/33] drm/amd/display: Set ODM policy based on number of DSC slices brichang
2022-08-26 22:50 ` [PATCH 02/33] drm/amd/display: Don't choose SubVP display if ActiveMargin > 0 brichang
2022-08-26 22:50 ` [PATCH 03/33] drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming brichang
2022-08-26 22:50 ` [PATCH 04/33] drm/amd/display: Refine aux transaction before retrieve caps brichang
2022-08-26 22:50 ` [PATCH 05/33] drm/amd/display: Fix OTG H timing reset for dcn314 brichang
2022-08-26 22:50 ` [PATCH 06/33] drm/amd/display: add dcn35 basic support brichang
2022-08-26 22:50 ` [PATCH 07/33] drm/amd/display: set dig fifo read start level to 7 before dig fifo reset brichang
2022-08-26 22:50 ` [PATCH 08/33] drm/amd/display: Remove assert from PHY state update brichang
2022-08-26 22:50 ` [PATCH 09/33] drm/amd/display: Only commit SubVP state after pipe programming brichang
2022-08-26 22:50 ` [PATCH 10/33] drm/amd/display: add a override flag as wa for some specific dongle brichang
2022-08-26 22:50 ` [PATCH 11/33] drm/amd/display: Add DC debug option to force LTTPR mode brichang
2022-08-26 22:50 ` [PATCH 12/33] drm/amd/display: Cursor lag with PSR1 eDP brichang
2022-08-26 22:50 ` [PATCH 13/33] drm/amd/display: Cleanup PSR flag brichang
2022-08-26 22:50 ` [PATCH 14/33] drm/amd/display: Allow PHY state update between same states brichang
2022-08-26 22:50 ` brichang [this message]
2022-08-26 22:50 ` [PATCH 16/33] drm/amd/display: Add support for visual confirm color brichang
2022-08-26 22:50 ` [PATCH 17/33] drm/amd/display: SubVP missing scaling case brichang
2022-08-26 22:50 ` [PATCH 18/33] drm/amd/display: Refactor edp dsc codes brichang
2022-08-26 22:50 ` [PATCH 19/33] drm/amd/display: Missing HPO instance added brichang
2022-08-26 22:50 ` [PATCH 20/33] drm/amd/display: Fix CAB cursor size allocation for DCN32/321 brichang
2022-08-26 22:50 ` [PATCH 21/33] drm/amd/display: disable display fresh from MALL on an edge case for DCN321 brichang
2022-08-26 22:50 ` [PATCH 22/33] drm/amd/display: use actual cursor size instead of max for CAB allocation brichang
2022-08-26 22:50 ` [PATCH 23/33] drm/amd/display: fix wrong register access brichang
2022-08-26 22:50 ` [PATCH 24/33] drm/amd/display: Fix primary EDP link detection brichang
2022-08-26 22:50 ` [PATCH 25/33] drm/amd/display: Revert "program k1/k2 divider for virtual signal for DCN32" brichang
2022-08-26 22:50 ` [PATCH 26/33] drm/amd/display: Add comments brichang
2022-08-26 22:50 ` [PATCH 27/33] drm/amd/display: [FW Promotion] Release 0.0.132.0 brichang
2022-08-26 22:50 ` [PATCH 28/33] drm/amd/display: 3.2.201 brichang
2022-08-26 22:50 ` [PATCH 29/33] drm/amd/display: Use correct plane for CAB cursor size allocation brichang
2022-08-26 22:50 ` [PATCH 30/33] drm/amd/display: Re-initialize viewport after pipe merge brichang
2022-08-26 22:50 ` [PATCH 31/33] drm/amd/display: Fix check for stream and plane brichang
2022-08-26 22:50 ` [PATCH 32/33] drm/amd/display: Fix black flash when switching from ODM2to1 to ODMBypass brichang
2022-08-26 22:50 ` [PATCH 33/33] drm/amd/display: Correct cursor position on horizontal mirror brichang
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