From: brichang <Brian.Chang@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Brian Chang <Brian.Chang@amd.com>,
Aric Cyr <Aric.Cyr@amd.com>, Anthony Koo <Anthony.Koo@amd.com>,
Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com,
wayne.lin@amd.com, "Leo \(Hanghong\) Ma" <hanghong.ma@amd.com>,
Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com,
pavle.kotarac@amd.com
Subject: [PATCH 16/33] drm/amd/display: Add support for visual confirm color
Date: Sat, 27 Aug 2022 06:50:36 +0800 [thread overview]
Message-ID: <20220826225053.1435588-17-Brian.Chang@amd.com> (raw)
In-Reply-To: <20220826225053.1435588-1-Brian.Chang@amd.com>
From: "Leo (Hanghong) Ma" <hanghong.ma@amd.com>
[Why]
We want to get the visual confirm color of the bottom-most pipe
for test automation.
[How]
Save the visual confirm color to plane_state before program to MPC;
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 31 +++++++++++++
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 1 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +-
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 +-
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 +
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 44 +++++++++++++++++++
7 files changed, 84 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index eef38d2e4753..a53863bddee0 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1184,6 +1184,7 @@ struct dc_plane_state {
/* private to dc_surface.c */
enum dc_irq_source irq_source;
struct kref refcount;
+ struct tg_color visual_confirm_color;
};
struct dc_plane_info {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index cd7225d98b3d..61dfe5358d1c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -387,6 +387,37 @@ void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub)
}
}
+void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)
+{
+ union dmub_rb_cmd cmd = { 0 };
+ enum dmub_status status;
+ unsigned int panel_inst = 0;
+
+ dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst);
+
+ memset(&cmd, 0, sizeof(cmd));
+
+ // Prepare fw command
+ cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR;
+ cmd.visual_confirm_color.header.sub_type = 0;
+ cmd.visual_confirm_color.header.ret_status = 1;
+ cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data);
+ cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst;
+
+ // Send command to fw
+ status = dmub_srv_cmd_with_reply_data(dc->ctx->dmub_srv->dmub, &cmd);
+
+ ASSERT(status == DMUB_STATUS_OK);
+
+ // If command was processed, copy feature caps to dmub srv
+ if (status == DMUB_STATUS_OK &&
+ cmd.visual_confirm_color.header.ret_status == 0) {
+ memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,
+ &cmd.visual_confirm_color.visual_confirm_color_data,
+ sizeof(struct dmub_visual_confirm_color));
+ }
+}
+
#ifdef CONFIG_DRM_AMD_DC_DCN
/**
* ***********************************************************************************************
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index 159782cd6659..9f5b47b9a83d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -78,6 +78,7 @@ void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst);
bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool enable_pstate, struct dc_state *context);
void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub);
+void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx);
void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv);
void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv);
void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 2118ad3e37d0..d3f6a2609c8c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2539,8 +2539,10 @@ void dcn10_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx,
color_space_to_black_color(
dc, pipe_ctx->stream->output_color_space, color);
- if (mpc->funcs->set_bg_color)
+ if (mpc->funcs->set_bg_color) {
+ memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color));
mpc->funcs->set_bg_color(mpc, color, mpcc_id);
+ }
}
void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 4b4368456477..6271caca4d9a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2468,8 +2468,10 @@ void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx,
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)
get_subvp_visual_confirm_color(dc, pipe_ctx, color);
- if (mpc->funcs->set_bg_color)
+ if (mpc->funcs->set_bg_color) {
+ memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color));
mpc->funcs->set_bg_color(mpc, color, mpcc_id);
+ }
}
void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 840460ad0bf8..fdaa6f4fdde1 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -442,6 +442,7 @@ struct dmub_srv {
/* Feature capabilities reported by fw */
struct dmub_feature_caps feature_caps;
+ struct dmub_visual_confirm_color visual_confirm_color;
};
/**
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 829410a883a1..1184bef22673 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -246,6 +246,16 @@ struct dmub_feature_caps {
uint8_t reserved[6];
};
+struct dmub_visual_confirm_color {
+ /**
+ * Maximum 10 bits color value
+ */
+ uint16_t color_r_cr;
+ uint16_t color_g_y;
+ uint16_t color_b_cb;
+ uint16_t panel_inst;
+};
+
#if defined(__cplusplus)
}
#endif
@@ -644,6 +654,10 @@ enum dmub_cmd_type {
* Command type used to query FW feature caps.
*/
DMUB_CMD__QUERY_FEATURE_CAPS = 6,
+ /**
+ * Command type used to get visual confirm color.
+ */
+ DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,
/**
* Command type used for all PSR commands.
*/
@@ -2778,6 +2792,31 @@ struct dmub_rb_cmd_query_feature_caps {
struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
};
+/**
+ * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
+ */
+struct dmub_cmd_visual_confirm_color_data {
+ /**
+ * DMUB feature capabilities.
+ * After DMUB init, driver will query FW capabilities prior to enabling certain features.
+ */
+struct dmub_visual_confirm_color visual_confirm_color;
+};
+
+/**
+ * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
+ */
+struct dmub_rb_cmd_get_visual_confirm_color {
+ /**
+ * Command header.
+ */
+ struct dmub_cmd_header header;
+ /**
+ * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
+ */
+ struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
+};
+
struct dmub_optc_state {
uint32_t v_total_max;
uint32_t v_total_min;
@@ -3150,6 +3189,11 @@ union dmub_rb_cmd {
* Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
*/
struct dmub_rb_cmd_query_feature_caps query_feature_caps;
+
+ /**
+ * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
+ */
+ struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;
struct dmub_rb_cmd_drr_update drr_update;
struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;
--
2.25.1
next prev parent reply other threads:[~2022-08-27 2:51 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-26 22:50 [PATCH 00/33] DC Patches August 27 ,2022 brichang
2022-08-26 22:50 ` [PATCH 01/33] drm/amd/display: Set ODM policy based on number of DSC slices brichang
2022-08-26 22:50 ` [PATCH 02/33] drm/amd/display: Don't choose SubVP display if ActiveMargin > 0 brichang
2022-08-26 22:50 ` [PATCH 03/33] drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming brichang
2022-08-26 22:50 ` [PATCH 04/33] drm/amd/display: Refine aux transaction before retrieve caps brichang
2022-08-26 22:50 ` [PATCH 05/33] drm/amd/display: Fix OTG H timing reset for dcn314 brichang
2022-08-26 22:50 ` [PATCH 06/33] drm/amd/display: add dcn35 basic support brichang
2022-08-26 22:50 ` [PATCH 07/33] drm/amd/display: set dig fifo read start level to 7 before dig fifo reset brichang
2022-08-26 22:50 ` [PATCH 08/33] drm/amd/display: Remove assert from PHY state update brichang
2022-08-26 22:50 ` [PATCH 09/33] drm/amd/display: Only commit SubVP state after pipe programming brichang
2022-08-26 22:50 ` [PATCH 10/33] drm/amd/display: add a override flag as wa for some specific dongle brichang
2022-08-26 22:50 ` [PATCH 11/33] drm/amd/display: Add DC debug option to force LTTPR mode brichang
2022-08-26 22:50 ` [PATCH 12/33] drm/amd/display: Cursor lag with PSR1 eDP brichang
2022-08-26 22:50 ` [PATCH 13/33] drm/amd/display: Cleanup PSR flag brichang
2022-08-26 22:50 ` [PATCH 14/33] drm/amd/display: Allow PHY state update between same states brichang
2022-08-26 22:50 ` [PATCH 15/33] drm/amd/display: Add visual confirm color support for SubVP brichang
2022-08-26 22:50 ` brichang [this message]
2022-08-26 22:50 ` [PATCH 17/33] drm/amd/display: SubVP missing scaling case brichang
2022-08-26 22:50 ` [PATCH 18/33] drm/amd/display: Refactor edp dsc codes brichang
2022-08-26 22:50 ` [PATCH 19/33] drm/amd/display: Missing HPO instance added brichang
2022-08-26 22:50 ` [PATCH 20/33] drm/amd/display: Fix CAB cursor size allocation for DCN32/321 brichang
2022-08-26 22:50 ` [PATCH 21/33] drm/amd/display: disable display fresh from MALL on an edge case for DCN321 brichang
2022-08-26 22:50 ` [PATCH 22/33] drm/amd/display: use actual cursor size instead of max for CAB allocation brichang
2022-08-26 22:50 ` [PATCH 23/33] drm/amd/display: fix wrong register access brichang
2022-08-26 22:50 ` [PATCH 24/33] drm/amd/display: Fix primary EDP link detection brichang
2022-08-26 22:50 ` [PATCH 25/33] drm/amd/display: Revert "program k1/k2 divider for virtual signal for DCN32" brichang
2022-08-26 22:50 ` [PATCH 26/33] drm/amd/display: Add comments brichang
2022-08-26 22:50 ` [PATCH 27/33] drm/amd/display: [FW Promotion] Release 0.0.132.0 brichang
2022-08-26 22:50 ` [PATCH 28/33] drm/amd/display: 3.2.201 brichang
2022-08-26 22:50 ` [PATCH 29/33] drm/amd/display: Use correct plane for CAB cursor size allocation brichang
2022-08-26 22:50 ` [PATCH 30/33] drm/amd/display: Re-initialize viewport after pipe merge brichang
2022-08-26 22:50 ` [PATCH 31/33] drm/amd/display: Fix check for stream and plane brichang
2022-08-26 22:50 ` [PATCH 32/33] drm/amd/display: Fix black flash when switching from ODM2to1 to ODMBypass brichang
2022-08-26 22:50 ` [PATCH 33/33] drm/amd/display: Correct cursor position on horizontal mirror brichang
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