From: Hamza Mahfooz <hamza.mahfooz@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
roman.li@amd.com, Wenjing Liu <wenjing.liu@amd.com>,
Daniel Wheeler <daniel.wheeler@amd.com>,
solomon.chiu@amd.com, jerry.zuo@amd.com,
Aurabindo.Pillai@amd.com, hamza.mahfooz@amd.com,
wayne.lin@amd.com, Jun Lei <jun.lei@amd.com>,
Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com,
pavle.kotarac@amd.com
Subject: [PATCH 09/21] drm/amd/display: add new resource interface for acquiring sec opp heads and release pipe
Date: Wed, 23 Aug 2023 11:58:11 -0400 [thread overview]
Message-ID: <20230823160347.176991-10-hamza.mahfooz@amd.com> (raw)
In-Reply-To: <20230823160347.176991-1-hamza.mahfooz@amd.com>
From: Wenjing Liu <wenjing.liu@amd.com>
[why]
We need a new algorithm for acquiring secondary opp heads for ODM combine
in dcn32 and a release pipe interface to properly release pipe resources.
[how]
add two new interfaces in DCN specific resource file.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 21 +++++
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 81 +++++++++++++++++++
.../drm/amd/display/dc/dcn32/dcn32_resource.h | 10 +++
.../gpu/drm/amd/display/dc/inc/core_types.h | 10 +++
drivers/gpu/drm/amd/display/dc/inc/resource.h | 12 +++
5 files changed, 134 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index a2705771d790..20f9da625267 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1615,6 +1615,27 @@ struct pipe_ctx *resource_find_free_secondary_pipe_legacy(
return secondary_pipe;
}
+int resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(
+ const struct resource_context *cur_res_ctx,
+ struct resource_context *new_res_ctx,
+ const struct pipe_ctx *cur_otg_master)
+{
+ const struct pipe_ctx *cur_sec_opp_head = cur_otg_master->next_odm_pipe;
+ struct pipe_ctx *new_pipe;
+ int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
+
+ while (cur_sec_opp_head) {
+ new_pipe = &new_res_ctx->pipe_ctx[cur_sec_opp_head->pipe_idx];
+ if (resource_is_pipe_type(new_pipe, FREE_PIPE)) {
+ free_pipe_idx = cur_sec_opp_head->pipe_idx;
+ break;
+ }
+ cur_sec_opp_head = cur_sec_opp_head->next_odm_pipe;
+ }
+
+ return free_pipe_idx;
+}
+
int resource_find_free_pipe_used_in_cur_mpc_blending_tree(
const struct resource_context *cur_res_ctx,
struct resource_context *new_res_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index f9d601c8c721..072c5ba4c99c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2039,6 +2039,8 @@ static struct resource_funcs dcn32_res_pool_funcs = {
.calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
.populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
+ .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
+ .release_pipe = dcn32_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
@@ -2669,6 +2671,33 @@ static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
return idle_pipe;
}
+static int find_optimal_free_pipe_as_secondary_opp_head(
+ const struct resource_context *cur_res_ctx,
+ struct resource_context *new_res_ctx,
+ const struct resource_pool *pool,
+ const struct pipe_ctx *new_otg_master)
+{
+ const struct pipe_ctx *cur_otg_master;
+ int free_pipe_idx;
+
+ cur_otg_master = &cur_res_ctx->pipe_ctx[new_otg_master->pipe_idx];
+ free_pipe_idx = resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(
+ cur_res_ctx, new_res_ctx, cur_otg_master);
+
+ /* Up until here if we have not found a free secondary pipe, we will
+ * need to wait for at least one frame to complete the transition
+ * sequence.
+ */
+ if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
+ free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(
+ cur_res_ctx, new_res_ctx, pool);
+
+ if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
+ free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool);
+
+ return free_pipe_idx;
+}
+
struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
const struct dc_state *cur_ctx,
struct dc_state *new_ctx,
@@ -2706,6 +2735,58 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
return free_pipe;
}
+struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(
+ const struct dc_state *cur_ctx,
+ struct dc_state *new_ctx,
+ const struct resource_pool *pool,
+ const struct pipe_ctx *otg_master)
+{
+ int free_pipe_idx = find_optimal_free_pipe_as_secondary_opp_head(
+ &cur_ctx->res_ctx, &new_ctx->res_ctx,
+ pool, otg_master);
+ struct pipe_ctx *free_pipe;
+
+ if (free_pipe_idx >= 0) {
+ free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
+ free_pipe->pipe_idx = free_pipe_idx;
+ free_pipe->stream = otg_master->stream;
+ free_pipe->stream_res.tg = otg_master->stream_res.tg;
+ free_pipe->stream_res.dsc = NULL;
+ free_pipe->stream_res.opp = pool->opps[free_pipe_idx];
+ free_pipe->plane_res.mi = pool->mis[free_pipe_idx];
+ free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx];
+ free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx];
+ free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx];
+ free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx];
+ free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst;
+ if (free_pipe->stream->timing.flags.DSC == 1) {
+ dcn20_acquire_dsc(free_pipe->stream->ctx->dc,
+ &new_ctx->res_ctx,
+ &free_pipe->stream_res.dsc,
+ free_pipe_idx);
+ ASSERT(free_pipe->stream_res.dsc);
+ if (free_pipe->stream_res.dsc == NULL) {
+ memset(free_pipe, 0, sizeof(*free_pipe));
+ free_pipe = NULL;
+ }
+ }
+ } else {
+ ASSERT(otg_master);
+ free_pipe = NULL;
+ }
+
+ return free_pipe;
+}
+
+void dcn32_release_pipe(struct dc_state *context,
+ struct pipe_ctx *pipe,
+ const struct resource_pool *pool)
+{
+ if (resource_is_pipe_type(pipe, OPP_HEAD) && pipe->stream_res.dsc)
+ dcn20_release_dsc(&context->res_ctx, pool, &pipe->stream_res.dsc);
+ memset(pipe, 0, sizeof(*pipe));
+}
+
unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans)
{
/*
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
index 0c6ca3da66d9..4caebcaca031 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -142,6 +142,16 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
const struct resource_pool *pool,
const struct pipe_ctx *opp_head_pipe);
+struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(
+ const struct dc_state *cur_ctx,
+ struct dc_state *new_ctx,
+ const struct resource_pool *pool,
+ const struct pipe_ctx *otg_master);
+
+void dcn32_release_pipe(struct dc_state *context,
+ struct pipe_ctx *pipe,
+ const struct resource_pool *pool);
+
void dcn32_determine_det_override(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index b55848480485..77457c9c46f3 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -132,6 +132,16 @@ struct resource_funcs {
const struct resource_pool *pool,
const struct pipe_ctx *opp_head_pipe);
+ struct pipe_ctx *(*acquire_free_pipe_as_secondary_opp_head)(
+ const struct dc_state *cur_ctx,
+ struct dc_state *new_ctx,
+ const struct resource_pool *pool,
+ const struct pipe_ctx *otg_master);
+
+ void (*release_pipe)(struct dc_state *context,
+ struct pipe_ctx *pipe,
+ const struct resource_pool *pool);
+
enum dc_status (*validate_plane)(
const struct dc_plane_state *plane_state,
struct dc_caps *caps);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index e546b9c506c1..7a503d87fe9f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -280,6 +280,18 @@ bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type)
*/
bool resource_is_for_mpcc_combine(const struct pipe_ctx *pipe_ctx);
+/*
+ * Look for a free pipe in new resource context that is used as a secondary OPP
+ * head by cur_otg_master.
+ *
+ * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise
+ * pipe idx of the free pipe
+ */
+int resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(
+ const struct resource_context *cur_res_ctx,
+ struct resource_context *new_res_ctx,
+ const struct pipe_ctx *cur_otg_master);
+
/*
* Look for a free pipe in new resource context that is used as a secondary DPP
* pipe in MPC blending tree associated with input OPP head pipe.
--
2.41.0
next prev parent reply other threads:[~2023-08-23 16:04 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 01/21] Partially revert "drm/amd/display: update add plane to context logic with a new algorithm" Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 02/21] drm/amd/display: Add support for 1080p SubVP to reduce idle power Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 03/21] drm/amd/display: Add smu write msg id fail retry process Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 04/21] drm/amd/display: update blank state on ODM changes Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 05/21] drm/amd/display: always switch off ODM before committing more streams Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 06/21] drm/amd/display: Add DPIA Link Encoder Assignment Fix Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 07/21] drm/amd/display: add comments to add plane functions Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 08/21] drm/amd/display: rename function to add otg master for stream Hamza Mahfooz
2023-08-23 15:58 ` Hamza Mahfooz [this message]
2023-08-23 15:58 ` [PATCH 10/21] drm/amd/display: add new resource interfaces to update odm mpc slice count Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 11/21] drm/amd/display: add more pipe resource interfaces Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 12/21] drm/amd/display: use new pipe allocation interface in dcn32 fpu Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 13/21] drm/amd/display: switch to new ODM policy for windowed MPO ODM support Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 14/21] drm/amd/display: add pipe topology update log Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 15/21] drm/amd/display: Remove wait while locked Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 16/21] drm/amd/display: Skip dmub memory flush when not needed Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 17/21] drm/amd/display: Fix incorrect comment Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 18/21] drm/amd/display: correct z8_watermark 16bit to 20bit mask Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 19/21] drm/amd/display: Add debugfs interface for ODM combine info Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 20/21] drm/amd/display: fix pipe topology logging error Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 21/21] drm/amd/display: 3.2.249 Hamza Mahfooz
2023-08-28 13:21 ` [PATCH 00/21] DC Patches August 23, 2023 Wheeler, Daniel
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