From: Hamza Mahfooz <hamza.mahfooz@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
roman.li@amd.com, Wenjing Liu <wenjing.liu@amd.com>,
Daniel Wheeler <daniel.wheeler@amd.com>,
solomon.chiu@amd.com, jerry.zuo@amd.com,
Aurabindo.Pillai@amd.com, hamza.mahfooz@amd.com,
wayne.lin@amd.com, Jun Lei <jun.lei@amd.com>,
Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com,
pavle.kotarac@amd.com
Subject: [PATCH 14/21] drm/amd/display: add pipe topology update log
Date: Wed, 23 Aug 2023 11:58:16 -0400 [thread overview]
Message-ID: <20230823160347.176991-15-hamza.mahfooz@amd.com> (raw)
In-Reply-To: <20230823160347.176991-1-hamza.mahfooz@amd.com>
From: Wenjing Liu <wenjing.liu@amd.com>
Given an issue with pipe topology transition. It is very hard to tell
the before and after pipe topology without a pipe topology logging. The
change adds such logging to help with visualizing the issue.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 159 ++++++++++++++++++
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 10 +-
drivers/gpu/drm/amd/display/dc/inc/resource.h | 7 +
3 files changed, 168 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 84db7c5fb852..f32337122f5b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1865,6 +1865,165 @@ int resource_get_odm_slice_index(const struct pipe_ctx *pipe_ctx)
return index;
}
+bool resource_is_pipe_topology_changed(const struct dc_state *state_a,
+ const struct dc_state *state_b)
+{
+ int i;
+ const struct pipe_ctx *pipe_a, *pipe_b;
+
+ if (state_a->stream_count != state_b->stream_count)
+ return true;
+
+ for (i = 0; i < MAX_PIPES; i++) {
+ pipe_a = &state_a->res_ctx.pipe_ctx[i];
+ pipe_b = &state_b->res_ctx.pipe_ctx[i];
+
+ if (pipe_a->stream && !pipe_b->stream)
+ return true;
+ else if (!pipe_a->stream && pipe_b->stream)
+ return true;
+
+ if (pipe_a->plane_state && !pipe_b->plane_state)
+ return true;
+ else if (!pipe_a->plane_state && pipe_b->plane_state)
+ return true;
+
+ if (pipe_a->bottom_pipe && pipe_b->bottom_pipe) {
+ if (pipe_a->bottom_pipe->pipe_idx != pipe_b->bottom_pipe->pipe_idx)
+ return true;
+ if ((pipe_a->bottom_pipe->plane_state == pipe_a->plane_state) &&
+ (pipe_b->bottom_pipe->plane_state != pipe_b->plane_state))
+ return true;
+ else if ((pipe_a->bottom_pipe->plane_state != pipe_a->plane_state) &&
+ (pipe_b->bottom_pipe->plane_state == pipe_b->plane_state))
+ return true;
+ } else if (pipe_a->bottom_pipe || pipe_b->bottom_pipe) {
+ return true;
+ }
+
+ if (pipe_a->next_odm_pipe && pipe_b->next_odm_pipe) {
+ if (pipe_a->next_odm_pipe->pipe_idx != pipe_b->next_odm_pipe->pipe_idx)
+ return true;
+ } else if (pipe_a->next_odm_pipe || pipe_b->next_odm_pipe) {
+ return true;
+ }
+ }
+ return false;
+}
+
+/*
+ * Sample log:
+ * pipe topology update
+ * ________________________
+ * | plane0 slice0 stream0|
+ * |DPP0----OPP0----OTG0----| <--- case 0 (OTG master pipe with plane)
+ * | plane1 | | |
+ * |DPP1----| | | <--- case 5 (DPP pipe not in last slice)
+ * | plane0 slice1 | |
+ * |DPP2----OPP2----| | <--- case 2 (OPP head pipe with plane)
+ * | plane1 | |
+ * |DPP3----| | <--- case 4 (DPP pipe in last slice)
+ * | slice0 stream1|
+ * |DPG4----OPP4----OTG4----| <--- case 1 (OTG master pipe without plane)
+ * | slice1 | |
+ * |DPG5----OPP5----| | <--- case 3 (OPP head pipe without plane)
+ * |________________________|
+ */
+
+static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,
+ int stream_idx, int slice_idx, int plane_idx, int slice_count,
+ bool is_primary)
+{
+ DC_LOGGER_INIT(dc->ctx->logger);
+
+ if (slice_idx == 0 && plane_idx == 0 && is_primary) {
+ /* case 0 (OTG master pipe with plane) */
+ DC_LOG_DC(" | plane%d slice%d stream%d|",
+ plane_idx, slice_idx, stream_idx);
+ DC_LOG_DC(" |DPP%d----OPP%d----OTG%d----|",
+ pipe->plane_res.dpp->inst,
+ pipe->stream_res.opp->inst,
+ pipe->stream_res.tg->inst);
+ } else if (slice_idx == 0 && plane_idx == -1) {
+ /* case 1 (OTG master pipe without plane) */
+ DC_LOG_DC(" | slice%d stream%d|",
+ slice_idx, stream_idx);
+ DC_LOG_DC(" |DPG%d----OPP%d----OTG%d----|",
+ pipe->stream_res.opp->inst,
+ pipe->stream_res.opp->inst,
+ pipe->stream_res.tg->inst);
+ } else if (slice_idx != 0 && plane_idx == 0 && is_primary) {
+ /* case 2 (OPP head pipe with plane) */
+ DC_LOG_DC(" | plane%d slice%d | |",
+ plane_idx, slice_idx);
+ DC_LOG_DC(" |DPP%d----OPP%d----| |",
+ pipe->plane_res.dpp->inst,
+ pipe->stream_res.opp->inst);
+ } else if (slice_idx != 0 && plane_idx == -1) {
+ /* case 3 (OPP head pipe without plane) */
+ DC_LOG_DC(" | slice%d | |", slice_idx);
+ DC_LOG_DC(" |DPG%d----OPP%d----| |",
+ pipe->plane_res.dpp->inst,
+ pipe->stream_res.opp->inst);
+ } else if (slice_idx == slice_count - 1) {
+ /* case 4 (DPP pipe in last slice) */
+ DC_LOG_DC(" | plane%d | |", plane_idx);
+ DC_LOG_DC(" |DPP%d----| |",
+ pipe->plane_res.dpp->inst);
+ } else {
+ /* case 5 (DPP pipe not in last slice) */
+ DC_LOG_DC(" | plane%d | | |", plane_idx);
+ DC_LOG_DC(" |DPP%d----| | |",
+ pipe->plane_res.dpp->inst);
+ }
+}
+
+void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)
+{
+ struct pipe_ctx *otg_master;
+ struct pipe_ctx *opp_heads[MAX_PIPES];
+ struct pipe_ctx *dpp_pipes[MAX_PIPES];
+
+ int stream_idx, slice_idx, dpp_idx, plane_idx, slice_count, dpp_count;
+ bool is_primary;
+ DC_LOGGER_INIT(dc->ctx->logger);
+
+ DC_LOG_DC(" pipe topology update");
+ DC_LOG_DC(" ________________________");
+ for (stream_idx = 0; stream_idx < state->stream_count; stream_idx++) {
+ otg_master = resource_get_otg_master_for_stream(
+ &state->res_ctx, state->streams[stream_idx]);
+ slice_count = resource_get_opp_heads_for_otg_master(otg_master,
+ &state->res_ctx, opp_heads);
+ for (slice_idx = 0; slice_idx < slice_count; slice_idx++) {
+ if (opp_heads[slice_idx]->plane_state) {
+ plane_idx = 0;
+ dpp_count = resource_get_dpp_pipes_for_opp_head(
+ opp_heads[slice_idx],
+ &state->res_ctx,
+ dpp_pipes);
+ for (dpp_idx = 0; dpp_idx < dpp_count; dpp_idx++) {
+ is_primary = !dpp_pipes[dpp_idx]->top_pipe ||
+ dpp_pipes[dpp_idx]->top_pipe->plane_state != dpp_pipes[dpp_idx]->plane_state;
+ resource_log_pipe(dc, dpp_pipes[dpp_idx],
+ stream_idx, slice_idx,
+ plane_idx, slice_count,
+ is_primary);
+ if (is_primary)
+ plane_idx++;
+ }
+ } else {
+ plane_idx = -1;
+ resource_log_pipe(dc, opp_heads[slice_idx],
+ stream_idx, slice_idx, plane_idx,
+ slice_count, true);
+ }
+
+ }
+ }
+ DC_LOG_DC(" |________________________|\n");
+}
+
static struct pipe_ctx *get_tail_pipe(
struct pipe_ctx *head_pipe)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 347156d02f21..dd4c7a7faf28 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1816,14 +1816,8 @@ void dcn20_program_front_end_for_ctx(
struct dce_hwseq *hws = dc->hwseq;
DC_LOGGER_INIT(dc->ctx->logger);
- /* Carry over GSL groups in case the context is changing. */
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
- struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
-
- if (pipe_ctx->stream == old_pipe_ctx->stream)
- pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group;
- }
+ if (resource_is_pipe_topology_changed(dc->current_state, context))
+ resource_log_pipe_topology_update(dc, context);
if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 55efd5600521..6777b07d0727 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -437,6 +437,13 @@ int resource_get_odm_slice_count(const struct pipe_ctx *otg_master);
/* Get the ODM slice index counting from 0 from left most slice */
int resource_get_odm_slice_index(const struct pipe_ctx *opp_head);
+/* determine if pipe topology is changed between state a and state b */
+bool resource_is_pipe_topology_changed(const struct dc_state *state_a,
+ const struct dc_state *state_b);
+
+/* log the pipe topology update in state */
+void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state);
+
/*
* Look for a free pipe in new resource context that is used as a secondary OPP
* head by cur_otg_master.
--
2.41.0
next prev parent reply other threads:[~2023-08-23 16:04 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 01/21] Partially revert "drm/amd/display: update add plane to context logic with a new algorithm" Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 02/21] drm/amd/display: Add support for 1080p SubVP to reduce idle power Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 03/21] drm/amd/display: Add smu write msg id fail retry process Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 04/21] drm/amd/display: update blank state on ODM changes Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 05/21] drm/amd/display: always switch off ODM before committing more streams Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 06/21] drm/amd/display: Add DPIA Link Encoder Assignment Fix Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 07/21] drm/amd/display: add comments to add plane functions Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 08/21] drm/amd/display: rename function to add otg master for stream Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 09/21] drm/amd/display: add new resource interface for acquiring sec opp heads and release pipe Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 10/21] drm/amd/display: add new resource interfaces to update odm mpc slice count Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 11/21] drm/amd/display: add more pipe resource interfaces Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 12/21] drm/amd/display: use new pipe allocation interface in dcn32 fpu Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 13/21] drm/amd/display: switch to new ODM policy for windowed MPO ODM support Hamza Mahfooz
2023-08-23 15:58 ` Hamza Mahfooz [this message]
2023-08-23 15:58 ` [PATCH 15/21] drm/amd/display: Remove wait while locked Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 16/21] drm/amd/display: Skip dmub memory flush when not needed Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 17/21] drm/amd/display: Fix incorrect comment Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 18/21] drm/amd/display: correct z8_watermark 16bit to 20bit mask Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 19/21] drm/amd/display: Add debugfs interface for ODM combine info Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 20/21] drm/amd/display: fix pipe topology logging error Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 21/21] drm/amd/display: 3.2.249 Hamza Mahfooz
2023-08-28 13:21 ` [PATCH 00/21] DC Patches August 23, 2023 Wheeler, Daniel
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