From: Hamza Mahfooz <hamza.mahfooz@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
roman.li@amd.com, stable@vger.kernel.org,
Gabe Teeger <gabe.teeger@amd.com>,
Daniel Wheeler <daniel.wheeler@amd.com>,
solomon.chiu@amd.com, jerry.zuo@amd.com,
Aurabindo.Pillai@amd.com, hamza.mahfooz@amd.com,
wayne.lin@amd.com, Jun Lei <jun.lei@amd.com>,
Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com,
pavle.kotarac@amd.com
Subject: [PATCH 15/21] drm/amd/display: Remove wait while locked
Date: Wed, 23 Aug 2023 11:58:17 -0400 [thread overview]
Message-ID: <20230823160347.176991-16-hamza.mahfooz@amd.com> (raw)
In-Reply-To: <20230823160347.176991-1-hamza.mahfooz@amd.com>
From: Gabe Teeger <gabe.teeger@amd.com>
[Why]
We wait for mpc idle while in a locked state, leading to potential
deadlock.
[What]
Move the wait_for_idle call to outside of HW lock. This and a
call to wait_drr_doublebuffer_pending_clear are moved added to a new
static helper function called wait_for_outstanding_hw_updates, to make
the interface clearer.
Cc: stable@vger.kernel.org
Fixes: 8f0d304d21b3 ("drm/amd/display: Do not commit pipe when updating DRR")
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
---
drivers/gpu/drm/amd/display/dc/Makefile | 1 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 58 +++++++++++++------
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 11 ----
3 files changed, 42 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index 69ffd4424dc7..1b8c2aef4633 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -78,3 +78,4 @@ DC_EDID += dc_edid_parser.o
AMD_DISPLAY_DMUB = $(addprefix $(AMDDALPATH)/dc/,$(DC_DMUB))
AMD_DISPLAY_EDID = $(addprefix $(AMDDALPATH)/dc/,$(DC_EDID))
AMD_DISPLAY_FILES += $(AMD_DISPLAY_DMUB) $(AMD_DISPLAY_EDID)
+
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c6f6dc972c2a..5aab67868cb6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3501,6 +3501,45 @@ static void commit_planes_for_stream_fast(struct dc *dc,
top_pipe_to_program->stream->update_flags.raw = 0;
}
+static void wait_for_outstanding_hw_updates(struct dc *dc, const struct dc_state *dc_context)
+{
+/*
+ * This function calls HWSS to wait for any potentially double buffered
+ * operations to complete. It should be invoked as a pre-amble prior
+ * to full update programming before asserting any HW locks.
+ */
+ int pipe_idx;
+ int opp_inst;
+ int opp_count = dc->res_pool->pipe_count;
+ struct hubp *hubp;
+ int mpcc_inst;
+ const struct pipe_ctx *pipe_ctx;
+
+ for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
+ pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx];
+
+ if (!pipe_ctx->stream)
+ continue;
+
+ if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear)
+ pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg);
+
+ hubp = pipe_ctx->plane_res.hubp;
+ if (!hubp)
+ continue;
+
+ mpcc_inst = hubp->inst;
+ // MPCC inst is equal to pipe index in practice
+ for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
+ if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
+ dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
+ dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
+ break;
+ }
+ }
+ }
+}
+
static void commit_planes_for_stream(struct dc *dc,
struct dc_surface_update *srf_updates,
int surface_count,
@@ -3519,24 +3558,9 @@ static void commit_planes_for_stream(struct dc *dc,
// dc->current_state anymore, so we have to cache it before we apply
// the new SubVP context
subvp_prev_use = false;
-
-
dc_z10_restore(dc);
-
- if (update_type == UPDATE_TYPE_FULL) {
- /* wait for all double-buffer activity to clear on all pipes */
- int pipe_idx;
-
- for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
-
- if (!pipe_ctx->stream)
- continue;
-
- if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear)
- pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg);
- }
- }
+ if (update_type == UPDATE_TYPE_FULL)
+ wait_for_outstanding_hw_updates(dc, context);
if (update_type == UPDATE_TYPE_FULL) {
dc_allow_idle_optimizations(dc, false);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index dd4c7a7faf28..971fa8bf6d1f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1563,17 +1563,6 @@ static void dcn20_update_dchubp_dpp(
|| plane_state->update_flags.bits.global_alpha_change
|| plane_state->update_flags.bits.per_pixel_alpha_change) {
// MPCC inst is equal to pipe index in practice
- int mpcc_inst = hubp->inst;
- int opp_inst;
- int opp_count = dc->res_pool->pipe_count;
-
- for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
- if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
- dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
- dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
- break;
- }
- }
hws->funcs.update_mpcc(dc, pipe_ctx);
}
--
2.41.0
next prev parent reply other threads:[~2023-08-23 16:04 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 01/21] Partially revert "drm/amd/display: update add plane to context logic with a new algorithm" Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 02/21] drm/amd/display: Add support for 1080p SubVP to reduce idle power Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 03/21] drm/amd/display: Add smu write msg id fail retry process Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 04/21] drm/amd/display: update blank state on ODM changes Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 05/21] drm/amd/display: always switch off ODM before committing more streams Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 06/21] drm/amd/display: Add DPIA Link Encoder Assignment Fix Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 07/21] drm/amd/display: add comments to add plane functions Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 08/21] drm/amd/display: rename function to add otg master for stream Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 09/21] drm/amd/display: add new resource interface for acquiring sec opp heads and release pipe Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 10/21] drm/amd/display: add new resource interfaces to update odm mpc slice count Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 11/21] drm/amd/display: add more pipe resource interfaces Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 12/21] drm/amd/display: use new pipe allocation interface in dcn32 fpu Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 13/21] drm/amd/display: switch to new ODM policy for windowed MPO ODM support Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 14/21] drm/amd/display: add pipe topology update log Hamza Mahfooz
2023-08-23 15:58 ` Hamza Mahfooz [this message]
2023-08-23 15:58 ` [PATCH 16/21] drm/amd/display: Skip dmub memory flush when not needed Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 17/21] drm/amd/display: Fix incorrect comment Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 18/21] drm/amd/display: correct z8_watermark 16bit to 20bit mask Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 19/21] drm/amd/display: Add debugfs interface for ODM combine info Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 20/21] drm/amd/display: fix pipe topology logging error Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 21/21] drm/amd/display: 3.2.249 Hamza Mahfooz
2023-08-28 13:21 ` [PATCH 00/21] DC Patches August 23, 2023 Wheeler, Daniel
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