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From: Hamza Mahfooz <hamza.mahfooz@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Martin Leung <martin.leung@amd.com>,
	Rodrigo.Siqueira@amd.com, roman.li@amd.com,
	Wenjing Liu <wenjing.liu@amd.com>,
	Daniel Wheeler <daniel.wheeler@amd.com>,
	solomon.chiu@amd.com, jerry.zuo@amd.com,
	Aurabindo.Pillai@amd.com, hamza.mahfooz@amd.com,
	wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com,
	agustin.gutierrez@amd.com, pavle.kotarac@amd.com
Subject: [PATCH 01/21] Partially revert "drm/amd/display: update add plane to context logic with a new algorithm"
Date: Wed, 23 Aug 2023 11:58:03 -0400	[thread overview]
Message-ID: <20230823160347.176991-2-hamza.mahfooz@amd.com> (raw)
In-Reply-To: <20230823160347.176991-1-hamza.mahfooz@amd.com>

From: Wenjing Liu <wenjing.liu@amd.com>

This partially reverts commit e170066a4719 ("drm/amd/display: update add
plane to context logic with a new algorithm").

The new secondary pipe allocation logic triggers an issue with a
specific hardware state transition and causes a frame of corruption when
toggling between windowed MPO and ODM desktop only mode. Ideally hwss is
supposed to handle this scenario. We are temporarily reverting the logic
and investigate the root cause why this transition would cause
corruptions.

Reviewed-by: Martin Leung <martin.leung@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
 .../drm/amd/display/dc/dcn32/dcn32_resource.c | 118 +++++++++++++++++-
 1 file changed, 114 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 935cd23e6a01..f9d601c8c721 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2564,18 +2564,128 @@ static int find_optimal_free_pipe_as_secondary_dpp_pipe(
 	return free_pipe_idx;
 }
 
+static struct pipe_ctx *find_idle_secondary_pipe_check_mpo(
+		struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		const struct pipe_ctx *primary_pipe)
+{
+	int i;
+	struct pipe_ctx *secondary_pipe = NULL;
+	struct pipe_ctx *next_odm_mpo_pipe = NULL;
+	int primary_index, preferred_pipe_idx;
+	struct pipe_ctx *old_primary_pipe = NULL;
+
+	/*
+	 * Modified from find_idle_secondary_pipe
+	 * With windowed MPO and ODM, we want to avoid the case where we want a
+	 *  free pipe for the left side but the free pipe is being used on the
+	 *  right side.
+	 * Add check on current_state if the primary_pipe is the left side,
+	 *  to check the right side ( primary_pipe->next_odm_pipe ) to see if
+	 *  it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe )
+	 * - If so, then don't use this pipe
+	 * EXCEPTION - 3 plane ( 2 MPO plane ) case
+	 * - in this case, the primary pipe has already gotten a free pipe for the
+	 *  MPO window in the left
+	 * - when it tries to get a free pipe for the MPO window on the right,
+	 *  it will see that it is already assigned to the right side
+	 *  ( primary_pipe->next_odm_pipe ).  But in this case, we want this
+	 *  free pipe, since it will be for the right side.  So add an
+	 *  additional condition, that skipping the free pipe on the right only
+	 *  applies if the primary pipe has no bottom pipe currently assigned
+	 */
+	if (primary_pipe) {
+		primary_index = primary_pipe->pipe_idx;
+		old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index];
+		if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe)
+			&& (!primary_pipe->bottom_pipe))
+			next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe;
+
+		preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
+		if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) &&
+			!(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) {
+			secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
+			secondary_pipe->pipe_idx = preferred_pipe_idx;
+		}
+	}
+
+	/*
+	 * search backwards for the second pipe to keep pipe
+	 * assignment more consistent
+	 */
+	if (!secondary_pipe)
+		for (i = pool->pipe_count - 1; i >= 0; i--) {
+			if ((res_ctx->pipe_ctx[i].stream == NULL) &&
+				!(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) {
+				secondary_pipe = &res_ctx->pipe_ctx[i];
+				secondary_pipe->pipe_idx = i;
+				break;
+			}
+		}
+
+	return secondary_pipe;
+}
+
+static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
+		struct dc_state *state,
+		const struct resource_pool *pool,
+		struct dc_stream_state *stream,
+		const struct pipe_ctx *head_pipe)
+{
+	struct resource_context *res_ctx = &state->res_ctx;
+	struct pipe_ctx *idle_pipe, *pipe;
+	struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx;
+	int head_index;
+
+	if (!head_pipe)
+		ASSERT(0);
+
+	/*
+	 * Modified from dcn20_acquire_idle_pipe_for_layer
+	 * Check if head_pipe in old_context already has bottom_pipe allocated.
+	 * - If so, check if that pipe is available in the current context.
+	 * --  If so, reuse pipe from old_context
+	 */
+	head_index = head_pipe->pipe_idx;
+	pipe = &old_ctx->pipe_ctx[head_index];
+	if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) {
+		idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx];
+		idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx;
+	} else {
+		idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe);
+		if (!idle_pipe)
+			return NULL;
+	}
+
+	idle_pipe->stream = head_pipe->stream;
+	idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
+	idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
+
+	idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
+	idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
+	idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
+	idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
+
+	return idle_pipe;
+}
+
 struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
 		const struct dc_state *cur_ctx,
 		struct dc_state *new_ctx,
 		const struct resource_pool *pool,
 		const struct pipe_ctx *opp_head_pipe)
 {
-	int free_pipe_idx =
-			find_optimal_free_pipe_as_secondary_dpp_pipe(
-					&cur_ctx->res_ctx, &new_ctx->res_ctx,
-					pool, opp_head_pipe);
+
+	int free_pipe_idx;
 	struct pipe_ctx *free_pipe;
 
+	if (!opp_head_pipe->stream->ctx->dc->config.enable_windowed_mpo_odm)
+		return dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
+				new_ctx, pool, opp_head_pipe->stream, opp_head_pipe);
+
+	free_pipe_idx = find_optimal_free_pipe_as_secondary_dpp_pipe(
+					&cur_ctx->res_ctx, &new_ctx->res_ctx,
+					pool, opp_head_pipe);
 	if (free_pipe_idx >= 0) {
 		free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
 		free_pipe->pipe_idx = free_pipe_idx;
-- 
2.41.0


  reply	other threads:[~2023-08-23 16:04 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
2023-08-23 15:58 ` Hamza Mahfooz [this message]
2023-08-23 15:58 ` [PATCH 02/21] drm/amd/display: Add support for 1080p SubVP to reduce idle power Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 03/21] drm/amd/display: Add smu write msg id fail retry process Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 04/21] drm/amd/display: update blank state on ODM changes Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 05/21] drm/amd/display: always switch off ODM before committing more streams Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 06/21] drm/amd/display: Add DPIA Link Encoder Assignment Fix Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 07/21] drm/amd/display: add comments to add plane functions Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 08/21] drm/amd/display: rename function to add otg master for stream Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 09/21] drm/amd/display: add new resource interface for acquiring sec opp heads and release pipe Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 10/21] drm/amd/display: add new resource interfaces to update odm mpc slice count Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 11/21] drm/amd/display: add more pipe resource interfaces Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 12/21] drm/amd/display: use new pipe allocation interface in dcn32 fpu Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 13/21] drm/amd/display: switch to new ODM policy for windowed MPO ODM support Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 14/21] drm/amd/display: add pipe topology update log Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 15/21] drm/amd/display: Remove wait while locked Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 16/21] drm/amd/display: Skip dmub memory flush when not needed Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 17/21] drm/amd/display: Fix incorrect comment Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 18/21] drm/amd/display: correct z8_watermark 16bit to 20bit mask Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 19/21] drm/amd/display: Add debugfs interface for ODM combine info Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 20/21] drm/amd/display: fix pipe topology logging error Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 21/21] drm/amd/display: 3.2.249 Hamza Mahfooz
2023-08-28 13:21 ` [PATCH 00/21] DC Patches August 23, 2023 Wheeler, Daniel

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