* [PATCH 01/21] Partially revert "drm/amd/display: update add plane to context logic with a new algorithm"
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 02/21] drm/amd/display: Add support for 1080p SubVP to reduce idle power Hamza Mahfooz
` (20 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Martin Leung, Rodrigo.Siqueira, roman.li, Wenjing Liu,
Daniel Wheeler, solomon.chiu, jerry.zuo, Aurabindo.Pillai,
hamza.mahfooz, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Wenjing Liu <wenjing.liu@amd.com>
This partially reverts commit e170066a4719 ("drm/amd/display: update add
plane to context logic with a new algorithm").
The new secondary pipe allocation logic triggers an issue with a
specific hardware state transition and causes a frame of corruption when
toggling between windowed MPO and ODM desktop only mode. Ideally hwss is
supposed to handle this scenario. We are temporarily reverting the logic
and investigate the root cause why this transition would cause
corruptions.
Reviewed-by: Martin Leung <martin.leung@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 118 +++++++++++++++++-
1 file changed, 114 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 935cd23e6a01..f9d601c8c721 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2564,18 +2564,128 @@ static int find_optimal_free_pipe_as_secondary_dpp_pipe(
return free_pipe_idx;
}
+static struct pipe_ctx *find_idle_secondary_pipe_check_mpo(
+ struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+ const struct pipe_ctx *primary_pipe)
+{
+ int i;
+ struct pipe_ctx *secondary_pipe = NULL;
+ struct pipe_ctx *next_odm_mpo_pipe = NULL;
+ int primary_index, preferred_pipe_idx;
+ struct pipe_ctx *old_primary_pipe = NULL;
+
+ /*
+ * Modified from find_idle_secondary_pipe
+ * With windowed MPO and ODM, we want to avoid the case where we want a
+ * free pipe for the left side but the free pipe is being used on the
+ * right side.
+ * Add check on current_state if the primary_pipe is the left side,
+ * to check the right side ( primary_pipe->next_odm_pipe ) to see if
+ * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe )
+ * - If so, then don't use this pipe
+ * EXCEPTION - 3 plane ( 2 MPO plane ) case
+ * - in this case, the primary pipe has already gotten a free pipe for the
+ * MPO window in the left
+ * - when it tries to get a free pipe for the MPO window on the right,
+ * it will see that it is already assigned to the right side
+ * ( primary_pipe->next_odm_pipe ). But in this case, we want this
+ * free pipe, since it will be for the right side. So add an
+ * additional condition, that skipping the free pipe on the right only
+ * applies if the primary pipe has no bottom pipe currently assigned
+ */
+ if (primary_pipe) {
+ primary_index = primary_pipe->pipe_idx;
+ old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index];
+ if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe)
+ && (!primary_pipe->bottom_pipe))
+ next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe;
+
+ preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
+ if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) &&
+ !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) {
+ secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
+ secondary_pipe->pipe_idx = preferred_pipe_idx;
+ }
+ }
+
+ /*
+ * search backwards for the second pipe to keep pipe
+ * assignment more consistent
+ */
+ if (!secondary_pipe)
+ for (i = pool->pipe_count - 1; i >= 0; i--) {
+ if ((res_ctx->pipe_ctx[i].stream == NULL) &&
+ !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) {
+ secondary_pipe = &res_ctx->pipe_ctx[i];
+ secondary_pipe->pipe_idx = i;
+ break;
+ }
+ }
+
+ return secondary_pipe;
+}
+
+static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
+ struct dc_state *state,
+ const struct resource_pool *pool,
+ struct dc_stream_state *stream,
+ const struct pipe_ctx *head_pipe)
+{
+ struct resource_context *res_ctx = &state->res_ctx;
+ struct pipe_ctx *idle_pipe, *pipe;
+ struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx;
+ int head_index;
+
+ if (!head_pipe)
+ ASSERT(0);
+
+ /*
+ * Modified from dcn20_acquire_idle_pipe_for_layer
+ * Check if head_pipe in old_context already has bottom_pipe allocated.
+ * - If so, check if that pipe is available in the current context.
+ * -- If so, reuse pipe from old_context
+ */
+ head_index = head_pipe->pipe_idx;
+ pipe = &old_ctx->pipe_ctx[head_index];
+ if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) {
+ idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx];
+ idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx;
+ } else {
+ idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe);
+ if (!idle_pipe)
+ return NULL;
+ }
+
+ idle_pipe->stream = head_pipe->stream;
+ idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
+ idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
+
+ idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
+ idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
+ idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
+ idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
+
+ return idle_pipe;
+}
+
struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
const struct dc_state *cur_ctx,
struct dc_state *new_ctx,
const struct resource_pool *pool,
const struct pipe_ctx *opp_head_pipe)
{
- int free_pipe_idx =
- find_optimal_free_pipe_as_secondary_dpp_pipe(
- &cur_ctx->res_ctx, &new_ctx->res_ctx,
- pool, opp_head_pipe);
+
+ int free_pipe_idx;
struct pipe_ctx *free_pipe;
+ if (!opp_head_pipe->stream->ctx->dc->config.enable_windowed_mpo_odm)
+ return dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
+ new_ctx, pool, opp_head_pipe->stream, opp_head_pipe);
+
+ free_pipe_idx = find_optimal_free_pipe_as_secondary_dpp_pipe(
+ &cur_ctx->res_ctx, &new_ctx->res_ctx,
+ pool, opp_head_pipe);
if (free_pipe_idx >= 0) {
free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
free_pipe->pipe_idx = free_pipe_idx;
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 02/21] drm/amd/display: Add support for 1080p SubVP to reduce idle power
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 01/21] Partially revert "drm/amd/display: update add plane to context logic with a new algorithm" Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 03/21] drm/amd/display: Add smu write msg id fail retry process Hamza Mahfooz
` (19 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, Alvin Lee, Daniel Wheeler,
solomon.chiu, jerry.zuo, Aurabindo.Pillai, hamza.mahfooz,
wayne.lin, Bhawanpreet.Lakha, Ethan Bitnun, agustin.gutierrez,
pavle.kotarac
From: Ethan Bitnun <ethan.bitnun@amd.com>
- Override the det to adjust microschedule timings allow for
1080p configs with SubVP
- To lower unnecessary risk, we prevent multi 1080p configs
from using SubVP, as multi 1080p already has low idle power.
- Count the number of streams to verify that we are in a
SubVP config before overriding
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Ethan Bitnun <ethan.bitnun@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_stream.c | 2 +-
.../drm/amd/display/dc/dcn32/dcn32_resource.h | 2 +-
.../display/dc/dcn32/dcn32_resource_helpers.c | 46 +++++++++++++++++++
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 3 +-
4 files changed, 50 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 01fe2d2fd241..dad1c85a1df3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -322,7 +322,7 @@ static bool is_subvp_high_refresh_candidate(struct dc_stream_state *stream)
* then cause corruption.
*/
if ((refresh_rate >= 120 && refresh_rate <= 175 &&
- stream->timing.v_addressable >= 1440 &&
+ stream->timing.v_addressable >= 1080 &&
stream->timing.v_addressable <= 2160) &&
(dc->current_state->stream_count > 1 ||
(dc->current_state->stream_count == 1 && !stream->allow_freesync)))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
index 103a2b54d025..0c6ca3da66d9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -38,7 +38,7 @@
#define DCN3_2_MBLK_HEIGHT_4BPE 128
#define DCN3_2_MBLK_HEIGHT_8BPE 64
#define DCN3_2_DCFCLK_DS_INIT_KHZ 10000 // Choose 10Mhz for init DCFCLK DS freq
-#define SUBVP_HIGH_REFRESH_LIST_LEN 3
+#define SUBVP_HIGH_REFRESH_LIST_LEN 4
#define DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ 1800
#define DCN3_2_VMIN_DISPCLK_HZ 717000000
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 3ad2b48954e0..f5705b3e6e42 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -255,6 +255,51 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
return psr_capable;
}
+static void override_det_for_subvp(struct dc *dc, struct dc_state *context, uint8_t pipe_segments[])
+{
+ uint32_t i;
+ uint8_t fhd_count = 0;
+ uint8_t subvp_high_refresh_count = 0;
+ uint8_t stream_count = 0;
+
+ // Do not override if a stream has multiple planes
+ for (i = 0; i < context->stream_count; i++) {
+ if (context->stream_status[i].plane_count > 1) {
+ return;
+ }
+ if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) {
+ stream_count++;
+ }
+ }
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+ if (pipe_ctx->stream && pipe_ctx->plane_state && pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) {
+ if (dcn32_allow_subvp_high_refresh_rate(dc, context, pipe_ctx)) {
+
+ if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {
+ fhd_count++;
+ }
+ subvp_high_refresh_count++;
+ }
+ }
+ }
+
+ if (stream_count == 2 && subvp_high_refresh_count == 2 && fhd_count == 1) {
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+ if (pipe_ctx->stream && pipe_ctx->plane_state && pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) {
+ if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {
+ if (pipe_segments[i] > 4)
+ pipe_segments[i] = 4;
+ }
+ }
+ }
+ }
+}
+
/**
* dcn32_determine_det_override(): Determine DET allocation for each pipe
*
@@ -336,6 +381,7 @@ void dcn32_determine_det_override(struct dc *dc,
}
}
+ override_det_for_subvp(dc, context, pipe_segments);
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
continue;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index b3252db43ecb..96e3075e6dd0 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -41,7 +41,8 @@ static const struct subvp_high_refresh_list subvp_high_refresh_list = {
.res = {
{.width = 3840, .height = 2160, },
{.width = 3440, .height = 1440, },
- {.width = 2560, .height = 1440, }},
+ {.width = 2560, .height = 1440, },
+ {.width = 1920, .height = 1080, }},
};
struct _vcs_dpi_ip_params_st dcn3_2_ip = {
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 03/21] drm/amd/display: Add smu write msg id fail retry process
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 01/21] Partially revert "drm/amd/display: update add plane to context logic with a new algorithm" Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 02/21] drm/amd/display: Add support for 1080p SubVP to reduce idle power Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 04/21] drm/amd/display: update blank state on ODM changes Hamza Mahfooz
` (18 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Fudong Wang, Charlene Liu, Sunpeng.Li,
Harry.Wentland, qingqing.zhuo, Rodrigo.Siqueira, roman.li, stable,
Daniel Wheeler, solomon.chiu, jerry.zuo, Aurabindo.Pillai,
hamza.mahfooz, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Fudong Wang <fudong.wang@amd.com>
A benchmark stress test (12-40 machines x 48hours) found that DCN315 has
cases where DC writes to an indirect register to set the smu clock msg
id, but when we go to read the same indirect register the returned msg
id doesn't match with what we just set it to. So, to fix this retry the
write until the register's value matches with the requested value.
Cc: stable@vger.kernel.org # 6.1+
Fixes: f94903996140 ("drm/amd/display: Add DCN315 CLK_MGR")
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Fudong Wang <fudong.wang@amd.com>
---
.../display/dc/clk_mgr/dcn315/dcn315_smu.c | 20 +++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
index 3e0da873cf4c..1042cf1a3ab0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
@@ -32,6 +32,7 @@
#define MAX_INSTANCE 6
#define MAX_SEGMENT 6
+#define SMU_REGISTER_WRITE_RETRY_COUNT 5
struct IP_BASE_INSTANCE {
unsigned int segment[MAX_SEGMENT];
@@ -132,6 +133,8 @@ static int dcn315_smu_send_msg_with_param(
unsigned int msg_id, unsigned int param)
{
uint32_t result;
+ uint32_t i = 0;
+ uint32_t read_back_data;
result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
@@ -148,10 +151,19 @@ static int dcn315_smu_send_msg_with_param(
/* Set the parameter register for the SMU message, unit is Mhz */
REG_WRITE(MP1_SMN_C2PMSG_37, param);
- /* Trigger the message transaction by writing the message ID */
- generic_write_indirect_reg(CTX,
- REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
- mmMP1_C2PMSG_3, msg_id);
+ for (i = 0; i < SMU_REGISTER_WRITE_RETRY_COUNT; i++) {
+ /* Trigger the message transaction by writing the message ID */
+ generic_write_indirect_reg(CTX,
+ REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
+ mmMP1_C2PMSG_3, msg_id);
+ read_back_data = generic_read_indirect_reg(CTX,
+ REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
+ mmMP1_C2PMSG_3);
+ if (read_back_data == msg_id)
+ break;
+ udelay(2);
+ smu_print("SMU msg id write fail %x times. \n", i + 1);
+ }
result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 04/21] drm/amd/display: update blank state on ODM changes
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (2 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 03/21] drm/amd/display: Add smu write msg id fail retry process Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 05/21] drm/amd/display: always switch off ODM before committing more streams Hamza Mahfooz
` (17 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Dillon Varone, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, roman.li, stable, Wenjing Liu,
Daniel Wheeler, solomon.chiu, jerry.zuo, Aurabindo.Pillai,
hamza.mahfooz, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Wenjing Liu <wenjing.liu@amd.com>
When we are dynamically adding new ODM slices, we didn't update
blank state, if the pipe used by new ODM slice is previously blanked,
we will continue outputting blank pixel data on that slice causing
right half of the screen showing blank image.
The previous fix was a temporary hack to directly update current state
when committing new state. This could potentially cause hw and sw
state synchronization issues and it is not permitted by dc commit
design.
Cc: stable@vger.kernel.org
Fixes: 7fbf451e7639 ("drm/amd/display: Reinit DPG when exiting dynamic ODM")
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 36 +++++--------------
1 file changed, 9 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index d3caba52d2fc..f3db16cd10db 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1106,29 +1106,6 @@ void dcn20_blank_pixel_data(
v_active,
offset);
- if (!blank && dc->debug.enable_single_display_2to1_odm_policy) {
- /* when exiting dynamic ODM need to reinit DPG state for unused pipes */
- struct pipe_ctx *old_odm_pipe = dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx].next_odm_pipe;
-
- odm_pipe = pipe_ctx->next_odm_pipe;
-
- while (old_odm_pipe) {
- if (!odm_pipe || old_odm_pipe->pipe_idx != odm_pipe->pipe_idx)
- dc->hwss.set_disp_pattern_generator(dc,
- old_odm_pipe,
- CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
- CONTROLLER_DP_COLOR_SPACE_UDEFINED,
- COLOR_DEPTH_888,
- NULL,
- 0,
- 0,
- 0);
- old_odm_pipe = old_odm_pipe->next_odm_pipe;
- if (odm_pipe)
- odm_pipe = odm_pipe->next_odm_pipe;
- }
- }
-
if (!blank)
if (stream_res->abm) {
dc->hwss.set_pipe(pipe_ctx);
@@ -1732,11 +1709,16 @@ static void dcn20_program_pipe(
struct dc_state *context)
{
struct dce_hwseq *hws = dc->hwseq;
- /* Only need to unblank on top pipe */
- if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
- && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
- hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
+ /* Only need to unblank on top pipe */
+ if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) {
+ if (pipe_ctx->update_flags.bits.enable ||
+ pipe_ctx->update_flags.bits.odm ||
+ pipe_ctx->stream->update_flags.bits.abm_level)
+ hws->funcs.blank_pixel_data(dc, pipe_ctx,
+ !pipe_ctx->plane_state ||
+ !pipe_ctx->plane_state->visible);
+ }
/* Only update TG on top pipe */
if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 05/21] drm/amd/display: always switch off ODM before committing more streams
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (3 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 04/21] drm/amd/display: update blank state on ODM changes Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 06/21] drm/amd/display: Add DPIA Link Encoder Assignment Fix Hamza Mahfooz
` (16 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Dillon Varone, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, roman.li, stable, Wenjing Liu,
Daniel Wheeler, solomon.chiu, jerry.zuo, Aurabindo.Pillai,
hamza.mahfooz, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Wenjing Liu <wenjing.liu@amd.com>
ODM power optimization is only supported with single stream. When ODM
power optimization is enabled, we might not have enough free pipes for
enabling other stream. So when we are committing more than 1 stream we
should first switch off ODM power optimization to make room for new
stream and then allocating pipe resource for the new stream.
Cc: stable@vger.kernel.org
Fixes: 4fbcb04a2ff5 ("drm/amd/display: add ODM case when looking for first split pipe")
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 025e0fdf486d..c6f6dc972c2a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2073,12 +2073,12 @@ enum dc_status dc_commit_streams(struct dc *dc,
}
}
- /* Check for case where we are going from odm 2:1 to max
- * pipe scenario. For these cases, we will call
- * commit_minimal_transition_state() to exit out of odm 2:1
- * first before processing new streams
+ /* ODM Combine 2:1 power optimization is only applied for single stream
+ * scenario, it uses extra pipes than needed to reduce power consumption
+ * We need to switch off this feature to make room for new streams.
*/
- if (stream_count == dc->res_pool->pipe_count) {
+ if (stream_count > dc->current_state->stream_count &&
+ dc->current_state->stream_count == 1) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->next_odm_pipe)
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 06/21] drm/amd/display: Add DPIA Link Encoder Assignment Fix
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (4 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 05/21] drm/amd/display: always switch off ODM before committing more streams Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 07/21] drm/amd/display: add comments to add plane functions Hamza Mahfooz
` (15 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
George Shen, Rodrigo.Siqueira, roman.li, Daniel Wheeler,
solomon.chiu, jerry.zuo, Aurabindo.Pillai, hamza.mahfooz,
wayne.lin, Mustapha Ghaddar, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Mustapha Ghaddar <mghaddar@amd.com>
For DPIA we should have preferred DIG assignment based on DPIA selected
as per the ASIC design.
Reviewed-by: George Shen <george.shen@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Mustapha Ghaddar <mghaddar@amd.com>
---
.../drm/amd/display/dc/core/dc_link_enc_cfg.c | 35 +++++++++++++++----
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../amd/display/dc/dcn314/dcn314_resource.c | 23 ++++++++++++
.../gpu/drm/amd/display/dc/inc/core_types.h | 1 +
.../drm/amd/display/dc/link/link_factory.c | 4 +++
5 files changed, 58 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
index 30c0644d4418..b66eeac4d3d2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
@@ -169,11 +169,23 @@ static void add_link_enc_assignment(
/* Return first available DIG link encoder. */
static enum engine_id find_first_avail_link_enc(
const struct dc_context *ctx,
- const struct dc_state *state)
+ const struct dc_state *state,
+ enum engine_id eng_id_requested)
{
enum engine_id eng_id = ENGINE_ID_UNKNOWN;
int i;
+ if (eng_id_requested != ENGINE_ID_UNKNOWN) {
+
+ for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) {
+ eng_id = state->res_ctx.link_enc_cfg_ctx.link_enc_avail[i];
+ if (eng_id == eng_id_requested)
+ return eng_id;
+ }
+ }
+
+ eng_id = ENGINE_ID_UNKNOWN;
+
for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) {
eng_id = state->res_ctx.link_enc_cfg_ctx.link_enc_avail[i];
if (eng_id != ENGINE_ID_UNKNOWN)
@@ -287,7 +299,7 @@ void link_enc_cfg_link_encs_assign(
struct dc_stream_state *streams[],
uint8_t stream_count)
{
- enum engine_id eng_id = ENGINE_ID_UNKNOWN;
+ enum engine_id eng_id = ENGINE_ID_UNKNOWN, eng_id_req = ENGINE_ID_UNKNOWN;
int i;
int j;
@@ -377,8 +389,15 @@ void link_enc_cfg_link_encs_assign(
* assigned to that endpoint.
*/
link_enc = get_link_enc_used_by_link(state, stream->link);
- if (link_enc == NULL)
- eng_id = find_first_avail_link_enc(stream->ctx, state);
+ if (link_enc == NULL) {
+
+ if (stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
+ stream->link->dpia_preferred_eng_id != ENGINE_ID_UNKNOWN)
+ eng_id_req = stream->link->dpia_preferred_eng_id;
+
+ if (eng_id == ENGINE_ID_UNKNOWN)
+ eng_id = find_first_avail_link_enc(stream->ctx, state, eng_id_req);
+ }
else
eng_id = link_enc->preferred_engine;
@@ -402,7 +421,9 @@ void link_enc_cfg_link_encs_assign(
DC_LOG_DEBUG("%s: CUR %s(%d) - enc_id(%d)\n",
__func__,
assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? "PHY" : "DPIA",
- assignment.ep_id.link_id.enum_id - 1,
+ assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ?
+ assignment.ep_id.link_id.enum_id :
+ assignment.ep_id.link_id.enum_id - 1,
assignment.eng_id);
}
for (i = 0; i < MAX_PIPES; i++) {
@@ -413,7 +434,9 @@ void link_enc_cfg_link_encs_assign(
DC_LOG_DEBUG("%s: NEW %s(%d) - enc_id(%d)\n",
__func__,
assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? "PHY" : "DPIA",
- assignment.ep_id.link_id.enum_id - 1,
+ assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ?
+ assignment.ep_id.link_id.enum_id :
+ assignment.ep_id.link_id.enum_id - 1,
assignment.eng_id);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 9f9e8da3e4db..5d41a14844da 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1496,6 +1496,7 @@ struct dc_link {
* object creation.
*/
enum engine_id eng_id;
+ enum engine_id dpia_preferred_eng_id;
bool test_pattern_enabled;
enum dp_test_pattern current_test_pattern;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 1c1fb2fa0822..004beed9bd44 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -1032,6 +1032,28 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
};
+/* ========================================================== */
+
+/*
+ * DPIA index | Preferred Encoder | Host Router
+ * 0 | C | 0
+ * 1 | First Available | 0
+ * 2 | D | 1
+ * 3 | First Available | 1
+ */
+/* ========================================================== */
+static const enum engine_id dpia_to_preferred_enc_id_table[] = {
+ ENGINE_ID_DIGC,
+ ENGINE_ID_DIGC,
+ ENGINE_ID_DIGD,
+ ENGINE_ID_DIGD
+};
+
+static enum engine_id dcn314_get_preferred_eng_id_dpia(unsigned int dpia_index)
+{
+ return dpia_to_preferred_enc_id_table[dpia_index];
+}
+
static struct dce_i2c_hw *dcn31_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst)
@@ -1785,6 +1807,7 @@ static struct resource_funcs dcn314_res_pool_funcs = {
.update_bw_bounding_box = dcn314_update_bw_bounding_box,
.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
.get_panel_config_defaults = dcn314_get_panel_config_defaults,
+ .get_preferred_eng_id_dpia = dcn314_get_preferred_eng_id_dpia,
};
static struct clock_source *dcn30_clock_source_create(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 7f9c75ffda18..b55848480485 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -65,6 +65,7 @@ struct resource_context;
struct clk_bw_params;
struct resource_funcs {
+ enum engine_id (*get_preferred_eng_id_dpia)(unsigned int dpia_index);
void (*destroy)(struct resource_pool **pool);
void (*link_init)(struct dc_link *link);
struct panel_cntl*(*panel_cntl_create)(
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
index 11b5ac218154..e406561c2c23 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
@@ -792,6 +792,10 @@ static bool construct_dpia(struct dc_link *link,
/* Set dpia port index : 0 to number of dpia ports */
link->ddc_hw_inst = init_params->connector_index;
+ // Assign Dpia preferred eng_id
+ if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia)
+ link->dpia_preferred_eng_id = link->dc->res_pool->funcs->get_preferred_eng_id_dpia(link->ddc_hw_inst);
+
/* TODO: Create link encoder */
link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 07/21] drm/amd/display: add comments to add plane functions
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (5 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 06/21] drm/amd/display: Add DPIA Link Encoder Assignment Fix Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 08/21] drm/amd/display: rename function to add otg master for stream Hamza Mahfooz
` (14 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, Wenjing Liu, Daniel Wheeler,
solomon.chiu, jerry.zuo, Aurabindo.Pillai, hamza.mahfooz,
wayne.lin, Jun Lei, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Wenjing Liu <wenjing.liu@amd.com>
Adding detail comments describing the problem we are solving with add
plane function.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 91 ++++++++++++++-----
1 file changed, 70 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index f7b51aca6020..e4fb76d8e603 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1828,6 +1828,30 @@ static int acquire_first_split_pipe(
return UNABLE_TO_SPLIT;
}
+/* For each OPP head of an OTG master, add top plane at plane index 0.
+ *
+ * In the following example, the stream has 2 ODM slices without a top plane.
+ * By adding a plane 0 to OPP heads, we are configuring our hardware to render
+ * plane 0 by using each OPP head's DPP.
+ *
+ * Inter-pipe Relation (Before Adding Plane)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | | slice 0 | |
+ * | 0 | |blank ----ODM----------- |
+ * | | | slice 1 | | |
+ * | 1 | |blank ---- | |
+ * |________|_______________|___________|_____________|
+ *
+ * Inter-pipe Relation (After Adding Plane)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | plane 0 | slice 0 | |
+ * | 0 | -------------------------ODM----------- |
+ * | | plane 0 | slice 1 | | |
+ * | 1 | ------------------------- | |
+ * |________|_______________|___________|_____________|
+ */
static bool add_plane_to_opp_head_pipes(struct pipe_ctx *otg_master_pipe,
struct dc_plane_state *plane_state,
struct dc_state *context)
@@ -1846,24 +1870,36 @@ static bool add_plane_to_opp_head_pipes(struct pipe_ctx *otg_master_pipe,
return true;
}
-static void insert_secondary_dpp_pipe_with_plane(struct pipe_ctx *opp_head_pipe,
- struct pipe_ctx *sec_pipe, struct dc_plane_state *plane_state)
-{
- struct pipe_ctx *tail_pipe = get_tail_pipe(opp_head_pipe);
-
- tail_pipe->bottom_pipe = sec_pipe;
- sec_pipe->top_pipe = tail_pipe;
- if (tail_pipe->prev_odm_pipe) {
- ASSERT(tail_pipe->prev_odm_pipe->bottom_pipe);
- sec_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
- tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = sec_pipe;
- }
- sec_pipe->plane_state = plane_state;
-}
-
-/* for each opp head pipe of an otg master pipe, acquire a secondary dpp pipe
- * and add the plane. So the plane is added to all MPC blend trees associated
- * with the otg master pipe.
+/* For each OPP head of an OTG master, acquire a secondary DPP pipe and add
+ * the plane. So the plane is added to all ODM slices associated with the OTG
+ * master pipe in the bottom layer.
+ *
+ * In the following example, the stream has 2 ODM slices and a top plane 0.
+ * By acquiring secondary DPP pipes and adding a plane 1, we are configuring our
+ * hardware to render the plane 1 by acquiring a new pipe for each ODM slice and
+ * render plane 1 using new pipes' DPP in the Z axis below plane 0.
+ *
+ * Inter-pipe Relation (Before Adding Plane)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | plane 0 | slice 0 | |
+ * | 0 | -------------------------ODM----------- |
+ * | | plane 0 | slice 1 | | |
+ * | 1 | ------------------------- | |
+ * |________|_______________|___________|_____________|
+ *
+ * Inter-pipe Relation (After Acquiring and Adding Plane)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | plane 0 | slice 0 | |
+ * | 0 | -------------MPC---------ODM----------- |
+ * | | plane 1 | | | | |
+ * | 2 | ------------- | | | |
+ * | | plane 0 | slice 1 | | |
+ * | 1 | -------------MPC--------- | |
+ * | | plane 1 | | | |
+ * | 3 | ------------- | | |
+ * |________|_______________|___________|_____________|
*/
static bool acquire_secondary_dpp_pipes_and_add_plane(
struct pipe_ctx *otg_master_pipe,
@@ -1872,7 +1908,7 @@ static bool acquire_secondary_dpp_pipes_and_add_plane(
struct dc_state *cur_ctx,
struct resource_pool *pool)
{
- struct pipe_ctx *opp_head_pipe, *sec_pipe;
+ struct pipe_ctx *opp_head_pipe, *sec_pipe, *tail_pipe;
if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe)
return false;
@@ -1897,8 +1933,21 @@ static bool acquire_secondary_dpp_pipes_and_add_plane(
if (!sec_pipe)
return false;
- insert_secondary_dpp_pipe_with_plane(opp_head_pipe, sec_pipe,
- plane_state);
+ sec_pipe->plane_state = plane_state;
+
+ /* establish pipe relationship */
+ tail_pipe = get_tail_pipe(opp_head_pipe);
+ tail_pipe->bottom_pipe = sec_pipe;
+ sec_pipe->top_pipe = tail_pipe;
+ sec_pipe->bottom_pipe = NULL;
+ if (tail_pipe->prev_odm_pipe) {
+ ASSERT(tail_pipe->prev_odm_pipe->bottom_pipe);
+ sec_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
+ tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = sec_pipe;
+ } else {
+ sec_pipe->prev_odm_pipe = NULL;
+ }
+
opp_head_pipe = opp_head_pipe->next_odm_pipe;
}
return true;
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 08/21] drm/amd/display: rename function to add otg master for stream
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (6 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 07/21] drm/amd/display: add comments to add plane functions Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 09/21] drm/amd/display: add new resource interface for acquiring sec opp heads and release pipe Hamza Mahfooz
` (13 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, Wenjing Liu, Daniel Wheeler,
solomon.chiu, jerry.zuo, Aurabindo.Pillai, hamza.mahfooz,
wayne.lin, Jun Lei, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Wenjing Liu <wenjing.liu@amd.com>
We are renaming acquire first free pipe to add
otg master pipe for stream because the former name
doesn't indicate that it acquires the first free pipe
to use as an otg master pipe. This could cause coding
errors if someone uses it to acquire a different pipe type.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 113 +++++++++++-------
1 file changed, 69 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index e4fb76d8e603..a2705771d790 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1825,7 +1825,7 @@ static int acquire_first_split_pipe(
return i;
}
}
- return UNABLE_TO_SPLIT;
+ return FREE_PIPE_INDEX_NOT_FOUND;
}
/* For each OPP head of an OTG master, add top plane at plane index 0.
@@ -1953,6 +1953,66 @@ static bool acquire_secondary_dpp_pipes_and_add_plane(
return true;
}
+/*
+ * Acquire a pipe as OTG master and assign to the stream in new dc context.
+ * return - true if OTG master pipe is acquired and new dc context is updated.
+ * false if it fails to acquire an OTG master pipe for this stream.
+ *
+ * In the example below, we acquired pipe 0 as OTG master pipe for the stream.
+ * After the function its Inter-pipe Relation is represented by the diagram
+ * below.
+ *
+ * Inter-pipe Relation
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | | | |
+ * | 0 | |blank ------------------ |
+ * |________|_______________|___________|_____________|
+ */
+static bool acquire_otg_master_pipe_for_stream(
+ struct dc_state *new_ctx,
+ const struct resource_pool *pool,
+ struct dc_stream_state *stream)
+{
+ /* TODO: Move this function to DCN specific resource file and acquire
+ * DSC resource here. The reason is that the function should have the
+ * same level of responsibility as when we acquire secondary OPP head.
+ * We acquire DSC when we acquire secondary OPP head, so we should
+ * acquire DSC when we acquire OTG master.
+ */
+ int pipe_idx;
+ struct pipe_ctx *pipe_ctx = NULL;
+
+ pipe_idx = resource_find_any_free_pipe(&new_ctx->res_ctx, pool);
+ if (pipe_idx != FREE_PIPE_INDEX_NOT_FOUND) {
+ pipe_ctx = &new_ctx->res_ctx.pipe_ctx[pipe_idx];
+ memset(pipe_ctx, 0, sizeof(*pipe_ctx));
+ pipe_ctx->pipe_idx = pipe_idx;
+ pipe_ctx->stream_res.tg = pool->timing_generators[pipe_idx];
+ pipe_ctx->plane_res.mi = pool->mis[pipe_idx];
+ pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx];
+ pipe_ctx->plane_res.ipp = pool->ipps[pipe_idx];
+ pipe_ctx->plane_res.xfm = pool->transforms[pipe_idx];
+ pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx];
+ pipe_ctx->stream_res.opp = pool->opps[pipe_idx];
+ if (pool->dpps[pipe_idx])
+ pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
+
+ if (pipe_idx >= pool->timing_generator_count) {
+ int tg_inst = pool->timing_generator_count - 1;
+
+ pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
+ pipe_ctx->stream_res.opp = pool->opps[tg_inst];
+ }
+
+ pipe_ctx->stream = stream;
+ } else {
+ pipe_idx = acquire_first_split_pipe(&new_ctx->res_ctx, pool, stream);
+ }
+
+ return pipe_idx != FREE_PIPE_INDEX_NOT_FOUND;
+}
+
bool dc_add_plane_to_context(
const struct dc *dc,
struct dc_stream_state *stream,
@@ -2372,42 +2432,6 @@ void update_audio_usage(
}
}
-static int acquire_first_free_pipe(
- struct resource_context *res_ctx,
- const struct resource_pool *pool,
- struct dc_stream_state *stream)
-{
- int i;
-
- for (i = 0; i < pool->pipe_count; i++) {
- if (!res_ctx->pipe_ctx[i].stream) {
- struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
-
- pipe_ctx->stream_res.tg = pool->timing_generators[i];
- pipe_ctx->plane_res.mi = pool->mis[i];
- pipe_ctx->plane_res.hubp = pool->hubps[i];
- pipe_ctx->plane_res.ipp = pool->ipps[i];
- pipe_ctx->plane_res.xfm = pool->transforms[i];
- pipe_ctx->plane_res.dpp = pool->dpps[i];
- pipe_ctx->stream_res.opp = pool->opps[i];
- if (pool->dpps[i])
- pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
- pipe_ctx->pipe_idx = i;
-
- if (i >= pool->timing_generator_count) {
- int tg_inst = pool->timing_generator_count - 1;
-
- pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
- pipe_ctx->stream_res.opp = pool->opps[tg_inst];
- }
-
- pipe_ctx->stream = stream;
- return i;
- }
- }
- return -1;
-}
-
static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for_link(
struct resource_context *res_ctx,
const struct resource_pool *pool,
@@ -2770,6 +2794,7 @@ enum dc_status resource_map_pool_resources(
struct dc_context *dc_ctx = dc->ctx;
struct pipe_ctx *pipe_ctx = NULL;
int pipe_idx = -1;
+ bool acquired = false;
calculate_phy_pix_clks(stream);
@@ -2783,20 +2808,20 @@ enum dc_status resource_map_pool_resources(
if (pipe_idx < 0)
/* hw resource was assigned to other stream */
stream->apply_seamless_boot_optimization = false;
+ else
+ acquired = true;
}
- if (pipe_idx < 0)
+ if (!acquired)
/* acquire new resources */
- pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
+ acquired = acquire_otg_master_pipe_for_stream(
+ context, pool, stream);
- if (pipe_idx < 0)
- pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
+ pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
- if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
+ if (!pipe_ctx || pipe_ctx->stream_res.tg == NULL)
return DC_NO_CONTROLLER_RESOURCE;
- pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
-
pipe_ctx->stream_res.stream_enc =
dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
&context->res_ctx, pool, stream);
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 09/21] drm/amd/display: add new resource interface for acquiring sec opp heads and release pipe
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (7 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 08/21] drm/amd/display: rename function to add otg master for stream Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 10/21] drm/amd/display: add new resource interfaces to update odm mpc slice count Hamza Mahfooz
` (12 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, Wenjing Liu, Daniel Wheeler,
solomon.chiu, jerry.zuo, Aurabindo.Pillai, hamza.mahfooz,
wayne.lin, Jun Lei, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Wenjing Liu <wenjing.liu@amd.com>
[why]
We need a new algorithm for acquiring secondary opp heads for ODM combine
in dcn32 and a release pipe interface to properly release pipe resources.
[how]
add two new interfaces in DCN specific resource file.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 21 +++++
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 81 +++++++++++++++++++
.../drm/amd/display/dc/dcn32/dcn32_resource.h | 10 +++
.../gpu/drm/amd/display/dc/inc/core_types.h | 10 +++
drivers/gpu/drm/amd/display/dc/inc/resource.h | 12 +++
5 files changed, 134 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index a2705771d790..20f9da625267 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1615,6 +1615,27 @@ struct pipe_ctx *resource_find_free_secondary_pipe_legacy(
return secondary_pipe;
}
+int resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(
+ const struct resource_context *cur_res_ctx,
+ struct resource_context *new_res_ctx,
+ const struct pipe_ctx *cur_otg_master)
+{
+ const struct pipe_ctx *cur_sec_opp_head = cur_otg_master->next_odm_pipe;
+ struct pipe_ctx *new_pipe;
+ int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
+
+ while (cur_sec_opp_head) {
+ new_pipe = &new_res_ctx->pipe_ctx[cur_sec_opp_head->pipe_idx];
+ if (resource_is_pipe_type(new_pipe, FREE_PIPE)) {
+ free_pipe_idx = cur_sec_opp_head->pipe_idx;
+ break;
+ }
+ cur_sec_opp_head = cur_sec_opp_head->next_odm_pipe;
+ }
+
+ return free_pipe_idx;
+}
+
int resource_find_free_pipe_used_in_cur_mpc_blending_tree(
const struct resource_context *cur_res_ctx,
struct resource_context *new_res_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index f9d601c8c721..072c5ba4c99c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2039,6 +2039,8 @@ static struct resource_funcs dcn32_res_pool_funcs = {
.calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
.populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
+ .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
+ .release_pipe = dcn32_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
@@ -2669,6 +2671,33 @@ static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
return idle_pipe;
}
+static int find_optimal_free_pipe_as_secondary_opp_head(
+ const struct resource_context *cur_res_ctx,
+ struct resource_context *new_res_ctx,
+ const struct resource_pool *pool,
+ const struct pipe_ctx *new_otg_master)
+{
+ const struct pipe_ctx *cur_otg_master;
+ int free_pipe_idx;
+
+ cur_otg_master = &cur_res_ctx->pipe_ctx[new_otg_master->pipe_idx];
+ free_pipe_idx = resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(
+ cur_res_ctx, new_res_ctx, cur_otg_master);
+
+ /* Up until here if we have not found a free secondary pipe, we will
+ * need to wait for at least one frame to complete the transition
+ * sequence.
+ */
+ if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
+ free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(
+ cur_res_ctx, new_res_ctx, pool);
+
+ if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
+ free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool);
+
+ return free_pipe_idx;
+}
+
struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
const struct dc_state *cur_ctx,
struct dc_state *new_ctx,
@@ -2706,6 +2735,58 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
return free_pipe;
}
+struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(
+ const struct dc_state *cur_ctx,
+ struct dc_state *new_ctx,
+ const struct resource_pool *pool,
+ const struct pipe_ctx *otg_master)
+{
+ int free_pipe_idx = find_optimal_free_pipe_as_secondary_opp_head(
+ &cur_ctx->res_ctx, &new_ctx->res_ctx,
+ pool, otg_master);
+ struct pipe_ctx *free_pipe;
+
+ if (free_pipe_idx >= 0) {
+ free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
+ free_pipe->pipe_idx = free_pipe_idx;
+ free_pipe->stream = otg_master->stream;
+ free_pipe->stream_res.tg = otg_master->stream_res.tg;
+ free_pipe->stream_res.dsc = NULL;
+ free_pipe->stream_res.opp = pool->opps[free_pipe_idx];
+ free_pipe->plane_res.mi = pool->mis[free_pipe_idx];
+ free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx];
+ free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx];
+ free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx];
+ free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx];
+ free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst;
+ if (free_pipe->stream->timing.flags.DSC == 1) {
+ dcn20_acquire_dsc(free_pipe->stream->ctx->dc,
+ &new_ctx->res_ctx,
+ &free_pipe->stream_res.dsc,
+ free_pipe_idx);
+ ASSERT(free_pipe->stream_res.dsc);
+ if (free_pipe->stream_res.dsc == NULL) {
+ memset(free_pipe, 0, sizeof(*free_pipe));
+ free_pipe = NULL;
+ }
+ }
+ } else {
+ ASSERT(otg_master);
+ free_pipe = NULL;
+ }
+
+ return free_pipe;
+}
+
+void dcn32_release_pipe(struct dc_state *context,
+ struct pipe_ctx *pipe,
+ const struct resource_pool *pool)
+{
+ if (resource_is_pipe_type(pipe, OPP_HEAD) && pipe->stream_res.dsc)
+ dcn20_release_dsc(&context->res_ctx, pool, &pipe->stream_res.dsc);
+ memset(pipe, 0, sizeof(*pipe));
+}
+
unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans)
{
/*
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
index 0c6ca3da66d9..4caebcaca031 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -142,6 +142,16 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
const struct resource_pool *pool,
const struct pipe_ctx *opp_head_pipe);
+struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(
+ const struct dc_state *cur_ctx,
+ struct dc_state *new_ctx,
+ const struct resource_pool *pool,
+ const struct pipe_ctx *otg_master);
+
+void dcn32_release_pipe(struct dc_state *context,
+ struct pipe_ctx *pipe,
+ const struct resource_pool *pool);
+
void dcn32_determine_det_override(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index b55848480485..77457c9c46f3 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -132,6 +132,16 @@ struct resource_funcs {
const struct resource_pool *pool,
const struct pipe_ctx *opp_head_pipe);
+ struct pipe_ctx *(*acquire_free_pipe_as_secondary_opp_head)(
+ const struct dc_state *cur_ctx,
+ struct dc_state *new_ctx,
+ const struct resource_pool *pool,
+ const struct pipe_ctx *otg_master);
+
+ void (*release_pipe)(struct dc_state *context,
+ struct pipe_ctx *pipe,
+ const struct resource_pool *pool);
+
enum dc_status (*validate_plane)(
const struct dc_plane_state *plane_state,
struct dc_caps *caps);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index e546b9c506c1..7a503d87fe9f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -280,6 +280,18 @@ bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type)
*/
bool resource_is_for_mpcc_combine(const struct pipe_ctx *pipe_ctx);
+/*
+ * Look for a free pipe in new resource context that is used as a secondary OPP
+ * head by cur_otg_master.
+ *
+ * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise
+ * pipe idx of the free pipe
+ */
+int resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(
+ const struct resource_context *cur_res_ctx,
+ struct resource_context *new_res_ctx,
+ const struct pipe_ctx *cur_otg_master);
+
/*
* Look for a free pipe in new resource context that is used as a secondary DPP
* pipe in MPC blending tree associated with input OPP head pipe.
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 10/21] drm/amd/display: add new resource interfaces to update odm mpc slice count
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (8 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 09/21] drm/amd/display: add new resource interface for acquiring sec opp heads and release pipe Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 11/21] drm/amd/display: add more pipe resource interfaces Hamza Mahfooz
` (11 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, Wenjing Liu, Daniel Wheeler,
solomon.chiu, jerry.zuo, Aurabindo.Pillai, hamza.mahfooz,
wayne.lin, Jun Lei, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Wenjing Liu <wenjing.liu@amd.com>
Define two new interfaces to update mpc and odm slice count.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 369 +++++++++++++++++-
drivers/gpu/drm/amd/display/dc/inc/resource.h | 69 +++-
2 files changed, 432 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 20f9da625267..b7ab357d1b9d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -763,7 +763,7 @@ int resource_get_num_odm_splits(const struct pipe_ctx *pipe)
return odm_split_count;
}
-static int get_odm_split_index(struct pipe_ctx *pipe_ctx)
+int resource_get_odm_split_index(struct pipe_ctx *pipe_ctx)
{
int index = 0;
@@ -779,7 +779,7 @@ static int get_odm_split_index(struct pipe_ctx *pipe_ctx)
return index;
}
-static int get_mpc_split_index(struct pipe_ctx *pipe_ctx)
+int resource_get_mpc_split_index(struct pipe_ctx *pipe_ctx)
{
struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
int index = 0;
@@ -845,7 +845,7 @@ static struct rect calculate_odm_slice_in_timing_active(struct pipe_ctx *pipe_ct
{
const struct dc_stream_state *stream = pipe_ctx->stream;
int odm_slice_count = resource_get_num_odm_splits(pipe_ctx) + 1;
- int odm_slice_idx = get_odm_split_index(pipe_ctx);
+ int odm_slice_idx = resource_get_odm_split_index(pipe_ctx);
bool is_last_odm_slice = (odm_slice_idx + 1) == odm_slice_count;
int h_active = stream->timing.h_addressable +
stream->timing.h_border_left +
@@ -963,7 +963,7 @@ static struct rect calculate_mpc_slice_in_timing_active(
{
const struct dc_stream_state *stream = pipe_ctx->stream;
int mpc_slice_count = resource_get_num_mpc_splits(pipe_ctx) + 1;
- int mpc_slice_idx = get_mpc_split_index(pipe_ctx);
+ int mpc_slice_idx = resource_get_mpc_split_index(pipe_ctx);
int epimo = mpc_slice_count - plane_clip_rec->width % mpc_slice_count - 1;
struct rect mpc_rec;
@@ -1814,6 +1814,59 @@ static struct pipe_ctx *get_tail_pipe(
return head_pipe;
}
+static struct pipe_ctx *get_last_opp_head(
+ struct pipe_ctx *opp_head)
+{
+ ASSERT(resource_is_pipe_type(opp_head, OPP_HEAD));
+ while (opp_head->next_odm_pipe)
+ opp_head = opp_head->next_odm_pipe;
+ return opp_head;
+}
+
+static struct pipe_ctx *get_last_dpp_pipe_in_mpcc_combine(
+ struct pipe_ctx *dpp_pipe)
+{
+ ASSERT(resource_is_pipe_type(dpp_pipe, DPP_PIPE));
+ while (dpp_pipe->bottom_pipe &&
+ dpp_pipe->plane_state == dpp_pipe->bottom_pipe->plane_state)
+ dpp_pipe = dpp_pipe->bottom_pipe;
+ return dpp_pipe;
+}
+
+static bool update_pipe_params_after_odm_slice_count_change(
+ const struct dc_stream_state *stream,
+ struct dc_state *context,
+ const struct resource_pool *pool)
+{
+ int i;
+ struct pipe_ctx *pipe;
+ bool result = true;
+
+ for (i = 0; i < pool->pipe_count && result; i++) {
+ pipe = &context->res_ctx.pipe_ctx[i];
+ if (pipe->stream == stream && pipe->plane_state)
+ result = resource_build_scaling_params(pipe);
+ }
+ return result;
+}
+
+static bool update_pipe_params_after_mpc_slice_count_change(
+ const struct dc_plane_state *plane,
+ struct dc_state *context,
+ const struct resource_pool *pool)
+{
+ int i;
+ struct pipe_ctx *pipe;
+ bool result = true;
+
+ for (i = 0; i < pool->pipe_count && result; i++) {
+ pipe = &context->res_ctx.pipe_ctx[i];
+ if (pipe->plane_state == plane)
+ result = resource_build_scaling_params(pipe);
+ }
+ return result;
+}
+
static int acquire_first_split_pipe(
struct resource_context *res_ctx,
const struct resource_pool *pool,
@@ -2034,6 +2087,302 @@ static bool acquire_otg_master_pipe_for_stream(
return pipe_idx != FREE_PIPE_INDEX_NOT_FOUND;
}
+/*
+ * Increase ODM slice count by 1 by acquiring pipes and adding a new ODM slice
+ * at the last index.
+ * return - true if a new ODM slice is added and required pipes are acquired.
+ * false if new_ctx is no longer a valid state after new ODM slice is added.
+ *
+ * This is achieved by duplicating MPC blending tree from previous ODM slice.
+ * In the following example, we have a single MPC tree and 1 ODM slice 0. We
+ * want to add a new odm slice by duplicating the MPC blending tree and add
+ * ODM slice 1.
+ *
+ * Inter-pipe Relation (Before Acquiring and Adding ODM Slice)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | plane 0 | slice 0 | |
+ * | 0 | -------------MPC---------ODM----------- |
+ * | | plane 1 | | | |
+ * | 1 | ------------- | | |
+ * |________|_______________|___________|_____________|
+ *
+ * Inter-pipe Relation (After Acquiring and Adding ODM Slice)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | plane 0 | slice 0 | |
+ * | 0 | -------------MPC---------ODM----------- |
+ * | | plane 1 | | | | |
+ * | 1 | ------------- | | | |
+ * | | plane 0 | slice 1 | | |
+ * | 2 | -------------MPC--------- | |
+ * | | plane 1 | | | |
+ * | 3 | ------------- | | |
+ * |________|_______________|___________|_____________|
+ */
+static bool acquire_pipes_and_add_odm_slice(
+ struct pipe_ctx *otg_master_pipe,
+ struct dc_state *new_ctx,
+ const struct dc_state *cur_ctx,
+ const struct resource_pool *pool)
+{
+ struct pipe_ctx *last_opp_head = get_last_opp_head(otg_master_pipe);
+ struct pipe_ctx *new_opp_head = pool->funcs->acquire_free_pipe_as_secondary_opp_head(
+ cur_ctx, new_ctx, pool,
+ otg_master_pipe);
+ struct pipe_ctx *last_top_dpp_pipe, *last_bottom_dpp_pipe,
+ *new_top_dpp_pipe, *new_bottom_dpp_pipe;
+
+ if (!new_opp_head)
+ return false;
+
+ last_opp_head->next_odm_pipe = new_opp_head;
+ new_opp_head->prev_odm_pipe = last_opp_head;
+ new_opp_head->next_odm_pipe = NULL;
+ new_opp_head->plane_state = last_opp_head->plane_state;
+ last_top_dpp_pipe = last_opp_head;
+ new_top_dpp_pipe = new_opp_head;
+
+ while (last_top_dpp_pipe->bottom_pipe) {
+ last_bottom_dpp_pipe = last_top_dpp_pipe->bottom_pipe;
+ new_bottom_dpp_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
+ cur_ctx, new_ctx, pool,
+ new_opp_head);
+ if (!new_bottom_dpp_pipe)
+ return false;
+
+ new_bottom_dpp_pipe->plane_state = last_bottom_dpp_pipe->plane_state;
+ new_top_dpp_pipe->bottom_pipe = new_bottom_dpp_pipe;
+ new_bottom_dpp_pipe->top_pipe = new_top_dpp_pipe;
+ last_bottom_dpp_pipe->next_odm_pipe = new_bottom_dpp_pipe;
+ new_bottom_dpp_pipe->prev_odm_pipe = last_bottom_dpp_pipe;
+ new_bottom_dpp_pipe->next_odm_pipe = NULL;
+ last_top_dpp_pipe = last_bottom_dpp_pipe;
+ }
+
+ return true;
+}
+
+/*
+ * Decrease ODM slice count by 1 by releasing pipes and removing the ODM slice
+ * at the last index.
+ * return - true if the last ODM slice is removed and related pipes are
+ * released. false if there is no removable ODM slice.
+ *
+ * In the following example, we have 2 MPC trees and ODM slice 0 and slice 1.
+ * We want to remove the last ODM i.e slice 1. We are releasing secondary DPP
+ * pipe 3 and OPP head pipe 2.
+ *
+ * Inter-pipe Relation (Before Releasing and Removing ODM Slice)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | plane 0 | slice 0 | |
+ * | 0 | -------------MPC---------ODM----------- |
+ * | | plane 1 | | | | |
+ * | 1 | ------------- | | | |
+ * | | plane 0 | slice 1 | | |
+ * | 2 | -------------MPC--------- | |
+ * | | plane 1 | | | |
+ * | 3 | ------------- | | |
+ * |________|_______________|___________|_____________|
+ *
+ * Inter-pipe Relation (After Releasing and Removing ODM Slice)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | plane 0 | slice 0 | |
+ * | 0 | -------------MPC---------ODM----------- |
+ * | | plane 1 | | | |
+ * | 1 | ------------- | | |
+ * |________|_______________|___________|_____________|
+ */
+static bool release_pipes_and_remove_odm_slice(
+ struct pipe_ctx *otg_master_pipe,
+ struct dc_state *context,
+ const struct resource_pool *pool)
+{
+ struct pipe_ctx *last_opp_head = get_last_opp_head(otg_master_pipe);
+ struct pipe_ctx *tail_pipe = get_tail_pipe(last_opp_head);
+
+ if (resource_is_pipe_type(last_opp_head, OTG_MASTER))
+ return false;
+
+ while (tail_pipe->top_pipe) {
+ tail_pipe->prev_odm_pipe->next_odm_pipe = NULL;
+ tail_pipe = tail_pipe->top_pipe;
+ pool->funcs->release_pipe(context, tail_pipe->bottom_pipe, pool);
+ tail_pipe->bottom_pipe = NULL;
+ }
+ last_opp_head->prev_odm_pipe->next_odm_pipe = NULL;
+ pool->funcs->release_pipe(context, last_opp_head, pool);
+
+ return true;
+}
+
+/*
+ * Increase MPC slice count by 1 by acquiring a new DPP pipe and add it as the
+ * last MPC slice of the plane associated with dpp_pipe.
+ *
+ * return - true if a new MPC slice is added and required pipes are acquired.
+ * false if new_ctx is no longer a valid state after new MPC slice is added.
+ *
+ * In the following example, we add a new MPC slice for plane 0 into the
+ * new_ctx. To do so we pass pipe 0 as dpp_pipe. The function acquires a new DPP
+ * pipe 2 for plane 0 as the bottom most pipe for plane 0.
+ *
+ * Inter-pipe Relation (Before Acquiring and Adding MPC Slice)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | plane 0 | | |
+ * | 0 | -------------MPC----------------------- |
+ * | | plane 1 | | | |
+ * | 1 | ------------- | | |
+ * |________|_______________|___________|_____________|
+ *
+ * Inter-pipe Relation (After Acquiring and Adding MPC Slice)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | plane 0 | | |
+ * | 0 | -------------MPC----------------------- |
+ * | | plane 0 | | | |
+ * | 2 | ------------- | | |
+ * | | plane 1 | | | |
+ * | 1 | ------------- | | |
+ * |________|_______________|___________|_____________|
+ */
+static bool acquire_dpp_pipe_and_add_mpc_slice(
+ struct pipe_ctx *dpp_pipe,
+ struct dc_state *new_ctx,
+ const struct dc_state *cur_ctx,
+ const struct resource_pool *pool)
+{
+ struct pipe_ctx *last_dpp_pipe =
+ get_last_dpp_pipe_in_mpcc_combine(dpp_pipe);
+ struct pipe_ctx *opp_head = resource_get_opp_head(dpp_pipe);
+ struct pipe_ctx *new_dpp_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
+ cur_ctx, new_ctx, pool, opp_head);
+
+ if (!new_dpp_pipe || resource_get_num_odm_splits(dpp_pipe) > 0)
+ return false;
+
+ new_dpp_pipe->bottom_pipe = last_dpp_pipe->bottom_pipe;
+ if (new_dpp_pipe->bottom_pipe)
+ new_dpp_pipe->bottom_pipe->top_pipe = new_dpp_pipe;
+ new_dpp_pipe->top_pipe = last_dpp_pipe;
+ last_dpp_pipe->bottom_pipe = new_dpp_pipe;
+ new_dpp_pipe->plane_state = last_dpp_pipe->plane_state;
+
+ return true;
+}
+
+/*
+ * Reduce MPC slice count by 1 by releasing the bottom DPP pipe in MPCC combine
+ * with dpp_pipe and removing last MPC slice of the plane associated with
+ * dpp_pipe.
+ *
+ * return - true if the last MPC slice of the plane associated with dpp_pipe is
+ * removed and last DPP pipe in MPCC combine with dpp_pipe is released.
+ * false if there is no removable MPC slice.
+ *
+ * In the following example, we remove an MPC slice for plane 0 from the
+ * context. To do so we pass pipe 0 as dpp_pipe. The function releases pipe 1 as
+ * it is the last pipe for plane 0.
+ *
+ * Inter-pipe Relation (Before Releasing and Removing MPC Slice)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | plane 0 | | |
+ * | 0 | -------------MPC----------------------- |
+ * | | plane 0 | | | |
+ * | 1 | ------------- | | |
+ * | | plane 1 | | | |
+ * | 2 | ------------- | | |
+ * |________|_______________|___________|_____________|
+ *
+ * Inter-pipe Relation (After Releasing and Removing MPC Slice)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | plane 0 | | |
+ * | 0 | -------------MPC----------------------- |
+ * | | plane 1 | | | |
+ * | 2 | ------------- | | |
+ * |________|_______________|___________|_____________|
+ */
+static bool release_dpp_pipe_and_remove_mpc_slice(
+ struct pipe_ctx *dpp_pipe,
+ struct dc_state *context,
+ const struct resource_pool *pool)
+{
+ struct pipe_ctx *last_dpp_pipe =
+ get_last_dpp_pipe_in_mpcc_combine(dpp_pipe);
+
+ if (resource_is_pipe_type(last_dpp_pipe, OPP_HEAD) ||
+ resource_get_num_odm_splits(dpp_pipe) > 0)
+ return false;
+
+ last_dpp_pipe->top_pipe->bottom_pipe = last_dpp_pipe->bottom_pipe;
+ if (last_dpp_pipe->bottom_pipe)
+ last_dpp_pipe->bottom_pipe->top_pipe = last_dpp_pipe->top_pipe;
+ pool->funcs->release_pipe(context, last_dpp_pipe, pool);
+
+ return true;
+}
+
+bool resource_update_pipes_with_odm_slice_count(
+ struct pipe_ctx *otg_master,
+ struct dc_state *new_ctx,
+ const struct dc_state *cur_ctx,
+ const struct resource_pool *pool,
+ int new_slice_count)
+{
+ int i;
+ int cur_slice_count = resource_get_num_odm_splits(otg_master) + 1;
+ bool result = true;
+
+ if (new_slice_count == cur_slice_count)
+ return result;
+
+ if (new_slice_count > cur_slice_count)
+ for (i = 0; i < new_slice_count - cur_slice_count && result; i++)
+ result = acquire_pipes_and_add_odm_slice(
+ otg_master, new_ctx, cur_ctx, pool);
+ else
+ for (i = 0; i < cur_slice_count - new_slice_count && result; i++)
+ result = release_pipes_and_remove_odm_slice(
+ otg_master, new_ctx, pool);
+ if (result)
+ result = update_pipe_params_after_odm_slice_count_change(
+ otg_master->stream, new_ctx, pool);
+ return result;
+}
+
+bool resource_update_pipes_with_mpc_slice_count(
+ struct pipe_ctx *dpp_pipe,
+ struct dc_state *new_ctx,
+ const struct dc_state *cur_ctx,
+ const struct resource_pool *pool,
+ int new_slice_count)
+{
+ int i;
+ int cur_slice_count = resource_get_num_mpc_splits(dpp_pipe) + 1;
+ bool result = true;
+
+ if (new_slice_count == cur_slice_count)
+ return result;
+
+ if (new_slice_count > cur_slice_count)
+ for (i = 0; i < new_slice_count - cur_slice_count && result; i++)
+ result = acquire_dpp_pipe_and_add_mpc_slice(
+ dpp_pipe, new_ctx, cur_ctx, pool);
+ else
+ for (i = 0; i < cur_slice_count - new_slice_count && result; i++)
+ result = release_dpp_pipe_and_remove_mpc_slice(
+ dpp_pipe, new_ctx, pool);
+ if (result)
+ result = update_pipe_params_after_mpc_slice_count_change(
+ dpp_pipe->plane_state, new_ctx, pool);
+ return result;
+}
+
bool dc_add_plane_to_context(
const struct dc *dc,
struct dc_stream_state *stream,
@@ -4342,7 +4691,17 @@ bool is_h_timing_divisible_by_2(struct dc_stream_state *stream)
return divisible;
}
-bool dc_resource_acquire_secondary_pipe_for_mpc_odm(
+/* This interface is deprecated for new DCNs. It is replaced by the following
+ * new interfaces. These two interfaces encapsulate pipe selection priority
+ * with DCN specific minimum hardware transition optimization algorithm. With
+ * the new interfaces caller no longer needs to know the implementation detail
+ * of a pipe topology.
+ *
+ * resource_update_pipes_with_odm_slice_count
+ * resource_update_pipes_with_mpc_slice_count
+ *
+ */
+bool dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy(
const struct dc *dc,
struct dc_state *state,
struct pipe_ctx *pri_pipe,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 7a503d87fe9f..4344c5a239e1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -213,6 +213,21 @@ bool resource_attach_surfaces_to_context(
* | | | | |
* | 5 | (FREE) | | |
* |________|_______________|___________|_____________|
+ *
+ * The following is a quick reference of the class relation:
+ *
+ * DC state ---1--------0..N--- streams
+ *
+ * stream ---1-----------1--- OTG Master pipe
+ *
+ * OTG Master pipe ---1--------1..N--- OPP Head pipes
+ *
+ * OPP Head pipe ---1--------0..N--- DPP pipes
+ *
+ * stream ---1--------0..N--- Planes
+ *
+ * Plane ---1--------1..N--- DPP pipes
+ *
*/
enum pipe_type {
/* free pipe - free pipe is an uninitialized pipe without a stream
@@ -354,6 +369,9 @@ struct pipe_ctx *resource_find_free_secondary_pipe_legacy(
*/
int resource_get_num_mpc_splits(const struct pipe_ctx *pipe);
+int resource_get_mpc_split_index(struct pipe_ctx *pipe_ctx);
+
+
/*
* Get number of ODM "cuts" of the timing associated with the pipe. ODM slice
* count is equal to ODM splits + 1. For example if a timing is cut 3 times, it
@@ -363,6 +381,8 @@ int resource_get_num_mpc_splits(const struct pipe_ctx *pipe);
*/
int resource_get_num_odm_splits(const struct pipe_ctx *pipe);
+int resource_get_odm_split_index(struct pipe_ctx *pipe_ctx);
+
/*
* Get the OTG master pipe in resource context associated with the stream.
* return - NULL if not found. Otherwise the OTG master pipe associated with the
@@ -386,6 +406,53 @@ struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx);
*/
struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx);
+/*
+ * Update ODM slice count by acquiring or releasing pipes. If new slices need
+ * to be added, it is going to add them to the last ODM index. If existing
+ * slices need to be removed, it is going to remove them from the last ODM
+ * index.
+ *
+ * return - true if ODM slices are updated and required pipes are acquired. All
+ * affected pipe parameters are updated.
+ *
+ * false if resource fails to complete this update. The function is not designed
+ * to recover the creation of invalid topologies. Returning false is typically
+ * an indication of insufficient validation in caller's stack. The function will
+ * return the new_ctx up until the last valid step performed in the function.
+ * Caller may use the returned new_ctx for debugging the error or it may attempt
+ * to restore new_ctx by calling this function again with original slice count.
+ */
+bool resource_update_pipes_with_odm_slice_count(
+ struct pipe_ctx *otg_master_pipe,
+ struct dc_state *new_ctx,
+ const struct dc_state *cur_ctx,
+ const struct resource_pool *pool,
+ int slice_count);
+
+/*
+ * Update MPC slice count by acquiring or releasing DPP pipes. If new slices
+ * need to be added it is going to add to the last MPC index. If existing
+ * slices need to be removed, it is going to remove them from the last MPC
+ * index.
+ *
+ * @dpp_pipe - top most dpp pipe for MPCC combine.
+ *
+ * return - true if MPC slices are updated and required pipes are acquired. All
+ * affected pipe parameters are updated.
+ *
+ * false if resource fails to complete this update. The function is not designed
+ * to recover the creation of invalid topologies. Returning false is typically
+ * an indication of insufficient validation in caller's stack. The function will
+ * return the new_ctx up until the last valid step performed in the function.
+ * Caller may use the returned new_ctx for debugging the error or it may attempt
+ * to restore new_ctx by calling this function again with original slice count.
+ */
+bool resource_update_pipes_with_mpc_slice_count(
+ struct pipe_ctx *dpp_pipe,
+ struct dc_state *new_ctx,
+ const struct dc_state *cur_ctx,
+ const struct resource_pool *pool,
+ int slice_count);
bool resource_validate_attach_surfaces(
const struct dc_validation_set set[],
@@ -451,7 +518,7 @@ const struct link_hwss *get_link_hwss(const struct dc_link *link,
bool is_h_timing_divisible_by_2(struct dc_stream_state *stream);
-bool dc_resource_acquire_secondary_pipe_for_mpc_odm(
+bool dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy(
const struct dc *dc,
struct dc_state *state,
struct pipe_ctx *pri_pipe,
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 11/21] drm/amd/display: add more pipe resource interfaces
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (9 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 10/21] drm/amd/display: add new resource interfaces to update odm mpc slice count Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 12/21] drm/amd/display: use new pipe allocation interface in dcn32 fpu Hamza Mahfooz
` (10 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, Wenjing Liu, Daniel Wheeler,
solomon.chiu, jerry.zuo, Aurabindo.Pillai, hamza.mahfooz,
wayne.lin, Jun Lei, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Wenjing Liu <wenjing.liu@amd.com>
Redesign pipe resource interfaces in resource.h file. The new interface
design addresses the issue with lack of pipe topology encapsulation and
lack of pipe accessors.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 951 ++++++++++--------
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 22 +-
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 4 +-
.../amd/display/dc/dcn201/dcn201_resource.c | 1 +
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 1 +
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 1 +
.../amd/display/dc/dcn301/dcn301_resource.c | 1 +
.../amd/display/dc/dcn302/dcn302_resource.c | 1 +
.../amd/display/dc/dcn303/dcn303_resource.c | 1 +
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 1 +
.../amd/display/dc/dcn314/dcn314_resource.c | 1 +
.../amd/display/dc/dcn315/dcn315_resource.c | 1 +
.../amd/display/dc/dcn316/dcn316_resource.c | 1 +
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 11 +-
.../amd/display/dc/dcn321/dcn321_resource.c | 1 +
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 6 +-
drivers/gpu/drm/amd/display/dc/inc/resource.h | 278 ++---
18 files changed, 740 insertions(+), 545 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index b7ab357d1b9d..84db7c5fb852 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -732,66 +732,6 @@ static inline void get_vp_scan_direction(
*flip_horz_scan_dir = !*flip_horz_scan_dir;
}
-int resource_get_num_mpc_splits(const struct pipe_ctx *pipe)
-{
- int mpc_split_count = 0;
- const struct pipe_ctx *other_pipe = pipe->bottom_pipe;
-
- while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
- mpc_split_count++;
- other_pipe = other_pipe->bottom_pipe;
- }
- other_pipe = pipe->top_pipe;
- while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
- mpc_split_count++;
- other_pipe = other_pipe->top_pipe;
- }
-
- return mpc_split_count;
-}
-
-int resource_get_num_odm_splits(const struct pipe_ctx *pipe)
-{
- int odm_split_count = 0;
-
- pipe = resource_get_otg_master(pipe);
-
- while (pipe->next_odm_pipe) {
- odm_split_count++;
- pipe = pipe->next_odm_pipe;
- }
- return odm_split_count;
-}
-
-int resource_get_odm_split_index(struct pipe_ctx *pipe_ctx)
-{
- int index = 0;
-
- pipe_ctx = resource_get_opp_head(pipe_ctx);
- if (!pipe_ctx)
- return 0;
-
- while (pipe_ctx->prev_odm_pipe) {
- index++;
- pipe_ctx = pipe_ctx->prev_odm_pipe;
- }
-
- return index;
-}
-
-int resource_get_mpc_split_index(struct pipe_ctx *pipe_ctx)
-{
- struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
- int index = 0;
-
- while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
- index++;
- split_pipe = split_pipe->top_pipe;
- }
-
- return index;
-}
-
/*
* This is a preliminary vp size calculation to allow us to check taps support.
* The result is completely overridden afterwards.
@@ -844,8 +784,8 @@ static struct rect shift_rec(const struct rect *rec_in, int x, int y)
static struct rect calculate_odm_slice_in_timing_active(struct pipe_ctx *pipe_ctx)
{
const struct dc_stream_state *stream = pipe_ctx->stream;
- int odm_slice_count = resource_get_num_odm_splits(pipe_ctx) + 1;
- int odm_slice_idx = resource_get_odm_split_index(pipe_ctx);
+ int odm_slice_count = resource_get_odm_slice_count(pipe_ctx);
+ int odm_slice_idx = resource_get_odm_slice_index(pipe_ctx);
bool is_last_odm_slice = (odm_slice_idx + 1) == odm_slice_count;
int h_active = stream->timing.h_addressable +
stream->timing.h_border_left +
@@ -962,8 +902,8 @@ static struct rect calculate_mpc_slice_in_timing_active(
struct rect *plane_clip_rec)
{
const struct dc_stream_state *stream = pipe_ctx->stream;
- int mpc_slice_count = resource_get_num_mpc_splits(pipe_ctx) + 1;
- int mpc_slice_idx = resource_get_mpc_split_index(pipe_ctx);
+ int mpc_slice_count = resource_get_mpc_slice_count(pipe_ctx);
+ int mpc_slice_idx = resource_get_mpc_slice_index(pipe_ctx);
int epimo = mpc_slice_count - plane_clip_rec->width % mpc_slice_count - 1;
struct rect mpc_rec;
@@ -1699,7 +1639,7 @@ int resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(
if (resource_is_pipe_type(cur_pipe, DPP_PIPE) &&
!resource_is_pipe_type(cur_pipe, OPP_HEAD) &&
- resource_is_for_mpcc_combine(cur_pipe) &&
+ resource_get_mpc_slice_index(cur_pipe) > 0 &&
resource_is_pipe_type(new_pipe, FREE_PIPE)) {
free_pipe_idx = i;
break;
@@ -1763,14 +1703,9 @@ bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type)
}
}
-bool resource_is_for_mpcc_combine(const struct pipe_ctx *pipe_ctx)
-{
- return resource_get_num_mpc_splits(pipe_ctx) > 0;
-}
-
struct pipe_ctx *resource_get_otg_master_for_stream(
struct resource_context *res_ctx,
- struct dc_stream_state *stream)
+ const struct dc_stream_state *stream)
{
int i;
@@ -1782,6 +1717,75 @@ struct pipe_ctx *resource_get_otg_master_for_stream(
return NULL;
}
+int resource_get_opp_heads_for_otg_master(const struct pipe_ctx *otg_master,
+ struct resource_context *res_ctx,
+ struct pipe_ctx *opp_heads[MAX_PIPES])
+{
+ struct pipe_ctx *opp_head = &res_ctx->pipe_ctx[otg_master->pipe_idx];
+ int i = 0;
+
+ if (!resource_is_pipe_type(otg_master, OTG_MASTER)) {
+ ASSERT(0);
+ return 0;
+ }
+ while (opp_head) {
+ ASSERT(i < MAX_PIPES);
+ opp_heads[i++] = opp_head;
+ opp_head = opp_head->next_odm_pipe;
+ }
+ return i;
+}
+
+int resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx *opp_head,
+ struct resource_context *res_ctx,
+ struct pipe_ctx *dpp_pipes[MAX_PIPES])
+{
+ struct pipe_ctx *pipe = &res_ctx->pipe_ctx[opp_head->pipe_idx];
+ int i = 0;
+
+ if (!resource_is_pipe_type(opp_head, OPP_HEAD)) {
+ ASSERT(0);
+ return 0;
+ }
+ while (pipe && resource_is_pipe_type(pipe, DPP_PIPE)) {
+ ASSERT(i < MAX_PIPES);
+ dpp_pipes[i++] = pipe;
+ pipe = pipe->bottom_pipe;
+ }
+ return i;
+}
+
+int resource_get_dpp_pipes_for_plane(const struct dc_plane_state *plane,
+ struct resource_context *res_ctx,
+ struct pipe_ctx *dpp_pipes[MAX_PIPES])
+{
+ int i = 0, j;
+ struct pipe_ctx *pipe;
+
+ for (j = 0; j < MAX_PIPES; j++) {
+ pipe = &res_ctx->pipe_ctx[j];
+ if (pipe->plane_state == plane && pipe->prev_odm_pipe == NULL) {
+ if (resource_is_pipe_type(pipe, OPP_HEAD) ||
+ pipe->top_pipe->plane_state != plane)
+ break;
+ }
+ }
+
+ if (j < MAX_PIPES) {
+ if (pipe->next_odm_pipe)
+ while (pipe) {
+ dpp_pipes[i++] = pipe;
+ pipe = pipe->next_odm_pipe;
+ }
+ else
+ while (pipe && pipe->plane_state == plane) {
+ dpp_pipes[i++] = pipe;
+ pipe = pipe->bottom_pipe;
+ }
+ }
+ return i;
+}
+
struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx)
{
struct pipe_ctx *otg_master = resource_get_opp_head(pipe_ctx);
@@ -1801,6 +1805,66 @@ struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx)
return opp_head;
}
+int resource_get_mpc_slice_index(const struct pipe_ctx *pipe_ctx)
+{
+ struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
+ int index = 0;
+
+ while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
+ index++;
+ split_pipe = split_pipe->top_pipe;
+ }
+
+ return index;
+}
+
+int resource_get_mpc_slice_count(const struct pipe_ctx *pipe)
+{
+ int mpc_split_count = 1;
+ const struct pipe_ctx *other_pipe = pipe->bottom_pipe;
+
+ while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
+ mpc_split_count++;
+ other_pipe = other_pipe->bottom_pipe;
+ }
+ other_pipe = pipe->top_pipe;
+ while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
+ mpc_split_count++;
+ other_pipe = other_pipe->top_pipe;
+ }
+
+ return mpc_split_count;
+}
+
+int resource_get_odm_slice_count(const struct pipe_ctx *pipe)
+{
+ int odm_split_count = 1;
+
+ pipe = resource_get_otg_master(pipe);
+
+ while (pipe->next_odm_pipe) {
+ odm_split_count++;
+ pipe = pipe->next_odm_pipe;
+ }
+ return odm_split_count;
+}
+
+int resource_get_odm_slice_index(const struct pipe_ctx *pipe_ctx)
+{
+ int index = 0;
+
+ pipe_ctx = resource_get_opp_head(pipe_ctx);
+ if (!pipe_ctx)
+ return 0;
+
+ while (pipe_ctx->prev_odm_pipe) {
+ index++;
+ pipe_ctx = pipe_ctx->prev_odm_pipe;
+ }
+
+ return index;
+}
+
static struct pipe_ctx *get_tail_pipe(
struct pipe_ctx *head_pipe)
{
@@ -1902,97 +1966,265 @@ static int acquire_first_split_pipe(
return FREE_PIPE_INDEX_NOT_FOUND;
}
-/* For each OPP head of an OTG master, add top plane at plane index 0.
- *
- * In the following example, the stream has 2 ODM slices without a top plane.
- * By adding a plane 0 to OPP heads, we are configuring our hardware to render
- * plane 0 by using each OPP head's DPP.
- *
- * Inter-pipe Relation (Before Adding Plane)
- * __________________________________________________
- * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
- * | | | slice 0 | |
- * | 0 | |blank ----ODM----------- |
- * | | | slice 1 | | |
- * | 1 | |blank ---- | |
- * |________|_______________|___________|_____________|
- *
- * Inter-pipe Relation (After Adding Plane)
- * __________________________________________________
- * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
- * | | plane 0 | slice 0 | |
- * | 0 | -------------------------ODM----------- |
- * | | plane 0 | slice 1 | | |
- * | 1 | ------------------------- | |
- * |________|_______________|___________|_____________|
- */
-static bool add_plane_to_opp_head_pipes(struct pipe_ctx *otg_master_pipe,
- struct dc_plane_state *plane_state,
- struct dc_state *context)
+static void update_stream_engine_usage(
+ struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+ struct stream_encoder *stream_enc,
+ bool acquired)
{
- struct pipe_ctx *opp_head_pipe = otg_master_pipe;
+ int i;
- while (opp_head_pipe) {
- if (opp_head_pipe->plane_state) {
- ASSERT(0);
- return false;
- }
- opp_head_pipe->plane_state = plane_state;
- opp_head_pipe = opp_head_pipe->next_odm_pipe;
+ for (i = 0; i < pool->stream_enc_count; i++) {
+ if (pool->stream_enc[i] == stream_enc)
+ res_ctx->is_stream_enc_acquired[i] = acquired;
}
+}
- return true;
+static void update_hpo_dp_stream_engine_usage(
+ struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+ struct hpo_dp_stream_encoder *hpo_dp_stream_enc,
+ bool acquired)
+{
+ int i;
+
+ for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
+ if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc)
+ res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired;
+ }
}
-/* For each OPP head of an OTG master, acquire a secondary DPP pipe and add
- * the plane. So the plane is added to all ODM slices associated with the OTG
- * master pipe in the bottom layer.
- *
- * In the following example, the stream has 2 ODM slices and a top plane 0.
- * By acquiring secondary DPP pipes and adding a plane 1, we are configuring our
- * hardware to render the plane 1 by acquiring a new pipe for each ODM slice and
- * render plane 1 using new pipes' DPP in the Z axis below plane 0.
- *
- * Inter-pipe Relation (Before Adding Plane)
- * __________________________________________________
- * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
- * | | plane 0 | slice 0 | |
- * | 0 | -------------------------ODM----------- |
- * | | plane 0 | slice 1 | | |
- * | 1 | ------------------------- | |
- * |________|_______________|___________|_____________|
- *
- * Inter-pipe Relation (After Acquiring and Adding Plane)
- * __________________________________________________
- * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
- * | | plane 0 | slice 0 | |
- * | 0 | -------------MPC---------ODM----------- |
- * | | plane 1 | | | | |
- * | 2 | ------------- | | | |
- * | | plane 0 | slice 1 | | |
- * | 1 | -------------MPC--------- | |
- * | | plane 1 | | | |
- * | 3 | ------------- | | |
- * |________|_______________|___________|_____________|
- */
-static bool acquire_secondary_dpp_pipes_and_add_plane(
- struct pipe_ctx *otg_master_pipe,
- struct dc_plane_state *plane_state,
- struct dc_state *new_ctx,
- struct dc_state *cur_ctx,
- struct resource_pool *pool)
+static inline int find_acquired_hpo_dp_link_enc_for_link(
+ const struct resource_context *res_ctx,
+ const struct dc_link *link)
{
- struct pipe_ctx *opp_head_pipe, *sec_pipe, *tail_pipe;
+ int i;
- if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe)
- return false;
+ for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_to_link_idx); i++)
+ if (res_ctx->hpo_dp_link_enc_ref_cnts[i] > 0 &&
+ res_ctx->hpo_dp_link_enc_to_link_idx[i] == link->link_index)
+ return i;
- opp_head_pipe = otg_master_pipe;
- while (opp_head_pipe) {
- sec_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
- cur_ctx,
- new_ctx,
- pool,
+ return -1;
+}
+
+static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx,
+ const struct resource_pool *pool)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++)
+ if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0)
+ break;
+
+ return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) &&
+ i < pool->hpo_dp_link_enc_count) ? i : -1;
+}
+
+static inline void acquire_hpo_dp_link_enc(
+ struct resource_context *res_ctx,
+ unsigned int link_index,
+ int enc_index)
+{
+ res_ctx->hpo_dp_link_enc_to_link_idx[enc_index] = link_index;
+ res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] = 1;
+}
+
+static inline void retain_hpo_dp_link_enc(
+ struct resource_context *res_ctx,
+ int enc_index)
+{
+ res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++;
+}
+
+static inline void release_hpo_dp_link_enc(
+ struct resource_context *res_ctx,
+ int enc_index)
+{
+ ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0);
+ res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--;
+}
+
+static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+ struct pipe_ctx *pipe_ctx,
+ struct dc_stream_state *stream)
+{
+ int enc_index;
+
+ enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
+
+ if (enc_index >= 0) {
+ retain_hpo_dp_link_enc(res_ctx, enc_index);
+ } else {
+ enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
+ if (enc_index >= 0)
+ acquire_hpo_dp_link_enc(res_ctx, stream->link->link_index, enc_index);
+ }
+
+ if (enc_index >= 0)
+ pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
+
+ return pipe_ctx->link_res.hpo_dp_link_enc != NULL;
+}
+
+static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
+ struct pipe_ctx *pipe_ctx,
+ struct dc_stream_state *stream)
+{
+ int enc_index;
+
+ enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
+
+ if (enc_index >= 0) {
+ release_hpo_dp_link_enc(res_ctx, enc_index);
+ pipe_ctx->link_res.hpo_dp_link_enc = NULL;
+ }
+}
+
+enum dc_status resource_add_otg_master_for_stream_output(struct dc_state *new_ctx,
+ const struct resource_pool *pool,
+ struct dc_stream_state *stream)
+{
+ struct dc *dc = stream->ctx->dc;
+
+ return dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
+}
+
+void resource_remove_otg_master_for_stream_output(struct dc_state *context,
+ const struct resource_pool *pool,
+ struct dc_stream_state *stream)
+{
+ struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(
+ &context->res_ctx, stream);
+
+ ASSERT(resource_get_odm_slice_count(otg_master) == 1);
+ ASSERT(otg_master->plane_state == NULL);
+ ASSERT(otg_master->stream_res.stream_enc);
+ update_stream_engine_usage(
+ &context->res_ctx,
+ pool,
+ otg_master->stream_res.stream_enc,
+ false);
+
+ if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master)) {
+ update_hpo_dp_stream_engine_usage(
+ &context->res_ctx, pool,
+ otg_master->stream_res.hpo_dp_stream_enc,
+ false);
+ remove_hpo_dp_link_enc_from_ctx(
+ &context->res_ctx, otg_master, stream);
+ }
+ if (otg_master->stream_res.audio)
+ update_audio_usage(
+ &context->res_ctx,
+ pool,
+ otg_master->stream_res.audio,
+ false);
+
+ resource_unreference_clock_source(&context->res_ctx,
+ pool,
+ otg_master->clock_source);
+
+ if (pool->funcs->remove_stream_from_ctx)
+ pool->funcs->remove_stream_from_ctx(
+ stream->ctx->dc, context, stream);
+ memset(otg_master, 0, sizeof(*otg_master));
+}
+
+/* For each OPP head of an OTG master, add top plane at plane index 0.
+ *
+ * In the following example, the stream has 2 ODM slices without a top plane.
+ * By adding a plane 0 to OPP heads, we are configuring our hardware to render
+ * plane 0 by using each OPP head's DPP.
+ *
+ * Inter-pipe Relation (Before Adding Plane)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | | slice 0 | |
+ * | 0 | |blank ----ODM----------- |
+ * | | | slice 1 | | |
+ * | 1 | |blank ---- | |
+ * |________|_______________|___________|_____________|
+ *
+ * Inter-pipe Relation (After Adding Plane)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | plane 0 | slice 0 | |
+ * | 0 | -------------------------ODM----------- |
+ * | | plane 0 | slice 1 | | |
+ * | 1 | ------------------------- | |
+ * |________|_______________|___________|_____________|
+ */
+static bool add_plane_to_opp_head_pipes(struct pipe_ctx *otg_master_pipe,
+ struct dc_plane_state *plane_state,
+ struct dc_state *context)
+{
+ struct pipe_ctx *opp_head_pipe = otg_master_pipe;
+
+ while (opp_head_pipe) {
+ if (opp_head_pipe->plane_state) {
+ ASSERT(0);
+ return false;
+ }
+ opp_head_pipe->plane_state = plane_state;
+ opp_head_pipe = opp_head_pipe->next_odm_pipe;
+ }
+
+ return true;
+}
+
+/* For each OPP head of an OTG master, acquire a secondary DPP pipe and add
+ * the plane. So the plane is added to all ODM slices associated with the OTG
+ * master pipe in the bottom layer.
+ *
+ * In the following example, the stream has 2 ODM slices and a top plane 0.
+ * By acquiring secondary DPP pipes and adding a plane 1, we are configuring our
+ * hardware to render the plane 1 by acquiring a new pipe for each ODM slice and
+ * render plane 1 using new pipes' DPP in the Z axis below plane 0.
+ *
+ * Inter-pipe Relation (Before Adding Plane)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | plane 0 | slice 0 | |
+ * | 0 | -------------------------ODM----------- |
+ * | | plane 0 | slice 1 | | |
+ * | 1 | ------------------------- | |
+ * |________|_______________|___________|_____________|
+ *
+ * Inter-pipe Relation (After Acquiring and Adding Plane)
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | plane 0 | slice 0 | |
+ * | 0 | -------------MPC---------ODM----------- |
+ * | | plane 1 | | | | |
+ * | 2 | ------------- | | | |
+ * | | plane 0 | slice 1 | | |
+ * | 1 | -------------MPC--------- | |
+ * | | plane 1 | | | |
+ * | 3 | ------------- | | |
+ * |________|_______________|___________|_____________|
+ */
+static bool acquire_secondary_dpp_pipes_and_add_plane(
+ struct pipe_ctx *otg_master_pipe,
+ struct dc_plane_state *plane_state,
+ struct dc_state *new_ctx,
+ struct dc_state *cur_ctx,
+ struct resource_pool *pool)
+{
+ struct pipe_ctx *opp_head_pipe, *sec_pipe, *tail_pipe;
+
+ if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe) {
+ ASSERT(0);
+ return false;
+ }
+
+ opp_head_pipe = otg_master_pipe;
+ while (opp_head_pipe) {
+ sec_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
+ cur_ctx,
+ new_ctx,
+ pool,
opp_head_pipe);
if (!sec_pipe) {
/* try tearing down MPCC combine */
@@ -2027,64 +2259,52 @@ static bool acquire_secondary_dpp_pipes_and_add_plane(
return true;
}
-/*
- * Acquire a pipe as OTG master and assign to the stream in new dc context.
- * return - true if OTG master pipe is acquired and new dc context is updated.
- * false if it fails to acquire an OTG master pipe for this stream.
- *
- * In the example below, we acquired pipe 0 as OTG master pipe for the stream.
- * After the function its Inter-pipe Relation is represented by the diagram
- * below.
- *
- * Inter-pipe Relation
- * __________________________________________________
- * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
- * | | | | |
- * | 0 | |blank ------------------ |
- * |________|_______________|___________|_____________|
- */
-static bool acquire_otg_master_pipe_for_stream(
+bool resource_append_dpp_pipes_for_plane_composition(
struct dc_state *new_ctx,
+ struct dc_state *cur_ctx,
+ struct resource_pool *pool,
+ struct pipe_ctx *otg_master_pipe,
+ struct dc_plane_state *plane_state)
+{
+ if (otg_master_pipe->plane_state == NULL)
+ return add_plane_to_opp_head_pipes(otg_master_pipe,
+ plane_state, new_ctx);
+ else
+ return acquire_secondary_dpp_pipes_and_add_plane(
+ otg_master_pipe, plane_state, new_ctx,
+ cur_ctx, pool);
+}
+
+void resource_remove_dpp_pipes_for_plane_composition(
+ struct dc_state *context,
const struct resource_pool *pool,
- struct dc_stream_state *stream)
+ const struct dc_plane_state *plane_state)
{
- /* TODO: Move this function to DCN specific resource file and acquire
- * DSC resource here. The reason is that the function should have the
- * same level of responsibility as when we acquire secondary OPP head.
- * We acquire DSC when we acquire secondary OPP head, so we should
- * acquire DSC when we acquire OTG master.
- */
- int pipe_idx;
- struct pipe_ctx *pipe_ctx = NULL;
+ int i;
+ for (i = pool->pipe_count - 1; i >= 0; i--) {
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
- pipe_idx = resource_find_any_free_pipe(&new_ctx->res_ctx, pool);
- if (pipe_idx != FREE_PIPE_INDEX_NOT_FOUND) {
- pipe_ctx = &new_ctx->res_ctx.pipe_ctx[pipe_idx];
- memset(pipe_ctx, 0, sizeof(*pipe_ctx));
- pipe_ctx->pipe_idx = pipe_idx;
- pipe_ctx->stream_res.tg = pool->timing_generators[pipe_idx];
- pipe_ctx->plane_res.mi = pool->mis[pipe_idx];
- pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx];
- pipe_ctx->plane_res.ipp = pool->ipps[pipe_idx];
- pipe_ctx->plane_res.xfm = pool->transforms[pipe_idx];
- pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx];
- pipe_ctx->stream_res.opp = pool->opps[pipe_idx];
- if (pool->dpps[pipe_idx])
- pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
+ if (pipe_ctx->plane_state == plane_state) {
+ if (pipe_ctx->top_pipe)
+ pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
- if (pipe_idx >= pool->timing_generator_count) {
- int tg_inst = pool->timing_generator_count - 1;
+ /* Second condition is to avoid setting NULL to top pipe
+ * of tail pipe making it look like head pipe in subsequent
+ * deletes
+ */
+ if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
+ pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
- pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
- pipe_ctx->stream_res.opp = pool->opps[tg_inst];
+ /*
+ * For head pipe detach surfaces from pipe for tail
+ * pipe just zero it out
+ */
+ if (!pipe_ctx->top_pipe)
+ pipe_ctx->plane_state = NULL;
+ else
+ memset(pipe_ctx, 0, sizeof(*pipe_ctx));
}
-
- pipe_ctx->stream = stream;
- } else {
- pipe_idx = acquire_first_split_pipe(&new_ctx->res_ctx, pool, stream);
}
-
- return pipe_idx != FREE_PIPE_INDEX_NOT_FOUND;
}
/*
@@ -2127,12 +2347,17 @@ static bool acquire_pipes_and_add_odm_slice(
const struct resource_pool *pool)
{
struct pipe_ctx *last_opp_head = get_last_opp_head(otg_master_pipe);
- struct pipe_ctx *new_opp_head = pool->funcs->acquire_free_pipe_as_secondary_opp_head(
- cur_ctx, new_ctx, pool,
- otg_master_pipe);
+ struct pipe_ctx *new_opp_head;
struct pipe_ctx *last_top_dpp_pipe, *last_bottom_dpp_pipe,
*new_top_dpp_pipe, *new_bottom_dpp_pipe;
+ if (!pool->funcs->acquire_free_pipe_as_secondary_opp_head) {
+ ASSERT(0);
+ return false;
+ }
+ new_opp_head = pool->funcs->acquire_free_pipe_as_secondary_opp_head(
+ cur_ctx, new_ctx, pool,
+ otg_master_pipe);
if (!new_opp_head)
return false;
@@ -2203,6 +2428,11 @@ static bool release_pipes_and_remove_odm_slice(
struct pipe_ctx *last_opp_head = get_last_opp_head(otg_master_pipe);
struct pipe_ctx *tail_pipe = get_tail_pipe(last_opp_head);
+ if (!pool->funcs->release_pipe) {
+ ASSERT(0);
+ return false;
+ }
+
if (resource_is_pipe_type(last_opp_head, OTG_MASTER))
return false;
@@ -2258,10 +2488,15 @@ static bool acquire_dpp_pipe_and_add_mpc_slice(
struct pipe_ctx *last_dpp_pipe =
get_last_dpp_pipe_in_mpcc_combine(dpp_pipe);
struct pipe_ctx *opp_head = resource_get_opp_head(dpp_pipe);
- struct pipe_ctx *new_dpp_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
- cur_ctx, new_ctx, pool, opp_head);
+ struct pipe_ctx *new_dpp_pipe;
- if (!new_dpp_pipe || resource_get_num_odm_splits(dpp_pipe) > 0)
+ if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe) {
+ ASSERT(0);
+ return false;
+ }
+ new_dpp_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
+ cur_ctx, new_ctx, pool, opp_head);
+ if (!new_dpp_pipe || resource_get_odm_slice_count(dpp_pipe) > 1)
return false;
new_dpp_pipe->bottom_pipe = last_dpp_pipe->bottom_pipe;
@@ -2315,8 +2550,13 @@ static bool release_dpp_pipe_and_remove_mpc_slice(
struct pipe_ctx *last_dpp_pipe =
get_last_dpp_pipe_in_mpcc_combine(dpp_pipe);
+ if (!pool->funcs->release_pipe) {
+ ASSERT(0);
+ return false;
+ }
+
if (resource_is_pipe_type(last_dpp_pipe, OPP_HEAD) ||
- resource_get_num_odm_splits(dpp_pipe) > 0)
+ resource_get_odm_slice_count(dpp_pipe) > 1)
return false;
last_dpp_pipe->top_pipe->bottom_pipe = last_dpp_pipe->bottom_pipe;
@@ -2327,15 +2567,17 @@ static bool release_dpp_pipe_and_remove_mpc_slice(
return true;
}
-bool resource_update_pipes_with_odm_slice_count(
- struct pipe_ctx *otg_master,
+bool resource_update_pipes_for_stream_with_slice_count(
struct dc_state *new_ctx,
const struct dc_state *cur_ctx,
const struct resource_pool *pool,
+ const struct dc_stream_state *stream,
int new_slice_count)
{
int i;
- int cur_slice_count = resource_get_num_odm_splits(otg_master) + 1;
+ struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(
+ &new_ctx->res_ctx, stream);
+ int cur_slice_count = resource_get_odm_slice_count(otg_master);
bool result = true;
if (new_slice_count == cur_slice_count)
@@ -2355,31 +2597,38 @@ bool resource_update_pipes_with_odm_slice_count(
return result;
}
-bool resource_update_pipes_with_mpc_slice_count(
- struct pipe_ctx *dpp_pipe,
+bool resource_update_pipes_for_plane_with_slice_count(
struct dc_state *new_ctx,
const struct dc_state *cur_ctx,
const struct resource_pool *pool,
+ const struct dc_plane_state *plane,
int new_slice_count)
{
int i;
- int cur_slice_count = resource_get_num_mpc_splits(dpp_pipe) + 1;
+ int dpp_pipe_count;
+ int cur_slice_count;
+ struct pipe_ctx *dpp_pipes[MAX_PIPES];
bool result = true;
+ dpp_pipe_count = resource_get_dpp_pipes_for_plane(plane,
+ &new_ctx->res_ctx, dpp_pipes);
+ ASSERT(dpp_pipe_count > 0);
+ cur_slice_count = resource_get_mpc_slice_count(dpp_pipes[0]);
+
if (new_slice_count == cur_slice_count)
return result;
if (new_slice_count > cur_slice_count)
for (i = 0; i < new_slice_count - cur_slice_count && result; i++)
result = acquire_dpp_pipe_and_add_mpc_slice(
- dpp_pipe, new_ctx, cur_ctx, pool);
+ dpp_pipes[0], new_ctx, cur_ctx, pool);
else
for (i = 0; i < cur_slice_count - new_slice_count && result; i++)
result = release_dpp_pipe_and_remove_mpc_slice(
- dpp_pipe, new_ctx, pool);
+ dpp_pipes[0], new_ctx, pool);
if (result)
result = update_pipe_params_after_mpc_slice_count_change(
- dpp_pipe->plane_state, new_ctx, pool);
+ dpp_pipes[0]->plane_state, new_ctx, pool);
return result;
}
@@ -2406,13 +2655,9 @@ bool dc_add_plane_to_context(
otg_master_pipe = resource_get_otg_master_for_stream(
&context->res_ctx, stream);
- if (otg_master_pipe->plane_state == NULL)
- added = add_plane_to_opp_head_pipes(otg_master_pipe,
- plane_state, context);
- else
- added = acquire_secondary_dpp_pipes_and_add_plane(
- otg_master_pipe, plane_state, context,
- dc->current_state, pool);
+ added = resource_append_dpp_pipes_for_plane_composition(context,
+ dc->current_state, pool, otg_master_pipe, plane_state);
+
if (added) {
stream_status->plane_states[stream_status->plane_count] =
plane_state;
@@ -2448,32 +2693,8 @@ bool dc_remove_plane_from_context(
return false;
}
- /* release pipe for plane*/
- for (i = pool->pipe_count - 1; i >= 0; i--) {
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-
- if (pipe_ctx->plane_state == plane_state) {
- if (pipe_ctx->top_pipe)
- pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
-
- /* Second condition is to avoid setting NULL to top pipe
- * of tail pipe making it look like head pipe in subsequent
- * deletes
- */
- if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
- pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
-
- /*
- * For head pipe detach surfaces from pipe for tail
- * pipe just zero it out
- */
- if (!pipe_ctx->top_pipe)
- pipe_ctx->plane_state = NULL;
- else
- memset(pipe_ctx, 0, sizeof(*pipe_ctx));
- }
- }
-
+ resource_remove_dpp_pipes_for_plane_composition(
+ context, pool, plane_state);
for (i = 0; i < stream_status->plane_count; i++) {
if (stream_status->plane_states[i] == plane_state) {
@@ -2672,122 +2893,6 @@ bool dc_is_stream_scaling_unchanged(struct dc_stream_state *old_stream,
return true;
}
-static void update_stream_engine_usage(
- struct resource_context *res_ctx,
- const struct resource_pool *pool,
- struct stream_encoder *stream_enc,
- bool acquired)
-{
- int i;
-
- for (i = 0; i < pool->stream_enc_count; i++) {
- if (pool->stream_enc[i] == stream_enc)
- res_ctx->is_stream_enc_acquired[i] = acquired;
- }
-}
-
-static void update_hpo_dp_stream_engine_usage(
- struct resource_context *res_ctx,
- const struct resource_pool *pool,
- struct hpo_dp_stream_encoder *hpo_dp_stream_enc,
- bool acquired)
-{
- int i;
-
- for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
- if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc)
- res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired;
- }
-}
-
-static inline int find_acquired_hpo_dp_link_enc_for_link(
- const struct resource_context *res_ctx,
- const struct dc_link *link)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_to_link_idx); i++)
- if (res_ctx->hpo_dp_link_enc_ref_cnts[i] > 0 &&
- res_ctx->hpo_dp_link_enc_to_link_idx[i] == link->link_index)
- return i;
-
- return -1;
-}
-
-static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx,
- const struct resource_pool *pool)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++)
- if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0)
- break;
-
- return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) &&
- i < pool->hpo_dp_link_enc_count) ? i : -1;
-}
-
-static inline void acquire_hpo_dp_link_enc(
- struct resource_context *res_ctx,
- unsigned int link_index,
- int enc_index)
-{
- res_ctx->hpo_dp_link_enc_to_link_idx[enc_index] = link_index;
- res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] = 1;
-}
-
-static inline void retain_hpo_dp_link_enc(
- struct resource_context *res_ctx,
- int enc_index)
-{
- res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++;
-}
-
-static inline void release_hpo_dp_link_enc(
- struct resource_context *res_ctx,
- int enc_index)
-{
- ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0);
- res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--;
-}
-
-static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
- const struct resource_pool *pool,
- struct pipe_ctx *pipe_ctx,
- struct dc_stream_state *stream)
-{
- int enc_index;
-
- enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
-
- if (enc_index >= 0) {
- retain_hpo_dp_link_enc(res_ctx, enc_index);
- } else {
- enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
- if (enc_index >= 0)
- acquire_hpo_dp_link_enc(res_ctx, stream->link->link_index, enc_index);
- }
-
- if (enc_index >= 0)
- pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
-
- return pipe_ctx->link_res.hpo_dp_link_enc != NULL;
-}
-
-static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
- struct pipe_ctx *pipe_ctx,
- struct dc_stream_state *stream)
-{
- int enc_index;
-
- enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
-
- if (enc_index >= 0) {
- release_hpo_dp_link_enc(res_ctx, enc_index);
- pipe_ctx->link_res.hpo_dp_link_enc = NULL;
- }
-}
-
/* TODO: release audio object */
void update_audio_usage(
struct resource_context *res_ctx,
@@ -2872,7 +2977,8 @@ enum dc_status dc_add_stream_to_ctx(
dc_stream_retain(stream);
new_ctx->stream_count++;
- res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
+ res = resource_add_otg_master_for_stream_output(
+ new_ctx, dc->res_pool, stream);
if (res != DC_OK)
DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
@@ -2889,53 +2995,18 @@ enum dc_status dc_remove_stream_from_ctx(
{
int i;
struct dc_context *dc_ctx = dc->ctx;
- struct pipe_ctx *del_pipe = resource_get_otg_master_for_stream(&new_ctx->res_ctx, stream);
- struct pipe_ctx *odm_pipe;
+ struct pipe_ctx *del_pipe = resource_get_otg_master_for_stream(
+ &new_ctx->res_ctx, stream);
if (!del_pipe) {
DC_ERROR("Pipe not found for stream %p !\n", stream);
return DC_ERROR_UNEXPECTED;
}
- odm_pipe = del_pipe->next_odm_pipe;
-
- /* Release primary pipe */
- ASSERT(del_pipe->stream_res.stream_enc);
- update_stream_engine_usage(
- &new_ctx->res_ctx,
- dc->res_pool,
- del_pipe->stream_res.stream_enc,
- false);
-
- if (dc->link_srv->dp_is_128b_132b_signal(del_pipe)) {
- update_hpo_dp_stream_engine_usage(
- &new_ctx->res_ctx, dc->res_pool,
- del_pipe->stream_res.hpo_dp_stream_enc,
- false);
- remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
- }
-
- if (del_pipe->stream_res.audio)
- update_audio_usage(
- &new_ctx->res_ctx,
- dc->res_pool,
- del_pipe->stream_res.audio,
- false);
-
- resource_unreference_clock_source(&new_ctx->res_ctx,
- dc->res_pool,
- del_pipe->clock_source);
-
- if (dc->res_pool->funcs->remove_stream_from_ctx)
- dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
-
- while (odm_pipe) {
- struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
-
- memset(odm_pipe, 0, sizeof(*odm_pipe));
- odm_pipe = next_odm_pipe;
- }
- memset(del_pipe, 0, sizeof(*del_pipe));
+ resource_update_pipes_for_stream_with_slice_count(new_ctx,
+ dc->current_state, dc->res_pool, stream, 1);
+ resource_remove_otg_master_for_stream_output(
+ new_ctx, dc->res_pool, stream);
for (i = 0; i < new_ctx->stream_count; i++)
if (new_ctx->streams[i] == stream)
@@ -3154,6 +3225,66 @@ static void mark_seamless_boot_stream(
}
}
+/*
+ * Acquire a pipe as OTG master and assign to the stream in new dc context.
+ * return - true if OTG master pipe is acquired and new dc context is updated.
+ * false if it fails to acquire an OTG master pipe for this stream.
+ *
+ * In the example below, we acquired pipe 0 as OTG master pipe for the stream.
+ * After the function its Inter-pipe Relation is represented by the diagram
+ * below.
+ *
+ * Inter-pipe Relation
+ * __________________________________________________
+ * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
+ * | | | | |
+ * | 0 | |blank ------------------ |
+ * |________|_______________|___________|_____________|
+ */
+static bool acquire_otg_master_pipe_for_stream(
+ struct dc_state *new_ctx,
+ const struct resource_pool *pool,
+ struct dc_stream_state *stream)
+{
+ /* TODO: Move this function to DCN specific resource file and acquire
+ * DSC resource here. The reason is that the function should have the
+ * same level of responsibility as when we acquire secondary OPP head.
+ * We acquire DSC when we acquire secondary OPP head, so we should
+ * acquire DSC when we acquire OTG master.
+ */
+ int pipe_idx;
+ struct pipe_ctx *pipe_ctx = NULL;
+
+ pipe_idx = resource_find_any_free_pipe(&new_ctx->res_ctx, pool);
+ if (pipe_idx != FREE_PIPE_INDEX_NOT_FOUND) {
+ pipe_ctx = &new_ctx->res_ctx.pipe_ctx[pipe_idx];
+ memset(pipe_ctx, 0, sizeof(*pipe_ctx));
+ pipe_ctx->pipe_idx = pipe_idx;
+ pipe_ctx->stream_res.tg = pool->timing_generators[pipe_idx];
+ pipe_ctx->plane_res.mi = pool->mis[pipe_idx];
+ pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx];
+ pipe_ctx->plane_res.ipp = pool->ipps[pipe_idx];
+ pipe_ctx->plane_res.xfm = pool->transforms[pipe_idx];
+ pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx];
+ pipe_ctx->stream_res.opp = pool->opps[pipe_idx];
+ if (pool->dpps[pipe_idx])
+ pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
+
+ if (pipe_idx >= pool->timing_generator_count) {
+ int tg_inst = pool->timing_generator_count - 1;
+
+ pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
+ pipe_ctx->stream_res.opp = pool->opps[tg_inst];
+ }
+
+ pipe_ctx->stream = stream;
+ } else {
+ pipe_idx = acquire_first_split_pipe(&new_ctx->res_ctx, pool, stream);
+ }
+
+ return pipe_idx != FREE_PIPE_INDEX_NOT_FOUND;
+}
+
enum dc_status resource_map_pool_resources(
const struct dc *dc,
struct dc_state *context,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index f3db16cd10db..347156d02f21 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -614,6 +614,8 @@ void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
pipe_ctx->top_pipe = NULL;
pipe_ctx->bottom_pipe = NULL;
+ pipe_ctx->prev_odm_pipe = NULL;
+ pipe_ctx->next_odm_pipe = NULL;
pipe_ctx->plane_state = NULL;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index d587f807dfd7..2820393d5c6f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1948,7 +1948,7 @@ int dcn20_validate_apply_pipe_split_flags(
v->ODMCombineEnablePerState[vlevel][pipe_plane];
if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {
- if (resource_get_num_mpc_splits(pipe) == 1) {
+ if (resource_get_mpc_slice_count(pipe) == 2) {
/*If need split for mpc but 2 way split already*/
if (split[i] == 4)
split[i] = 2; /* 2 -> 4 MPC */
@@ -1956,7 +1956,7 @@ int dcn20_validate_apply_pipe_split_flags(
split[i] = 0; /* 2 -> 2 MPC */
else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
merge[i] = true; /* 2 -> 1 MPC */
- } else if (resource_get_num_mpc_splits(pipe) == 3) {
+ } else if (resource_get_mpc_slice_count(pipe) == 4) {
/*If need split for mpc but 4 way split already*/
if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe)
|| !pipe->bottom_pipe)) {
@@ -1965,7 +1965,7 @@ int dcn20_validate_apply_pipe_split_flags(
pipe->top_pipe->plane_state == pipe->plane_state)
merge[i] = true; /* 4 -> 1 MPC */
split[i] = 0;
- } else if (resource_get_num_odm_splits(pipe)) {
+ } else if (resource_get_odm_slice_count(pipe) > 1) {
/* ODM -> MPC transition */
if (pipe->prev_odm_pipe) {
split[i] = 0;
@@ -1973,7 +1973,7 @@ int dcn20_validate_apply_pipe_split_flags(
}
}
} else {
- if (resource_get_num_odm_splits(pipe) == 1) {
+ if (resource_get_odm_slice_count(pipe) == 2) {
/*If need split for odm but 2 way split already*/
if (split[i] == 4)
split[i] = 2; /* 2 -> 4 ODM */
@@ -1983,7 +1983,7 @@ int dcn20_validate_apply_pipe_split_flags(
ASSERT(0); /* NOT expected yet */
merge[i] = true; /* exit ODM */
}
- } else if (resource_get_num_odm_splits(pipe) == 3) {
+ } else if (resource_get_odm_slice_count(pipe) == 4) {
/*If need split for odm but 4 way split already*/
if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe)
|| !pipe->next_odm_pipe)) {
@@ -1993,7 +1993,7 @@ int dcn20_validate_apply_pipe_split_flags(
merge[i] = true; /* exit ODM */
}
split[i] = 0;
- } else if (resource_get_num_mpc_splits(pipe)) {
+ } else if (resource_get_mpc_slice_count(pipe) > 1) {
/* MPC -> ODM transition */
ASSERT(0); /* NOT expected yet */
if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
@@ -2211,12 +2211,22 @@ enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_stat
return DC_OK;
}
+void dcn20_release_pipe(struct dc_state *context,
+ struct pipe_ctx *pipe,
+ const struct resource_pool *pool)
+{
+ if (resource_is_pipe_type(pipe, OPP_HEAD) && pipe->stream_res.dsc)
+ dcn20_release_dsc(&context->res_ctx, pool, &pipe->stream_res.dsc);
+ memset(pipe, 0, sizeof(*pipe));
+}
+
static const struct resource_funcs dcn20_res_pool_funcs = {
.destroy = dcn20_destroy_resource_pool,
.link_enc_create = dcn20_link_encoder_create,
.panel_cntl_create = dcn20_panel_cntl_create,
.validate_bandwidth = dcn20_validate_bandwidth,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
+ .release_pipe = dcn20_release_pipe,
.add_stream_to_ctx = dcn20_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
index 6d1a8924e57b..37ecaccc5d12 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
@@ -63,7 +63,9 @@ struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(
struct dc_state *new_ctx,
const struct resource_pool *pool,
const struct pipe_ctx *opp_head_pipe);
-
+void dcn20_release_pipe(struct dc_state *context,
+ struct pipe_ctx *pipe,
+ const struct resource_pool *pool);
struct stream_encoder *dcn20_stream_encoder_create(
enum engine_id eng_id,
struct dc_context *ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
index 2dc4d2c1410b..9389bd8df42b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
@@ -1069,6 +1069,7 @@ static struct resource_funcs dcn201_res_pool_funcs = {
.add_dsc_to_stream_resource = NULL,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn201_acquire_free_pipe_for_layer,
+ .release_pipe = dcn20_release_pipe,
.populate_dml_writeback_from_context = dcn201_populate_dml_writeback_from_context,
.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
.set_mcif_arb_params = dcn20_set_mcif_arb_params,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index d1a25fe6c44f..71e82692dd7c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1389,6 +1389,7 @@ static const struct resource_funcs dcn21_res_pool_funcs = {
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
+ .release_pipe = dcn20_release_pipe,
.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
.patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
.set_mcif_arb_params = dcn20_set_mcif_arb_params,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 88c0b24a3249..da56962227fd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2217,6 +2217,7 @@ static const struct resource_funcs dcn30_res_pool_funcs = {
.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
+ .release_pipe = dcn20_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 79d6697d13b6..c489ad043b87 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1380,6 +1380,7 @@ static struct resource_funcs dcn301_res_pool_funcs = {
.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
+ .release_pipe = dcn20_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index 447abcd593be..f5b8b92a84f2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -1137,6 +1137,7 @@ static struct resource_funcs dcn302_res_pool_funcs = {
.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
+ .release_pipe = dcn20_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
index adf4989177f7..d59561605c17 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
@@ -1063,6 +1063,7 @@ static struct resource_funcs dcn303_res_pool_funcs = {
.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
+ .release_pipe = dcn20_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 82de4fe2637f..994289b3d5a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1824,6 +1824,7 @@ static struct resource_funcs dcn31_res_pool_funcs = {
.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
.populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
+ .release_pipe = dcn20_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 004beed9bd44..4d0052ca742f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -1796,6 +1796,7 @@ static struct resource_funcs dcn314_res_pool_funcs = {
.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
.populate_dml_pipes = dcn314_populate_dml_pipes_from_context,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
+ .release_pipe = dcn20_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index 127487ea3d7d..8e3acb92385b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -1819,6 +1819,7 @@ static struct resource_funcs dcn315_res_pool_funcs = {
.update_soc_for_wm_a = dcn315_update_soc_for_wm_a,
.populate_dml_pipes = dcn315_populate_dml_pipes_from_context,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
+ .release_pipe = dcn20_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
index 5fe2c61527df..9133a1ea4ca0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
@@ -1706,6 +1706,7 @@ static struct resource_funcs dcn316_res_pool_funcs = {
.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
.populate_dml_pipes = dcn316_populate_dml_pipes_from_context,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
+ .release_pipe = dcn20_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 072c5ba4c99c..88c9dbbacbd3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2040,7 +2040,7 @@ static struct resource_funcs dcn32_res_pool_funcs = {
.populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
.acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
- .release_pipe = dcn32_release_pipe,
+ .release_pipe = dcn20_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
@@ -2778,15 +2778,6 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(
return free_pipe;
}
-void dcn32_release_pipe(struct dc_state *context,
- struct pipe_ctx *pipe,
- const struct resource_pool *pool)
-{
- if (resource_is_pipe_type(pipe, OPP_HEAD) && pipe->stream_res.dsc)
- dcn20_release_dsc(&context->res_ctx, pool, &pipe->stream_res.dsc);
- memset(pipe, 0, sizeof(*pipe));
-}
-
unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans)
{
/*
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 8d73cceb485b..7d40fb6156f3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -1589,6 +1589,7 @@ static struct resource_funcs dcn321_res_pool_funcs = {
.calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
.populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
.acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
+ .release_pipe = dcn20_release_pipe,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 8afda5ecc0cd..0989a0152ae8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1305,11 +1305,11 @@ int dcn20_populate_dml_pipes_from_context(struct dc *dc,
pipes[pipe_cnt].dout.is_virtual = 0;
pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
- switch (resource_get_num_odm_splits(&res_ctx->pipe_ctx[i])) {
- case 1:
+ switch (resource_get_odm_slice_count(&res_ctx->pipe_ctx[i])) {
+ case 2:
pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
break;
- case 3:
+ case 4:
pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
break;
default:
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 4344c5a239e1..55efd5600521 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -238,8 +238,8 @@ enum pipe_type {
/* OTG master pipe - the master pipe of its OPP head pipes with a
* functional OTG. It merges all its OPP head pipes pixel data in ODM
- * block and output to backend DIG. OTG master pipe is responsible for
- * generating entire crtc timing to backend DIG. An OTG master pipe may
+ * block and output to back end DIG. OTG master pipe is responsible for
+ * generating entire CRTC timing to back end DIG. An OTG master pipe may
* or may not have a plane. If it has a plane it blends it as the left
* most MPC slice of the top most layer. If it doesn't have a plane it
* can output pixel data from its OPP head pipes' test pattern
@@ -267,33 +267,175 @@ enum pipe_type {
};
/*
- * Determine if the input pipe ctx is of a pipe type.
- * return - true if pipe ctx is of the input type.
+ * Determine if the input pipe_ctx is of a pipe type.
+ * return - true if pipe_ctx is of the input type.
*/
bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type);
/*
- * Determine if the input pipe ctx is used for rendering a plane with MPCC
- * combine. MPCC combine is a hardware feature to combine multiple DPP pipes
- * into a single plane. It is typically used for bypassing pipe bandwidth
- * limitation for rendering a very large plane or saving power by reducing UCLK
- * and DPPCLK speeds.
+ * Acquire a pipe as OTG master pipe and allocate pipe resources required to
+ * enable stream output.
+ */
+enum dc_status resource_add_otg_master_for_stream_output(struct dc_state *new_ctx,
+ const struct resource_pool *pool,
+ struct dc_stream_state *stream);
+
+/*
+ * Release pipe resources and the OTG master pipe associated with the stream
+ * The stream must have all planes removed and ODM/MPC slice counts are reset
+ * to 1 before invoking this interface.
+ */
+void resource_remove_otg_master_for_stream_output(struct dc_state *new_ctx,
+ const struct resource_pool *pool,
+ struct dc_stream_state *stream);
+
+/*
+ * Add plane to the bottom most layer in plane composition and allocate DPP pipe
+ * resources as needed.
+ * return - true if plane is added in plane composition, false otherwise.
+ */
+bool resource_append_dpp_pipes_for_plane_composition(
+ struct dc_state *new_ctx,
+ struct dc_state *cur_ctx,
+ struct resource_pool *pool,
+ struct pipe_ctx *otg_master_pipe,
+ struct dc_plane_state *plane_state);
+
+/*
+ * Add plane to the bottom most layer in plane composition and allocate DPP pipe
+ * resources as needed.
+ * return - true if plane is added in plane composition, false otherwise.
+ */
+void resource_remove_dpp_pipes_for_plane_composition(
+ struct dc_state *context,
+ const struct resource_pool *pool,
+ const struct dc_plane_state *plane_state);
+
+/*
+ * Update ODM slice count by acquiring or releasing pipes. If new slices need
+ * to be added, it is going to add them to the last ODM index. If existing
+ * slices need to be removed, it is going to remove them from the last ODM
+ * index.
*
- * For instance in the Inter-pipe Relation diagram shown below, both PIPE 0 and
- * 1 are for MPCC combine for plane 0
+ * return - true if ODM slices are updated and required pipes are acquired. All
+ * affected pipe parameters are updated.
*
- * Inter-pipe Relation
- * __________________________________________________
- * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
- * | | plane 0 | | |
- * | 0 | -------------MPC----------------------- |
- * | | plane 0 | | | |
- * | 1 | ------------- | | |
- * |________|_______________|___________|_____________|
+ * false if resource fails to complete this update. The function is not designed
+ * to recover the creation of invalid topologies. Returning false is typically
+ * an indication of insufficient validation in caller's stack. new_ctx will be
+ * invalid. Caller may attempt to restore new_ctx by calling this function
+ * again with original slice count.
+ */
+bool resource_update_pipes_for_stream_with_slice_count(
+ struct dc_state *new_ctx,
+ const struct dc_state *cur_ctx,
+ const struct resource_pool *pool,
+ const struct dc_stream_state *stream,
+ int new_slice_count);
+
+/*
+ * Update MPC slice count by acquiring or releasing DPP pipes. If new slices
+ * need to be added it is going to add to the last MPC index. If existing
+ * slices need to be removed, it is going to remove them from the last MPC
+ * index.
+ *
+ * @dpp_pipe - top most dpp pipe for MPCC combine.
+ *
+ * return - true if MPC slices are updated and required pipes are acquired. All
+ * affected pipe parameters are updated.
*
- * return - true if pipe ctx is used for mpcc combine.
+ * false if resource fails to complete this update. The function is not designed
+ * to recover the creation of invalid topologies. Returning false is typically
+ * an indication of insufficient validation in caller's stack. new_ctx will be
+ * invalid. Caller may attempt to restore new_ctx by calling this function
+ * again with original slice count.
+ */
+bool resource_update_pipes_for_plane_with_slice_count(
+ struct dc_state *new_ctx,
+ const struct dc_state *cur_ctx,
+ const struct resource_pool *pool,
+ const struct dc_plane_state *plane,
+ int slice_count);
+
+/*
+ * Get the OTG master pipe in resource context associated with the stream.
+ * return - NULL if not found. Otherwise the OTG master pipe associated with the
+ * stream.
+ */
+struct pipe_ctx *resource_get_otg_master_for_stream(
+ struct resource_context *res_ctx,
+ const struct dc_stream_state *stream);
+
+/*
+ * Get an array of OPP heads in opp_heads ordered with index low to high for OTG
+ * master pipe in res_ctx.
+ * return - number of OPP heads in the array. If otg_master passed in is not
+ * an OTG master, the function returns 0.
+ */
+int resource_get_opp_heads_for_otg_master(const struct pipe_ctx *otg_master,
+ struct resource_context *res_ctx,
+ struct pipe_ctx *opp_heads[MAX_PIPES]);
+
+/*
+ * Get an array of DPP pipes in dpp_pipes ordered with index low to high for OPP
+ * head pipe in res_ctx.
+ * return - number of DPP pipes in the array. If opp_head passed in is not
+ * an OPP pipe, the function returns 0.
+ */
+int resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx *opp_head,
+ struct resource_context *res_ctx,
+ struct pipe_ctx *dpp_pipes[MAX_PIPES]);
+
+/*
+ * Get an array of DPP pipes in dpp_pipes ordered with index low to high for
+ * plane in res_ctx.
+ * return - number of DPP pipes in the array.
+ */
+int resource_get_dpp_pipes_for_plane(const struct dc_plane_state *plane,
+ struct resource_context *res_ctx,
+ struct pipe_ctx *dpp_pipes[MAX_PIPES]);
+
+/*
+ * Get the OTG master pipe for the input pipe context.
+ * return - the OTG master pipe for the input pipe
+ * context.
+ */
+struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx);
+
+/*
+ * Get the OPP head pipe for the input pipe context.
+ * return - the OPP head pipe for the input pipe
+ * context.
+ */
+struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx);
+
+/*
+ * Get the MPC slice index counting from 0 from left most slice
+ * For example, if a DPP pipe is used as a secondary pipe in MPCC combine, MPC
+ * split index is greater than 0.
+ */
+int resource_get_mpc_slice_index(const struct pipe_ctx *dpp_pipe);
+
+/*
+ * Get number of MPC "cuts" of the plane associated with the pipe. MPC slice
+ * count is equal to MPC splits + 1. For example if a plane is cut 3 times, it
+ * will have 4 pieces of slice.
+ * return - 0 if pipe is not used for a plane with MPCC combine. otherwise
+ * the number of MPC "cuts" for the plane.
+ */
+int resource_get_mpc_slice_count(const struct pipe_ctx *opp_head);
+
+/*
+ * Get number of ODM "cuts" of the timing associated with the pipe. ODM slice
+ * count is equal to ODM splits + 1. For example if a timing is cut 3 times, it
+ * will have 4 pieces of slice.
+ * return - 0 if pipe is not used for ODM combine. otherwise
+ * the number of ODM "cuts" for the timing.
*/
-bool resource_is_for_mpcc_combine(const struct pipe_ctx *pipe_ctx);
+int resource_get_odm_slice_count(const struct pipe_ctx *otg_master);
+
+/* Get the ODM slice index counting from 0 from left most slice */
+int resource_get_odm_slice_index(const struct pipe_ctx *opp_head);
/*
* Look for a free pipe in new resource context that is used as a secondary OPP
@@ -360,100 +502,6 @@ struct pipe_ctx *resource_find_free_secondary_pipe_legacy(
const struct resource_pool *pool,
const struct pipe_ctx *primary_pipe);
-/*
- * Get number of MPC "cuts" of the plane associated with the pipe. MPC slice
- * count is equal to MPC splits + 1. For example if a plane is cut 3 times, it
- * will have 4 pieces of slice.
- * return - 0 if pipe is not used for a plane with MPCC combine. otherwise
- * the number of MPC "cuts" for the plane.
- */
-int resource_get_num_mpc_splits(const struct pipe_ctx *pipe);
-
-int resource_get_mpc_split_index(struct pipe_ctx *pipe_ctx);
-
-
-/*
- * Get number of ODM "cuts" of the timing associated with the pipe. ODM slice
- * count is equal to ODM splits + 1. For example if a timing is cut 3 times, it
- * will have 4 pieces of slice.
- * return - 0 if pipe is not used for ODM combine. otherwise
- * the number of ODM "cuts" for the timing.
- */
-int resource_get_num_odm_splits(const struct pipe_ctx *pipe);
-
-int resource_get_odm_split_index(struct pipe_ctx *pipe_ctx);
-
-/*
- * Get the OTG master pipe in resource context associated with the stream.
- * return - NULL if not found. Otherwise the OTG master pipe associated with the
- * stream.
- */
-struct pipe_ctx *resource_get_otg_master_for_stream(
- struct resource_context *res_ctx,
- struct dc_stream_state *stream);
-
-/*
- * Get the OTG master pipe for the input pipe context.
- * return - the OTG master pipe for the input pipe
- * context.
- */
-struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx);
-
-/*
- * Get the OPP head pipe for the input pipe context.
- * return - the OPP head pipe for the input pipe
- * context.
- */
-struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx);
-
-/*
- * Update ODM slice count by acquiring or releasing pipes. If new slices need
- * to be added, it is going to add them to the last ODM index. If existing
- * slices need to be removed, it is going to remove them from the last ODM
- * index.
- *
- * return - true if ODM slices are updated and required pipes are acquired. All
- * affected pipe parameters are updated.
- *
- * false if resource fails to complete this update. The function is not designed
- * to recover the creation of invalid topologies. Returning false is typically
- * an indication of insufficient validation in caller's stack. The function will
- * return the new_ctx up until the last valid step performed in the function.
- * Caller may use the returned new_ctx for debugging the error or it may attempt
- * to restore new_ctx by calling this function again with original slice count.
- */
-bool resource_update_pipes_with_odm_slice_count(
- struct pipe_ctx *otg_master_pipe,
- struct dc_state *new_ctx,
- const struct dc_state *cur_ctx,
- const struct resource_pool *pool,
- int slice_count);
-
-/*
- * Update MPC slice count by acquiring or releasing DPP pipes. If new slices
- * need to be added it is going to add to the last MPC index. If existing
- * slices need to be removed, it is going to remove them from the last MPC
- * index.
- *
- * @dpp_pipe - top most dpp pipe for MPCC combine.
- *
- * return - true if MPC slices are updated and required pipes are acquired. All
- * affected pipe parameters are updated.
- *
- * false if resource fails to complete this update. The function is not designed
- * to recover the creation of invalid topologies. Returning false is typically
- * an indication of insufficient validation in caller's stack. The function will
- * return the new_ctx up until the last valid step performed in the function.
- * Caller may use the returned new_ctx for debugging the error or it may attempt
- * to restore new_ctx by calling this function again with original slice count.
- */
-bool resource_update_pipes_with_mpc_slice_count(
- struct pipe_ctx *dpp_pipe,
- struct dc_state *new_ctx,
- const struct dc_state *cur_ctx,
- const struct resource_pool *pool,
- int slice_count);
-
bool resource_validate_attach_surfaces(
const struct dc_validation_set set[],
int set_count,
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 12/21] drm/amd/display: use new pipe allocation interface in dcn32 fpu
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (10 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 11/21] drm/amd/display: add more pipe resource interfaces Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 13/21] drm/amd/display: switch to new ODM policy for windowed MPO ODM support Hamza Mahfooz
` (9 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, Wenjing Liu, Daniel Wheeler,
solomon.chiu, jerry.zuo, Aurabindo.Pillai, hamza.mahfooz,
wayne.lin, Jun Lei, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Wenjing Liu <wenjing.liu@amd.com>
This commit implements a new pipe resource allocation logic for DCN32
when windowed ODM MPO flag is set to enable testing. By default the
flag is not set. It will be toggled on after we complete testing.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 488 ++++++++++++------
1 file changed, 339 insertions(+), 149 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 96e3075e6dd0..0c68cd97a461 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1654,6 +1654,188 @@ static bool dcn32_split_stream_for_mpc_or_odm(
return true;
}
+struct pipe_slice_table {
+ struct {
+ struct dc_stream_state *stream;
+ int slice_count;
+ } odm_combines[MAX_STREAMS];
+ int odm_combine_count;
+
+ struct {
+ struct dc_plane_state *plane;
+ int slice_count;
+ } mpc_combines[MAX_SURFACES];
+ int mpc_combine_count;
+};
+
+static void update_slice_table_for_stream(struct pipe_slice_table *table,
+ struct dc_stream_state *stream, int diff)
+{
+ int i;
+
+ for (i = 0; i < table->odm_combine_count; i++) {
+ if (table->odm_combines[i].stream == stream) {
+ table->odm_combines[i].slice_count += diff;
+ break;
+ }
+ }
+
+ if (i == table->odm_combine_count) {
+ table->odm_combine_count++;
+ table->odm_combines[i].stream = stream;
+ table->odm_combines[i].slice_count = diff;
+ }
+}
+
+static void update_slice_table_for_plane(struct pipe_slice_table *table,
+ struct dc_plane_state *plane, int diff)
+{
+ int i;
+
+ for (i = 0; i < table->mpc_combine_count; i++) {
+ if (table->mpc_combines[i].plane == plane) {
+ table->mpc_combines[i].slice_count += diff;
+ break;
+ }
+ }
+
+ if (i == table->mpc_combine_count) {
+ table->mpc_combine_count++;
+ table->mpc_combines[i].plane = plane;
+ table->mpc_combines[i].slice_count = diff;
+ }
+}
+
+static void init_pipe_slice_table_from_context(
+ struct pipe_slice_table *table,
+ struct dc_state *context)
+{
+ int i, j;
+ struct pipe_ctx *otg_master;
+ struct pipe_ctx *dpp_pipes[MAX_PIPES];
+ struct dc_stream_state *stream;
+ int count;
+
+ memset(table, 0, sizeof(*table));
+
+ for (i = 0; i < context->stream_count; i++) {
+ stream = context->streams[i];
+ otg_master = resource_get_otg_master_for_stream(
+ &context->res_ctx, stream);
+ count = resource_get_odm_slice_count(otg_master);
+ update_slice_table_for_stream(table, stream, count);
+
+ count = resource_get_dpp_pipes_for_opp_head(otg_master,
+ &context->res_ctx, dpp_pipes);
+ for (j = 0; j < count; j++)
+ if (dpp_pipes[j]->plane_state)
+ update_slice_table_for_plane(table,
+ dpp_pipes[j]->plane_state, 1);
+ }
+}
+
+static bool update_pipe_slice_table_with_split_flags(
+ struct pipe_slice_table *table,
+ struct dc *dc,
+ struct dc_state *context,
+ struct vba_vars_st *vba,
+ int split[MAX_PIPES],
+ bool merge[MAX_PIPES])
+{
+ /* NOTE: we are deprecating the support for the concept of pipe splitting
+ * or pipe merging. Instead we append slices to the end and remove
+ * slices from the end. The following code converts a pipe split or
+ * merge to an append or remove operation.
+ *
+ * For example:
+ * When split flags describe the following pipe connection transition
+ *
+ * from:
+ * pipe 0 (split=2) -> pipe 1 (split=2)
+ * to: (old behavior)
+ * pipe 0 -> pipe 2 -> pipe 1 -> pipe 3
+ *
+ * the code below actually does:
+ * pipe 0 -> pipe 1 -> pipe 2 -> pipe 3
+ *
+ * This is the new intended behavior and for future DCNs we will retire
+ * the old concept completely.
+ */
+ struct pipe_ctx *pipe;
+ bool odm;
+ int i;
+ bool updated = false;
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ pipe = &context->res_ctx.pipe_ctx[i];
+
+ if (merge[i]) {
+ if (resource_is_pipe_type(pipe, OPP_HEAD))
+ /* merging OPP head means reducing ODM slice
+ * count by 1
+ */
+ update_slice_table_for_stream(table, pipe->stream, -1);
+ else if (resource_is_pipe_type(pipe, DPP_PIPE) &&
+ resource_get_odm_slice_index(resource_get_opp_head(pipe)) == 0)
+ /* merging DPP pipe of the first ODM slice means
+ * reducing MPC slice count by 1
+ */
+ update_slice_table_for_plane(table, pipe->plane_state, -1);
+ updated = true;
+ }
+
+ if (split[i]) {
+ odm = vba->ODMCombineEnabled[vba->pipe_plane[i]] !=
+ dm_odm_combine_mode_disabled;
+ if (odm && resource_is_pipe_type(pipe, OPP_HEAD))
+ update_slice_table_for_stream(
+ table, pipe->stream, split[i] - 1);
+ else if (!odm && resource_is_pipe_type(pipe, DPP_PIPE))
+ update_slice_table_for_plane(
+ table, pipe->plane_state, split[i] - 1);
+ updated = true;
+ }
+ }
+ return updated;
+}
+
+static void update_pipes_with_slice_table(struct dc *dc, struct dc_state *context,
+ struct pipe_slice_table *table)
+{
+ int i;
+
+ for (i = 0; i < table->odm_combine_count; i++) {
+ resource_update_pipes_for_stream_with_slice_count(context,
+ dc->current_state, dc->res_pool,
+ table->odm_combines[i].stream,
+ table->odm_combines[i].slice_count);
+ /* TODO: move this into the function above */
+ dcn20_build_mapped_resource(dc, context,
+ table->odm_combines[i].stream);
+ }
+
+ for (i = 0; i < table->mpc_combine_count; i++)
+ resource_update_pipes_for_plane_with_slice_count(context,
+ dc->current_state, dc->res_pool,
+ table->mpc_combines[i].plane,
+ table->mpc_combines[i].slice_count);
+}
+
+static bool update_pipes_with_split_flags(struct dc *dc, struct dc_state *context,
+ struct vba_vars_st *vba, int split[MAX_PIPES],
+ bool merge[MAX_PIPES])
+{
+ struct pipe_slice_table slice_table;
+ bool updated;
+
+ init_pipe_slice_table_from_context(&slice_table, context);
+ updated = update_pipe_slice_table_with_split_flags(
+ &slice_table, dc, context, vba,
+ split, merge);
+ update_pipes_with_slice_table(dc, context, &slice_table);
+ return updated;
+}
+
bool dcn32_internal_validate_bw(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
@@ -1749,173 +1931,181 @@ bool dcn32_internal_validate_bw(struct dc *dc,
pipe_idx++;
}
- /* merge pipes if necessary */
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ if (dc->config.enable_windowed_mpo_odm) {
+ repopulate_pipes = update_pipes_with_split_flags(
+ dc, context, vba, split, merge);
+ } else {
+ /* the code below will be removed once windowed mpo odm is fully
+ * enabled.
+ */
+ /* merge pipes if necessary */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
- /*skip pipes that don't need merging*/
- if (!merge[i])
- continue;
+ /*skip pipes that don't need merging*/
+ if (!merge[i])
+ continue;
- /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
- if (pipe->prev_odm_pipe) {
- /*split off odm pipe*/
- pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
- if (pipe->next_odm_pipe)
- pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
-
- /*2:1ODM+MPC Split MPO to Single Pipe + MPC Split MPO*/
- if (pipe->bottom_pipe) {
- if (pipe->bottom_pipe->prev_odm_pipe || pipe->bottom_pipe->next_odm_pipe) {
- /*MPC split rules will handle this case*/
- pipe->bottom_pipe->top_pipe = NULL;
- } else {
- /* when merging an ODM pipes, the bottom MPC pipe must now point to
- * the previous ODM pipe and its associated stream assets
- */
- if (pipe->prev_odm_pipe->bottom_pipe) {
- /* 3 plane MPO*/
- pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe->bottom_pipe;
- pipe->prev_odm_pipe->bottom_pipe->bottom_pipe = pipe->bottom_pipe;
+ /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
+ if (pipe->prev_odm_pipe) {
+ /*split off odm pipe*/
+ pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
+ if (pipe->next_odm_pipe)
+ pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
+
+ /*2:1ODM+MPC Split MPO to Single Pipe + MPC Split MPO*/
+ if (pipe->bottom_pipe) {
+ if (pipe->bottom_pipe->prev_odm_pipe || pipe->bottom_pipe->next_odm_pipe) {
+ /*MPC split rules will handle this case*/
+ pipe->bottom_pipe->top_pipe = NULL;
} else {
- /* 2 plane MPO*/
- pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe;
- pipe->prev_odm_pipe->bottom_pipe = pipe->bottom_pipe;
+ /* when merging an ODM pipes, the bottom MPC pipe must now point to
+ * the previous ODM pipe and its associated stream assets
+ */
+ if (pipe->prev_odm_pipe->bottom_pipe) {
+ /* 3 plane MPO*/
+ pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe->bottom_pipe;
+ pipe->prev_odm_pipe->bottom_pipe->bottom_pipe = pipe->bottom_pipe;
+ } else {
+ /* 2 plane MPO*/
+ pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe;
+ pipe->prev_odm_pipe->bottom_pipe = pipe->bottom_pipe;
+ }
+
+ memcpy(&pipe->bottom_pipe->stream_res, &pipe->bottom_pipe->top_pipe->stream_res, sizeof(struct stream_resource));
}
+ }
- memcpy(&pipe->bottom_pipe->stream_res, &pipe->bottom_pipe->top_pipe->stream_res, sizeof(struct stream_resource));
+ if (pipe->top_pipe) {
+ pipe->top_pipe->bottom_pipe = NULL;
}
- }
- if (pipe->top_pipe) {
- pipe->top_pipe->bottom_pipe = NULL;
- }
+ pipe->bottom_pipe = NULL;
+ pipe->next_odm_pipe = NULL;
+ pipe->plane_state = NULL;
+ pipe->stream = NULL;
+ pipe->top_pipe = NULL;
+ pipe->prev_odm_pipe = NULL;
+ if (pipe->stream_res.dsc)
+ dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
+ memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
+ memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
+ memset(&pipe->link_res, 0, sizeof(pipe->link_res));
+ repopulate_pipes = true;
+ } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
+ struct pipe_ctx *top_pipe = pipe->top_pipe;
+ struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
+
+ top_pipe->bottom_pipe = bottom_pipe;
+ if (bottom_pipe)
+ bottom_pipe->top_pipe = top_pipe;
+
+ pipe->top_pipe = NULL;
+ pipe->bottom_pipe = NULL;
+ pipe->plane_state = NULL;
+ pipe->stream = NULL;
+ memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
+ memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
+ memset(&pipe->link_res, 0, sizeof(pipe->link_res));
+ repopulate_pipes = true;
+ } else
+ ASSERT(0); /* Should never try to merge master pipe */
- pipe->bottom_pipe = NULL;
- pipe->next_odm_pipe = NULL;
- pipe->plane_state = NULL;
- pipe->stream = NULL;
- pipe->top_pipe = NULL;
- pipe->prev_odm_pipe = NULL;
- if (pipe->stream_res.dsc)
- dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
- memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
- memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
- memset(&pipe->link_res, 0, sizeof(pipe->link_res));
- repopulate_pipes = true;
- } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
- struct pipe_ctx *top_pipe = pipe->top_pipe;
- struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
-
- top_pipe->bottom_pipe = bottom_pipe;
- if (bottom_pipe)
- bottom_pipe->top_pipe = top_pipe;
-
- pipe->top_pipe = NULL;
- pipe->bottom_pipe = NULL;
- pipe->plane_state = NULL;
- pipe->stream = NULL;
- memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
- memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
- memset(&pipe->link_res, 0, sizeof(pipe->link_res));
- repopulate_pipes = true;
- } else
- ASSERT(0); /* Should never try to merge master pipe */
-
- }
-
- for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
- struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
- struct pipe_ctx *hsplit_pipe = NULL;
- bool odm;
- int old_index = -1;
+ }
- if (!pipe->stream || newly_split[i])
- continue;
+ for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *hsplit_pipe = NULL;
+ bool odm;
+ int old_index = -1;
- pipe_idx++;
- odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
+ if (!pipe->stream || newly_split[i])
+ continue;
- if (!pipe->plane_state && !odm)
- continue;
+ pipe_idx++;
+ odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
- if (split[i]) {
- if (odm) {
- if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
- old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
- else if (old_pipe->next_odm_pipe)
+ if (!pipe->plane_state && !odm)
+ continue;
+
+ if (split[i]) {
+ if (odm) {
+ if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
+ old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
+ else if (old_pipe->next_odm_pipe)
+ old_index = old_pipe->next_odm_pipe->pipe_idx;
+ } else {
+ if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
+ old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
+ old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
+ else if (old_pipe->bottom_pipe &&
+ old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
+ old_index = old_pipe->bottom_pipe->pipe_idx;
+ }
+ hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);
+ ASSERT(hsplit_pipe);
+ if (!hsplit_pipe)
+ goto validate_fail;
+
+ if (!dcn32_split_stream_for_mpc_or_odm(
+ dc, &context->res_ctx,
+ pipe, hsplit_pipe, odm))
+ goto validate_fail;
+
+ newly_split[hsplit_pipe->pipe_idx] = true;
+ repopulate_pipes = true;
+ }
+ if (split[i] == 4) {
+ struct pipe_ctx *pipe_4to1;
+
+ if (odm && old_pipe->next_odm_pipe)
old_index = old_pipe->next_odm_pipe->pipe_idx;
- } else {
- if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
- old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
- old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
- else if (old_pipe->bottom_pipe &&
- old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
+ else if (!odm && old_pipe->bottom_pipe &&
+ old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
old_index = old_pipe->bottom_pipe->pipe_idx;
+ else
+ old_index = -1;
+ pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
+ ASSERT(pipe_4to1);
+ if (!pipe_4to1)
+ goto validate_fail;
+ if (!dcn32_split_stream_for_mpc_or_odm(
+ dc, &context->res_ctx,
+ pipe, pipe_4to1, odm))
+ goto validate_fail;
+ newly_split[pipe_4to1->pipe_idx] = true;
+
+ if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
+ && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
+ old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
+ else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
+ old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
+ old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
+ old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
+ else
+ old_index = -1;
+ pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
+ ASSERT(pipe_4to1);
+ if (!pipe_4to1)
+ goto validate_fail;
+ if (!dcn32_split_stream_for_mpc_or_odm(
+ dc, &context->res_ctx,
+ hsplit_pipe, pipe_4to1, odm))
+ goto validate_fail;
+ newly_split[pipe_4to1->pipe_idx] = true;
}
- hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);
- ASSERT(hsplit_pipe);
- if (!hsplit_pipe)
- goto validate_fail;
-
- if (!dcn32_split_stream_for_mpc_or_odm(
- dc, &context->res_ctx,
- pipe, hsplit_pipe, odm))
- goto validate_fail;
-
- newly_split[hsplit_pipe->pipe_idx] = true;
- repopulate_pipes = true;
- }
- if (split[i] == 4) {
- struct pipe_ctx *pipe_4to1;
-
- if (odm && old_pipe->next_odm_pipe)
- old_index = old_pipe->next_odm_pipe->pipe_idx;
- else if (!odm && old_pipe->bottom_pipe &&
- old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
- old_index = old_pipe->bottom_pipe->pipe_idx;
- else
- old_index = -1;
- pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
- ASSERT(pipe_4to1);
- if (!pipe_4to1)
- goto validate_fail;
- if (!dcn32_split_stream_for_mpc_or_odm(
- dc, &context->res_ctx,
- pipe, pipe_4to1, odm))
- goto validate_fail;
- newly_split[pipe_4to1->pipe_idx] = true;
-
- if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
- && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
- old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
- else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
- old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
- old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
- old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
- else
- old_index = -1;
- pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
- ASSERT(pipe_4to1);
- if (!pipe_4to1)
- goto validate_fail;
- if (!dcn32_split_stream_for_mpc_or_odm(
- dc, &context->res_ctx,
- hsplit_pipe, pipe_4to1, odm))
- goto validate_fail;
- newly_split[pipe_4to1->pipe_idx] = true;
+ if (odm)
+ dcn20_build_mapped_resource(dc, context, pipe->stream);
}
- if (odm)
- dcn20_build_mapped_resource(dc, context, pipe->stream);
- }
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
- if (pipe->plane_state) {
- if (!resource_build_scaling_params(pipe))
- goto validate_fail;
+ if (pipe->plane_state) {
+ if (!resource_build_scaling_params(pipe))
+ goto validate_fail;
+ }
}
}
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 13/21] drm/amd/display: switch to new ODM policy for windowed MPO ODM support
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (11 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 12/21] drm/amd/display: use new pipe allocation interface in dcn32 fpu Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 14/21] drm/amd/display: add pipe topology update log Hamza Mahfooz
` (8 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, Wenjing Liu, Daniel Wheeler,
solomon.chiu, jerry.zuo, Aurabindo.Pillai, hamza.mahfooz,
wayne.lin, Jun Lei, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Wenjing Liu <wenjing.liu@amd.com>
We need to align windowed MPO ODM support on DCN3x with new ODM policy.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 84 ++++++++++++++-----
1 file changed, 65 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 88c9dbbacbd3..fd12791995a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -1885,6 +1885,67 @@ bool dcn32_validate_bandwidth(struct dc *dc,
return out;
}
+static bool should_allow_odm_power_optimization(struct dc *dc,
+ struct dc_state *context)
+{
+ struct dc_stream_state *stream = context->streams[0];
+
+ /*
+ * this debug flag allows us to disable ODM power optimization feature
+ * unconditionally. we force the feature off if this is set to false.
+ */
+ if (!dc->debug.enable_single_display_2to1_odm_policy)
+ return false;
+
+ /* current design and test coverage is only limited to allow ODM power
+ * optimization for single stream. Supporting it for multiple streams
+ * use case would require additional algorithm to decide how to
+ * optimize power consumption when there are not enough free pipes to
+ * allocate for all the streams. This level of optimization would
+ * require multiple attempts of revalidation to make an optimized
+ * decision. Unfortunately We do not support revalidation flow in
+ * current version of DML.
+ */
+ if (context->stream_count != 1)
+ return false;
+
+ /*
+ * Our hardware doesn't support ODM for HDMI TMDS
+ */
+ if (dc_is_hdmi_signal(stream->signal))
+ return false;
+
+ /*
+ * ODM Combine 2:1 requires horizontal timing divisible by 2 so each
+ * ODM segment has the same size.
+ */
+ if (!is_h_timing_divisible_by_2(stream))
+ return false;
+
+ /*
+ * No power benefits if the timing's pixel clock is not high enough to
+ * raise display clock from minimum power state.
+ */
+ if (stream->timing.pix_clk_100hz * 100 <= DCN3_2_VMIN_DISPCLK_HZ)
+ return false;
+
+ /* the new ODM power optimization feature reduces software design
+ * limitation and allows ODM power optimization to be supported even
+ * with presence of overlay planes. The new feature is enabled based on
+ * enable_windowed_mpo_odm flag. If the flag is not set, we limit our
+ * feature scope due to previous software design limitation */
+ if (!dc->config.enable_windowed_mpo_odm) {
+ if (context->stream_status[0].plane_count != 1)
+ return false;
+
+ if (stream->src.width >= 5120 &&
+ stream->src.width > stream->dst.width)
+ return false;
+ }
+
+ return true;
+}
+
int dcn32_populate_dml_pipes_from_context(
struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes,
@@ -1895,35 +1956,20 @@ int dcn32_populate_dml_pipes_from_context(
struct pipe_ctx *pipe = NULL;
bool subvp_in_use = false;
struct dc_crtc_timing *timing;
- bool vsr_odm_support = false;
dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
- /* Determine whether we will apply ODM 2to1 policy:
- * Applies to single display and where the number of planes is less than 3.
- * For 3 plane case ( 2 MPO planes ), we will not set the policy for the MPO pipes.
- *
+ /*
* Apply pipe split policy first so we can predict the pipe split correctly
* (dcn32_predict_pipe_split).
*/
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
if (!res_ctx->pipe_ctx[i].stream)
continue;
- pipe = &res_ctx->pipe_ctx[i];
- timing = &pipe->stream->timing;
-
- pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
- vsr_odm_support = (res_ctx->pipe_ctx[i].stream->src.width >= 5120 &&
- res_ctx->pipe_ctx[i].stream->src.width > res_ctx->pipe_ctx[i].stream->dst.width);
- if (context->stream_count == 1 &&
- context->stream_status[0].plane_count == 1 &&
- !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) &&
- is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) &&
- pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ &&
- dc->debug.enable_single_display_2to1_odm_policy &&
- !vsr_odm_support) { //excluding 2to1 ODM combine on >= 5k vsr
+ if (should_allow_odm_power_optimization(dc, context))
pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
- }
+ else
+ pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
pipe_cnt++;
}
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 14/21] drm/amd/display: add pipe topology update log
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (12 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 13/21] drm/amd/display: switch to new ODM policy for windowed MPO ODM support Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 15/21] drm/amd/display: Remove wait while locked Hamza Mahfooz
` (7 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, Wenjing Liu, Daniel Wheeler,
solomon.chiu, jerry.zuo, Aurabindo.Pillai, hamza.mahfooz,
wayne.lin, Jun Lei, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Wenjing Liu <wenjing.liu@amd.com>
Given an issue with pipe topology transition. It is very hard to tell
the before and after pipe topology without a pipe topology logging. The
change adds such logging to help with visualizing the issue.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 159 ++++++++++++++++++
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 10 +-
drivers/gpu/drm/amd/display/dc/inc/resource.h | 7 +
3 files changed, 168 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 84db7c5fb852..f32337122f5b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1865,6 +1865,165 @@ int resource_get_odm_slice_index(const struct pipe_ctx *pipe_ctx)
return index;
}
+bool resource_is_pipe_topology_changed(const struct dc_state *state_a,
+ const struct dc_state *state_b)
+{
+ int i;
+ const struct pipe_ctx *pipe_a, *pipe_b;
+
+ if (state_a->stream_count != state_b->stream_count)
+ return true;
+
+ for (i = 0; i < MAX_PIPES; i++) {
+ pipe_a = &state_a->res_ctx.pipe_ctx[i];
+ pipe_b = &state_b->res_ctx.pipe_ctx[i];
+
+ if (pipe_a->stream && !pipe_b->stream)
+ return true;
+ else if (!pipe_a->stream && pipe_b->stream)
+ return true;
+
+ if (pipe_a->plane_state && !pipe_b->plane_state)
+ return true;
+ else if (!pipe_a->plane_state && pipe_b->plane_state)
+ return true;
+
+ if (pipe_a->bottom_pipe && pipe_b->bottom_pipe) {
+ if (pipe_a->bottom_pipe->pipe_idx != pipe_b->bottom_pipe->pipe_idx)
+ return true;
+ if ((pipe_a->bottom_pipe->plane_state == pipe_a->plane_state) &&
+ (pipe_b->bottom_pipe->plane_state != pipe_b->plane_state))
+ return true;
+ else if ((pipe_a->bottom_pipe->plane_state != pipe_a->plane_state) &&
+ (pipe_b->bottom_pipe->plane_state == pipe_b->plane_state))
+ return true;
+ } else if (pipe_a->bottom_pipe || pipe_b->bottom_pipe) {
+ return true;
+ }
+
+ if (pipe_a->next_odm_pipe && pipe_b->next_odm_pipe) {
+ if (pipe_a->next_odm_pipe->pipe_idx != pipe_b->next_odm_pipe->pipe_idx)
+ return true;
+ } else if (pipe_a->next_odm_pipe || pipe_b->next_odm_pipe) {
+ return true;
+ }
+ }
+ return false;
+}
+
+/*
+ * Sample log:
+ * pipe topology update
+ * ________________________
+ * | plane0 slice0 stream0|
+ * |DPP0----OPP0----OTG0----| <--- case 0 (OTG master pipe with plane)
+ * | plane1 | | |
+ * |DPP1----| | | <--- case 5 (DPP pipe not in last slice)
+ * | plane0 slice1 | |
+ * |DPP2----OPP2----| | <--- case 2 (OPP head pipe with plane)
+ * | plane1 | |
+ * |DPP3----| | <--- case 4 (DPP pipe in last slice)
+ * | slice0 stream1|
+ * |DPG4----OPP4----OTG4----| <--- case 1 (OTG master pipe without plane)
+ * | slice1 | |
+ * |DPG5----OPP5----| | <--- case 3 (OPP head pipe without plane)
+ * |________________________|
+ */
+
+static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,
+ int stream_idx, int slice_idx, int plane_idx, int slice_count,
+ bool is_primary)
+{
+ DC_LOGGER_INIT(dc->ctx->logger);
+
+ if (slice_idx == 0 && plane_idx == 0 && is_primary) {
+ /* case 0 (OTG master pipe with plane) */
+ DC_LOG_DC(" | plane%d slice%d stream%d|",
+ plane_idx, slice_idx, stream_idx);
+ DC_LOG_DC(" |DPP%d----OPP%d----OTG%d----|",
+ pipe->plane_res.dpp->inst,
+ pipe->stream_res.opp->inst,
+ pipe->stream_res.tg->inst);
+ } else if (slice_idx == 0 && plane_idx == -1) {
+ /* case 1 (OTG master pipe without plane) */
+ DC_LOG_DC(" | slice%d stream%d|",
+ slice_idx, stream_idx);
+ DC_LOG_DC(" |DPG%d----OPP%d----OTG%d----|",
+ pipe->stream_res.opp->inst,
+ pipe->stream_res.opp->inst,
+ pipe->stream_res.tg->inst);
+ } else if (slice_idx != 0 && plane_idx == 0 && is_primary) {
+ /* case 2 (OPP head pipe with plane) */
+ DC_LOG_DC(" | plane%d slice%d | |",
+ plane_idx, slice_idx);
+ DC_LOG_DC(" |DPP%d----OPP%d----| |",
+ pipe->plane_res.dpp->inst,
+ pipe->stream_res.opp->inst);
+ } else if (slice_idx != 0 && plane_idx == -1) {
+ /* case 3 (OPP head pipe without plane) */
+ DC_LOG_DC(" | slice%d | |", slice_idx);
+ DC_LOG_DC(" |DPG%d----OPP%d----| |",
+ pipe->plane_res.dpp->inst,
+ pipe->stream_res.opp->inst);
+ } else if (slice_idx == slice_count - 1) {
+ /* case 4 (DPP pipe in last slice) */
+ DC_LOG_DC(" | plane%d | |", plane_idx);
+ DC_LOG_DC(" |DPP%d----| |",
+ pipe->plane_res.dpp->inst);
+ } else {
+ /* case 5 (DPP pipe not in last slice) */
+ DC_LOG_DC(" | plane%d | | |", plane_idx);
+ DC_LOG_DC(" |DPP%d----| | |",
+ pipe->plane_res.dpp->inst);
+ }
+}
+
+void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)
+{
+ struct pipe_ctx *otg_master;
+ struct pipe_ctx *opp_heads[MAX_PIPES];
+ struct pipe_ctx *dpp_pipes[MAX_PIPES];
+
+ int stream_idx, slice_idx, dpp_idx, plane_idx, slice_count, dpp_count;
+ bool is_primary;
+ DC_LOGGER_INIT(dc->ctx->logger);
+
+ DC_LOG_DC(" pipe topology update");
+ DC_LOG_DC(" ________________________");
+ for (stream_idx = 0; stream_idx < state->stream_count; stream_idx++) {
+ otg_master = resource_get_otg_master_for_stream(
+ &state->res_ctx, state->streams[stream_idx]);
+ slice_count = resource_get_opp_heads_for_otg_master(otg_master,
+ &state->res_ctx, opp_heads);
+ for (slice_idx = 0; slice_idx < slice_count; slice_idx++) {
+ if (opp_heads[slice_idx]->plane_state) {
+ plane_idx = 0;
+ dpp_count = resource_get_dpp_pipes_for_opp_head(
+ opp_heads[slice_idx],
+ &state->res_ctx,
+ dpp_pipes);
+ for (dpp_idx = 0; dpp_idx < dpp_count; dpp_idx++) {
+ is_primary = !dpp_pipes[dpp_idx]->top_pipe ||
+ dpp_pipes[dpp_idx]->top_pipe->plane_state != dpp_pipes[dpp_idx]->plane_state;
+ resource_log_pipe(dc, dpp_pipes[dpp_idx],
+ stream_idx, slice_idx,
+ plane_idx, slice_count,
+ is_primary);
+ if (is_primary)
+ plane_idx++;
+ }
+ } else {
+ plane_idx = -1;
+ resource_log_pipe(dc, opp_heads[slice_idx],
+ stream_idx, slice_idx, plane_idx,
+ slice_count, true);
+ }
+
+ }
+ }
+ DC_LOG_DC(" |________________________|\n");
+}
+
static struct pipe_ctx *get_tail_pipe(
struct pipe_ctx *head_pipe)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 347156d02f21..dd4c7a7faf28 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1816,14 +1816,8 @@ void dcn20_program_front_end_for_ctx(
struct dce_hwseq *hws = dc->hwseq;
DC_LOGGER_INIT(dc->ctx->logger);
- /* Carry over GSL groups in case the context is changing. */
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
- struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
-
- if (pipe_ctx->stream == old_pipe_ctx->stream)
- pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group;
- }
+ if (resource_is_pipe_topology_changed(dc->current_state, context))
+ resource_log_pipe_topology_update(dc, context);
if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 55efd5600521..6777b07d0727 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -437,6 +437,13 @@ int resource_get_odm_slice_count(const struct pipe_ctx *otg_master);
/* Get the ODM slice index counting from 0 from left most slice */
int resource_get_odm_slice_index(const struct pipe_ctx *opp_head);
+/* determine if pipe topology is changed between state a and state b */
+bool resource_is_pipe_topology_changed(const struct dc_state *state_a,
+ const struct dc_state *state_b);
+
+/* log the pipe topology update in state */
+void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state);
+
/*
* Look for a free pipe in new resource context that is used as a secondary OPP
* head by cur_otg_master.
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 15/21] drm/amd/display: Remove wait while locked
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (13 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 14/21] drm/amd/display: add pipe topology update log Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 16/21] drm/amd/display: Skip dmub memory flush when not needed Hamza Mahfooz
` (6 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, stable, Gabe Teeger, Daniel Wheeler,
solomon.chiu, jerry.zuo, Aurabindo.Pillai, hamza.mahfooz,
wayne.lin, Jun Lei, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Gabe Teeger <gabe.teeger@amd.com>
[Why]
We wait for mpc idle while in a locked state, leading to potential
deadlock.
[What]
Move the wait_for_idle call to outside of HW lock. This and a
call to wait_drr_doublebuffer_pending_clear are moved added to a new
static helper function called wait_for_outstanding_hw_updates, to make
the interface clearer.
Cc: stable@vger.kernel.org
Fixes: 8f0d304d21b3 ("drm/amd/display: Do not commit pipe when updating DRR")
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
---
drivers/gpu/drm/amd/display/dc/Makefile | 1 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 58 +++++++++++++------
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 11 ----
3 files changed, 42 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index 69ffd4424dc7..1b8c2aef4633 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -78,3 +78,4 @@ DC_EDID += dc_edid_parser.o
AMD_DISPLAY_DMUB = $(addprefix $(AMDDALPATH)/dc/,$(DC_DMUB))
AMD_DISPLAY_EDID = $(addprefix $(AMDDALPATH)/dc/,$(DC_EDID))
AMD_DISPLAY_FILES += $(AMD_DISPLAY_DMUB) $(AMD_DISPLAY_EDID)
+
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c6f6dc972c2a..5aab67868cb6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3501,6 +3501,45 @@ static void commit_planes_for_stream_fast(struct dc *dc,
top_pipe_to_program->stream->update_flags.raw = 0;
}
+static void wait_for_outstanding_hw_updates(struct dc *dc, const struct dc_state *dc_context)
+{
+/*
+ * This function calls HWSS to wait for any potentially double buffered
+ * operations to complete. It should be invoked as a pre-amble prior
+ * to full update programming before asserting any HW locks.
+ */
+ int pipe_idx;
+ int opp_inst;
+ int opp_count = dc->res_pool->pipe_count;
+ struct hubp *hubp;
+ int mpcc_inst;
+ const struct pipe_ctx *pipe_ctx;
+
+ for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
+ pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx];
+
+ if (!pipe_ctx->stream)
+ continue;
+
+ if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear)
+ pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg);
+
+ hubp = pipe_ctx->plane_res.hubp;
+ if (!hubp)
+ continue;
+
+ mpcc_inst = hubp->inst;
+ // MPCC inst is equal to pipe index in practice
+ for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
+ if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
+ dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
+ dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
+ break;
+ }
+ }
+ }
+}
+
static void commit_planes_for_stream(struct dc *dc,
struct dc_surface_update *srf_updates,
int surface_count,
@@ -3519,24 +3558,9 @@ static void commit_planes_for_stream(struct dc *dc,
// dc->current_state anymore, so we have to cache it before we apply
// the new SubVP context
subvp_prev_use = false;
-
-
dc_z10_restore(dc);
-
- if (update_type == UPDATE_TYPE_FULL) {
- /* wait for all double-buffer activity to clear on all pipes */
- int pipe_idx;
-
- for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
-
- if (!pipe_ctx->stream)
- continue;
-
- if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear)
- pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg);
- }
- }
+ if (update_type == UPDATE_TYPE_FULL)
+ wait_for_outstanding_hw_updates(dc, context);
if (update_type == UPDATE_TYPE_FULL) {
dc_allow_idle_optimizations(dc, false);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index dd4c7a7faf28..971fa8bf6d1f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1563,17 +1563,6 @@ static void dcn20_update_dchubp_dpp(
|| plane_state->update_flags.bits.global_alpha_change
|| plane_state->update_flags.bits.per_pixel_alpha_change) {
// MPCC inst is equal to pipe index in practice
- int mpcc_inst = hubp->inst;
- int opp_inst;
- int opp_count = dc->res_pool->pipe_count;
-
- for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
- if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
- dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
- dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
- break;
- }
- }
hws->funcs.update_mpcc(dc, pipe_ctx);
}
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 16/21] drm/amd/display: Skip dmub memory flush when not needed
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (14 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 15/21] drm/amd/display: Remove wait while locked Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 17/21] drm/amd/display: Fix incorrect comment Hamza Mahfooz
` (5 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Dillon Varone, Chris Park, Sunpeng.Li,
Harry.Wentland, qingqing.zhuo, Rodrigo.Siqueira, roman.li,
Daniel Wheeler, solomon.chiu, jerry.zuo, Aurabindo.Pillai,
hamza.mahfooz, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Dillon Varone <dillon.varone@amd.com>
[WHY&HOW]
Readback is only necessary when loaded via CPU.
Reviewed-by: Chris Park <chris.park@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 8 ++++++++
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 3 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index e7a50cbf2540..7a892f7bc7b0 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -142,6 +142,13 @@ enum dpia_notify_bw_alloc_status {
DPIA_BW_ALLOC_CAPS_CHANGED
};
+/* enum dmub_memory_access_type - memory access method */
+enum dmub_memory_access_type {
+ DMUB_MEMORY_ACCESS_DEFAULT,
+ DMUB_MEMORY_ACCESS_CPU = DMUB_MEMORY_ACCESS_DEFAULT,
+ DMUB_MEMORY_ACCESS_DMA
+};
+
/**
* struct dmub_region - dmub hw memory region
* @base: base address for region, must be 256 byte aligned
@@ -264,6 +271,7 @@ struct dmub_srv_hw_params {
bool dpia_hpd_int_enable_supported;
bool disable_clock_gate;
bool disallow_dispclk_dppclk_ds;
+ enum dmub_memory_access_type mem_access_type;
};
/**
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 53464c3e49c1..d7d142c5b06a 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -564,7 +564,8 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
* DMCUB when backdoor loading if the write from x86 hasn't been
* flushed yet. This only occurs in backdoor loading.
*/
- dmub_flush_buffer_mem(inst_fb);
+ if (params->mem_access_type == DMUB_MEMORY_ACCESS_CPU)
+ dmub_flush_buffer_mem(inst_fb);
if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode)
dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1);
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 17/21] drm/amd/display: Fix incorrect comment
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (15 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 16/21] drm/amd/display: Skip dmub memory flush when not needed Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 18/21] drm/amd/display: correct z8_watermark 16bit to 20bit mask Hamza Mahfooz
` (4 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, Daniel Wheeler, solomon.chiu,
jerry.zuo, Aurabindo Pillai, hamza.mahfooz, wayne.lin,
Bhawanpreet.Lakha, agustin.gutierrez, pavle.kotarac
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
Fix incorrect comment about hardware capabilities debugfs interface.
Reviewed-by: Jerry Zuo <jerry.zuo@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index b5f3b33b625d..0c4dd922cfaf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -3606,8 +3606,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
disable_hpd_set, "%llu\n");
/*
- * Returns 1 if hardware supports MALL cache
- * 0 otherwise.
+ * Prints hardware capabilities. These are used for IGT testing.
*/
static int capabilities_show(struct seq_file *m, void *unused)
{
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 18/21] drm/amd/display: correct z8_watermark 16bit to 20bit mask
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (16 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 17/21] drm/amd/display: Fix incorrect comment Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 19/21] drm/amd/display: Add debugfs interface for ODM combine info Hamza Mahfooz
` (3 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Charlene Liu, Muhammad Ahmed, Sunpeng.Li,
Harry.Wentland, qingqing.zhuo, Rodrigo.Siqueira, roman.li,
Daniel Wheeler, solomon.chiu, jerry.zuo, Aurabindo.Pillai,
hamza.mahfooz, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Charlene Liu <charlene.liu@amd.com>
remove double adjustment for DPREFCLK SS. dprefclk adjusted with SS is
used for dp audio only. if adjust DP_DTO, need to adjust VID_M/N
Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
---
.../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 32 +++++++++----------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
index 1f4e0b6261ad..f6b59c29cee2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
@@ -355,7 +355,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,
DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
@@ -371,7 +371,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->a.cstate_pstate.cstate_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->a.cstate_pstate.cstate_exit_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,
DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n"
@@ -387,7 +387,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns;
prog_wm_value = convert_and_clamp(
watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, 0,
DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_A calculated =%d\n"
@@ -403,7 +403,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->a.cstate_pstate.cstate_exit_z8_ns;
prog_wm_value = convert_and_clamp(
watermarks->a.cstate_pstate.cstate_exit_z8_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, 0,
DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_A calculated =%d\n"
@@ -420,7 +420,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,
DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n"
@@ -436,7 +436,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->b.cstate_pstate.cstate_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->b.cstate_pstate.cstate_exit_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,
DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n"
@@ -452,7 +452,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns;
prog_wm_value = convert_and_clamp(
watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, 0,
DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_B calculated =%d\n"
@@ -468,7 +468,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->b.cstate_pstate.cstate_exit_z8_ns;
prog_wm_value = convert_and_clamp(
watermarks->b.cstate_pstate.cstate_exit_z8_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, 0,
DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_B calculated =%d\n"
@@ -485,7 +485,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0,
DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n"
@@ -501,7 +501,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->c.cstate_pstate.cstate_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->c.cstate_pstate.cstate_exit_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0,
DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n"
@@ -517,7 +517,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns;
prog_wm_value = convert_and_clamp(
watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, 0,
DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_C calculated =%d\n"
@@ -533,7 +533,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->c.cstate_pstate.cstate_exit_z8_ns;
prog_wm_value = convert_and_clamp(
watermarks->c.cstate_pstate.cstate_exit_z8_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, 0,
DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_C calculated =%d\n"
@@ -550,7 +550,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0,
DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n"
@@ -566,7 +566,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->d.cstate_pstate.cstate_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->d.cstate_pstate.cstate_exit_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0,
DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n"
@@ -582,7 +582,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns;
prog_wm_value = convert_and_clamp(
watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, 0,
DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_D calculated =%d\n"
@@ -598,7 +598,7 @@ static bool hubbub31_program_stutter_watermarks(
watermarks->d.cstate_pstate.cstate_exit_z8_ns;
prog_wm_value = convert_and_clamp(
watermarks->d.cstate_pstate.cstate_exit_z8_ns,
- refclk_mhz, 0xffff);
+ refclk_mhz, 0xfffff);
REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, 0,
DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_D calculated =%d\n"
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 19/21] drm/amd/display: Add debugfs interface for ODM combine info
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (17 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 18/21] drm/amd/display: correct z8_watermark 16bit to 20bit mask Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 20/21] drm/amd/display: fix pipe topology logging error Hamza Mahfooz
` (2 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Rodrigo.Siqueira, roman.li, Wenjing Liu, Daniel Wheeler,
solomon.chiu, jerry.zuo, Aurabindo Pillai, hamza.mahfooz,
wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez, pavle.kotarac
From: Aurabindo Pillai <aurabindo.pillai@amd.com>
[Why]
For use with IGT tests in userspace, the number of ODM segments in use
is required to be exposed to userspace to verify that ODM Combine is
working as expected when special timings are committed.
[How]
Add a connector specific debugfs entry that prints the number of ODM
segments in use.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 33 ++++++++++++++++++-
.../gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 25 ++++++++++++++
.../gpu/drm/amd/display/dc/dcn32/dcn32_optc.h | 1 +
.../amd/display/dc/inc/hw/timing_generator.h | 1 +
4 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 0c4dd922cfaf..17d1990ea832 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1201,6 +1201,35 @@ static int internal_display_show(struct seq_file *m, void *data)
return 0;
}
+/*
+ * Returns the number of segments used if ODM Combine mode is enabled.
+ * Example usage: cat /sys/kernel/debug/dri/0/DP-1/odm_combine_segments
+ */
+static int odm_combine_segments_show(struct seq_file *m, void *unused)
+{
+ struct drm_connector *connector = m->private;
+ struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+ struct dc_link *link = aconnector->dc_link;
+ struct pipe_ctx *pipe_ctx = NULL;
+ int i, segments = 0;
+
+ for (i = 0; i < MAX_PIPES; i++) {
+ pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
+ if (pipe_ctx->stream &&
+ pipe_ctx->stream->link == link)
+ break;
+ }
+
+ if (connector->status != connector_status_connected)
+ return -ENODEV;
+
+ if (pipe_ctx != NULL && pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments)
+ pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments);
+
+ seq_printf(m, "%d\n", segments);
+ return 0;
+}
+
/* function description
*
* generic SDP message access for testing
@@ -2713,6 +2742,7 @@ DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
DEFINE_SHOW_ATTRIBUTE(internal_display);
+DEFINE_SHOW_ATTRIBUTE(odm_combine_segments);
DEFINE_SHOW_ATTRIBUTE(psr_capability);
DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector);
DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status);
@@ -2991,7 +3021,8 @@ static const struct {
} connector_debugfs_entries[] = {
{"force_yuv420_output", &force_yuv420_output_fops},
{"trigger_hotplug", &trigger_hotplug_debugfs_fops},
- {"internal_display", &internal_display_fops}
+ {"internal_display", &internal_display_fops},
+ {"odm_combine_segments", &odm_combine_segments_fops}
};
/*
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
index 8abb94f60078..e7e25c58c692 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
@@ -98,6 +98,30 @@ static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, i
optc1->opp_count = opp_cnt;
}
+void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combine_segments)
+{
+ struct optc *optc1 = DCN10TG_FROM_TG(tg);
+ int segments;
+
+ REG_GET(OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, &segments);
+
+ switch (segments) {
+ case 0:
+ *odm_combine_segments = 1;
+ break;
+ case 1:
+ *odm_combine_segments = 2;
+ break;
+ case 3:
+ *odm_combine_segments = 4;
+ break;
+ /* 2 is reserved */
+ case 2:
+ default:
+ *odm_combine_segments = -1;
+ }
+}
+
void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
@@ -303,6 +327,7 @@ static struct timing_generator_funcs dcn32_tg_funcs = {
.set_dwb_source = NULL,
.set_odm_bypass = optc32_set_odm_bypass,
.set_odm_combine = optc32_set_odm_combine,
+ .get_odm_combine_segments = optc32_get_odm_combine_segments,
.set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
.get_optc_source = optc2_get_optc_source,
.set_out_mux = optc3_set_out_mux,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
index abf0121a1006..93cc7fc8472c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
@@ -180,5 +180,6 @@
void dcn32_timing_generator_init(struct optc *optc1);
void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode);
+void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combine_segments);
#endif /* __DC_OPTC_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index c21e7ffd5bd0..9a00a99317b2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -309,6 +309,7 @@ struct timing_generator_funcs {
*/
void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
struct dc_crtc_timing *timing);
+ void (*get_odm_combine_segments)(struct timing_generator *tg, int *odm_segments);
void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode);
void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
void (*set_gsl_source_select)(struct timing_generator *optc,
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 20/21] drm/amd/display: fix pipe topology logging error
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (18 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 19/21] drm/amd/display: Add debugfs interface for ODM combine info Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-23 15:58 ` [PATCH 21/21] drm/amd/display: 3.2.249 Hamza Mahfooz
2023-08-28 13:21 ` [PATCH 00/21] DC Patches August 23, 2023 Wheeler, Daniel
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Dillon Varone, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, roman.li, Wenjing Liu,
Daniel Wheeler, solomon.chiu, jerry.zuo, Aurabindo.Pillai,
hamza.mahfooz, wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez,
pavle.kotarac
From: Wenjing Liu <wenjing.liu@amd.com>
[why]
There is a logging error in the recently added pipe topology log.
If the plane with index 0 uses MPC combine, the log shows that
as two separate planes.
[how]
Initialize plane idx as -1 and increment plane idx before logging
any primary dpp pipes of a plane.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index f32337122f5b..30424ba7761d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1996,8 +1996,8 @@ void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)
slice_count = resource_get_opp_heads_for_otg_master(otg_master,
&state->res_ctx, opp_heads);
for (slice_idx = 0; slice_idx < slice_count; slice_idx++) {
+ plane_idx = -1;
if (opp_heads[slice_idx]->plane_state) {
- plane_idx = 0;
dpp_count = resource_get_dpp_pipes_for_opp_head(
opp_heads[slice_idx],
&state->res_ctx,
@@ -2005,15 +2005,14 @@ void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)
for (dpp_idx = 0; dpp_idx < dpp_count; dpp_idx++) {
is_primary = !dpp_pipes[dpp_idx]->top_pipe ||
dpp_pipes[dpp_idx]->top_pipe->plane_state != dpp_pipes[dpp_idx]->plane_state;
+ if (is_primary)
+ plane_idx++;
resource_log_pipe(dc, dpp_pipes[dpp_idx],
stream_idx, slice_idx,
plane_idx, slice_count,
is_primary);
- if (is_primary)
- plane_idx++;
}
} else {
- plane_idx = -1;
resource_log_pipe(dc, opp_heads[slice_idx],
stream_idx, slice_idx, plane_idx,
slice_count, true);
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 21/21] drm/amd/display: 3.2.249
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (19 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 20/21] drm/amd/display: fix pipe topology logging error Hamza Mahfooz
@ 2023-08-23 15:58 ` Hamza Mahfooz
2023-08-28 13:21 ` [PATCH 00/21] DC Patches August 23, 2023 Wheeler, Daniel
21 siblings, 0 replies; 23+ messages in thread
From: Hamza Mahfooz @ 2023-08-23 15:58 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
Martin Leung, Rodrigo.Siqueira, roman.li, Daniel Wheeler,
solomon.chiu, jerry.zuo, Aurabindo.Pillai, hamza.mahfooz,
wayne.lin, Bhawanpreet.Lakha, agustin.gutierrez, pavle.kotarac
From: Martin Leung <martin.leung@amd.com>
This version brings along the following:
- DCN315 fixes
- DCN31 fixes
- DPIA fixes
- Dump the pipe topology when it updates
- Misc code cleanups
- New debugfs interface to query the current ODM combine configuration
- ODM fixes
- Potential deadlock while waiting for MPC idle fix
- Support for windowed MPO ODM
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Martin Leung <martin.leung@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 5d41a14844da..e663260f0619 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
struct set_config_cmd_payload;
struct dmub_notification;
-#define DC_VER "3.2.248"
+#define DC_VER "3.2.249"
#define MAX_SURFACES 3
#define MAX_PLANES 6
--
2.41.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* RE: [PATCH 00/21] DC Patches August 23, 2023
2023-08-23 15:58 [PATCH 00/21] DC Patches August 23, 2023 Hamza Mahfooz
` (20 preceding siblings ...)
2023-08-23 15:58 ` [PATCH 21/21] drm/amd/display: 3.2.249 Hamza Mahfooz
@ 2023-08-28 13:21 ` Wheeler, Daniel
21 siblings, 0 replies; 23+ messages in thread
From: Wheeler, Daniel @ 2023-08-28 13:21 UTC (permalink / raw)
To: Mahfooz, Hamza, amd-gfx@lists.freedesktop.org
Cc: Wang, Chao-kai (Stylon), Li, Sun peng (Leo), Wentland, Harry,
Zhuo, Qingqing (Lillian), Siqueira, Rodrigo, Li, Roman,
Chiu, Solomon, Zuo, Jerry, Pillai, Aurabindo, Lin, Wayne,
Lakha, Bhawanpreet, Gutierrez, Agustin, Kotarac, Pavle
[Public]
Hi all,
This week this patchset was tested on the following systems:
* Lenovo ThinkBook T13s Gen4 with AMD Ryzen 5 6600U
* MSI Gaming X Trio RX 6800
* Gigabyte Gaming OC RX 7900 XTX
These systems were tested on the following display/connection types:
* eDP, (1080p 60hz [5650U]) (1920x1200 60hz [6600U]) (2560x1600 120hz[6600U])
* VGA and DVI (1680x1050 60hz [DP to VGA/DVI, USB-C to VGA/DVI])
* DP/HDMI/USB-C (1440p 170hz, 4k 60hz, 4k 144hz, 4k 240hz [Includes USB-C to DP/HDMI adapters])
* Thunderbolt (LG Ultrafine 5k)
* MST (Startech MST14DP123DP [DP to 3x DP] and 2x 4k 60Hz displays)
* DSC (with Cable Matters 101075 [DP to 3x DP] with 3x 4k60 displays, and HP Hook G2 with 1 4k60 display)
* USB 4 (Kensington SD5700T and 1x 4k 60Hz display)
* PCON (Club3D CAC-1085 and 1x 4k 144Hz display [at 4k 120HZ, as that is the max the adapter supports])
The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to):
* Changing display configurations and settings
* Benchmark testing
* Feature testing (Freesync, etc.)
Automated testing includes (but is not limited to):
* Script testing (scripts to automate some of the manual checks)
* IGT testing
The patchset consists of the amd-staging-drm-next branch (Head commit - 1d35782cce09 drm/amdgpu: Fix the return for gpu mode1_reset) with new patches added on top of it.
Tested on Ubuntu 22.04.3, on Wayland and X11, using Gnome for both.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Thank you,
Dan Wheeler
Sr. Technologist | AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
amd.com
-----Original Message-----
From: Mahfooz, Hamza <Hamza.Mahfooz@amd.com>
Sent: Wednesday, August 23, 2023 11:58 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry <Harry.Wentland@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Li, Roman <Roman.Li@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>; Chiu, Solomon <Solomon.Chiu@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Zuo, Jerry <Jerry.Zuo@amd.com>; Mahfooz, Hamza <Hamza.Mahfooz@amd.com>; Wheeler, Daniel <Daniel.Wheeler@amd.com>
Subject: [PATCH 00/21] DC Patches August 23, 2023
This DC patch-set brings improvements in multiple areas. In summary, we
highlight:
* DCN315 fixes
* DCN31 fixes
* DPIA fixes
* Dump the pipe topology when it updates
* Misc code cleanups
* New debugfs interface to query the current ODM combine configuration
* ODM fixes
* Potential deadlock while waiting for MPC idle fix
* Support for windowed MPO ODM
Cc: Daniel Wheeler <daniel.wheeler@amd.com>
Aurabindo Pillai (2):
drm/amd/display: Fix incorrect comment
drm/amd/display: Add debugfs interface for ODM combine info
Charlene Liu (1):
drm/amd/display: correct z8_watermark 16bit to 20bit mask
Dillon Varone (1):
drm/amd/display: Skip dmub memory flush when not needed
Ethan Bitnun (1):
drm/amd/display: Add support for 1080p SubVP to reduce idle power
Fudong Wang (1):
drm/amd/display: Add smu write msg id fail retry process
Gabe Teeger (1):
drm/amd/display: Remove wait while locked
Martin Leung (1):
drm/amd/display: 3.2.249
Mustapha Ghaddar (1):
drm/amd/display: Add DPIA Link Encoder Assignment Fix
Wenjing Liu (12):
Partially revert "drm/amd/display: update add plane to context logic
with a new algorithm"
drm/amd/display: update blank state on ODM changes
drm/amd/display: always switch off ODM before committing more streams
drm/amd/display: add comments to add plane functions
drm/amd/display: rename function to add otg master for stream
drm/amd/display: add new resource interface for acquiring sec opp
heads and release pipe
drm/amd/display: add new resource interfaces to update odm mpc slice
count
drm/amd/display: add more pipe resource interfaces
drm/amd/display: use new pipe allocation interface in dcn32 fpu
drm/amd/display: switch to new ODM policy for windowed MPO ODM support
drm/amd/display: add pipe topology update log
drm/amd/display: fix pipe topology logging error
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 36 +-
drivers/gpu/drm/amd/display/dc/Makefile | 1 +
.../display/dc/clk_mgr/dcn315/dcn315_smu.c | 20 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 68 +-
.../drm/amd/display/dc/core/dc_link_enc_cfg.c | 35 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 1473 +++++++++++++----
.../gpu/drm/amd/display/dc/core/dc_stream.c | 2 +-
drivers/gpu/drm/amd/display/dc/dc.h | 3 +-
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 59 +-
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 22 +-
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 4 +-
.../amd/display/dc/dcn201/dcn201_resource.c | 1 +
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 1 +
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 1 +
.../amd/display/dc/dcn301/dcn301_resource.c | 1 +
.../amd/display/dc/dcn302/dcn302_resource.c | 1 +
.../amd/display/dc/dcn303/dcn303_resource.c | 1 +
.../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 32 +-
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 1 +
.../amd/display/dc/dcn314/dcn314_resource.c | 24 +
.../amd/display/dc/dcn315/dcn315_resource.c | 1 +
.../amd/display/dc/dcn316/dcn316_resource.c | 1 +
.../gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 25 +
.../gpu/drm/amd/display/dc/dcn32/dcn32_optc.h | 1 +
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 274 ++-
.../drm/amd/display/dc/dcn32/dcn32_resource.h | 12 +-
.../display/dc/dcn32/dcn32_resource_helpers.c | 46 +
.../amd/display/dc/dcn321/dcn321_resource.c | 1 +
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 6 +-
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 491 ++++--
.../gpu/drm/amd/display/dc/inc/core_types.h | 11 +
.../amd/display/dc/inc/hw/timing_generator.h | 1 +
drivers/gpu/drm/amd/display/dc/inc/resource.h | 262 ++-
.../drm/amd/display/dc/link/link_factory.c | 4 +
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 8 +
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 3 +-
36 files changed, 2220 insertions(+), 713 deletions(-)
--
2.41.0
^ permalink raw reply [flat|nested] 23+ messages in thread