From: Alex Deucher <alexander.deucher@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Alex Deucher <alexander.deucher@amd.com>,
Shaoyun.liu <Shaoyun.liu@amd.com>
Subject: [PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling
Date: Wed, 19 Mar 2025 15:08:47 -0400 [thread overview]
Message-ID: <20250319190850.3899718-1-alexander.deucher@amd.com> (raw)
Break when we get to the end of the supported pipes
rather than continuing the loop.
Reviewed-by: Shaoyun.liu <Shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 3b83880f9e2cc..10f14bf925778 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -132,7 +132,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
/* use only 1st MEC pipes */
if (i >= adev->gfx.mec.num_pipe_per_mec)
- continue;
+ break;
adev->mes.compute_hqd_mask[i] = 0xc;
}
--
2.48.1
next reply other threads:[~2025-03-19 19:09 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-19 19:08 Alex Deucher [this message]
2025-03-19 19:08 ` [PATCH 2/4] drm/amdgpu/mes: enable compute pipes across all MEC Alex Deucher
2025-03-20 10:17 ` Liang, Prike
2025-03-20 11:14 ` Lazar, Lijo
2025-03-20 13:00 ` Alex Deucher
2025-03-19 19:08 ` [PATCH 3/4] drm/amdgpu/mes: drop MES 10.x leftovers Alex Deucher
2025-03-20 10:20 ` Liang, Prike
2025-03-19 19:08 ` [PATCH 4/4] drm/amdgpu/mes: clean up SDMA HQD loop Alex Deucher
2025-03-20 12:06 ` Liang, Prike
2025-03-20 10:14 ` [PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling Liang, Prike
2025-03-20 11:14 ` Lazar, Lijo
2025-03-20 12:13 ` Liang, Prike
2025-03-20 12:51 ` Alex Deucher
2025-03-20 13:44 ` Lazar, Lijo
2025-03-20 13:53 ` Alex Deucher
2025-03-20 14:21 ` Lazar, Lijo
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