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From: "Lazar, Lijo" <lijo.lazar@amd.com>
To: Alex Deucher <alexdeucher@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>,
	amd-gfx@lists.freedesktop.org,
	"Shaoyun.liu" <Shaoyun.liu@amd.com>
Subject: Re: [PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling
Date: Thu, 20 Mar 2025 19:14:01 +0530	[thread overview]
Message-ID: <878f6a71-204c-4f3b-becc-c8bb7ef80252@amd.com> (raw)
In-Reply-To: <CADnq5_Mw834v4AkCFW6tSqwE-i1poAK+83GpKt_cvb8HaHDjRQ@mail.gmail.com>



On 3/20/2025 6:21 PM, Alex Deucher wrote:
> On Thu, Mar 20, 2025 at 7:14 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>>
>>
>>
>> On 3/20/2025 12:38 AM, Alex Deucher wrote:
>>> Break when we get to the end of the supported pipes
>>> rather than continuing the loop.
>>>
>>> Reviewed-by: Shaoyun.liu <Shaoyun.liu@amd.com>
>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>> ---
>>>  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
>>> index 3b83880f9e2cc..10f14bf925778 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
>>> @@ -132,7 +132,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
>>>       for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
>>
>> Unless I'm not seeing something, why not just keep it i <
>> adev->gfx.mec.num_pipe_per_mec?
> 
> AMDGPU_MES_MAX_COMPUTE_PIPES Is the size of the array and I think it
> is aligned to the max supported by the firmware, so if we had
> num_pipe_per_mec larger than that for some reason this would prevent
> an overflow.
> 

I think it should be kept the other way and array size should be fixed,
otherwise it hides a real problem.

Thanks,
Lijo

> Alex
> 
>>
>> Thanks,
>> Lijo
>>
>>>               /* use only 1st MEC pipes */
>>>               if (i >= adev->gfx.mec.num_pipe_per_mec)
>>> -                     continue;
>>> +                     break;
>>>               adev->mes.compute_hqd_mask[i] = 0xc;
>>>       }
>>>
>>


  reply	other threads:[~2025-03-20 13:44 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-19 19:08 [PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling Alex Deucher
2025-03-19 19:08 ` [PATCH 2/4] drm/amdgpu/mes: enable compute pipes across all MEC Alex Deucher
2025-03-20 10:17   ` Liang, Prike
2025-03-20 11:14   ` Lazar, Lijo
2025-03-20 13:00     ` Alex Deucher
2025-03-19 19:08 ` [PATCH 3/4] drm/amdgpu/mes: drop MES 10.x leftovers Alex Deucher
2025-03-20 10:20   ` Liang, Prike
2025-03-19 19:08 ` [PATCH 4/4] drm/amdgpu/mes: clean up SDMA HQD loop Alex Deucher
2025-03-20 12:06   ` Liang, Prike
2025-03-20 10:14 ` [PATCH 1/4] drm/amdgpu/mes: optimize compute loop handling Liang, Prike
2025-03-20 11:14 ` Lazar, Lijo
2025-03-20 12:13   ` Liang, Prike
2025-03-20 12:51   ` Alex Deucher
2025-03-20 13:44     ` Lazar, Lijo [this message]
2025-03-20 13:53       ` Alex Deucher
2025-03-20 14:21         ` Lazar, Lijo

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