[PATCH 1/3] drm/amdgpu/gfx10: fix wptr reset in KGQ init

[PATCH 1/3] drm/amdgpu/gfx10: fix wptr reset in KGQ init

[Alex Deucher]

wptr is a 64 bit value and we need to update the
full value, not just 32 bits. Align with what we
already do for KCQs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index e9254ec3b6417..ef7d91a4437ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -6883,7 +6883,7 @@ static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
 			memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
 		/* reset the ring */
 		ring->wptr = 0;
-		*ring->wptr_cpu_addr = 0;
+		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
 		amdgpu_ring_clear_ring(ring);
 	}
 
-- 
2.52.0

[PATCH 2/3] drm/amdgpu/gfx11: fix wptr reset in KGQ init

[Alex Deucher]

wptr is a 64 bit value and we need to update the
full value, not just 32 bits. Align with what we
already do for KCQs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 6145cfc0334b2..b5a2d09fc3469 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4224,7 +4224,7 @@ static int gfx_v11_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
 			memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
 		/* reset the ring */
 		ring->wptr = 0;
-		*ring->wptr_cpu_addr = 0;
+		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
 		amdgpu_ring_clear_ring(ring);
 	}
 
-- 
2.52.0

[PATCH 3/3] drm/amdgpu/gfx12: fix wptr reset in KGQ init

[Alex Deucher]

wptr is a 64 bit value and we need to update the
full value, not just 32 bits. Align with what we
already do for KCQs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 9e48045b036a4..d8ab93c82366d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -3096,7 +3096,7 @@ static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
 			memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
 		/* reset the ring */
 		ring->wptr = 0;
-		*ring->wptr_cpu_addr = 0;
+		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
 		amdgpu_ring_clear_ring(ring);
 	}
 
-- 
2.52.0

RE: [PATCH 3/3] drm/amdgpu/gfx12: fix wptr reset in KGQ init

[Zhang, Jesse(Jie)]

[AMD Official Use Only - AMD Internal Distribution Only]

Series is :
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex
> Deucher
> Sent: Thursday, January 29, 2026 12:35 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: [PATCH 3/3] drm/amdgpu/gfx12: fix wptr reset in KGQ init
>
> wptr is a 64 bit value and we need to update the full value, not just 32 bits. Align with
> what we already do for KCQs.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> index 9e48045b036a4..d8ab93c82366d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> @@ -3096,7 +3096,7 @@ static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring
> *ring, bool reset)
>                       memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx],
> sizeof(*mqd));
>               /* reset the ring */
>               ring->wptr = 0;
> -             *ring->wptr_cpu_addr = 0;
> +             atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
>               amdgpu_ring_clear_ring(ring);
>       }
>
> --
> 2.52.0

Re: [PATCH 1/3] drm/amdgpu/gfx10: fix wptr reset in KGQ init

[Timur Kristóf]

On Thursday, January 29, 2026 5:34:44 AM Central European Standard Time Alex 
Deucher wrote:
> wptr is a 64 bit value and we need to update the
> full value, not just 32 bits. Align with what we
> already do for KCQs.
> 
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
for the series.

I notice that the code base already does this for gfx9, but is rather 
inconsistent on gfx6-8. If you think that's useful, I could submit some 
patches to do the same on older GPUs. What do you think?

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index e9254ec3b6417..ef7d91a4437ec
> 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -6883,7 +6883,7 @@ static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring
> *ring, bool reset) memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx],
> sizeof(*mqd)); /* reset the ring */
>  		ring->wptr = 0;
> -		*ring->wptr_cpu_addr = 0;
> +		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
>  		amdgpu_ring_clear_ring(ring);
>  	}

Re: [PATCH 1/3] drm/amdgpu/gfx10: fix wptr reset in KGQ init

[Alex Deucher]

On Thu, Jan 29, 2026 at 4:42 AM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> On Thursday, January 29, 2026 5:34:44 AM Central European Standard Time Alex
> Deucher wrote:
> > wptr is a 64 bit value and we need to update the
> > full value, not just 32 bits. Align with what we
> > already do for KCQs.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>
> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
> for the series.
>
> I notice that the code base already does this for gfx9, but is rather
> inconsistent on gfx6-8. If you think that's useful, I could submit some
> patches to do the same on older GPUs. What do you think?

Thanks.  Pre-gfx9 only had a 32 bit wptr so they don't use the upper 32 bits.

Alex

>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index e9254ec3b6417..ef7d91a4437ec
> > 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -6883,7 +6883,7 @@ static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring
> > *ring, bool reset) memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx],
> > sizeof(*mqd)); /* reset the ring */
> >               ring->wptr = 0;
> > -             *ring->wptr_cpu_addr = 0;
> > +             atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
> >               amdgpu_ring_clear_ring(ring);
> >       }
>
>
>
>

Re: [PATCH 1/3] drm/amdgpu/gfx10: fix wptr reset in KGQ init

[Tvrtko Ursulin]

On 29/01/2026 04:34, Alex Deucher wrote:
> wptr is a 64 bit value and we need to update the
> full value, not just 32 bits. Align with what we
> already do for KCQs.
> 
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index e9254ec3b6417..ef7d91a4437ec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -6883,7 +6883,7 @@ static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
>   			memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
>   		/* reset the ring */
>   		ring->wptr = 0;
> -		*ring->wptr_cpu_addr = 0;
> +		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);

For my education could I ask if this just about writing the 64-bit value 
or the atomic part is also important?

Regards,

Tvrtko

>   		amdgpu_ring_clear_ring(ring);
>   	}
>   

Re: [PATCH 1/3] drm/amdgpu/gfx10: fix wptr reset in KGQ init

[Alex Deucher]

On Thu, Jan 29, 2026 at 11:27 AM Tvrtko Ursulin <tursulin@ursulin.net> wrote:
>
>
> On 29/01/2026 04:34, Alex Deucher wrote:
> > wptr is a 64 bit value and we need to update the
> > full value, not just 32 bits. Align with what we
> > already do for KCQs.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index e9254ec3b6417..ef7d91a4437ec 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -6883,7 +6883,7 @@ static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
> >                       memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
> >               /* reset the ring */
> >               ring->wptr = 0;
> > -             *ring->wptr_cpu_addr = 0;
> > +             atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
>
> For my education could I ask if this just about writing the 64-bit value
> or the atomic part is also important?

Just the 64 bit value in this case.

Alex

>
> Regards,
>
> Tvrtko
>
> >               amdgpu_ring_clear_ring(ring);
> >       }
> >
>

Re: [PATCH 1/3] drm/amdgpu/gfx10: fix wptr reset in KGQ init

[Tvrtko Ursulin]

On 29/01/2026 16:39, Alex Deucher wrote:
> On Thu, Jan 29, 2026 at 11:27 AM Tvrtko Ursulin <tursulin@ursulin.net> wrote:
>>
>>
>> On 29/01/2026 04:34, Alex Deucher wrote:
>>> wptr is a 64 bit value and we need to update the
>>> full value, not just 32 bits. Align with what we
>>> already do for KCQs.
>>>
>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>> ---
>>>    drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> index e9254ec3b6417..ef7d91a4437ec 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> @@ -6883,7 +6883,7 @@ static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
>>>                        memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
>>>                /* reset the ring */
>>>                ring->wptr = 0;
>>> -             *ring->wptr_cpu_addr = 0;
>>> +             atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
>>
>> For my education could I ask if this just about writing the 64-bit value
>> or the atomic part is also important?
> 
> Just the 64 bit value in this case.

Thank you, it was a bit confusing for me. Even in the context of what 
you explained to Timur that pre-gfx9 wptr is 32-bit, becauase when I 
looked into for example the gfx8 code, I saw it doing a mix of 64- and 
32-bit writes.

I guess the layout of the write back info block thingy is fully 
software/driver defined which is why this is not an issue?

Would it be worth getting rid of the atomics to lessen the confusion and 
attempt to somehow make this area more self-documenting?

Regards,

Tvrtko

Re: [PATCH 1/3] drm/amdgpu/gfx10: fix wptr reset in KGQ init

[Alex Deucher]

On Fri, Jan 30, 2026 at 5:28 AM Tvrtko Ursulin <tursulin@ursulin.net> wrote:
>
>
> On 29/01/2026 16:39, Alex Deucher wrote:
> > On Thu, Jan 29, 2026 at 11:27 AM Tvrtko Ursulin <tursulin@ursulin.net> wrote:
> >>
> >>
> >> On 29/01/2026 04:34, Alex Deucher wrote:
> >>> wptr is a 64 bit value and we need to update the
> >>> full value, not just 32 bits. Align with what we
> >>> already do for KCQs.
> >>>
> >>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> >>> ---
> >>>    drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
> >>>    1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> >>> index e9254ec3b6417..ef7d91a4437ec 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> >>> @@ -6883,7 +6883,7 @@ static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
> >>>                        memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
> >>>                /* reset the ring */
> >>>                ring->wptr = 0;
> >>> -             *ring->wptr_cpu_addr = 0;
> >>> +             atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
> >>
> >> For my education could I ask if this just about writing the 64-bit value
> >> or the atomic part is also important?
> >
> > Just the 64 bit value in this case.
>
> Thank you, it was a bit confusing for me. Even in the context of what
> you explained to Timur that pre-gfx9 wptr is 32-bit, becauase when I
> looked into for example the gfx8 code, I saw it doing a mix of 64- and
> 32-bit writes.
>
> I guess the layout of the write back info block thingy is fully
> software/driver defined which is why this is not an issue?

The buffer is 64 bits because we support a mix of GPUs, some of which
support 64 bit write pointers and some of which support 32 bit write
pointers, even on the same GPU (e.g., different IPs may have different
sizes).

>
> Would it be worth getting rid of the atomics to lessen the confusion and
> attempt to somehow make this area more self-documenting?

Yeah, I suspect the 64 bit updates came back to the older IPs as part
of code unification and cleanups from newer chips.  Each ring has a
ptr_mask in its ring data structure which defines its write pointer
size.

Alex

>
> Regards,
>
> Tvrtko