* [PATCH 0/7] Patch set to support dcn42
@ 2026-02-12 1:09 Roman.Li
2026-02-12 1:09 ` [PATCH 1/7] drm/amd/display: Add dcn42 version identifiers Roman.Li
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Roman.Li @ 2026-02-12 1:09 UTC (permalink / raw)
To: amd-gfx
Cc: Alex Deucher, Harry Wentland, Pratik Vishwakarma,
Aurabindo Pillai, Ivan Lipski, Alex Hung, Roman Li
From: Roman Li <Roman.Li@amd.com>
This series adds initial support for DCN 4.2.
Roman Li (7):
drm/amd/display: Add dcn42 version identifiers
drm/amd/display: Add dcn42 register headers
drm/amd/display: Add dcn42 DC resources
drm/amd/display: Add DMUB support for dcn42
drm/amd/display: Enable dcn42 DMUB
drm/amd/display: Enable dcn42 DC
drm/amd/display: Enable dcn42 in DM
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 41 +-
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 +-
.../display/dc/bios/command_table_helper2.c | 1 +
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 11 +-
.../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 1152 +
.../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h | 79 +
.../amd/display/dc/clk_mgr/dcn42/dcn42_smu.c | 431 +
.../amd/display/dc/clk_mgr/dcn42/dcn42_smu.h | 190 +
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 39 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 7 +
drivers/gpu/drm/amd/display/dc/dc.h | 10 +-
drivers/gpu/drm/amd/display/dc/dc_helper.c | 2 +
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 73 +
drivers/gpu/drm/amd/display/dc/dc_types.h | 6 +-
drivers/gpu/drm/amd/display/dc/dccg/Makefile | 11 +-
.../amd/display/dc/dccg/dcn20/dcn20_dccg.h | 15 +-
.../amd/display/dc/dccg/dcn42/dcn42_dccg.c | 278 +
.../amd/display/dc/dccg/dcn42/dcn42_dccg.h | 263 +
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 60 +-
drivers/gpu/drm/amd/display/dc/dio/Makefile | 11 +-
.../dc/dio/dcn10/dcn10_stream_encoder.h | 10 +-
.../dc/dio/dcn42/dcn42_dio_link_encoder.c | 205 +
.../dc/dio/dcn42/dcn42_dio_link_encoder.h | 140 +
.../dc/dio/dcn42/dcn42_dio_stream_encoder.c | 522 +
.../dc/dio/dcn42/dcn42_dio_stream_encoder.h | 206 +
drivers/gpu/drm/amd/display/dc/dpp/Makefile | 10 +-
.../amd/display/dc/dpp/dcn401/dcn401_dpp.h | 5 +-
.../drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c | 338 +
.../drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h | 469 +
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 13 +-
.../display/dc/gpio/dcn42/hw_factory_dcn42.c | 254 +
.../display/dc/gpio/dcn42/hw_factory_dcn42.h | 31 +
.../dc/gpio/dcn42/hw_translate_dcn42.c | 205 +
.../dc/gpio/dcn42/hw_translate_dcn42.h | 36 +
.../gpu/drm/amd/display/dc/gpio/hw_factory.c | 4 +
.../drm/amd/display/dc/gpio/hw_translate.c | 4 +
drivers/gpu/drm/amd/display/dc/hpo/Makefile | 11 +-
.../hpo/dcn31/dcn31_hpo_dp_stream_encoder.h | 10 +-
.../dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c | 93 +
.../dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.h | 17 +
.../gpu/drm/amd/display/dc/hubbub/Makefile | 10 +-
.../display/dc/hubbub/dcn10/dcn10_hubbub.h | 6 +-
.../display/dc/hubbub/dcn42/dcn42_hubbub.c | 539 +
.../display/dc/hubbub/dcn42/dcn42_hubbub.h | 268 +
drivers/gpu/drm/amd/display/dc/hubp/Makefile | 10 +-
.../amd/display/dc/hubp/dcn20/dcn20_hubp.h | 8 +-
.../amd/display/dc/hubp/dcn42/dcn42_hubp.c | 643 +
.../amd/display/dc/hubp/dcn42/dcn42_hubp.h | 79 +
drivers/gpu/drm/amd/display/dc/hwss/Makefile | 12 +-
.../drm/amd/display/dc/hwss/dce/dce_hwseq.h | 13 +-
.../amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 1476 +
.../amd/display/dc/hwss/dcn42/dcn42_hwseq.h | 53 +
.../amd/display/dc/hwss/dcn42/dcn42_init.c | 167 +
.../amd/display/dc/hwss/dcn42/dcn42_init.h | 11 +
.../drm/amd/display/dc/hwss/hw_sequencer.h | 17 +-
.../display/dc/hwss/hw_sequencer_private.h | 5 +-
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 24 +-
.../amd/display/dc/inc/hw/clk_mgr_internal.h | 42 +-
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 10 +-
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 20 +-
.../amd/display/dc/inc/hw/timing_generator.h | 4 +-
drivers/gpu/drm/amd/display/dc/irq/Makefile | 9 +
.../display/dc/irq/dcn42/irq_service_dcn42.c | 412 +
.../display/dc/irq/dcn42/irq_service_dcn42.h | 15 +
.../gpu/drm/amd/display/dc/mmhubbub/Makefile | 10 +-
.../dc/mmhubbub/dcn42/dcn42_mmhubbub.c | 25 +
.../dc/mmhubbub/dcn42/dcn42_mmhubbub.h | 13 +
drivers/gpu/drm/amd/display/dc/mpc/Makefile | 10 +-
.../amd/display/dc/mpc/dcn401/dcn401_mpc.c | 13 +-
.../amd/display/dc/mpc/dcn401/dcn401_mpc.h | 10 +-
.../drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c | 1121 +
.../drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h | 1006 +
drivers/gpu/drm/amd/display/dc/optc/Makefile | 10 +-
.../amd/display/dc/optc/dcn10/dcn10_optc.h | 20 +-
.../amd/display/dc/optc/dcn42/dcn42_optc.c | 198 +
.../amd/display/dc/optc/dcn42/dcn42_optc.h | 211 +
drivers/gpu/drm/amd/display/dc/pg/Makefile | 10 +-
.../amd/display/dc/pg/dcn42/dcn42_pg_cntl.c | 648 +
.../amd/display/dc/pg/dcn42/dcn42_pg_cntl.h | 175 +
.../gpu/drm/amd/display/dc/resource/Makefile | 18 +
.../dc/resource/dcn42/dcn42_resource.c | 2337 +
.../dc/resource/dcn42/dcn42_resource.h | 588 +
.../dc/resource/dcn42/dcn42_resource_fpu.c | 47 +
.../dc/resource/dcn42/dcn42_resource_fpu.h | 33 +
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 5 +-
drivers/gpu/drm/amd/display/dmub/src/Makefile | 3 +-
.../gpu/drm/amd/display/dmub/src/dmub_dcn42.c | 752 +
.../gpu/drm/amd/display/dmub/src/dmub_dcn42.h | 171 +
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 64 +-
.../gpu/drm/amd/display/include/dal_asic_id.h | 1 +
.../gpu/drm/amd/display/include/dal_types.h | 1 +
.../include/asic_reg/dcn/dcn_4_2_0_offset.h | 17872 ++++
.../include/asic_reg/dcn/dcn_4_2_0_sh_mask.h | 67277 ++++++++++++++++
.../include/asic_reg/dpcs/dpcs_4_0_0_offset.h | 142 +
.../asic_reg/dpcs/dpcs_4_0_0_sh_mask.h | 688 +
95 files changed, 102551 insertions(+), 47 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.h
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.h
create mode 100644 drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c
create mode 100644 drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.h
create mode 100644 drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c
create mode 100644 drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.h
create mode 100644 drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h
create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c
create mode 100644 drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.h
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.h
create mode 100644 drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.c
create mode 100644 drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.h
create mode 100644 drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c
create mode 100644 drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h
create mode 100644 drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
create mode 100644 drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
create mode 100644 drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c
create mode 100644 drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h
create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_sh_mask.h
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/7] drm/amd/display: Add dcn42 version identifiers
2026-02-12 1:09 [PATCH 0/7] Patch set to support dcn42 Roman.Li
@ 2026-02-12 1:09 ` Roman.Li
2026-02-12 1:09 ` [PATCH 4/7] drm/amd/display: Add DMUB support for dcn42 Roman.Li
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Roman.Li @ 2026-02-12 1:09 UTC (permalink / raw)
To: amd-gfx
Cc: Alex Deucher, Harry Wentland, Pratik Vishwakarma,
Aurabindo Pillai, Ivan Lipski, Alex Hung, Roman Li
From: Roman Li <Roman.Li@amd.com>
Add DCN 4.2 asic version identifiers.
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 1 +
drivers/gpu/drm/amd/display/include/dal_types.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 8aea50aa9533..92510af1bd65 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -252,6 +252,7 @@ enum {
#define AMDGPU_FAMILY_GC_11_0_0 145
#define AMDGPU_FAMILY_GC_11_0_1 148
#define AMDGPU_FAMILY_GC_11_5_0 150
+#define AMDGPU_FAMILY_GC_11_5_4 154
#define GC_11_0_0_A0 0x1
#define GC_11_0_2_A0 0x10
#define GC_11_0_3_A0 0x20
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index a021d12acd74..d30eb24cf11e 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -65,6 +65,7 @@ enum dce_version {
DCN_VERSION_3_51,
DCN_VERSION_3_6,
DCN_VERSION_4_01,
+ DCN_VERSION_4_2,
DCN_VERSION_MAX
};
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/7] drm/amd/display: Add DMUB support for dcn42
2026-02-12 1:09 [PATCH 0/7] Patch set to support dcn42 Roman.Li
2026-02-12 1:09 ` [PATCH 1/7] drm/amd/display: Add dcn42 version identifiers Roman.Li
@ 2026-02-12 1:09 ` Roman.Li
2026-02-12 1:09 ` [PATCH 5/7] drm/amd/display: Enable dcn42 DMUB Roman.Li
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Roman.Li @ 2026-02-12 1:09 UTC (permalink / raw)
To: amd-gfx
Cc: Alex Deucher, Harry Wentland, Pratik Vishwakarma,
Aurabindo Pillai, Ivan Lipski, Alex Hung, Roman Li
From: Roman Li <Roman.Li@amd.com>
DMUB support for DCN 4.2
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/display/dmub/src/dmub_dcn42.c | 752 ++++++++++++++++++
.../gpu/drm/amd/display/dmub/src/dmub_dcn42.h | 171 ++++
2 files changed, 923 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
new file mode 100644
index 000000000000..4d274b7034e8
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c
@@ -0,0 +1,752 @@
+// SPDX-License-Identifier: MIT
+//
+// Copyright 2026 Advanced Micro Devices, Inc.
+
+#include "../dmub_srv.h"
+#include "dmub_reg.h"
+#include "dmub_dcn35.h"
+#include "dmub_dcn401.h"
+#include "dmub_dcn42.h"
+
+#include "dcn/dcn_4_2_0_offset.h"
+#include "dcn/dcn_4_2_0_sh_mask.h"
+
+#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
+#define CTX dmub
+#define REGS dmub->regs_dcn42
+#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
+
+void dmub_srv_dcn42_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)
+{
+ struct dmub_srv_dcn42_regs *regs = dmub->regs_dcn42;
+#define REG_STRUCT regs
+
+#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
+ DMUB_DCN42_REGS()
+ DMCUB_INTERNAL_REGS()
+#undef DMUB_SR
+
+#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
+ DMUB_DCN42_FIELDS()
+#undef DMUB_SF
+
+#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
+ DMUB_DCN42_FIELDS()
+#undef DMUB_SF
+#undef REG_STRUCT
+}
+
+void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
+{
+ union dmub_fw_boot_options boot_options = {0};
+ union dmub_fw_boot_options cur_boot_options = {0};
+
+ cur_boot_options = dmub_dcn42_get_fw_boot_option(dmub);
+
+ boot_options.bits.z10_disable = params->disable_z10;
+ boot_options.bits.dpia_supported = params->dpia_supported;
+ boot_options.bits.enable_dpia = cur_boot_options.bits.enable_dpia && !params->disable_dpia;
+ boot_options.bits.usb4_cm_version = params->usb4_cm_version;
+ boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported;
+ boot_options.bits.power_optimization = params->power_optimization;
+ boot_options.bits.disable_clk_ds = params->disallow_dispclk_dppclk_ds;
+ boot_options.bits.disable_clk_gate = params->disable_clock_gate;
+ boot_options.bits.ips_disable = params->disable_ips;
+ boot_options.bits.ips_sequential_ono = params->ips_sequential_ono;
+ boot_options.bits.disable_sldo_opt = params->disable_sldo_opt;
+ boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig;
+ boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc;
+ boot_options.bits.skip_phy_access = params->disallow_phy_access;
+ boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation;
+
+ REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
+
+static void dmub_dcn42_get_fb_base_offset(struct dmub_srv *dmub,
+ uint64_t *fb_base,
+ uint64_t *fb_offset)
+{
+ uint32_t tmp;
+
+ /*
+ if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) {
+ *fb_base = dmub->soc_fb_info.fb_base;
+ *fb_offset = dmub->soc_fb_info.fb_offset;
+ return;
+ }
+ */
+
+ REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
+ *fb_base = (uint64_t)tmp << 24;
+
+ REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
+ *fb_offset = (uint64_t)tmp << 24;
+}
+
+static inline void dmub_dcn42_translate_addr(const union dmub_addr *addr_in,
+ uint64_t fb_base,
+ uint64_t fb_offset,
+ union dmub_addr *addr_out)
+{
+ addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
+}
+
+void dmub_dcn42_reset(struct dmub_srv *dmub)
+{
+ union dmub_gpint_data_register cmd;
+ const uint32_t timeout = 100000;
+ uint32_t in_reset, is_enabled, scratch, i, pwait_mode;
+
+ REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
+ REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled);
+
+ if (in_reset == 0 && is_enabled != 0) {
+ cmd.bits.status = 1;
+ cmd.bits.command_code = DMUB_GPINT__STOP_FW;
+ cmd.bits.param = 0;
+
+ dmub->hw_funcs.set_gpint(dmub, cmd);
+
+ for (i = 0; i < timeout; ++i) {
+ if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
+ break;
+
+ udelay(1);
+ }
+
+ for (i = 0; i < timeout; ++i) {
+ scratch = REG_READ(DMCUB_SCRATCH7);
+ if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
+ break;
+
+ udelay(1);
+ }
+
+ for (i = 0; i < timeout; ++i) {
+ REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode);
+ if (pwait_mode & (1 << 0))
+ break;
+
+ udelay(1);
+ }
+ /* Force reset in case we timed out, DMCUB is likely hung. */
+ }
+
+ if (is_enabled) {
+ REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
+ udelay(1);
+ REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
+ }
+
+ REG_WRITE(DMCUB_INBOX1_RPTR, 0);
+ REG_WRITE(DMCUB_INBOX1_WPTR, 0);
+ REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
+ REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
+ REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
+ REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
+ REG_WRITE(DMCUB_SCRATCH0, 0);
+
+ /* Clear the GPINT command manually so we don't send anything during boot. */
+ cmd.all = 0;
+ dmub->hw_funcs.set_gpint(dmub, cmd);
+}
+
+void dmub_dcn42_reset_release(struct dmub_srv *dmub)
+{
+ REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
+
+ REG_UPDATE_3(DMU_CLK_CNTL,
+ LONO_DISPCLK_GATE_DISABLE, 1,
+ LONO_SOCCLK_GATE_DISABLE, 1,
+ LONO_DMCUBCLK_GATE_DISABLE, 1);
+
+ REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
+ REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
+ REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
+}
+
+void dmub_dcn42_backdoor_load(struct dmub_srv *dmub,
+ const struct dmub_window *cw0,
+ const struct dmub_window *cw1)
+{
+ union dmub_addr offset;
+ uint64_t fb_base, fb_offset;
+
+ dmub_dcn42_get_fb_base_offset(dmub, &fb_base, &fb_offset);
+
+ dmub_dcn42_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
+
+ REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
+ REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
+ REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
+ REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
+ DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
+ DMCUB_REGION3_CW0_ENABLE, 1);
+
+ dmub_dcn42_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
+
+ REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
+ REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
+ REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
+ REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
+ DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
+ DMCUB_REGION3_CW1_ENABLE, 1);
+
+ /* TODO: Do we need to set DMCUB_MEM_UNIT_ID? */
+ REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0);
+}
+
+void dmub_dcn42_backdoor_load_zfb_mode(struct dmub_srv *dmub,
+ const struct dmub_window *cw0,
+ const struct dmub_window *cw1)
+{
+ union dmub_addr offset;
+
+ REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
+ offset = cw0->offset;
+ REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
+ REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
+ REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
+ REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
+ DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
+ DMCUB_REGION3_CW0_ENABLE, 1);
+ offset = cw1->offset;
+ REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
+ REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
+ REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
+ REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
+ DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
+ DMCUB_REGION3_CW1_ENABLE, 1);
+ REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
+ 0x20);
+}
+void dmub_dcn42_setup_windows(struct dmub_srv *dmub,
+ const struct dmub_window *cw2,
+ const struct dmub_window *cw3,
+ const struct dmub_window *cw4,
+ const struct dmub_window *cw5,
+ const struct dmub_window *cw6,
+ const struct dmub_window *region6)
+{
+ union dmub_addr offset;
+
+ offset = cw3->offset;
+
+ REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
+ REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
+ REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
+ REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
+ DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
+ DMCUB_REGION3_CW3_ENABLE, 1);
+
+ offset = cw4->offset;
+
+ REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
+ REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
+ REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
+ REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
+ DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
+ DMCUB_REGION3_CW4_ENABLE, 1);
+
+ offset = cw5->offset;
+
+ REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
+ REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
+ REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
+ REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
+ DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
+ DMCUB_REGION3_CW5_ENABLE, 1);
+
+ REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
+ REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
+ REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
+ DMCUB_REGION5_TOP_ADDRESS,
+ cw5->region.top - cw5->region.base - 1,
+ DMCUB_REGION5_ENABLE, 1);
+
+ offset = cw6->offset;
+
+ REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
+ REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
+ REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
+ REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
+ DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
+ DMCUB_REGION3_CW6_ENABLE, 1);
+
+ offset = region6->offset;
+
+ REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part);
+ REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part);
+ REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0,
+ DMCUB_REGION6_TOP_ADDRESS,
+ region6->region.top - region6->region.base - 1,
+ DMCUB_REGION6_ENABLE, 1);
+}
+
+uint32_t dmub_dcn42_get_inbox1_wptr(struct dmub_srv *dmub)
+{
+ return REG_READ(DMCUB_INBOX1_WPTR);
+}
+
+uint32_t dmub_dcn42_get_inbox1_rptr(struct dmub_srv *dmub)
+{
+ return REG_READ(DMCUB_INBOX1_RPTR);
+}
+
+void dmub_dcn42_setup_out_mailbox(struct dmub_srv *dmub,
+ const struct dmub_region *outbox1)
+{
+ REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
+ REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
+}
+
+uint32_t dmub_dcn42_get_outbox1_wptr(struct dmub_srv *dmub)
+{
+ /**
+ * outbox1 wptr register is accessed without locks (dal & dc)
+ * and to be called only by dmub_srv_stat_get_notification()
+ */
+ return REG_READ(DMCUB_OUTBOX1_WPTR);
+}
+
+void dmub_dcn42_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
+{
+ /**
+ * outbox1 rptr register is accessed without locks (dal & dc)
+ * and to be called only by dmub_srv_stat_get_notification()
+ */
+ REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
+}
+
+bool dmub_dcn42_is_supported(struct dmub_srv *dmub)
+{
+ uint32_t supported = 0;
+
+ REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
+
+ return supported;
+}
+
+union dmub_fw_boot_options dmub_dcn42_get_fw_boot_option(struct dmub_srv *dmub)
+{
+ union dmub_fw_boot_options option;
+
+ option.all = REG_READ(DMCUB_SCRATCH14);
+ return option;
+}
+
+void dmub_dcn42_setup_outbox0(struct dmub_srv *dmub,
+ const struct dmub_region *outbox0)
+{
+ REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
+
+ REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
+}
+
+bool dmub_dcn42_should_detect(struct dmub_srv *dmub)
+{
+ uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0);
+ bool should_detect = (fw_boot_status & DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED) != 0;
+ return should_detect;
+}
+
+void dmub_dcn42_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)
+{
+ REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
+}
+
+uint32_t dmub_dcn42_read_inbox0_ack_register(struct dmub_srv *dmub)
+{
+ return REG_READ(DMCUB_SCRATCH17);
+}
+
+bool dmub_dcn42_is_hw_powered_up(struct dmub_srv *dmub)
+{
+ union dmub_fw_boot_status status;
+ uint32_t is_enable;
+
+ REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable);
+ if (is_enable == 0)
+ return false;
+
+ status.all = REG_READ(DMCUB_SCRATCH0);
+
+ return (status.bits.dal_fw && status.bits.hw_power_init_done && status.bits.mailbox_rdy) ||
+ (!status.bits.dal_fw && status.bits.mailbox_rdy);
+}
+
+void dmub_dcn42_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
+{
+ REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
+}
+
+bool dmub_dcn42_is_hw_init(struct dmub_srv *dmub)
+{
+ union dmub_fw_boot_status status;
+ uint32_t is_hw_init;
+
+ status.all = REG_READ(DMCUB_SCRATCH0);
+ REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
+
+ return is_hw_init != 0 && status.bits.dal_fw;
+}
+
+union dmub_fw_boot_status dmub_dcn42_get_fw_boot_status(struct dmub_srv *dmub)
+{
+ union dmub_fw_boot_status status;
+
+ status.all = REG_READ(DMCUB_SCRATCH0);
+ return status;
+}
+
+void dmub_dcn42_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
+{
+ union dmub_fw_boot_options boot_options;
+ boot_options.all = REG_READ(DMCUB_SCRATCH14);
+ boot_options.bits.skip_phy_init_panel_sequence = skip;
+ REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
+
+void dmub_dcn42_configure_dmub_in_system_memory(struct dmub_srv *dmub)
+{
+ /* DMCUB_REGION3_TMR_AXI_SPACE values:
+ * 0b011 (0x3) - FB physical address
+ * 0b100 (0x4) - GPU virtual address
+ *
+ * Default value is 0x3 (FB Physical address for TMR). When programming
+ * DMUB to be in system memory, change to 0x4. The system memory allocated
+ * is accessible by both GPU and CPU, so we use GPU virtual address.
+ */
+ REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
+}
+
+void dmub_dcn42_clear_inbox0_ack_register(struct dmub_srv *dmub)
+{
+ REG_WRITE(DMCUB_SCRATCH17, 0);
+}
+
+void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,
+ union dmub_rb_cmd *cmd)
+{
+ uint32_t *dwords = (uint32_t *)cmd;
+ int32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes;
+ uint32_t msg_index;
+ static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch");
+
+ /* read remaining data based on payload size */
+ for (msg_index = 0; msg_index < 15; msg_index++) {
+ if (payload_size_bytes <= msg_index * 4) {
+ break;
+ }
+
+ switch (msg_index) {
+ case 0:
+ REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[msg_index + 1]);
+ break;
+ case 1:
+ REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[msg_index + 1]);
+ break;
+ case 2:
+ REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[msg_index + 1]);
+ break;
+ case 3:
+ REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[msg_index + 1]);
+ break;
+ case 4:
+ REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[msg_index + 1]);
+ break;
+ case 5:
+ REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[msg_index + 1]);
+ break;
+ case 6:
+ REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[msg_index + 1]);
+ break;
+ case 7:
+ REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[msg_index + 1]);
+ break;
+ case 8:
+ REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[msg_index + 1]);
+ break;
+ case 9:
+ REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[msg_index + 1]);
+ break;
+ case 10:
+ REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[msg_index + 1]);
+ break;
+ case 11:
+ REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[msg_index + 1]);
+ break;
+ case 12:
+ REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[msg_index + 1]);
+ break;
+ case 13:
+ REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[msg_index + 1]);
+ break;
+ case 14:
+ REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[msg_index + 1]);
+ break;
+ }
+ }
+
+ /* writing to INBOX RDY register will trigger DMUB REG INBOX0 RDY
+ * interrupt.
+ */
+ REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[0]);
+}
+
+uint32_t dmub_dcn42_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub)
+{
+ uint32_t status;
+
+ REG_GET(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT, &status);
+ return status;
+}
+
+void dmub_dcn42_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,
+ union dmub_rb_cmd *cmd)
+{
+ uint32_t *dwords = (uint32_t *)cmd;
+
+ static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch");
+
+ dwords[0] = REG_READ(DMCUB_REG_INBOX0_RSP);
+ dwords[1] = REG_READ(DMCUB_REG_INBOX0_MSG0);
+ dwords[2] = REG_READ(DMCUB_REG_INBOX0_MSG1);
+ dwords[3] = REG_READ(DMCUB_REG_INBOX0_MSG2);
+ dwords[4] = REG_READ(DMCUB_REG_INBOX0_MSG3);
+ dwords[5] = REG_READ(DMCUB_REG_INBOX0_MSG4);
+ dwords[6] = REG_READ(DMCUB_REG_INBOX0_MSG5);
+ dwords[7] = REG_READ(DMCUB_REG_INBOX0_MSG6);
+ dwords[8] = REG_READ(DMCUB_REG_INBOX0_MSG7);
+ dwords[9] = REG_READ(DMCUB_REG_INBOX0_MSG8);
+ dwords[10] = REG_READ(DMCUB_REG_INBOX0_MSG9);
+ dwords[11] = REG_READ(DMCUB_REG_INBOX0_MSG10);
+ dwords[12] = REG_READ(DMCUB_REG_INBOX0_MSG11);
+ dwords[13] = REG_READ(DMCUB_REG_INBOX0_MSG12);
+ dwords[14] = REG_READ(DMCUB_REG_INBOX0_MSG13);
+ dwords[15] = REG_READ(DMCUB_REG_INBOX0_MSG14);
+}
+
+void dmub_dcn42_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)
+{
+ REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 1);
+}
+
+void dmub_dcn42_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)
+{
+ REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 0);
+}
+
+void dmub_dcn42_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable)
+{
+ REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN, enable ? 1:0);
+}
+
+void dmub_dcn42_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub)
+{
+ REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 1);
+ REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 0);
+}
+
+void dmub_dcn42_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg)
+{
+ *msg = REG_READ(DMCUB_REG_OUTBOX0_MSG0);
+}
+
+
+void dmub_dcn42_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable)
+{
+ REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN, enable ? 1:0);
+}
+
+uint32_t dmub_dcn42_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub)
+{
+ uint32_t status;
+
+ REG_GET(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT, &status);
+ return status;
+}
+
+void dmub_dcn42_setup_mailbox(struct dmub_srv *dmub,
+ const struct dmub_region *inbox1)
+{
+ REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
+ REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
+}
+
+void dmub_dcn42_set_gpint(struct dmub_srv *dmub,
+ union dmub_gpint_data_register reg)
+{
+ REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
+}
+
+bool dmub_dcn42_is_gpint_acked(struct dmub_srv *dmub,
+ union dmub_gpint_data_register reg)
+{
+ union dmub_gpint_data_register test;
+
+ reg.bits.status = 0;
+ test.all = REG_READ(DMCUB_GPINT_DATAIN1);
+
+ return test.all == reg.all;
+}
+
+uint32_t dmub_dcn42_get_gpint_response(struct dmub_srv *dmub)
+{
+ return REG_READ(DMCUB_SCRATCH7);
+}
+
+uint32_t dmub_dcn42_get_gpint_dataout(struct dmub_srv *dmub)
+{
+ uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
+
+ REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
+
+ REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
+ REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
+ REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
+
+ REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
+
+ return dataout;
+}
+
+uint32_t dmub_dcn42_get_outbox0_wptr(struct dmub_srv *dmub)
+{
+ return REG_READ(DMCUB_OUTBOX0_WPTR);
+}
+
+void dmub_dcn42_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
+{
+ REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
+}
+
+uint32_t dmub_dcn42_get_current_time(struct dmub_srv *dmub)
+{
+ return REG_READ(DMCUB_TIMER_CURRENT);
+}
+
+void dmub_dcn42_get_diagnostic_data(struct dmub_srv *dmub)
+{
+ uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset, is_pwait;
+ uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
+ struct dmub_timeout_info timeout = {0};
+
+ if (!dmub)
+ return;
+
+ /* timeout data filled externally, cache before resetting memory */
+ timeout = dmub->debug.timeout_info;
+ memset(&dmub->debug, 0, sizeof(dmub->debug));
+ dmub->debug.timeout_info = timeout;
+
+ dmub->debug.dmcub_version = dmub->fw_version;
+
+ dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);
+ dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);
+ dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);
+ dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);
+ dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);
+ dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);
+ dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);
+ dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);
+ dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);
+ dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);
+ dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);
+ dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);
+ dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);
+ dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);
+ dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);
+ dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);
+ dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);
+
+ dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
+ dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
+ dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
+
+ dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
+ dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
+ dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
+
+ dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
+ dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
+ dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
+
+ dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);
+ dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);
+ dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);
+
+ REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
+ dmub->debug.is_dmcub_enabled = is_dmub_enabled;
+
+ REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait);
+ dmub->debug.is_pwait = is_pwait;
+
+ REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
+ dmub->debug.is_dmcub_soft_reset = is_soft_reset;
+
+ REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
+ dmub->debug.is_dmcub_secure_reset = is_sec_reset;
+
+ REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
+ dmub->debug.is_traceport_en = is_traceport_enabled;
+
+ REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
+ dmub->debug.is_cw0_enabled = is_cw0_enabled;
+
+ REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
+ dmub->debug.is_cw6_enabled = is_cw6_enabled;
+
+ dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
+}
+
+bool dmub_dcn42_get_preos_fw_info(struct dmub_srv *dmub)
+{
+ uint64_t region3_cw5_offset;
+ uint32_t top_addr, top_addr_enable, offset_low;
+ uint32_t offset_high, base_addr, fw_version;
+ bool is_vbios_fw = false;
+
+ memset(&dmub->preos_info, 0, sizeof(dmub->preos_info));
+
+ fw_version = REG_READ(DMCUB_SCRATCH1);
+ is_vbios_fw = ((fw_version >> 6) & 0x01) ? true : false;
+ if (!is_vbios_fw)
+ return false;
+
+ dmub->preos_info.boot_status = REG_READ(DMCUB_SCRATCH0);
+ dmub->preos_info.fw_version = REG_READ(DMCUB_SCRATCH1);
+ dmub->preos_info.boot_options = REG_READ(DMCUB_SCRATCH14);
+ REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS,
+ DMCUB_REGION3_CW5_ENABLE, &top_addr_enable);
+ if (top_addr_enable) {
+ dmub_dcn42_get_fb_base_offset(dmub,
+ &dmub->preos_info.fb_base, &dmub->preos_info.fb_offset);
+ offset_low = REG_READ(DMCUB_REGION3_CW5_OFFSET);
+ offset_high = REG_READ(DMCUB_REGION3_CW5_OFFSET_HIGH);
+ region3_cw5_offset = ((uint64_t)offset_high << 32) | offset_low;
+ dmub->preos_info.trace_buffer_phy_addr = region3_cw5_offset
+ - dmub->preos_info.fb_base + dmub->preos_info.fb_offset;
+
+ REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS,
+ DMCUB_REGION3_CW5_TOP_ADDRESS, &top_addr);
+ base_addr = REG_READ(DMCUB_REGION3_CW5_BASE_ADDRESS) & 0x1FFFFFFF;
+ dmub->preos_info.trace_buffer_size =
+ (top_addr > base_addr) ? (top_addr - base_addr + 1) : 0;
+ }
+
+ return true;
+}
+
+void dmub_dcn42_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp)
+{
+ REG_WRITE(DMCUB_REG_OUTBOX0_RSP, *rsp);
+}
+
+uint32_t dmub_dcn42_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub)
+{
+ uint32_t status;
+
+ REG_GET(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT, &status);
+ return status;
+}
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h
new file mode 100644
index 000000000000..a49d88ab0455
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _DMUB_DCN42_H_
+#define _DMUB_DCN42_H_
+
+#include "dmub_dcn35.h"
+#include "dmub_dcn401.h"
+
+
+struct dmub_srv;
+
+/* DCN42 register definitions. */
+
+#define DMUB_DCN42_REGS() \
+ DMUB_DCN35_REGS() \
+ DMUB_SR(DMCUB_INTERRUPT_STATUS) \
+ DMUB_SR(DMCUB_REG_INBOX0_RDY) \
+ DMUB_SR(DMCUB_REG_INBOX0_MSG0) \
+ DMUB_SR(DMCUB_REG_INBOX0_MSG1) \
+ DMUB_SR(DMCUB_REG_INBOX0_MSG2) \
+ DMUB_SR(DMCUB_REG_INBOX0_MSG3) \
+ DMUB_SR(DMCUB_REG_INBOX0_MSG4) \
+ DMUB_SR(DMCUB_REG_INBOX0_MSG5) \
+ DMUB_SR(DMCUB_REG_INBOX0_MSG6) \
+ DMUB_SR(DMCUB_REG_INBOX0_MSG7) \
+ DMUB_SR(DMCUB_REG_INBOX0_MSG8) \
+ DMUB_SR(DMCUB_REG_INBOX0_MSG9) \
+ DMUB_SR(DMCUB_REG_INBOX0_MSG10) \
+ DMUB_SR(DMCUB_REG_INBOX0_MSG11) \
+ DMUB_SR(DMCUB_REG_INBOX0_MSG12) \
+ DMUB_SR(DMCUB_REG_INBOX0_MSG13) \
+ DMUB_SR(DMCUB_REG_INBOX0_MSG14) \
+ DMUB_SR(DMCUB_REG_INBOX0_RSP) \
+ DMUB_SR(DMCUB_REG_OUTBOX0_RDY) \
+ DMUB_SR(DMCUB_REG_OUTBOX0_MSG0) \
+ DMUB_SR(DMCUB_REG_OUTBOX0_RSP) \
+ DMUB_SR(HOST_INTERRUPT_CSR)
+
+#define DMUB_DCN42_FIELDS() \
+ DMUB_DCN35_FIELDS() \
+ DMUB_SF(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT) \
+ DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK) \
+ DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT) \
+ DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN) \
+ DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK) \
+ DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT) \
+ DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN)
+
+struct dmub_srv_dcn42_reg_offset {
+#define DMUB_SR(reg) uint32_t reg;
+ DMUB_DCN42_REGS()
+ DMCUB_INTERNAL_REGS()
+#undef DMUB_SR
+};
+
+struct dmub_srv_dcn42_reg_shift {
+#define DMUB_SF(reg, field) uint8_t reg##__##field;
+ DMUB_DCN42_FIELDS()
+#undef DMUB_SF
+};
+
+struct dmub_srv_dcn42_reg_mask {
+#define DMUB_SF(reg, field) uint32_t reg##__##field;
+ DMUB_DCN42_FIELDS()
+#undef DMUB_SF
+};
+
+struct dmub_srv_dcn42_regs {
+ struct dmub_srv_dcn42_reg_offset offset;
+ struct dmub_srv_dcn42_reg_mask mask;
+ struct dmub_srv_dcn42_reg_shift shift;
+};
+
+/* Function declarations */
+
+/* Initialization and configuration */
+void dmub_srv_dcn42_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);
+void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);
+void dmub_dcn42_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
+void dmub_dcn42_configure_dmub_in_system_memory(struct dmub_srv *dmub);
+
+/* Reset and control */
+void dmub_dcn42_reset(struct dmub_srv *dmub);
+void dmub_dcn42_reset_release(struct dmub_srv *dmub);
+
+/* Firmware loading */
+void dmub_dcn42_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1);
+void dmub_dcn42_backdoor_load_zfb_mode(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1);
+void dmub_dcn42_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6);
+
+/* Mailbox operations - Inbox1 */
+void dmub_dcn42_setup_mailbox(struct dmub_srv *dmub, const struct dmub_region *inbox1);
+uint32_t dmub_dcn42_get_inbox1_wptr(struct dmub_srv *dmub);
+uint32_t dmub_dcn42_get_inbox1_rptr(struct dmub_srv *dmub);
+void dmub_dcn42_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
+
+/* Mailbox operations - Outbox1 */
+void dmub_dcn42_setup_out_mailbox(struct dmub_srv *dmub, const struct dmub_region *outbox1);
+uint32_t dmub_dcn42_get_outbox1_wptr(struct dmub_srv *dmub);
+void dmub_dcn42_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
+
+/* Mailbox operations - Outbox0 */
+void dmub_dcn42_setup_outbox0(struct dmub_srv *dmub, const struct dmub_region *outbox0);
+uint32_t dmub_dcn42_get_outbox0_wptr(struct dmub_srv *dmub);
+void dmub_dcn42_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
+
+/* Mailbox operations - Inbox0 */
+void dmub_dcn42_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);
+void dmub_dcn42_clear_inbox0_ack_register(struct dmub_srv *dmub);
+uint32_t dmub_dcn42_read_inbox0_ack_register(struct dmub_srv *dmub);
+
+/* REG Inbox0/Outbox0 operations */
+void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, union dmub_rb_cmd *cmd);
+uint32_t dmub_dcn42_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub);
+void dmub_dcn42_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub, union dmub_rb_cmd *cmd);
+void dmub_dcn42_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);
+void dmub_dcn42_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);
+void dmub_dcn42_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable);
+
+void dmub_dcn42_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub);
+void dmub_dcn42_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg);
+void dmub_dcn42_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp);
+uint32_t dmub_dcn42_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub);
+void dmub_dcn42_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable);
+uint32_t dmub_dcn42_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub);
+
+/* GPINT operations */
+void dmub_dcn42_set_gpint(struct dmub_srv *dmub, union dmub_gpint_data_register reg);
+bool dmub_dcn42_is_gpint_acked(struct dmub_srv *dmub, union dmub_gpint_data_register reg);
+uint32_t dmub_dcn42_get_gpint_response(struct dmub_srv *dmub);
+uint32_t dmub_dcn42_get_gpint_dataout(struct dmub_srv *dmub);
+
+/* Status and detection */
+bool dmub_dcn42_is_hw_init(struct dmub_srv *dmub);
+bool dmub_dcn42_is_supported(struct dmub_srv *dmub);
+bool dmub_dcn42_is_hw_powered_up(struct dmub_srv *dmub);
+bool dmub_dcn42_should_detect(struct dmub_srv *dmub);
+
+
+/* Firmware boot status and options */
+union dmub_fw_boot_status dmub_dcn42_get_fw_boot_status(struct dmub_srv *dmub);
+union dmub_fw_boot_options dmub_dcn42_get_fw_boot_option(struct dmub_srv *dmub);
+
+/* Timing and diagnostics */
+uint32_t dmub_dcn42_get_current_time(struct dmub_srv *dmub);
+void dmub_dcn42_get_diagnostic_data(struct dmub_srv *dmub);
+bool dmub_dcn42_get_preos_fw_info(struct dmub_srv *dmub);
+
+#endif /* _DMUB_DCN42_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 5/7] drm/amd/display: Enable dcn42 DMUB
2026-02-12 1:09 [PATCH 0/7] Patch set to support dcn42 Roman.Li
2026-02-12 1:09 ` [PATCH 1/7] drm/amd/display: Add dcn42 version identifiers Roman.Li
2026-02-12 1:09 ` [PATCH 4/7] drm/amd/display: Add DMUB support for dcn42 Roman.Li
@ 2026-02-12 1:09 ` Roman.Li
2026-02-12 1:09 ` [PATCH 6/7] drm/amd/display: Enable dcn42 DC Roman.Li
2026-02-12 1:09 ` [PATCH 7/7] drm/amd/display: Enable dcn42 in DM Roman.Li
4 siblings, 0 replies; 6+ messages in thread
From: Roman.Li @ 2026-02-12 1:09 UTC (permalink / raw)
To: amd-gfx
Cc: Alex Deucher, Harry Wentland, Pratik Vishwakarma,
Aurabindo Pillai, Ivan Lipski, Alex Hung, Roman Li
From: Roman Li <Roman.Li@amd.com>
Enable DMUB support for DCN 4.2
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 5 +-
drivers/gpu/drm/amd/display/dmub/src/Makefile | 3 +-
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 64 ++++++++++++++++++-
3 files changed, 68 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 3b6bba017040..c18ff8f00bb8 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -1,5 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
- * Copyright 2019 Advanced Micro Devices, Inc.
+ * Copyright 2019-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -119,6 +120,7 @@ enum dmub_asic {
DMUB_ASIC_DCN351,
DMUB_ASIC_DCN36,
DMUB_ASIC_DCN401,
+ DMUB_ASIC_DCN42,
DMUB_ASIC_MAX,
};
@@ -602,6 +604,7 @@ struct dmub_srv {
struct dmub_srv_dcn32_regs *regs_dcn32;
struct dmub_srv_dcn35_regs *regs_dcn35;
const struct dmub_srv_dcn401_regs *regs_dcn401;
+ struct dmub_srv_dcn42_regs *regs_dcn42;
struct dmub_srv_base_funcs funcs;
struct dmub_srv_hw_funcs hw_funcs;
struct dmub_srv_inbox inbox1;
diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile
index 468b768c11ae..ac7b17d8fb0f 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/Makefile
+++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright 2019 Advanced Micro Devices, Inc.
+# Copyright 2019-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -28,6 +28,7 @@ DMUB += dmub_dcn35.o
DMUB += dmub_dcn351.o
DMUB += dmub_dcn36.o
DMUB += dmub_dcn401.o
+DMUB += dmub_dcn42.o
AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 83cf4888fb54..3bba256a288d 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -1,5 +1,6 @@
+// SPDX-License-Identifier: MIT
/*
- * Copyright 2019 Advanced Micro Devices, Inc.
+ * Copyright 2019-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -22,7 +23,6 @@
* Authors: AMD
*
*/
-
#include "../dmub_srv.h"
#include "dmub_dcn20.h"
#include "dmub_dcn21.h"
@@ -40,6 +40,7 @@
#include "dmub_dcn351.h"
#include "dmub_dcn36.h"
#include "dmub_dcn401.h"
+#include "dmub_dcn42.h"
#include "os_types.h"
/*
* Note: the DMUB service is standalone. No additional headers should be
@@ -87,6 +88,7 @@
static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs;
static struct dmub_srv_dcn35_regs dmub_srv_dcn35_regs;
+struct dmub_srv_dcn42_regs dmub_srv_dcn42_regs;
static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
{
@@ -410,6 +412,64 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up;
funcs->should_detect = dmub_dcn35_should_detect;
break;
+ case DMUB_ASIC_DCN42:
+ dmub->regs_dcn42 = &dmub_srv_dcn42_regs;
+ funcs->configure_dmub_in_system_memory = dmub_dcn42_configure_dmub_in_system_memory;
+ funcs->send_inbox0_cmd = dmub_dcn42_send_inbox0_cmd;
+ funcs->clear_inbox0_ack_register = dmub_dcn42_clear_inbox0_ack_register;
+ funcs->read_inbox0_ack_register = dmub_dcn42_read_inbox0_ack_register;
+ funcs->reset = dmub_dcn42_reset;
+ funcs->reset_release = dmub_dcn42_reset_release;
+ funcs->backdoor_load = dmub_dcn42_backdoor_load;
+ funcs->backdoor_load_zfb_mode = dmub_dcn42_backdoor_load_zfb_mode;
+ funcs->setup_windows = dmub_dcn42_setup_windows;
+ funcs->setup_mailbox = dmub_dcn42_setup_mailbox;
+ funcs->get_inbox1_wptr = dmub_dcn42_get_inbox1_wptr;
+ funcs->get_inbox1_rptr = dmub_dcn42_get_inbox1_rptr;
+ funcs->set_inbox1_wptr = dmub_dcn42_set_inbox1_wptr;
+ funcs->setup_out_mailbox = dmub_dcn42_setup_out_mailbox;
+ funcs->get_outbox1_wptr = dmub_dcn42_get_outbox1_wptr;
+ funcs->set_outbox1_rptr = dmub_dcn42_set_outbox1_rptr;
+ funcs->is_supported = dmub_dcn42_is_supported;
+ funcs->is_hw_init = dmub_dcn42_is_hw_init;
+ funcs->set_gpint = dmub_dcn42_set_gpint;
+ funcs->is_gpint_acked = dmub_dcn42_is_gpint_acked;
+ funcs->get_gpint_response = dmub_dcn42_get_gpint_response;
+ funcs->get_gpint_dataout = dmub_dcn42_get_gpint_dataout;
+ funcs->get_fw_status = dmub_dcn42_get_fw_boot_status;
+ funcs->get_fw_boot_option = dmub_dcn42_get_fw_boot_option;
+ funcs->enable_dmub_boot_options = dmub_dcn42_enable_dmub_boot_options;
+ funcs->skip_dmub_panel_power_sequence = dmub_dcn42_skip_dmub_panel_power_sequence;
+ /*outbox0 call stacks*/
+ funcs->setup_outbox0 = dmub_dcn42_setup_outbox0;
+ funcs->get_outbox0_wptr = dmub_dcn42_get_outbox0_wptr;
+ funcs->set_outbox0_rptr = dmub_dcn42_set_outbox0_rptr;
+
+ funcs->get_current_time = dmub_dcn42_get_current_time;
+ funcs->get_diagnostic_data = dmub_dcn42_get_diagnostic_data;
+ funcs->get_preos_fw_info = dmub_dcn42_get_preos_fw_info;
+
+ /*carried from dcn401*/
+ funcs->send_reg_inbox0_cmd_msg = dmub_dcn42_send_reg_inbox0_cmd_msg;
+ funcs->read_reg_inbox0_rsp_int_status = dmub_dcn42_read_reg_inbox0_rsp_int_status;
+ funcs->read_reg_inbox0_cmd_rsp = dmub_dcn42_read_reg_inbox0_cmd_rsp;
+ funcs->write_reg_inbox0_rsp_int_ack = dmub_dcn42_write_reg_inbox0_rsp_int_ack;
+ funcs->clear_reg_inbox0_rsp_int_ack = dmub_dcn42_clear_reg_inbox0_rsp_int_ack;
+ funcs->enable_reg_inbox0_rsp_int = dmub_dcn42_enable_reg_inbox0_rsp_int;
+ default_inbox_type = DMUB_CMD_INTERFACE_FB; /*still default to FB for now*/
+
+ funcs->write_reg_outbox0_rdy_int_ack = dmub_dcn42_write_reg_outbox0_rdy_int_ack;
+ funcs->read_reg_outbox0_msg = dmub_dcn42_read_reg_outbox0_msg;
+ funcs->write_reg_outbox0_rsp = dmub_dcn42_write_reg_outbox0_rsp;
+ funcs->read_reg_outbox0_rdy_int_status = dmub_dcn42_read_reg_outbox0_rdy_int_status;
+ funcs->read_reg_outbox0_rsp_int_status = dmub_dcn42_read_reg_outbox0_rsp_int_status;
+ funcs->enable_reg_inbox0_rsp_int = dmub_dcn42_enable_reg_inbox0_rsp_int;
+ funcs->enable_reg_outbox0_rdy_int = dmub_dcn42_enable_reg_outbox0_rdy_int;
+ funcs->init_reg_offsets = dmub_srv_dcn42_regs_init;
+
+ funcs->is_hw_powered_up = dmub_dcn42_is_hw_powered_up;
+ funcs->should_detect = dmub_dcn42_should_detect;
+ break;
case DMUB_ASIC_DCN401:
dmub->regs_dcn401 = &dmub_srv_dcn401_regs;
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 6/7] drm/amd/display: Enable dcn42 DC
2026-02-12 1:09 [PATCH 0/7] Patch set to support dcn42 Roman.Li
` (2 preceding siblings ...)
2026-02-12 1:09 ` [PATCH 5/7] drm/amd/display: Enable dcn42 DMUB Roman.Li
@ 2026-02-12 1:09 ` Roman.Li
2026-02-12 1:09 ` [PATCH 7/7] drm/amd/display: Enable dcn42 in DM Roman.Li
4 siblings, 0 replies; 6+ messages in thread
From: Roman.Li @ 2026-02-12 1:09 UTC (permalink / raw)
To: amd-gfx
Cc: Alex Deucher, Harry Wentland, Pratik Vishwakarma,
Aurabindo Pillai, Ivan Lipski, Alex Hung, Roman Li
From: Roman Li <Roman.Li@amd.com>
Add support for DCN 4.2 in Display Core
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../display/dc/bios/command_table_helper2.c | 1 +
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 11 ++-
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 39 +++++++++-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 7 ++
drivers/gpu/drm/amd/display/dc/dc.h | 10 ++-
drivers/gpu/drm/amd/display/dc/dc_helper.c | 2 +
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 73 +++++++++++++++++++
drivers/gpu/drm/amd/display/dc/dc_types.h | 6 +-
drivers/gpu/drm/amd/display/dc/dccg/Makefile | 11 ++-
.../amd/display/dc/dccg/dcn20/dcn20_dccg.h | 15 +++-
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 60 ++++++++++++++-
drivers/gpu/drm/amd/display/dc/dio/Makefile | 11 ++-
.../dc/dio/dcn10/dcn10_stream_encoder.h | 10 ++-
drivers/gpu/drm/amd/display/dc/dpp/Makefile | 10 ++-
.../amd/display/dc/dpp/dcn401/dcn401_dpp.h | 5 +-
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 13 +++-
.../gpu/drm/amd/display/dc/gpio/hw_factory.c | 4 +
.../drm/amd/display/dc/gpio/hw_translate.c | 4 +
drivers/gpu/drm/amd/display/dc/hpo/Makefile | 11 ++-
.../hpo/dcn31/dcn31_hpo_dp_stream_encoder.h | 10 ++-
.../gpu/drm/amd/display/dc/hubbub/Makefile | 10 ++-
.../display/dc/hubbub/dcn10/dcn10_hubbub.h | 6 +-
drivers/gpu/drm/amd/display/dc/hubp/Makefile | 10 ++-
.../amd/display/dc/hubp/dcn20/dcn20_hubp.h | 8 +-
drivers/gpu/drm/amd/display/dc/hwss/Makefile | 12 ++-
.../drm/amd/display/dc/hwss/dce/dce_hwseq.h | 13 +++-
.../drm/amd/display/dc/hwss/hw_sequencer.h | 17 ++++-
.../display/dc/hwss/hw_sequencer_private.h | 5 +-
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 24 +++++-
.../amd/display/dc/inc/hw/clk_mgr_internal.h | 42 ++++++++++-
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 10 ++-
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 20 ++++-
.../amd/display/dc/inc/hw/timing_generator.h | 4 +-
drivers/gpu/drm/amd/display/dc/irq/Makefile | 9 +++
.../gpu/drm/amd/display/dc/mmhubbub/Makefile | 10 ++-
drivers/gpu/drm/amd/display/dc/mpc/Makefile | 10 ++-
.../amd/display/dc/mpc/dcn401/dcn401_mpc.c | 13 +++-
.../amd/display/dc/mpc/dcn401/dcn401_mpc.h | 10 ++-
drivers/gpu/drm/amd/display/dc/optc/Makefile | 10 ++-
.../amd/display/dc/optc/dcn10/dcn10_optc.h | 20 ++++-
drivers/gpu/drm/amd/display/dc/pg/Makefile | 10 ++-
.../gpu/drm/amd/display/dc/resource/Makefile | 18 +++++
42 files changed, 568 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index 268e2414b34f..a93a8860535a 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -84,6 +84,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
case DCN_VERSION_3_51:
case DCN_VERSION_3_6:
case DCN_VERSION_4_01:
+ case DCN_VERSION_4_2:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index 60021671b386..586a35971350 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright 2017 Advanced Micro Devices, Inc.
+# Copyright 2017-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -188,4 +188,13 @@ CLK_MGR_DCN401 = dcn401_clk_mgr.o dcn401_clk_mgr_smu_msg.o
AMD_DAL_CLK_MGR_DCN401 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn401/,$(CLK_MGR_DCN401))
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN401)
+
+###############################################################################
+# DCN42
+###############################################################################
+CLK_MGR_DCN42 = dcn42_smu.o dcn42_clk_mgr.o
+
+AMD_DAL_CLK_MGR_DCN42 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn42/,$(CLK_MGR_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN42)
endif
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index a13d9d7dd6c5..8cef7b6c266d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 Advanced Micro Devices, Inc.
+ * Copyright 2015-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -846,6 +846,16 @@ void hwss_build_fast_sequence(struct dc *dc,
block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;
(*num_steps)++;
}
+ if (current_mpc_pipe->plane_state->update_flags.bits.cm_hist_change) {
+ block_sequence[*num_steps].params.control_cm_hist_params.dpp
+ = current_mpc_pipe->plane_res.dpp;
+ block_sequence[*num_steps].params.control_cm_hist_params.cm_hist_control
+ = current_mpc_pipe->plane_state->cm_hist_control;
+ block_sequence[*num_steps].params.control_cm_hist_params.color_space
+ = current_mpc_pipe->plane_state->color_space;
+ block_sequence[*num_steps].func = DPP_PROGRAM_CM_HIST;
+ (*num_steps)++;
+ }
}
if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) {
block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;
@@ -1029,6 +1039,9 @@ void hwss_execute_sequence(struct dc *dc,
case HUBP_PROGRAM_MCACHE_ID:
hwss_program_mcache_id_and_split_coordinate(params);
break;
+ case DPP_PROGRAM_CM_HIST:
+ hwss_program_cm_hist(params);
+ break;
case PROGRAM_CURSOR_UPDATE_NOW:
dc->hwss.program_cursor_offload_now(
params->program_cursor_update_now_params.dc,
@@ -2054,6 +2067,16 @@ void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *pa
}
+void hwss_program_cm_hist(union block_sequence_params *params)
+{
+ struct dpp *dpp = params->control_cm_hist_params.dpp;
+
+ if (dpp && dpp->funcs->dpp_cm_hist_control)
+ dpp->funcs->dpp_cm_hist_control(dpp,
+ params->control_cm_hist_params.cm_hist_control,
+ params->control_cm_hist_params.color_space);
+}
+
void get_surface_tile_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color)
@@ -3377,6 +3400,20 @@ void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_s
}
}
+void hwss_add_dpp_program_cm_hist(struct block_sequence_state *seq_state,
+ struct dpp *dpp,
+ struct cm_hist_control cm_hist_control,
+ enum dc_color_space color_space)
+{
+ if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
+ seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_CM_HIST;
+ seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.dpp = dpp;
+ seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.cm_hist_control = cm_hist_control;
+ seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.color_space = color_space;
+ (*seq_state->num_steps)++;
+ }
+}
+
void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state,
struct dc *dc,
bool enable)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 639831295b21..bad8515fda58 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -78,6 +78,7 @@
#include "dcn351/dcn351_resource.h"
#include "dcn36/dcn36_resource.h"
#include "dcn401/dcn401_resource.h"
+#include "dcn42/dcn42_resource.h"
#if defined(CONFIG_DRM_AMD_DC_FP)
#include "dc_spl_translate.h"
#endif
@@ -252,6 +253,9 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
ASICREV_IS_GC_12_0_0_A0(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_4_01;
break;
+ case AMDGPU_FAMILY_GC_11_5_4:
+ dc_version = DCN_VERSION_4_2;
+ break;
default:
dc_version = DCE_VERSION_UNKNOWN;
break;
@@ -368,6 +372,9 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
case DCN_VERSION_4_01:
res_pool = dcn401_create_resource_pool(init_data, dc);
break;
+ case DCN_VERSION_4_2:
+ res_pool = dcn42_create_resource_pool(init_data, dc);
+ break;
#endif /* CONFIG_DRM_AMD_DC_FP */
default:
break;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index ce08477d1ccd..94dd90d3cb67 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2012-2023 Advanced Micro Devices, Inc.
+ * Copyright 2012-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -734,6 +734,8 @@ struct dc_clocks {
struct {
uint8_t base_efficiency; //LP1
uint8_t low_power_efficiency; //LP2
+ uint8_t z8_stutter_efficiency;
+ int z8_stutter_period;
} stutter_efficiency;
};
@@ -1212,6 +1214,7 @@ struct dc_debug_options {
unsigned int num_fast_flips_to_steady_state_override;
bool enable_dmu_recovery;
unsigned int force_vmin_threshold;
+ bool enable_otg_frame_sync_pwa;
};
@@ -1420,6 +1423,7 @@ struct dc_plane_status {
struct dc_plane_address current_address;
bool is_flip_pending;
bool is_right_eye;
+ struct cm_hist cm_hist;
};
union surface_update_flags {
@@ -1456,6 +1460,7 @@ union surface_update_flags {
uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */
uint32_t full_update:1;
uint32_t sdr_white_level_nits:1;
+ uint32_t cm_hist_change:1;
} bits;
uint32_t raw;
@@ -1540,6 +1545,7 @@ struct dc_plane_state {
int sharpness_level;
enum linear_light_scaling linear_light_scaling;
unsigned int sdr_white_level_nits;
+ struct cm_hist_control cm_hist_control;
struct spl_sharpness_range sharpness_range;
enum sharpness_range_source sharpness_source;
};
@@ -1844,6 +1850,7 @@ struct dc_fast_update {
struct dc_transfer_func *out_transfer_func;
struct dc_csc_transform *output_csc_transform;
const struct dc_csc_transform *cursor_csc_color_matrix;
+ struct cm_hist_control *cm_hist_control;
};
struct dc_surface_update {
@@ -1876,6 +1883,7 @@ struct dc_surface_update {
const struct dc_csc_transform *cursor_csc_color_matrix;
unsigned int sdr_white_level_nits;
struct dc_bias_and_scale bias_and_scale;
+ struct cm_hist_control *cm_hist_control;
};
struct dc_underflow_debug_data {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 5a365bd19933..04b8b798dfff 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -751,6 +751,8 @@ char *dce_version_to_string(const int version)
return "DCN 3.6";
case DCN_VERSION_4_01:
return "DCN 4.0.1";
+ case DCN_VERSION_4_2:
+ return "DCN 4.2";
default:
return "Unknown";
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 7121629da38e..5de8b67f693d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -271,6 +271,15 @@ enum tile_split_values_new {
DC_SURF_TILE_SPLIT_1KB = 0x4,
};
+enum otg_pwa_sync_mode {
+ DC_OTG_PWA_FRAME_SYNC_MODE_VSYNC = 0x0,
+ DC_OTG_PWA_FRAME_SYNC_MODE_VSTARTUP = 0x1,
+};
+struct otc_pwa_frame_sync {
+ enum otg_pwa_sync_mode pwa_sync_mode;
+ uint32_t pwa_frame_sync_line_offset;
+};
+
/* TODO: These values come from hardware spec. We need to readdress this
* if they ever change.
*/
@@ -1138,6 +1147,7 @@ struct mcif_buf_params {
unsigned int warmup_pitch;
unsigned int swlock;
unsigned int p_vmid;
+ uint8_t tmz_id;
};
@@ -1163,5 +1173,68 @@ struct phy_state {
enum symclk_state symclk_state;
};
+enum cm_hist_tap_point {
+ CM_HIST_TAP_POINT_1,
+ CM_HIST_TAP_POINT_2,
+ CM_HIST_TAP_POINT_3,
+ CM_HIST_TAP_POINT_4,
+};
+
+enum cm_hist_src {
+ CM_HIST_SRC1,
+ CM_HIST_SRC2,
+ CM_HIST_SRC3,
+};
+
+enum cm_hist_format {
+ CM_HIST_FORMAT_FIXED_POINT,
+ CM_HIST_FORMAT_FP16_POS,
+ CM_HIST_FORMAT_FP16_POS_AND_NEG,
+};
+
+enum cm_hist_read_channel_mask {
+ CM_HIST_READ_DISABLED,
+ CM_HIST_READ_CH1,
+ CM_HIST_READ_CH2,
+ CM_HIST_READ_CH1_CH2,
+ CM_HIST_READ_CH3,
+ CM_HIST_READ_CH1_CH3,
+ CM_HIST_READ_CH2_CH3,
+ CM_HIST_READ_ALL,
+};
+
+enum cm_hist_src1_mode {
+ CM_HIST_SRC1_MODE_R_OR_CR,
+ CM_HIST_SRC1_MODE_MAX_RGB,
+};
+
+enum cm_hist_src2_mode {
+ CM_HIST_SRC2_MODE_G_OR_Y,
+ CM_HIST_SRC2_MODE_RGB_TO_Y,
+};
+
+enum cm_hist_src3_mode {
+ CM_HIST_SRC3_MODE_B_OR_CB,
+ CM_HIST_SRC3_MODE_MIN_RGB,
+};
+
+struct cm_hist_control {
+ enum cm_hist_tap_point tap_point;
+ uint32_t channels_enabled;
+ enum cm_hist_src1_mode src_1_select;
+ enum cm_hist_src2_mode src_2_select;
+ enum cm_hist_src3_mode src_3_select;
+ enum cm_hist_src ch1_src;
+ enum cm_hist_src ch2_src;
+ enum cm_hist_src ch3_src;
+ enum cm_hist_format format;
+ enum cm_hist_read_channel_mask read_channel_mask;
+};
+
+struct cm_hist {
+ uint32_t ch1[256];
+ uint32_t ch2[256];
+ uint32_t ch3[256];
+};
#endif /* DC_HW_TYPES_H */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index bddb16bb76d4..d2e60480fb2b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2012-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -1346,6 +1346,7 @@ enum dc_cm2_gpu_mem_layout {
enum dc_cm2_gpu_mem_pixel_component_order {
DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA,
+ DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_BGRA
};
enum dc_cm2_gpu_mem_format {
@@ -1367,6 +1368,9 @@ struct dc_cm2_gpu_mem_format_parameters {
enum dc_cm2_gpu_mem_size {
DC_CM2_GPU_MEM_SIZE_171717,
+ DC_CM2_GPU_MEM_SIZE_333333,
+ DC_CM2_GPU_MEM_SIZE_454545,
+ DC_CM2_GPU_MEM_SIZE_656565,
DC_CM2_GPU_MEM_SIZE_TRANSFORMED,
};
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/Makefile b/drivers/gpu/drm/amd/display/dc/dccg/Makefile
index 1d5cf0f8e79d..bf7e71166b5e 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dccg/Makefile
@@ -1,5 +1,5 @@
-# Copyright 2022 Advanced Micro Devices, Inc.
+# Copyright 2022-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -100,4 +100,13 @@ DCCG_DCN401 = dcn401_dccg.o
AMD_DAL_DCCG_DCN401 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn401/,$(DCCG_DCN401))
AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN401)
+
+###############################################################################
+# DCN42
+###############################################################################
+DCCG_DCN42 = dcn42_dccg.o
+
+AMD_DAL_DCCG_DCN42 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn42/,$(DCCG_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN42)
endif
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
index 8bdffd9ff31b..ac4d77cf763f 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2018 Advanced Micro Devices, Inc.
+ * Copyright 2018-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -359,6 +359,16 @@
type SYMCLK32_LE3_EN;\
type DP_DTO_ENABLE[MAX_PIPES];
+#define DCCG42_REG_FIELD_LIST(type) \
+ type OTG0_ADD_PIXEL;\
+ type OTG1_ADD_PIXEL;\
+ type OTG2_ADD_PIXEL;\
+ type OTG0_DROP_PIXEL;\
+ type OTG1_DROP_PIXEL;\
+ type OTG2_DROP_PIXEL;\
+ type OTG3_ADD_PIXEL;\
+ type OTG3_DROP_PIXEL;
+
struct dccg_shift {
DCCG_REG_FIELD_LIST(uint8_t)
DCCG3_REG_FIELD_LIST(uint8_t)
@@ -367,6 +377,7 @@ struct dccg_shift {
DCCG32_REG_FIELD_LIST(uint8_t)
DCCG35_REG_FIELD_LIST(uint8_t)
DCCG401_REG_FIELD_LIST(uint8_t)
+ DCCG42_REG_FIELD_LIST(uint8_t)
};
struct dccg_mask {
@@ -377,6 +388,7 @@ struct dccg_mask {
DCCG32_REG_FIELD_LIST(uint32_t)
DCCG35_REG_FIELD_LIST(uint32_t)
DCCG401_REG_FIELD_LIST(uint32_t)
+ DCCG42_REG_FIELD_LIST(uint32_t)
};
#define DCCG_REG_VARIABLE_LIST \
@@ -490,6 +502,7 @@ struct dccg_mask {
struct dccg_registers {
DCCG_REG_VARIABLE_LIST;
+ uint32_t OTG_ADD_DROP_PIXEL_CNTL;
};
struct dcn_dccg {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index 3d819fc5654c..1e9ab5ff3a31 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2012-16 Advanced Micro Devices, Inc.
+ * Copyright 2012-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -300,6 +300,64 @@
ABM_SF(ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, \
ABM1_HG_BIN_57_64_SHIFT_INDEX, mask_sh)
+#define ABM_MASK_SH_LIST_DCN42(mask_sh) \
+ ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
+ ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
+ ABM1_HG_VMAX_SEL, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
+ ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
+ ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
+ ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
+ ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
+ ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
+ BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
+ ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
+ BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
+ ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
+ BL1_PWM_USER_LEVEL, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
+ ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
+ ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
+ ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
+ ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
+ ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \
+ ABM1_ACE_SLOPE_DATA, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \
+ ABM1_ACE_OFFSET_DATA, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
+ ABM1_ACE_OFFSET_SLOPE_INDEX, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
+ ABM1_ACE_IGNORE_MASTER_LOCK_EN, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
+ ABM1_ACE_READBACK_DB_REG_VALUE_EN, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
+ ABM1_ACE_DBUF_REG_UPDATE_PENDING, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
+ ABM1_ACE_LOCK, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HG_RESULT_DATA, \
+ ABM1_HG_RESULT_DATA, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HG_RESULT_INDEX, \
+ ABM1_HG_RESULT_INDEX, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, \
+ ABM1_HG_BIN_33_40_SHIFT_INDEX, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, \
+ ABM1_HG_BIN_33_64_SHIFT_FLAG, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, \
+ ABM1_HG_BIN_41_48_SHIFT_INDEX, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, \
+ ABM1_HG_BIN_49_56_SHIFT_INDEX, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, \
+ ABM1_HG_BIN_57_64_SHIFT_INDEX, mask_sh)
+
#define ABM_REG_FIELD_LIST(type) \
type ABM1_HG_NUM_OF_BINS_SEL; \
type ABM1_HG_VMAX_SEL; \
diff --git a/drivers/gpu/drm/amd/display/dc/dio/Makefile b/drivers/gpu/drm/amd/display/dc/dio/Makefile
index 2f5619078e1f..4832533b9514 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dio/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright 2020 Advanced Micro Devices, Inc.
+# Copyright 2020-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -123,4 +123,13 @@ DIO_DCN401 = dcn401_dio_link_encoder.o dcn401_dio_stream_encoder.o
AMD_DAL_DIO_DCN401 = $(addprefix $(AMDDALPATH)/dc/dio/dcn401/,$(DIO_DCN401))
AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN401)
+
+###############################################################################
+# DCN42
+###############################################################################
+DIO_DCN42 = dcn42_dio_link_encoder.o dcn42_dio_stream_encoder.o
+
+AMD_DAL_DIO_DCN42 = $(addprefix $(AMDDALPATH)/dc/dio/dcn42/,$(DIO_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN42)
endif
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
index 54a6a4ebd636..755367506556 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2012-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -190,6 +190,7 @@ struct dcn10_stream_enc_registers {
uint32_t DIG_FE_CLK_CNTL;
uint32_t DIG_FE_EN_CNTL;
uint32_t STREAM_MAPPER_CONTROL;
+ uint32_t DIG_FE_AUDIO_CNTL;
};
@@ -598,6 +599,11 @@ struct dcn10_stream_enc_registers {
type DP_VID_N_INTERVAL;\
type DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE;\
type DP_STEER_FIFO_ENABLE
+
+#define SE_REG_FIELD_LIST_DCN_AUDIO_COMMON(type) \
+ type DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL;\
+ type APG_CLOCK_ENABLE
+
struct dcn10_stream_encoder_shift {
SE_REG_FIELD_LIST_DCN1_0(uint8_t);
uint8_t HDMI_ACP_SEND;
@@ -606,6 +612,7 @@ struct dcn10_stream_encoder_shift {
SE_REG_FIELD_LIST_DCN3_1_COMMON(uint8_t);
SE_REG_FIELD_LIST_DCN3_5_COMMON(uint8_t);
SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t);
+ SE_REG_FIELD_LIST_DCN_AUDIO_COMMON(uint32_t);
};
struct dcn10_stream_encoder_mask {
@@ -616,6 +623,7 @@ struct dcn10_stream_encoder_mask {
SE_REG_FIELD_LIST_DCN3_1_COMMON(uint32_t);
SE_REG_FIELD_LIST_DCN3_5_COMMON(uint32_t);
SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t);
+ SE_REG_FIELD_LIST_DCN_AUDIO_COMMON(uint32_t);
};
struct dcn10_stream_encoder {
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/Makefile b/drivers/gpu/drm/amd/display/dc/dpp/Makefile
index 8324a56fe7db..2595b2504f9d 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dpp/Makefile
@@ -1,5 +1,5 @@
-# Copyright 2022 Advanced Micro Devices, Inc.
+# Copyright 2022-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -80,4 +80,12 @@ AMD_DAL_DPP_DCN401 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn401/,$(DPP_DCN401))
AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN401)
+###############################################################################
+# DCN42
+###############################################################################
+DPP_DCN42 = dcn42_dpp.o
+
+AMD_DAL_DPP_DCN42 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn42/,$(DPP_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN42)
endif
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
index 58b9f1cd0825..debcf308cb3b 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
@@ -1,4 +1,5 @@
-/* Copyright 2023 Advanced Micro Devices, Inc.
+/* SPDX-License-Identifier: MIT */
+/* Copyright 2023-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -653,6 +654,8 @@
struct dcn401_dpp_registers {
DPP_REG_VARIABLE_LIST_DCN401;
+ uint32_t ALPHA_2BIT_LUT01;
+ uint32_t ALPHA_2BIT_LUT23;
};
struct dcn401_dpp_shift {
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
index b72e2a9f9a28..f8142ebf363f 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright 2017 Advanced Micro Devices, Inc.
+# Copyright 2017-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -132,3 +132,14 @@ AMD_DAL_GPIO_DCN401 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn401/,$(GPIO_DCN401))
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN401)
+###############################################################################
+# DCN 4.2
+###############################################################################
+
+GPIO_DCN42 = hw_translate_dcn42.o hw_factory_dcn42.o
+
+AMD_DAL_GPIO_DCN42 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn42/,$(GPIO_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN42)
+
+
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index 8bc67ca42197..f3d562c8df4c 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -53,6 +53,7 @@
#include "dcn315/hw_factory_dcn315.h"
#include "dcn32/hw_factory_dcn32.h"
#include "dcn401/hw_factory_dcn401.h"
+#include "dcn42/hw_factory_dcn42.h"
bool dal_hw_factory_init(
struct hw_factory *factory,
@@ -118,6 +119,9 @@ bool dal_hw_factory_init(
case DCN_VERSION_4_01:
dal_hw_factory_dcn401_init(factory);
return true;
+ case DCN_VERSION_4_2:
+ dal_hw_factory_dcn42_init(factory);
+ return true;
default:
ASSERT_CRITICAL(false);
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index cb79a2832287..1c977fc4d0e3 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -53,6 +53,7 @@
#include "dcn315/hw_translate_dcn315.h"
#include "dcn32/hw_translate_dcn32.h"
#include "dcn401/hw_translate_dcn401.h"
+#include "dcn42/hw_translate_dcn42.h"
/*
* This unit
@@ -119,6 +120,9 @@ bool dal_hw_translate_init(
case DCN_VERSION_4_01:
dal_hw_translate_dcn401_init(translate);
return true;
+ case DCN_VERSION_4_2:
+ dal_hw_translate_dcn42_init(translate);
+ return true;
default:
BREAK_TO_DEBUGGER();
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/hpo/Makefile b/drivers/gpu/drm/amd/display/dc/hpo/Makefile
index 7f2c9ee0dff1..25b196714bd8 100644
--- a/drivers/gpu/drm/amd/display/dc/hpo/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/hpo/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright 2020 Advanced Micro Devices, Inc.
+# Copyright 2020-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -47,4 +47,13 @@ HPO_DCN32 = dcn32_hpo_dp_link_encoder.o
AMD_DAL_HPO_DCN32 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn32/,$(HPO_DCN32))
AMD_DISPLAY_FILES += $(AMD_DAL_HPO_DCN32)
+
+###############################################################################
+# DCN42
+###############################################################################
+HPO_DCN42 = dcn42_hpo_dp_link_encoder.o
+
+AMD_DAL_HPO_DCN42 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn42/,$(HPO_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_HPO_DCN42)
endif
diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h
index 82c3b3ac1f0d..d96fcc59cc0e 100644
--- a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2019 Advanced Micro Devices, Inc.
+ * Copyright 2019-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -208,17 +208,24 @@
type CRC_CONT_MODE_ENABLE;\
type HBLANK_MINIMUM_SYMBOL_WIDTH
+#define DCN4_2_HPO_DP_STREAM_ENC_REG_FIELD_LIST(type) \
+ type DP_STREAM_ENC_APG_CLOCK_EN
+#define DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh)\
+ DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh),\
+ SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC_APG_CLOCK_EN, mask_sh)
struct dcn31_hpo_dp_stream_encoder_registers {
DCN3_1_HPO_DP_STREAM_ENC_REGS;
};
struct dcn31_hpo_dp_stream_encoder_shift {
DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint8_t);
+ DCN4_2_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint8_t);
};
struct dcn31_hpo_dp_stream_encoder_mask {
DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t);
+ DCN4_2_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t);
};
struct dcn31_hpo_dp_stream_encoder {
@@ -241,5 +248,4 @@ void dcn31_hpo_dp_stream_encoder_construct(
const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift,
const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask);
-
#endif // __DAL_DCN31_HPO_STREAM_ENCODER_H__
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/Makefile b/drivers/gpu/drm/amd/display/dc/hubbub/Makefile
index 66ca5a6a0415..29c8e2651442 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/Makefile
@@ -1,5 +1,5 @@
-# Copyright 2022 Advanced Micro Devices, Inc.
+# Copyright 2022-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -101,4 +101,12 @@ AMD_DAL_HUBBUB_DCN401 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn401/,$(HUBBUB_DCN
AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN401)
###############################################################################
+# DCN42
+###############################################################################
+HUBBUB_DCN42 = dcn42_hubbub.o
+
+AMD_DAL_HUBBUB_DCN42 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn42/,$(HUBBUB_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN42)
+
endif
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
index 990d3cd8e050..ff9a1ae29474 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2016 Advanced Micro Devices, Inc.
+ * Copyright 2016-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -441,6 +441,8 @@ struct dcn_hubbub_registers {
type DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE;\
type DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE
+#define HUBBUB_REG_FIELD_LIST_DCN4_2(type) \
+ type URGENT_ZERO_SIZE_REQ_EN
struct dcn_hubbub_shift {
DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);
@@ -449,6 +451,7 @@ struct dcn_hubbub_shift {
HUBBUB_REG_FIELD_LIST_DCN32(uint8_t);
HUBBUB_REG_FIELD_LIST_DCN35(uint8_t);
HUBBUB_REG_FIELD_LIST_DCN4_01(uint8_t);
+ HUBBUB_REG_FIELD_LIST_DCN4_2(uint8_t);
};
@@ -460,6 +463,7 @@ struct dcn_hubbub_mask {
HUBBUB_REG_FIELD_LIST_DCN32(uint32_t);
HUBBUB_REG_FIELD_LIST_DCN35(uint32_t);
HUBBUB_REG_FIELD_LIST_DCN4_01(uint32_t);
+ HUBBUB_REG_FIELD_LIST_DCN4_2(uint8_t);
};
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/Makefile b/drivers/gpu/drm/amd/display/dc/hubp/Makefile
index a2d1128de7a1..e0799bb873e6 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/hubp/Makefile
@@ -1,5 +1,5 @@
-# Copyright 2022 Advanced Micro Devices, Inc.
+# Copyright 2022-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -94,4 +94,12 @@ AMD_DAL_HUBP_DCN401 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn401/,$(HUBP_DCN401))
AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN401)
+###############################################################################
+
+HUBP_DCN42 = dcn42_hubp.o
+
+AMD_DAL_HUBP_DCN42 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn42/,$(HUBP_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN42)
+
endif
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
index 7062e6653062..80be394a8852 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2012-17 Advanced Micro Devices, Inc.
+ * Copyright 2012-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -288,16 +288,22 @@
type MCACHEID_MALL_PREF_2H_P1;\
type HUBP_FGCG_REP_DIS
+#define DCN42_HUBP_REG_FIELD_VARIABLE_LIST(type) \
+ type HUBP_3DLUT_CROSSBAR_SEL_G;\
+ type HUBP_3DLUT_CROSSBAR_SEL_B;\
+ type HUBP_3DLUT_CROSSBAR_SEL_R
struct dcn_hubp2_registers {
DCN401_HUBP_REG_COMMON_VARIABLE_LIST;
};
struct dcn_hubp2_shift {
DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
+ DCN42_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
};
struct dcn_hubp2_mask {
DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
+ DCN42_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
};
struct dcn20_hubp {
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/Makefile b/drivers/gpu/drm/amd/display/dc/hwss/Makefile
index bee617ca0838..08cbbf87a19f 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/hwss/Makefile
@@ -1,5 +1,4 @@
-
-# Copyright 2022 Advanced Micro Devices, Inc.
+# Copyright 2022-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -199,4 +198,13 @@ HWSS_DCN401 = dcn401_hwseq.o dcn401_init.o
AMD_DAL_HWSS_DCN401 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn401/,$(HWSS_DCN401))
AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN401)
+
+###############################################################################
+
+HWSS_DCN42 = dcn42_hwseq.o dcn42_init.o
+
+AMD_DAL_HWSS_DCN42 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn42/,$(HWSS_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN42)
+
endif
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
index f66a38f43a09..dc8feca578c5 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2016 Advanced Micro Devices, Inc.
+ * Copyright 2016, 2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -700,6 +700,8 @@ struct dce_hwseq_registers {
uint32_t DOMAIN23_PG_STATUS;
uint32_t DOMAIN24_PG_STATUS;
uint32_t DOMAIN25_PG_STATUS;
+ uint32_t DOMAIN26_PG_CONFIG;
+ uint32_t DOMAIN26_PG_STATUS;
};
/* set field name */
#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
@@ -1245,6 +1247,13 @@ struct dce_hwseq_registers {
type DOMAIN25_PGFSM_PWR_STATUS; \
type DOMAIN_DESIRED_PWR_STATE;
+#define HWSEQ_DCN42_REG_FIELD_LIST(type) \
+ type DPIASYMCLK4_GATE_DISABLE;\
+ type DPIASYMCLK5_GATE_DISABLE;\
+ type DOMAIN26_POWER_FORCEON; \
+ type DOMAIN26_POWER_GATE; \
+ type DOMAIN26_PGFSM_PWR_STATUS;
+
struct dce_hwseq_shift {
HWSEQ_REG_FIELD_LIST(uint8_t)
HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
@@ -1253,6 +1262,7 @@ struct dce_hwseq_shift {
HWSEQ_DCN31_REG_FIELD_LIST(uint8_t)
HWSEQ_DCN35_REG_FIELD_LIST(uint8_t)
HWSEQ_DCN401_REG_FIELD_LIST(uint8_t)
+ HWSEQ_DCN42_REG_FIELD_LIST(uint8_t)
};
struct dce_hwseq_mask {
@@ -1263,6 +1273,7 @@ struct dce_hwseq_mask {
HWSEQ_DCN31_REG_FIELD_LIST(uint32_t)
HWSEQ_DCN35_REG_FIELD_LIST(uint32_t)
HWSEQ_DCN401_REG_FIELD_LIST(uint32_t)
+ HWSEQ_DCN42_REG_FIELD_LIST(uint32_t)
};
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index 51b0f0fd8fcd..4ec324857759 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 Advanced Micro Devices, Inc.
+ * Copyright 2015-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -174,6 +174,12 @@ struct program_mcache_id_and_split_coordinate {
struct dml2_hubp_pipe_mcache_regs *mcache_regs;
};
+struct control_cm_hist_params {
+ struct dpp *dpp;
+ struct cm_hist_control cm_hist_control;
+ enum dc_color_space color_space;
+};
+
struct program_cursor_update_now_params {
struct dc *dc;
struct pipe_ctx *pipe_ctx;
@@ -755,6 +761,7 @@ union block_sequence_params {
struct dmub_hw_control_lock_fast_params dmub_hw_control_lock_fast_params;
struct program_surface_config_params program_surface_config_params;
struct program_mcache_id_and_split_coordinate program_mcache_id_and_split_coordinate;
+ struct control_cm_hist_params control_cm_hist_params;
struct program_cursor_update_now_params program_cursor_update_now_params;
struct hubp_wait_pipe_read_start_params hubp_wait_pipe_read_start_params;
struct apply_update_flags_for_phantom_params apply_update_flags_for_phantom_params;
@@ -879,6 +886,7 @@ enum block_sequence_func {
DMUB_HW_CONTROL_LOCK_FAST,
HUBP_PROGRAM_SURFACE_CONFIG,
HUBP_PROGRAM_MCACHE_ID,
+ DPP_PROGRAM_CM_HIST,
PROGRAM_CURSOR_UPDATE_NOW,
HUBP_WAIT_PIPE_READ_START,
HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM,
@@ -1411,6 +1419,8 @@ void hwss_program_surface_config(union block_sequence_params *params);
void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params);
+void hwss_program_cm_hist(union block_sequence_params *params);
+
void hwss_set_odm_combine(union block_sequence_params *params);
void hwss_set_odm_bypass(union block_sequence_params *params);
@@ -1761,6 +1771,11 @@ void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_s
bool use_default_params,
struct pipe_ctx *pipe_ctx);
+void hwss_add_dpp_program_cm_hist(struct block_sequence_state *seq_state,
+ struct dpp *dpp,
+ struct cm_hist_control cm_hist_control,
+ enum dc_color_space color_space);
+
void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state,
struct dc *dc,
bool enable);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
index 406db231bc72..8e3f54fb53fd 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 Advanced Micro Devices, Inc.
+ * Copyright 2015-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -222,6 +222,9 @@ struct hwseq_private_funcs {
void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only);
void (*set_wait_for_update_needed_for_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx);
void (*dc_ip_request_cntl)(struct dc *dc, bool enable);
+ void (*program_cm_hist)(struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ const struct dc_plane_state *plane_state);
};
struct dce_hwseq {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 2c9a4a12bd8a..91eba1985bab 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -1,5 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
- * Copyright 2012-16 Advanced Micro Devices, Inc.
+ * Copyright 2012-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -95,6 +96,26 @@ struct dcn301_clk_internal {
uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
};
+struct dcn42_clk_internal {
+ int dummy;
+ uint32_t CLK8_CLK0_CURRENT_CNT; //dispclk
+ uint32_t CLK8_CLK1_CURRENT_CNT; //dppclk
+ uint32_t CLK8_CLK2_CURRENT_CNT; //dprefclk
+ uint32_t CLK8_CLK3_CURRENT_CNT; //dcfclk
+ uint32_t CLK8_CLK4_CURRENT_CNT; //dtbclk
+ uint32_t CLK8_CLK0_DS_CNTL; //dispclk deep_sleep_divider
+ uint32_t CLK8_CLK1_DS_CNTL; //dppclk deep_sleep_divider
+ uint32_t CLK8_CLK2_DS_CNTL; //dprefclk deep_sleep_divider
+ uint32_t CLK8_CLK3_DS_CNTL; //dcfclk deep_sleep_divider
+ uint32_t CLK8_CLK4_DS_CNTL; //dtbclk deep_sleep_divider
+ uint32_t CLK8_CLK0_BYPASS_CNTL; //dispclk bypass
+ uint32_t CLK8_CLK1_BYPASS_CNTL; //dppclk bypass
+ uint32_t CLK8_CLK2_BYPASS_CNTL; //dprefclk bypass
+ uint32_t CLK8_CLK3_BYPASS_CNTL; //dcfclk bypass
+ uint32_t CLK8_CLK4_BYPASS_CNTL; //dtbclk bypass
+ uint32_t CLK8_CLK_TICK_CNT__TIMER_THRESHOLD;
+};
+
/* Will these bw structures be ASIC specific? */
#define MAX_NUM_DPM_LVL 8
@@ -194,6 +215,7 @@ struct clk_state_registers_and_bypass {
uint32_t dcfclk_bypass;
uint32_t dprefclk_bypass;
uint32_t dispclk_bypass;
+ uint32_t timer_threhold;
};
struct rv1_clk_internal {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index bac8febad69a..37521e17b72f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -1,5 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
- * Copyright 2018 Advanced Micro Devices, Inc.
+ * Copyright 2018-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -234,6 +235,29 @@ enum dentist_divider_range {
#define CLK_COMMON_MASK_SH_LIST_DCN401(mask_sh) \
CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh)
+#define CLK_REG_LIST_DCN42() \
+ SR(DENTIST_DISPCLK_CNTL), \
+ CLK_SR_DCN42(CLK8_CLK_TICK_CNT_CONFIG_REG), \
+ CLK_SR_DCN42(CLK8_CLK0_CURRENT_CNT), \
+ CLK_SR_DCN42(CLK8_CLK1_CURRENT_CNT), \
+ CLK_SR_DCN42(CLK8_CLK2_CURRENT_CNT), \
+ CLK_SR_DCN42(CLK8_CLK3_CURRENT_CNT), \
+ CLK_SR_DCN42(CLK8_CLK4_CURRENT_CNT), \
+ CLK_SR_DCN42(CLK8_CLK0_BYPASS_CNTL), \
+ CLK_SR_DCN42(CLK8_CLK1_BYPASS_CNTL), \
+ CLK_SR_DCN42(CLK8_CLK2_BYPASS_CNTL), \
+ CLK_SR_DCN42(CLK8_CLK3_BYPASS_CNTL), \
+ CLK_SR_DCN42(CLK8_CLK4_BYPASS_CNTL), \
+ CLK_SR_DCN42(CLK8_CLK0_DS_CNTL), \
+ CLK_SR_DCN42(CLK8_CLK1_DS_CNTL), \
+ CLK_SR_DCN42(CLK8_CLK2_DS_CNTL), \
+ CLK_SR_DCN42(CLK8_CLK3_DS_CNTL), \
+ CLK_SR_DCN42(CLK8_CLK4_DS_CNTL)
+
+#define CLK_COMMON_MASK_SH_LIST_DCN42(mask_sh) 0
+
+
+
#define CLK_REG_FIELD_LIST(type) \
type DPREFCLK_SRC_SEL; \
type DENTIST_DPREFCLK_WDIVIDER; \
@@ -309,6 +333,22 @@ struct clk_mgr_registers {
uint32_t CLK1_CLK5_ALLOW_DS;
uint32_t CLK5_spll_field_8;
uint32_t CLK6_spll_field_8;
+ uint32_t CLK8_CLK0_CURRENT_CNT;
+ uint32_t CLK8_CLK1_CURRENT_CNT;
+ uint32_t CLK8_CLK2_CURRENT_CNT;
+ uint32_t CLK8_CLK3_CURRENT_CNT;
+ uint32_t CLK8_CLK4_CURRENT_CNT;
+ uint32_t CLK8_CLK0_DS_CNTL;
+ uint32_t CLK8_CLK1_DS_CNTL;
+ uint32_t CLK8_CLK2_DS_CNTL;
+ uint32_t CLK8_CLK3_DS_CNTL;
+ uint32_t CLK8_CLK4_DS_CNTL;
+ uint32_t CLK8_CLK0_BYPASS_CNTL;
+ uint32_t CLK8_CLK1_BYPASS_CNTL;
+ uint32_t CLK8_CLK2_BYPASS_CNTL;
+ uint32_t CLK8_CLK3_BYPASS_CNTL;
+ uint32_t CLK8_CLK4_BYPASS_CNTL;
+ uint32_t CLK8_CLK_TICK_CNT_CONFIG_REG;
};
struct clk_mgr_shift {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index d88b57d4f512..39215ecb480e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2012-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -367,6 +367,14 @@ struct dpp_funcs {
void (*dpp_force_disable_cursor)(struct dpp *dpp_base);
+ void (*dpp_cm_hist_control)(
+ struct dpp *dpp_base,
+ struct cm_hist_control cm_hist_control,
+ enum dc_color_space color_space);
+
+ bool (*dpp_cm_hist_read)(
+ struct dpp *dpp_base,
+ struct cm_hist *cm_hist);
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index a8d1abe20f62..0db607f2a410 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2012-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -1042,6 +1042,24 @@ struct mpc_funcs {
void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx);
+/**
+ * @get_3dlut_fast_load_status:
+ *
+ * Get 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow pointers.
+ *
+ * Parameters:
+ * - [in/out] mpc - MPC context.
+ * - [in] mpcc_id
+ * - [in/out] done
+ * - [in/out] soft_underflow
+ * - [in/out] hard_underflow
+ *
+ * Return:
+ *
+ * void
+ */
+ void (*get_3dlut_fast_load_status)(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow);
+
/**
* @populate_lut:
*
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 671ab1fc7320..2f70bb476c97 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2012-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -518,6 +518,8 @@ struct timing_generator_funcs {
bool (*wait_update_lock_status)(struct timing_generator *tg, bool locked);
void (*read_otg_state)(struct timing_generator *tg, struct dcn_otg_state *s);
void (*optc_read_reg_state)(struct timing_generator *tg, struct dcn_optc_reg_state *optc_reg_state);
+ void (*enable_otg_pwa)(struct timing_generator *tg, struct otc_pwa_frame_sync *pwa_param);
+ void (*disable_otg_pwa)(struct timing_generator *tg);
};
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index b5e14d792378..807b73c2a758 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -198,3 +198,12 @@ IRQ_DCN401 = irq_service_dcn401.o
AMD_DAL_IRQ_DCN401= $(addprefix $(AMDDALPATH)/dc/irq/dcn401/,$(IRQ_DCN401))
AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN401)
+
+###############################################################################
+# DCN 42
+###############################################################################
+IRQ_DCN42 = irq_service_dcn42.o
+
+AMD_DAL_IRQ_DCN42= $(addprefix $(AMDDALPATH)/dc/irq/dcn42/,$(IRQ_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN42)
diff --git a/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile b/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile
index 2d4b7a85847d..afc376defa0b 100644
--- a/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright 2020 Advanced Micro Devices, Inc.
+# Copyright 2020-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -52,3 +52,11 @@ AMD_DAL_MMHUBBUB_DCN35 = $(addprefix $(AMDDALPATH)/dc/mmhubbub/dcn35/,$(MMHUBBUB
AMD_DISPLAY_FILES += $(AMD_DAL_MMHUBBUB_DCN35)
endif
+###############################################################################
+# DCN42
+###############################################################################
+MMHUBBUB_DCN42 = dcn42_mmhubbub.o
+
+AMD_DAL_MMHUBBUB_DCN42 = $(addprefix $(AMDDALPATH)/dc/mmhubbub/dcn42/,$(MMHUBBUB_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_MMHUBBUB_DCN42)
diff --git a/drivers/gpu/drm/amd/display/dc/mpc/Makefile b/drivers/gpu/drm/amd/display/dc/mpc/Makefile
index 5402c3529f5e..cc23aae3728a 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/mpc/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright 2020 Advanced Micro Devices, Inc.
+# Copyright 2020-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -69,4 +69,12 @@ AMD_DAL_MPC_DCN401 = $(addprefix $(AMDDALPATH)/dc/mpc/dcn401/,$(MPC_DCN401))
AMD_DISPLAY_FILES += $(AMD_DAL_MPC_DCN401)
+###############################################################################
+# DCN42
+###############################################################################
+MPC_DCN42 = dcn42_mpc.o
+
+AMD_DAL_MPC_DCN42 = $(addprefix $(AMDDALPATH)/dc/mpc/dcn42/,$(MPC_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_MPC_DCN42)
endif
diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
index eeac13fdd6f5..ce1ee2062e41 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2023 Advanced Micro Devices, Inc.
+ * Copyright 2023-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -47,6 +47,16 @@ void mpc401_update_3dlut_fast_load_select(struct mpc *mpc, int mpcc_id, int hubp
REG_SET(MPCC_MCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, MPCC_MCM_3DLUT_FL_SEL, hubp_idx);
}
+void mpc401_get_3dlut_fast_load_status(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow)
+{
+ struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);
+
+ REG_GET_3(MPCC_MCM_3DLUT_FAST_LOAD_STATUS[mpcc_id],
+ MPCC_MCM_3DLUT_FL_DONE, done,
+ MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW, soft_underflow,
+ MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW, hard_underflow);
+}
+
void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id)
{
struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);
@@ -602,6 +612,7 @@ static const struct mpc_funcs dcn401_mpc_funcs = {
.set_bg_color = mpc1_set_bg_color,
.set_movable_cm_location = mpc401_set_movable_cm_location,
.update_3dlut_fast_load_select = mpc401_update_3dlut_fast_load_select,
+ .get_3dlut_fast_load_status = mpc401_get_3dlut_fast_load_status,
.populate_lut = mpc401_populate_lut,
.program_lut_read_write_control = mpc401_program_lut_read_write_control,
.program_lut_mode = mpc401_program_lut_mode,
diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
index fdc42f8ab3ff..6d842d7b95c7 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2023 Advanced Micro Devices, Inc.
+ * Copyright 2023-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -184,6 +184,7 @@ struct dcn401_mpc_mask {
struct dcn401_mpc_registers {
MPC_REG_VARIABLE_LIST_DCN4_01
+ uint32_t MPCC_CONTROL2[MAX_MPCC];
};
struct dcn401_mpc {
@@ -249,6 +250,13 @@ void mpc_read_gamut_remap(struct mpc *mpc,
enum mpcc_gamut_remap_id gamut_remap_block_id,
uint32_t *mode_select);
+void mpc401_get_3dlut_fast_load_status(
+ struct mpc *mpc,
+ int mpcc_id,
+ uint32_t *done,
+ uint32_t *soft_underflow,
+ uint32_t *hard_underflow);
+
void mpc401_update_3dlut_fast_load_select(
struct mpc *mpc,
int mpcc_id,
diff --git a/drivers/gpu/drm/amd/display/dc/optc/Makefile b/drivers/gpu/drm/amd/display/dc/optc/Makefile
index 29fb610c8660..06c98d70eabc 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/optc/Makefile
@@ -104,11 +104,19 @@ AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN35)
###############################################################################
-###############################################################################
OPTC_DCN401 = dcn401_optc.o
AMD_DAL_OPTC_DCN401 = $(addprefix $(AMDDALPATH)/dc/optc/dcn401/,$(OPTC_DCN401))
AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN401)
+
+###############################################################################
+
+OPTC_DCN42 = dcn42_optc.o
+
+AMD_DAL_OPTC_DCN42 = $(addprefix $(AMDDALPATH)/dc/optc/dcn42/,$(OPTC_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN42)
+
endif
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
index 0b3f974f452e..cf05620fd8f5 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2012-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -253,8 +253,20 @@
uint32_t OTG_CRC1_DATA_B32
+#define OPTC_REG_VARIABLE_LIST_DCN42 \
+ uint32_t OTG_PWA_FRAME_SYNC_CONTROL; \
+ uint32_t OTG_CRC0_DATA_R; \
+ uint32_t OTG_CRC1_DATA_R; \
+ uint32_t OTG_CRC2_DATA_R; \
+ uint32_t OTG_CRC3_DATA_R; \
+ uint32_t OTG_CRC0_DATA_G; \
+ uint32_t OTG_CRC1_DATA_G; \
+ uint32_t OTG_CRC2_DATA_G; \
+ uint32_t OTG_CRC3_DATA_G
+
struct dcn_optc_registers {
OPTC_REG_VARIABLE_LIST_DCN;
+ OPTC_REG_VARIABLE_LIST_DCN42;
};
#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
@@ -679,6 +691,10 @@ struct dcn_optc_registers {
type OTG_UNBLANK;\
type OTG_PSTATE_ALLOW_WIDTH_MIN;
+#define TG_REG_FIELD_LIST_DCN42(type) \
+ type OTG_PWA_FRAME_SYNC_EN;\
+ type OTG_PWA_FRAME_SYNC_VCOUNT_MODE;\
+ type OTG_PWA_FRAME_SYNC_LINE;
struct dcn_optc_shift {
TG_REG_FIELD_LIST(uint8_t)
@@ -687,6 +703,7 @@ struct dcn_optc_shift {
TG_REG_FIELD_LIST_DCN3_5(uint8_t)
TG_REG_FIELD_LIST_DCN3_6(uint8_t)
TG_REG_FIELD_LIST_DCN401(uint8_t)
+ TG_REG_FIELD_LIST_DCN42(uint8_t)
};
struct dcn_optc_mask {
@@ -696,6 +713,7 @@ struct dcn_optc_mask {
TG_REG_FIELD_LIST_DCN3_5(uint32_t)
TG_REG_FIELD_LIST_DCN3_6(uint32_t)
TG_REG_FIELD_LIST_DCN401(uint32_t)
+ TG_REG_FIELD_LIST_DCN42(uint32_t)
};
void dcn10_timing_generator_init(struct optc *optc);
diff --git a/drivers/gpu/drm/amd/display/dc/pg/Makefile b/drivers/gpu/drm/amd/display/dc/pg/Makefile
index ec11d3157a57..56f610cc8406 100644
--- a/drivers/gpu/drm/amd/display/dc/pg/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/pg/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright 2020 Advanced Micro Devices, Inc.
+# Copyright 2020, 2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -32,4 +32,12 @@ PG_DCN35 = dcn35_pg_cntl.o
AMD_DAL_PG_DCN35 = $(addprefix $(AMDDALPATH)/dc/pg/dcn35/,$(PG_DCN35))
AMD_DISPLAY_FILES += $(AMD_DAL_PG_DCN35)
+###############################################################################
+# DCN42
+###############################################################################
+PG_DCN42 = dcn42_pg_cntl.o
+
+AMD_DAL_PG_DCN42 = $(addprefix $(AMDDALPATH)/dc/pg/dcn42/,$(PG_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_PG_DCN42)
endif
diff --git a/drivers/gpu/drm/amd/display/dc/resource/Makefile b/drivers/gpu/drm/amd/display/dc/resource/Makefile
index 5b42da8b79c2..1a17a885fe84 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/resource/Makefile
@@ -222,4 +222,22 @@ AMD_DAL_RESOURCE_DCN401 = $(addprefix $(AMDDALPATH)/dc/resource/dcn401/,$(RESOUR
AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN401)
+###############################################################################
+# DCN42
+###############################################################################
+RESOURCE_DCN42 = dcn42_resource.o dcn42_resource_fpu.o
+
+AMD_DAL_RESOURCE_DCN42 = $(addprefix $(AMDDALPATH)/dc/resource/dcn42/,$(RESOURCE_DCN42))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN42)
+
+# FPU Compile Flags for FPU files
+resource_ccflags := $(CC_FLAGS_FPU)
+resource_rcflags := $(CC_FLAGS_NO_FPU)
+
+CFLAGS_$(AMDDALPATH)/dc/resource/dcn42/dcn42_resource_fpu.o := $(resource_ccflags)
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/resource/dcn42/dcn42_resource_fpu.o := $(resource_rcflags)
+
+###############################################################################
endif
+
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 7/7] drm/amd/display: Enable dcn42 in DM
2026-02-12 1:09 [PATCH 0/7] Patch set to support dcn42 Roman.Li
` (3 preceding siblings ...)
2026-02-12 1:09 ` [PATCH 6/7] drm/amd/display: Enable dcn42 DC Roman.Li
@ 2026-02-12 1:09 ` Roman.Li
4 siblings, 0 replies; 6+ messages in thread
From: Roman.Li @ 2026-02-12 1:09 UTC (permalink / raw)
To: amd-gfx
Cc: Alex Deucher, Harry Wentland, Pratik Vishwakarma,
Aurabindo Pillai, Ivan Lipski, Alex Hung, Roman Li
From: Roman Li <Roman.Li@amd.com>
Add support for DCN 4.2 in Display Manager
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 41 ++++++++++++++++---
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 +-
2 files changed, 37 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 12bebdfd7fdc..024a502fbc58 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
- * Copyright 2015 Advanced Micro Devices, Inc.
+ * Copyright 2015-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -152,6 +152,9 @@ MODULE_FIRMWARE(FIRMWARE_DCN_36_DMUB);
#define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin"
MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB);
+#define FIRMWARE_DCN_42_DMUB "amdgpu/dcn_4_2_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_DCN_42_DMUB);
+
/**
* DOC: overview
*
@@ -1365,6 +1368,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
case IP_VERSION(3, 5, 0):
case IP_VERSION(3, 5, 1):
case IP_VERSION(3, 6, 0):
+ case IP_VERSION(4, 2, 0):
hw_params.ips_sequential_ono = adev->external_rev_id > 0x10;
hw_params.lower_hbr3_phy_ssc = true;
break;
@@ -1812,6 +1816,9 @@ static void *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *adev)
case IP_VERSION(4, 0, 1):
bb_size = sizeof(struct dml2_soc_bb);
break;
+ case IP_VERSION(4, 2, 0):
+ bb_size = sizeof(struct dml2_soc_bb);
+ break;
default:
return NULL;
}
@@ -1856,6 +1863,9 @@ static enum dmub_ips_disable_type dm_get_default_ips_mode(
case IP_VERSION(3, 5, 1):
ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
break;
+ case IP_VERSION(4, 2, 0):
+ ret = DMUB_IPS_DISABLE_ALL;
+ break;
default:
/* ASICs older than DCN35 do not have IPSs */
if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 5, 0))
@@ -1999,6 +2009,13 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0))
init_data.num_virtual_links = 1;
+ /* DCN42 and above dpia switch to unified link training path */
+ if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 2, 0)) {
+ init_data.flags.consolidated_dpia_dp_lt = true;
+ init_data.flags.enable_dpia_pre_training = true;
+ init_data.flags.unify_link_enc_assignment = true;
+ init_data.flags.usb4_bw_alloc_support = true;
+ }
retrieve_dmi_info(&adev->dm);
if (adev->dm.edp0_on_dp1_quirk)
init_data.flags.support_edp0_on_dp1 = true;
@@ -2366,6 +2383,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
case IP_VERSION(3, 5, 1):
case IP_VERSION(3, 6, 0):
case IP_VERSION(4, 0, 1):
+ case IP_VERSION(4, 2, 0):
return 0;
default:
break;
@@ -2499,7 +2517,9 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
case IP_VERSION(4, 0, 1):
dmub_asic = DMUB_ASIC_DCN401;
break;
-
+ case IP_VERSION(4, 2, 0):
+ dmub_asic = DMUB_ASIC_DCN42;
+ break;
default:
/* ASIC doesn't support DMUB. */
return 0;
@@ -5533,6 +5553,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
case IP_VERSION(3, 5, 1):
case IP_VERSION(3, 6, 0):
case IP_VERSION(4, 0, 1):
+ case IP_VERSION(4, 2, 0):
if (register_outbox_irq_handlers(dm->adev)) {
drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n");
goto fail;
@@ -5557,6 +5578,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
case IP_VERSION(3, 5, 1):
case IP_VERSION(3, 6, 0):
case IP_VERSION(4, 0, 1):
+ case IP_VERSION(4, 2, 0):
psr_feature_enabled = true;
break;
default:
@@ -5739,6 +5761,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
case IP_VERSION(3, 5, 1):
case IP_VERSION(3, 6, 0):
case IP_VERSION(4, 0, 1):
+ case IP_VERSION(4, 2, 0):
if (dcn10_register_irq_handlers(dm->adev)) {
drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n");
goto fail;
@@ -5887,6 +5910,9 @@ static int dm_init_microcode(struct amdgpu_device *adev)
case IP_VERSION(4, 0, 1):
fw_name_dmub = FIRMWARE_DCN_401_DMUB;
break;
+ case IP_VERSION(4, 2, 0):
+ fw_name_dmub = FIRMWARE_DCN_42_DMUB;
+ break;
default:
/* ASIC doesn't support DMUB. */
return 0;
@@ -6014,6 +6040,7 @@ static int dm_early_init(struct amdgpu_ip_block *ip_block)
case IP_VERSION(3, 5, 1):
case IP_VERSION(3, 6, 0):
case IP_VERSION(4, 0, 1):
+ case IP_VERSION(4, 2, 0):
adev->mode_info.num_crtc = 4;
adev->mode_info.num_hpd = 4;
adev->mode_info.num_dig = 4;
@@ -12304,10 +12331,11 @@ static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev,
int i;
/* Overlay cursor not supported on HW before DCN
- * DCN401 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions
- * as previous DCN generations, so enable native mode on DCN401
+ * DCN401/420 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions
+ * as previous DCN generations, so enable native mode on DCN401/420
*/
- if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) {
+ if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1) ||
+ amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0)) {
*cursor_mode = DM_CURSOR_NATIVE_MODE;
return 0;
}
@@ -12727,7 +12755,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
/* Check if rotation or scaling is enabled on DCN401 */
if ((drm_plane_mask(crtc->cursor) & new_crtc_state->plane_mask) &&
- amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) {
+ (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0) ||
+ amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1))) {
new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor);
is_rotated = new_cursor_state &&
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 4f4b868bd8dd..073710bff012 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT
/*
- * Copyright 2022 Advanced Micro Devices, Inc.
+ * Copyright 2022-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -758,6 +758,7 @@ static int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev, unsig
case AMDGPU_FAMILY_GC_11_0_0:
case AMDGPU_FAMILY_GC_11_0_1:
case AMDGPU_FAMILY_GC_11_5_0:
+ case AMDGPU_FAMILY_GC_11_5_4:
amdgpu_dm_plane_add_gfx11_modifiers(adev, mods, &size, &capacity);
break;
case AMDGPU_FAMILY_GC_12_0_0:
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-02-12 1:11 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2026-02-12 1:09 [PATCH 0/7] Patch set to support dcn42 Roman.Li
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2026-02-12 1:09 ` [PATCH 4/7] drm/amd/display: Add DMUB support for dcn42 Roman.Li
2026-02-12 1:09 ` [PATCH 5/7] drm/amd/display: Enable dcn42 DMUB Roman.Li
2026-02-12 1:09 ` [PATCH 6/7] drm/amd/display: Enable dcn42 DC Roman.Li
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