* [PATCH 01/20] drm/amd/display: Fix refresh rate round up case
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
@ 2026-05-06 4:30 ` James Lin
2026-05-06 4:31 ` [PATCH 02/20] drm/amd/display: Fix white screen on boot with OLED panel James Lin
` (19 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:30 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, ChunTao Tso, Robin Chen,
James Lin
From: ChunTao Tso <ChunTao.Tso@amd.com>
[Why & How]
fix refresh rate round up case
Reviewed-by: Robin Chen <robin.chen@amd.com>
Signed-off-by: ChunTao Tso <ChunTao.Tso@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
drivers/gpu/drm/amd/display/modules/power/power_helpers.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index f8b763db9b8c..f55c15199fb4 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -993,8 +993,8 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,
void set_replay_frame_skip_number(struct dc_link *link,
enum replay_coasting_vtotal_type type,
- uint32_t coasting_vtotal_refresh_rate_mhz,
- uint32_t flicker_free_refresh_rate_mhz,
+ uint32_t coasting_vtotal_refresh_rate_uhz,
+ uint32_t flicker_free_refresh_rate_uhz,
bool is_defer)
{
uint32_t *frame_skip_number_array = NULL;
@@ -1006,7 +1006,7 @@ void set_replay_frame_skip_number(struct dc_link *link,
if (false == link->replay_settings.config.frame_skip_supported)
return;
- if (flicker_free_refresh_rate_mhz == 0 || coasting_vtotal_refresh_rate_mhz == 0)
+ if (flicker_free_refresh_rate_uhz == 0 || coasting_vtotal_refresh_rate_uhz == 0)
return;
if (is_defer)
@@ -1017,7 +1017,7 @@ void set_replay_frame_skip_number(struct dc_link *link,
if (frame_skip_number_array == NULL)
return;
- frame_skip_number = coasting_vtotal_refresh_rate_mhz / flicker_free_refresh_rate_mhz;
+ frame_skip_number = (coasting_vtotal_refresh_rate_uhz + 500000) / flicker_free_refresh_rate_uhz;
if (frame_skip_number >= 1)
frame_skip_number_array[type] = frame_skip_number - 1;
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 02/20] drm/amd/display: Fix white screen on boot with OLED panel
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
2026-05-06 4:30 ` [PATCH 01/20] drm/amd/display: Fix refresh rate round up case James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 03/20] drm/amd/display: Fix CRC open failure during active rendering James Lin
` (18 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Ray Wu, James Lin
From: Ray Wu <ray.wu@amd.com>
[Why]
During mode change, replay_event_general_ui may remain set on the old
stream while replay_event_hw_programming is set. This can re-enable
Replay too early before hardware programming is complete.
[How]
Clear replay_event_general_ui in the mode-change path when setting
replay_event_hw_programming to keep Replay blocked until programming
finishes, avoiding white screen on OLED panels after boot.
Reviewed-by: Sunpeng Li <sunpeng.li@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e42a5eecdf46..7ff1af3528dd 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -10086,8 +10086,6 @@ static void amdgpu_dm_enable_self_refresh(struct amdgpu_display_manager *dm,
amdgpu_dm_psr_set_event(dm, acrtc_state->stream, false,
psr_event_hw_programming, false);
- amdgpu_dm_replay_set_event(dm, acrtc_state->stream, true,
- replay_event_general_ui, true);
amdgpu_dm_replay_set_event(dm, acrtc_state->stream, false,
replay_event_hw_programming, false);
}
@@ -10616,6 +10614,8 @@ static void amdgpu_dm_mod_power_update_streams(struct drm_atomic_state *state,
psr_event_hw_programming, true);
amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, true,
replay_event_hw_programming, true);
+ amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, false,
+ replay_event_general_ui, false);
}
}
@@ -10669,6 +10669,18 @@ static void amdgpu_dm_mod_power_setup_streams(struct drm_atomic_state *state,
mod_power_notify_mode_change(dm->power_module,
dm_new_crtc_state->stream,
false);
+
+ /*
+ * Block PSR / Replay on the new stream until display settles post-modeset.
+ * These events will be cleared by amdgpu_dm_enable_self_refresh() once
+ * allow_sr_entry becomes true.
+ */
+ amdgpu_dm_psr_set_event(dm, dm_new_crtc_state->stream, true,
+ psr_event_hw_programming, true);
+
+ amdgpu_dm_replay_set_event(dm, dm_new_crtc_state->stream, true,
+ replay_event_hw_programming | replay_event_general_ui,
+ true);
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 03/20] drm/amd/display: Fix CRC open failure during active rendering
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
2026-05-06 4:30 ` [PATCH 01/20] drm/amd/display: Fix refresh rate round up case James Lin
2026-05-06 4:31 ` [PATCH 02/20] drm/amd/display: Fix white screen on boot with OLED panel James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 04/20] drm/amd/display: Fix signed/unsigned comparison mismatches James Lin
` (17 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Ray Wu, James Lin
From: Tom Chung <chiahsuan.chung@amd.com>
[Why]
Opening the CRC data file during active rendering can fail with -EINVAL.
The wait for commit->hw_done returns remaining jiffies on success, but
the CRC path was treating that as an error.
[How]
Handle wait_for_completion_interruptible_timeout() correctly:
positive return as success, 0 as timeout, and negative as error.
Reviewed-by: Ray Wu <ray.wu@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index 2663593aa35c..e9834d7b6534 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -613,8 +613,13 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
*/
ret = wait_for_completion_interruptible_timeout(
&commit->hw_done, 10 * HZ);
- if (ret)
+ if (ret < 0)
+ goto cleanup;
+
+ if (ret == 0) {
+ ret = -ETIMEDOUT;
goto cleanup;
+ }
}
enable = amdgpu_dm_is_valid_crc_source(source);
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 04/20] drm/amd/display: Fix signed/unsigned comparison mismatches
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (2 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 03/20] drm/amd/display: Fix CRC open failure during active rendering James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 05/20] drm/amd/display: Fix compiler warnings in dml2 James Lin
` (16 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Gaghik Khachatrian,
Dillon Varone, James Lin
From: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
[Why]
Address signed/unsigned comparison warnings in DC paths
to keep builds warning-clean and improve type safety at comparison boundaries.
Most warnings came from signed loop/index temporaries compared against unsigned
counters (for example pipe_count, num_states, and resource-cap counters), plus a
small number of mixed signed/unsigned checks in writeback and clock-related assertions.
[How]
Aligned iterator and temporary variable types with the semantic type of the compared
bounds. Used unsigned indices for loops bounded by unsigned counters, and retained signed
types where values are semantically signed (for example arithmetic with sentinel or signed
intermediate values). Where mixed signed/unsigned comparisons are intentional, applied
explicit boundary casts or split assertions (for example non-negative signed-cap
checks before unsigned comparisons) instead of broad type changes.
No functional behavior changes are intended; this is a warning-resolution and
type-alignment cleanup.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +-
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 +-
.../amd/display/dc/dml/dcn301/dcn301_fpu.c | 2 +-
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 8 ++-
.../dc/resource/dce100/dce100_resource.c | 10 +--
.../dc/resource/dce110/dce110_resource.c | 8 +--
.../dc/resource/dce112/dce112_resource.c | 4 +-
.../dc/resource/dce120/dce120_resource.c | 6 +-
.../dc/resource/dce80/dce80_resource.c | 8 +--
.../dc/resource/dcn10/dcn10_resource.c | 15 ++---
.../dc/resource/dcn20/dcn20_resource.c | 60 +++++++++---------
.../dc/resource/dcn21/dcn21_resource.c | 26 ++++----
.../dc/resource/dcn30/dcn30_resource.c | 63 ++++++++++---------
.../dc/resource/dcn301/dcn301_resource.c | 31 ++++-----
.../dc/resource/dcn302/dcn302_resource.c | 22 +++----
.../dc/resource/dcn303/dcn303_resource.c | 22 +++----
.../dc/resource/dcn31/dcn31_resource.c | 30 ++++-----
.../dc/resource/dcn314/dcn314_resource.c | 26 ++++----
.../dc/resource/dcn315/dcn315_resource.c | 37 +++++------
.../dc/resource/dcn316/dcn316_resource.c | 29 ++++-----
.../dc/resource/dcn32/dcn32_resource.c | 25 ++++----
.../resource/dcn32/dcn32_resource_helpers.c | 6 +-
.../dc/resource/dcn321/dcn321_resource.c | 22 +++----
.../dc/resource/dcn35/dcn35_resource.c | 26 ++++----
.../dc/resource/dcn351/dcn351_resource.c | 26 ++++----
.../dc/resource/dcn36/dcn36_resource.c | 26 ++++----
.../dc/resource/dcn401/dcn401_resource.c | 32 +++++-----
.../dc/resource/dcn42/dcn42_resource.c | 40 ++++++------
28 files changed, 317 insertions(+), 301 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 09868145d2de..1e178becf949 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3845,7 +3845,7 @@ static void program_cursor_attributes_sequence(
struct pipe_ctx *pipe_to_program = NULL;
bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);
- for (k = 0; k < dc->res_pool->pipe_count; k++) {
+ for (k = 0; k < (int)dc->res_pool->pipe_count; k++) {
struct pipe_ctx *tmp_pipe = &context->res_ctx.pipe_ctx[k];
if (tmp_pipe->stream != stream)
@@ -3893,7 +3893,7 @@ static void program_cursor_position_sequence(
struct pipe_ctx *pipe_to_program = NULL;
bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);
- for (k = 0; k < dc->res_pool->pipe_count; k++) {
+ for (k = 0; k < (int)dc->res_pool->pipe_count; k++) {
struct pipe_ctx *tmp_pipe = &context->res_ctx.pipe_ctx[k];
if (tmp_pipe->stream != stream ||
@@ -4083,7 +4083,7 @@ static void commit_planes_do_stream_update_sequence(struct dc *dc,
*num_steps = 0; // Initialize to 0
// Stream updates
- for (j = 0; j < dc->res_pool->pipe_count; j++) {
+ for (j = 0; j < (int)dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_ctx->stream == stream) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index fac5a50fefb2..71710d96ffe3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -2217,7 +2217,7 @@ static void calculate_wm_set_for_vlevel(int vlevel,
{
double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
- ASSERT(vlevel < dml->soc.num_states);
+ ASSERT(vlevel < (int)dml->soc.num_states);
/* only pipe 0 is read for voltage and dcf/soc clocks */
pipes[0].clks_cfg.voltage = vlevel;
pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
index 81ef95f51d05..c4b73acd7140 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
@@ -298,7 +298,7 @@ static void calculate_wm_set_for_vlevel(int vlevel,
{
double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
- ASSERT(vlevel < dml->soc.num_states);
+ ASSERT(vlevel < (int)dml->soc.num_states);
/* only pipe 0 is read for voltage and dcf/soc clocks */
pipes[0].clks_cfg.voltage = vlevel;
pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index a2c8d4b21ac3..3c70d685ba65 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -262,7 +262,7 @@ static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,
struct dc *dc = pipe_ctx->stream->ctx->dc;
struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
bool result = false;
- int acquired_rmu = 0;
+ uint32_t acquired_rmu = 0;
int mpcc_id_projected = 0;
const struct pwl_params *shaper_lut = NULL;
@@ -439,7 +439,7 @@ static void dcn30_set_writeback(
ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
ASSERT(wb_info->wb_enabled);
ASSERT(wb_info->mpcc_inst >= 0);
- ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count);
+ ASSERT(wb_info->mpcc_inst < (int)dc->res_pool->mpcc_count);
mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
mcif_buf_params = &wb_info->mcif_buf_params;
@@ -593,7 +593,9 @@ void dcn30_program_all_writeback_pipes_in_tree(
}
ASSERT(stream_status);
- ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb);
+ // Assert non-negative signed capacity first.
+ ASSERT(dc->res_pool->res_cap->num_dwb >= 0);
+ ASSERT(stream->num_wb_info <= (unsigned int)dc->res_pool->res_cap->num_dwb);
/* For each writeback pipe */
for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) {
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
index 48e48363eb89..28055e571445 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
@@ -805,7 +805,7 @@ static void dce100_resource_destruct(struct dce110_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -870,7 +870,7 @@ enum dc_status dce100_validate_bandwidth(
enum dc_validate_mode validate_mode)
{
(void)validate_mode;
- int i;
+ unsigned int i;
bool at_least_one_pipe = false;
struct dc_stream_state *stream = NULL;
const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000);
@@ -979,7 +979,7 @@ struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link(
const struct resource_pool *pool,
struct dc_stream_state *stream)
{
- int i;
+ unsigned int i;
int j = -1;
struct dc_link *link = stream->link;
enum engine_id preferred_engine = link->link_enc->preferred_engine;
@@ -996,7 +996,7 @@ struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link(
/* Store first available for MST second display
* in daisy chain use case
*/
- j = i;
+ j = (int)i;
if (pool->stream_enc[i]->id == preferred_engine)
return pool->stream_enc[i];
}
@@ -1176,7 +1176,7 @@ static bool dce100_resource_construct(
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
index 0138868e198b..060af765c7ed 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
@@ -840,7 +840,7 @@ static void dce110_resource_destruct(struct dce110_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1214,7 +1214,7 @@ struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link(
const struct resource_pool *pool,
struct dc_stream_state *stream)
{
- int i;
+ unsigned int i;
int j = -1;
struct dc_link *link = stream->link;
@@ -1224,7 +1224,7 @@ struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link(
/* Store first available for MST second display
* in daisy chain use case
*/
- j = i;
+ j = (int)i;
if (pool->stream_enc[i]->id ==
link->link_enc->preferred_engine)
return pool->stream_enc[i];
@@ -1497,7 +1497,7 @@ static bool dce110_resource_construct(
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce110_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
index 1dd5e44a0d6e..ad0214d99a45 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
@@ -805,7 +805,7 @@ static void dce112_resource_destruct(struct dce110_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1383,7 +1383,7 @@ static bool dce112_resource_construct(
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
index 06d4a6918bbb..5b0a8453b747 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
@@ -627,7 +627,7 @@ static void dce120_resource_destruct(struct dce110_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -929,7 +929,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
struct dm_pp_clock_levels_with_latency eng_clks = {0};
struct dm_pp_clock_levels_with_latency mem_clks = {0};
struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
- int i;
+ unsigned int i;
unsigned int clk;
unsigned int latency;
/*original logic in dal3*/
@@ -1229,7 +1229,7 @@ static bool dce120_resource_construct(
j++;
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
index 22d6ad298a3b..d8881c9cfc31 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
@@ -855,7 +855,7 @@ static void dce80_resource_destruct(struct dce110_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1059,7 +1059,7 @@ static bool dce80_construct(
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -1259,7 +1259,7 @@ static bool dce81_construct(
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -1457,7 +1457,7 @@ static bool dce83_construct(
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
index b7bd7344065b..214461f5d2f2 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
@@ -978,7 +978,7 @@ static void dcn10_resource_destruct(struct dcn10_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
kfree(pool->base.hw_i2cs[i]);
@@ -1183,7 +1183,8 @@ static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_st
{
if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
&& caps->max_video_width != 0
- && plane_state->src_rect.width > caps->max_video_width)
+ && plane_state->src_rect.width > 0
+ && (unsigned int)plane_state->src_rect.width > caps->max_video_width)
return DC_FAIL_SURFACE_VALIDATE;
return DC_OK;
@@ -1268,7 +1269,7 @@ struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
const struct resource_pool *pool,
struct dc_stream_state *stream)
{
- int i;
+ unsigned int i;
int j = -1;
struct dc_link *link = stream->link;
@@ -1280,7 +1281,7 @@ struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
*/
if (pool->stream_enc[i]->id != ENGINE_ID_VIRTUAL)
- j = i;
+ j = (int)i;
if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id ==
link->link_enc->preferred_engine)
@@ -1342,7 +1343,7 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
{
- int i;
+ unsigned int i;
if (clks->num_levels == 0)
return false;
@@ -1360,7 +1361,7 @@ static bool dcn10_resource_construct(
struct dc *dc,
struct dcn10_resource_pool *pool)
{
- int i;
+ unsigned int i;
int j;
struct dc_context *ctx = dc->ctx;
uint32_t pipe_fuses = read_pipe_fuses(ctx);
@@ -1655,7 +1656,7 @@ static bool dcn10_resource_construct(
j++;
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
index 038798808e52..2cfe69708bf6 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
@@ -1120,7 +1120,7 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
@@ -1156,7 +1156,7 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1169,19 +1169,19 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
@@ -1415,7 +1415,7 @@ enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
struct dc_stream_state *dc_stream)
{
enum dc_status result = DC_OK;
- int i;
+ unsigned int i;
/* Get a DSC if required and available */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -1636,7 +1636,8 @@ void dcn20_set_mcif_arb_params(
{
enum mmhubbub_wbif_mode wbif_mode;
struct mcif_arb_params *wb_arb_params;
- int i, j, dwb_pipe;
+ int j, dwb_pipe;
+ unsigned int i;
/* Writeback MCIF_WB arbitration parameters */
dwb_pipe = 0;
@@ -1680,7 +1681,7 @@ void dcn20_set_mcif_arb_params(
bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
{
- int i;
+ unsigned int i;
/* Validate DSC config, dsc count validation is already done */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -1797,7 +1798,7 @@ void dcn20_merge_pipes_for_validate(
struct dc *dc,
struct dc_state *context)
{
- int i;
+ unsigned int i;
/* merge previously split odm pipes since mode support needs to make the decision */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -1864,7 +1865,8 @@ int dcn20_validate_apply_pipe_split_flags(
int *split,
bool *merge)
{
- int i, pipe_idx, vlevel_split;
+ unsigned int i;
+ int pipe_idx, vlevel_split;
int plane_count = 0;
bool force_split = false;
bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;
@@ -1897,7 +1899,7 @@ int dcn20_validate_apply_pipe_split_flags(
(!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
++plane_count;
}
- if (plane_count > dc->res_pool->pipe_count / 2)
+ if ((unsigned int)plane_count > dc->res_pool->pipe_count / 2)
avoid_split = true;
/* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */
@@ -1923,12 +1925,12 @@ int dcn20_validate_apply_pipe_split_flags(
if (!context->res_ctx.pipe_ctx[i].stream)
continue;
- for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
+ for (vlevel_split = vlevel; (unsigned int)vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
v->ModeSupport[vlevel][0])
break;
/* Impossible to not split this pipe */
- if (vlevel > context->bw_ctx.dml.soc.num_states)
+ if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states)
vlevel = vlevel_split;
else
max_mpc_comb = 0;
@@ -2064,7 +2066,8 @@ bool dcn20_fast_validate_bw(
bool out = false;
int split[MAX_PIPES] = { 0 };
bool merge[MAX_PIPES] = { false };
- int pipe_cnt, i, pipe_idx, vlevel;
+ int pipe_cnt, pipe_idx, vlevel;
+ unsigned int i;
ASSERT(pipes);
if (!pipes)
@@ -2083,7 +2086,7 @@ bool dcn20_fast_validate_bw(
vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
- if (vlevel > context->bw_ctx.dml.soc.num_states)
+ if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states)
goto validate_fail;
vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
@@ -2288,7 +2291,7 @@ static const struct resource_funcs dcn20_res_pool_funcs = {
bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -2311,7 +2314,7 @@ bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
ASSERT(pipe_count > 0);
@@ -2570,7 +2573,7 @@ static bool dcn20_resource_construct(
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; (unsigned int)i < pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
@@ -2618,12 +2621,12 @@ static bool dcn20_resource_construct(
if (!dc->debug.disable_pplib_wm_range) {
struct pp_smu_wm_range_sets ranges = {0};
- int i = 0;
+ int j = 0;
ranges.num_reader_wm_sets = 0;
if (loaded_bb->num_states == 1) {
- ranges.reader_wm_sets[0].wm_inst = (uint8_t)i;
+ ranges.reader_wm_sets[0].wm_inst = (uint8_t)j;
ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
@@ -2631,15 +2634,14 @@ static bool dcn20_resource_construct(
ranges.num_reader_wm_sets = 1;
} else if (loaded_bb->num_states > 1) {
- for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
- ranges.reader_wm_sets[i].wm_inst = (uint8_t)i;
- ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
- ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+ for (j = 0; j < 4 && (unsigned int)j < loaded_bb->num_states; j++) {
+ ranges.reader_wm_sets[j].wm_inst = (uint8_t)j;
+ ranges.reader_wm_sets[j].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+ ranges.reader_wm_sets[j].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
DC_FP_START();
- dcn20_fpu_set_wm_ranges(i, &ranges, loaded_bb);
+ dcn20_fpu_set_wm_ranges(j, &ranges, loaded_bb);
DC_FP_END();
-
- ranges.num_reader_wm_sets = i + 1;
+ ranges.num_reader_wm_sets = j + 1;
}
ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
@@ -2665,7 +2667,7 @@ static bool dcn20_resource_construct(
goto create_fail;
/* mem input -> ipp -> dpp -> opp -> TG */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; (unsigned int)i < pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -2793,7 +2795,7 @@ static bool dcn20_resource_construct(
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; (unsigned int)i < dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 2;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
index 775cfa901f08..0ee386c3bc23 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
@@ -684,7 +684,7 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
@@ -719,7 +719,7 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
dal_irq_service_destroy(&pool->base.irqs);
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -732,19 +732,19 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
@@ -804,7 +804,8 @@ bool dcn21_fast_validate_bw(struct dc *dc,
bool out = false;
int split[MAX_PIPES] = { 0 };
bool merge[MAX_PIPES] = { false };
- int pipe_cnt, i, pipe_idx, vlevel;
+ int pipe_cnt, pipe_idx, vlevel;
+ unsigned int i;
ASSERT(pipes);
if (!pipes)
@@ -829,7 +830,7 @@ bool dcn21_fast_validate_bw(struct dc *dc,
dm_allow_self_refresh_and_mclk_switch;
vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
- if (vlevel > context->bw_ctx.dml.soc.num_states) {
+ if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states) {
if (allow_self_refresh_only) {
/*
@@ -842,7 +843,7 @@ bool dcn21_fast_validate_bw(struct dc *dc,
context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
dm_allow_self_refresh;
vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
- if (vlevel > context->bw_ctx.dml.soc.num_states)
+ if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states)
goto validate_fail;
} else {
goto validate_fail;
@@ -1428,7 +1429,8 @@ static bool dcn21_resource_construct(
struct dc *dc,
struct dcn21_resource_pool *pool)
{
- int i, j;
+ unsigned int i;
+ int j;
struct dc_context *ctx = dc->ctx;
struct irq_service_init_data init_data;
uint32_t pipe_fuses = read_pipe_fuses(ctx);
@@ -1660,7 +1662,7 @@ static bool dcn21_resource_construct(
j++;
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -1704,11 +1706,11 @@ static bool dcn21_resource_construct(
goto create_fail;
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
if (pool->base.dscs[i] == NULL) {
BREAK_TO_DEBUGGER();
- dm_error("DC: failed to create display stream compressor %d!\n", i);
+ dm_error("DC: failed to create display stream compressor %u!\n", i);
goto create_fail;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
index baefddd03438..e49728cb41d9 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
@@ -1113,7 +1113,7 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
@@ -1149,7 +1149,7 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1162,19 +1162,19 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
@@ -1197,7 +1197,7 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
@@ -1252,7 +1252,7 @@ static struct hubp *dcn30_hubp_create(
static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1277,7 +1277,7 @@ static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool
static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1359,7 +1359,8 @@ int dcn30_populate_dml_pipes_from_context(
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt;
+ int pipe_cnt;
+ unsigned int i;
struct resource_context *res_ctx = &context->res_ctx;
DC_FP_START();
@@ -1417,7 +1418,8 @@ void dcn30_set_mcif_arb_params(
enum mmhubbub_wbif_mode wbif_mode;
struct display_mode_lib *dml = &context->bw_ctx.dml;
struct mcif_arb_params *wb_arb_params;
- int i, j, dwb_pipe;
+ int j, dwb_pipe;
+ unsigned int i;
/* Writeback MCIF_WB arbitration parameters */
dwb_pipe = 0;
@@ -1673,7 +1675,8 @@ noinline bool dcn30_internal_validate_bw(
int split[MAX_PIPES] = { 0 };
bool merge[MAX_PIPES] = { false };
bool newly_split[MAX_PIPES] = { false };
- int pipe_cnt, i, pipe_idx, vlevel = 0;
+ unsigned int i;
+ int pipe_cnt, pipe_idx, vlevel = 0;
struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
ASSERT(pipes);
@@ -1705,7 +1708,7 @@ noinline bool dcn30_internal_validate_bw(
dm_allow_self_refresh_and_mclk_switch;
vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
/* This may adjust vlevel and maxMpcComb */
- if (vlevel < context->bw_ctx.dml.soc.num_states)
+ if ((unsigned int)vlevel < context->bw_ctx.dml.soc.num_states)
vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
}
if (allow_self_refresh_only &&
@@ -1723,7 +1726,7 @@ noinline bool dcn30_internal_validate_bw(
dm_allow_self_refresh;
vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
- if (vlevel < context->bw_ctx.dml.soc.num_states) {
+ if ((unsigned int)vlevel < context->bw_ctx.dml.soc.num_states) {
memset(split, 0, sizeof(split));
memset(merge, 0, sizeof(merge));
vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
@@ -2163,13 +2166,13 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
if (bw_params->clk_table.entries[0].memclk_mhz) {
for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
- if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz)
+ if (bw_params->clk_table.entries[i].dcfclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz)
dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
- if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz)
+ if (bw_params->clk_table.entries[i].dispclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dispclk_mhz)
dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
- if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz)
+ if (bw_params->clk_table.entries[i].dppclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dppclk_mhz)
dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
- if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz)
+ if (bw_params->clk_table.entries[i].phyclk_mhz > (unsigned int)dcn30_bb_max_clk.max_phyclk_mhz)
dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
}
@@ -2177,14 +2180,14 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
dcn30_fpu_update_max_clk(&dcn30_bb_max_clk);
DC_FP_END();
- if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+ if ((unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz;
num_dcfclk_sta_targets++;
- } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+ } else if ((unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
for (i = 0; i < num_dcfclk_sta_targets; i++) {
- if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) {
+ if (dcfclk_sta_targets[i] > (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) {
dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz;
break;
}
@@ -2236,7 +2239,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
} else {
- if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
+ if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) {
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
} else {
@@ -2251,7 +2254,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
}
while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
- optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
+ optimal_dcfclk_for_uclk[j] <= (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) {
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
}
@@ -2311,7 +2314,7 @@ static bool dcn30_resource_construct(
struct dc *dc,
struct dcn30_resource_pool *pool)
{
- int i;
+ unsigned int i;
struct dc_context *ctx = dc->ctx;
struct irq_service_init_data init_data;
struct ddc_service_init_data ddc_init_data = {0};
@@ -2533,7 +2536,7 @@ static bool dcn30_resource_construct(
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
pool->base.opps[i] = dcn30_opp_create(ctx, i);
if (pool->base.opps[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -2543,7 +2546,7 @@ static bool dcn30_resource_construct(
}
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
pool->base.timing_generators[i] = dcn30_timing_generator_create(
ctx, i);
if (pool->base.timing_generators[i] == NULL) {
@@ -2563,13 +2566,13 @@ static bool dcn30_resource_construct(
}
/* ABM */
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
pool->base.multiple_abms[i] = dmub_abm_create(ctx,
&abm_regs[i],
&abm_shift,
&abm_mask);
if (pool->base.multiple_abms[i] == NULL) {
- dm_error("DC: failed to create abm for pipe %d!\n", i);
+ dm_error("DC: failed to create abm for pipe %u!\n", i);
BREAK_TO_DEBUGGER();
goto create_fail;
}
@@ -2582,11 +2585,11 @@ static bool dcn30_resource_construct(
goto create_fail;
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
if (pool->base.dscs[i] == NULL) {
BREAK_TO_DEBUGGER();
- dm_error("DC: failed to create display stream compressor %d!\n", i);
+ dm_error("DC: failed to create display stream compressor %u!\n", i);
goto create_fail;
}
}
@@ -2605,7 +2608,7 @@ static bool dcn30_resource_construct(
}
/* AUX and I2C */
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
index 625d9ec713a9..69890c26a8b1 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
@@ -1084,7 +1084,7 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
@@ -1120,7 +1120,7 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1133,19 +1133,19 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
@@ -1168,7 +1168,7 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
@@ -1184,7 +1184,7 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool)
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
@@ -1212,7 +1212,7 @@ static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst)
static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1237,7 +1237,7 @@ static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *poo
static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1448,7 +1448,8 @@ static bool dcn301_resource_construct(
struct dc *dc,
struct dcn301_resource_pool *pool)
{
- int i, j;
+ int j;
+ unsigned int i;
struct dc_context *ctx = dc->ctx;
struct irq_service_init_data init_data;
uint32_t pipe_fuses = read_pipe_fuses(ctx);
@@ -1680,13 +1681,13 @@ static bool dcn301_resource_construct(
/* ABM (or ABMs for NV2x) */
/* TODO: */
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
pool->base.multiple_abms[i] = dmub_abm_create(ctx,
&abm_regs[i],
&abm_shift,
&abm_mask);
if (pool->base.multiple_abms[i] == NULL) {
- dm_error("DC: failed to create abm for pipe %d!\n", i);
+ dm_error("DC: failed to create abm for pipe %u!\n", i);
BREAK_TO_DEBUGGER();
goto create_fail;
}
@@ -1700,11 +1701,11 @@ static bool dcn301_resource_construct(
goto create_fail;
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
pool->base.dscs[i] = dcn301_dsc_create(ctx, i);
if (pool->base.dscs[i] == NULL) {
BREAK_TO_DEBUGGER();
- dm_error("DC: failed to create display stream compressor %d!\n", i);
+ dm_error("DC: failed to create display stream compressor %u!\n", i);
goto create_fail;
}
}
@@ -1723,7 +1724,7 @@ static bool dcn301_resource_construct(
}
/* AUX and I2C */
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dcn301_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
index 6f380363033a..db7de6036408 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
@@ -738,7 +738,7 @@ static const struct dcn30_dwbc_mask dwbc30_mask = {
static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -773,7 +773,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1036,7 +1036,7 @@ static void dcn302_resource_destruct(struct resource_pool *pool)
}
}
- for (i = 0; i < pool->res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_dsc; i++) {
if (pool->dscs[i] != NULL)
dcn20_dsc_destroy(&pool->dscs[i]);
}
@@ -1071,7 +1071,7 @@ static void dcn302_resource_destruct(struct resource_pool *pool)
dal_irq_service_destroy(&pool->irqs);
}
- for (i = 0; i < pool->res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_ddc; i++) {
if (pool->engines[i] != NULL)
dce110_engine_destroy(&pool->engines[i]);
if (pool->hw_i2cs[i] != NULL) {
@@ -1084,19 +1084,19 @@ static void dcn302_resource_destruct(struct resource_pool *pool)
}
}
- for (i = 0; i < pool->res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_opp; i++) {
if (pool->opps[i] != NULL)
pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
}
- for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_timing_generator; i++) {
if (pool->timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
pool->timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_dwb; i++) {
if (pool->dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->dwbc[i]));
pool->dwbc[i] = NULL;
@@ -1120,7 +1120,7 @@ static void dcn302_resource_destruct(struct resource_pool *pool)
if (pool->dp_clock_source != NULL)
dcn20_clock_source_destroy(&pool->dp_clock_source);
- for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_mpc_3dlut; i++) {
if (pool->mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->mpc_lut[i]);
pool->mpc_lut[i] = NULL;
@@ -1371,7 +1371,7 @@ static bool dcn302_resource_construct(
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->clk_src_count; i++) {
+ for (i = 0; i < (int)pool->clk_src_count; i++) {
if (pool->clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
@@ -1416,7 +1416,7 @@ static bool dcn302_resource_construct(
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->pipe_count; i++) {
+ for (i = 0; i < (int)pool->pipe_count; i++) {
pool->hubps[i] = dcn302_hubp_create(ctx, i);
if (pool->hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -1526,7 +1526,7 @@ static bool dcn302_resource_construct(
dc->caps.max_planes = pool->pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
index 8a7f62ab98b5..fc7353451e8f 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
@@ -699,7 +699,7 @@ static const struct dcn30_dwbc_mask dwbc30_mask = {
static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -734,7 +734,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -980,7 +980,7 @@ static void dcn303_resource_destruct(struct resource_pool *pool)
}
}
- for (i = 0; i < pool->res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_dsc; i++) {
if (pool->dscs[i] != NULL)
dcn20_dsc_destroy(&pool->dscs[i]);
}
@@ -1015,7 +1015,7 @@ static void dcn303_resource_destruct(struct resource_pool *pool)
dal_irq_service_destroy(&pool->irqs);
}
- for (i = 0; i < pool->res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_ddc; i++) {
if (pool->engines[i] != NULL)
dce110_engine_destroy(&pool->engines[i]);
if (pool->hw_i2cs[i] != NULL) {
@@ -1028,19 +1028,19 @@ static void dcn303_resource_destruct(struct resource_pool *pool)
}
}
- for (i = 0; i < pool->res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_opp; i++) {
if (pool->opps[i] != NULL)
pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
}
- for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_timing_generator; i++) {
if (pool->timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
pool->timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_dwb; i++) {
if (pool->dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->dwbc[i]));
pool->dwbc[i] = NULL;
@@ -1064,7 +1064,7 @@ static void dcn303_resource_destruct(struct resource_pool *pool)
if (pool->dp_clock_source != NULL)
dcn20_clock_source_destroy(&pool->dp_clock_source);
- for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->res_cap->num_mpc_3dlut; i++) {
if (pool->mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->mpc_lut[i]);
pool->mpc_lut[i] = NULL;
@@ -1303,7 +1303,7 @@ static bool dcn303_resource_construct(
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->clk_src_count; i++) {
+ for (i = 0; i < (int)pool->clk_src_count; i++) {
if (pool->clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
@@ -1348,7 +1348,7 @@ static bool dcn303_resource_construct(
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->pipe_count; i++) {
+ for (i = 0; i < (int)pool->pipe_count; i++) {
pool->hubps[i] = dcn303_hubp_create(ctx, i);
if (pool->hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -1458,7 +1458,7 @@ static bool dcn303_resource_construct(
dc->caps.max_planes = pool->pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
index 200be0f46ab0..5925c40da6ee 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
@@ -1148,7 +1148,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal(
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
@@ -1414,7 +1414,7 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
@@ -1448,7 +1448,7 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1461,19 +1461,19 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
@@ -1496,7 +1496,7 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
@@ -1512,7 +1512,7 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
@@ -1548,7 +1548,7 @@ static struct hubp *dcn31_hubp_create(
static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1573,7 +1573,7 @@ static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool
static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1655,7 +1655,7 @@ int dcn31x_populate_dml_pipes_from_context(struct dc *dc,
enum dc_validate_mode validate_mode)
{
uint32_t pipe_cnt;
- int i;
+ unsigned int i;
dc_assert_fp_enabled();
@@ -1679,7 +1679,7 @@ int dcn31_populate_dml_pipes_from_context(
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt;
+ unsigned int i, pipe_cnt;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = 0;
bool upscaled = false;
@@ -2080,7 +2080,7 @@ static bool dcn31_resource_construct(
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
@@ -2119,7 +2119,7 @@ static bool dcn31_resource_construct(
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; i < (int)pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -2256,7 +2256,7 @@ static bool dcn31_resource_construct(
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
index 6a4094663050..16eee0c6f4bc 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
@@ -1206,7 +1206,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal(
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
@@ -1473,7 +1473,7 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
@@ -1506,7 +1506,7 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)
dal_irq_service_destroy(&pool->base.irqs);
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1519,19 +1519,19 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
@@ -1554,7 +1554,7 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
@@ -1570,7 +1570,7 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
@@ -1606,7 +1606,7 @@ static struct hubp *dcn31_hubp_create(
static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1631,7 +1631,7 @@ static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool
static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -2000,7 +2000,7 @@ static bool dcn314_resource_construct(
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
@@ -2037,7 +2037,7 @@ static bool dcn314_resource_construct(
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; i < (int)pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -2167,7 +2167,7 @@ static bool dcn314_resource_construct(
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
index 76b112426f33..37404aa0edd9 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
@@ -1147,7 +1147,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal(
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
@@ -1415,7 +1415,7 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
@@ -1449,7 +1449,7 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1462,19 +1462,19 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
@@ -1497,7 +1497,7 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
@@ -1513,7 +1513,7 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool)
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
@@ -1549,7 +1549,7 @@ static struct hubp *dcn31_hubp_create(
static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1574,7 +1574,7 @@ static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool
static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1670,7 +1670,7 @@ static int source_format_to_bpp (enum source_format_class SourcePixelFormat)
static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context)
{
- int i;
+ unsigned int i;
struct resource_context *res_ctx = &context->res_ctx;
/* Only apply for dual stream scenarios with edp*/
@@ -1703,7 +1703,8 @@ static int dcn315_populate_dml_pipes_from_context(
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt, crb_idx, crb_pipes;
+ unsigned int i;
+ int pipe_cnt, crb_idx, crb_pipes;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = NULL;
const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB;
@@ -1743,7 +1744,7 @@ static int dcn315_populate_dml_pipes_from_context(
if (approx_det_segs_required_for_pstate <= 2 * DCN3_15_MAX_DET_SEGS) {
bool split_required = approx_det_segs_required_for_pstate > DCN3_15_MAX_DET_SEGS;
- split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc);
+ split_required = split_required || (unsigned int)timing->pix_clk_100hz >= (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc);
split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);
/* Minimum 2 segments to allow mpc/odm combine if its used later */
@@ -1792,7 +1793,7 @@ static int dcn315_populate_dml_pipes_from_context(
continue;
}
- bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)
+ bool split_required = (unsigned int)pipe->stream->timing.pix_clk_100hz >= (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)
|| (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);
if (remaining_det_segs > MIN_RESERVED_DET_SEGS && crb_pipes != 0)
@@ -1829,7 +1830,7 @@ static int dcn315_populate_dml_pipes_from_context(
(max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB;
} else if (!is_dual_plane(pipe->plane_state->format)
&& pipe->plane_state->src_rect.width <= 5120
- && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {
+ && (unsigned int)pipe->stream->timing.pix_clk_100hz < (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {
/* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
pipes[0].pipe.src.unbounded_req_mode = true;
@@ -2030,7 +2031,7 @@ static bool dcn315_resource_construct(
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
@@ -2069,7 +2070,7 @@ static bool dcn315_resource_construct(
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; i < (int)pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -2196,7 +2197,7 @@ static bool dcn315_resource_construct(
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
index 2d34db42dd83..d946663f416a 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
@@ -1140,7 +1140,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal(
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
@@ -1410,7 +1410,7 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
@@ -1444,7 +1444,7 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1457,19 +1457,19 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
@@ -1492,7 +1492,7 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
@@ -1508,7 +1508,7 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool)
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
@@ -1541,7 +1541,7 @@ static struct hubp *dcn31_hubp_create(
static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1566,7 +1566,7 @@ static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool
static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1648,7 +1648,8 @@ static int dcn316_populate_dml_pipes_from_context(
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt;
+ unsigned int i;
+ int pipe_cnt;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = 0;
const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB;
@@ -1904,7 +1905,7 @@ static bool dcn316_resource_construct(
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
@@ -1943,7 +1944,7 @@ static bool dcn316_resource_construct(
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; i < (int)pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -2062,7 +2063,7 @@ static bool dcn316_resource_construct(
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index 6f0a3b0ff2d3..28d21dd30106 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -1421,7 +1421,7 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
@@ -1451,7 +1451,7 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1464,19 +1464,19 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
@@ -1499,7 +1499,7 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
@@ -1515,7 +1515,7 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
@@ -1541,7 +1541,7 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t dwb_count = pool->res_cap->num_dwb;
for (i = 0; i < dwb_count; i++) {
@@ -1570,7 +1570,7 @@ static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool
static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t dwb_count = pool->res_cap->num_dwb;
for (i = 0; i < dwb_count; i++) {
@@ -1906,7 +1906,8 @@ int dcn32_populate_dml_pipes_from_context(
display_e2e_pipe_params_st *pipes,
enum dc_validate_mode validate_mode)
{
- int i, pipe_cnt;
+ unsigned int i;
+ int pipe_cnt;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = NULL;
bool subvp_in_use = false;
@@ -2380,7 +2381,7 @@ static bool dcn32_resource_construct(
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
@@ -2550,7 +2551,7 @@ static bool dcn32_resource_construct(
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
index b2eac83ef02c..602a0e4e5dc0 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
@@ -382,7 +382,8 @@ void dcn32_determine_det_override(struct dc *dc,
void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes)
{
- int i, pipe_cnt;
+ unsigned int i;
+ int pipe_cnt;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = 0;
bool disable_unbounded_requesting = dc->debug.disable_z9_mpc || dc->debug.disable_unbounded_requesting;
@@ -751,7 +752,8 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int
void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes)
{
- int i, pipe_cnt;
+ unsigned int i;
+ int pipe_cnt;
struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe = NULL;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
index 663e9335fdec..296558258672 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
@@ -1402,7 +1402,7 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
@@ -1431,7 +1431,7 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)
dal_irq_service_destroy(&pool->base.irqs);
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1444,19 +1444,19 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
@@ -1479,7 +1479,7 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
@@ -1495,7 +1495,7 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
@@ -1521,7 +1521,7 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)
static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t dwb_count = pool->res_cap->num_dwb;
for (i = 0; i < dwb_count; i++) {
@@ -1550,7 +1550,7 @@ static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *poo
static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t dwb_count = pool->res_cap->num_dwb;
for (i = 0; i < dwb_count; i++) {
@@ -1879,7 +1879,7 @@ static bool dcn321_resource_construct(
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
@@ -2044,7 +2044,7 @@ static bool dcn321_resource_construct(
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 27f8f13912b3..c7fba9f39e19 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -1154,7 +1154,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal(
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
@@ -1484,7 +1484,7 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
@@ -1514,7 +1514,7 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1527,19 +1527,19 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
@@ -1562,7 +1562,7 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
@@ -1578,7 +1578,7 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool)
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
@@ -1635,7 +1635,7 @@ static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1674,7 +1674,7 @@ static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -2040,7 +2040,7 @@ static bool dcn35_resource_construct(
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
@@ -2092,7 +2092,7 @@ static bool dcn35_resource_construct(
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; i < (int)pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -2224,7 +2224,7 @@ static bool dcn35_resource_construct(
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index d032db65108b..e9fc43abf342 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -1134,7 +1134,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal(
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
@@ -1464,7 +1464,7 @@ static void dcn351_resource_destruct(struct dcn351_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
@@ -1494,7 +1494,7 @@ static void dcn351_resource_destruct(struct dcn351_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1507,19 +1507,19 @@ static void dcn351_resource_destruct(struct dcn351_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
@@ -1542,7 +1542,7 @@ static void dcn351_resource_destruct(struct dcn351_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
@@ -1558,7 +1558,7 @@ static void dcn351_resource_destruct(struct dcn351_resource_pool *pool)
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
@@ -1615,7 +1615,7 @@ static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1654,7 +1654,7 @@ static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -2012,7 +2012,7 @@ static bool dcn351_resource_construct(
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
@@ -2064,7 +2064,7 @@ static bool dcn351_resource_construct(
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; i < (int)pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -2196,7 +2196,7 @@ static bool dcn351_resource_construct(
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
index 42fa8883d1b7..eb597be989a6 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
@@ -1141,7 +1141,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal(
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
@@ -1471,7 +1471,7 @@ static void dcn36_resource_destruct(struct dcn36_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn20_dsc_destroy(&pool->base.dscs[i]);
}
@@ -1501,7 +1501,7 @@ static void dcn36_resource_destruct(struct dcn36_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1514,19 +1514,19 @@ static void dcn36_resource_destruct(struct dcn36_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
@@ -1549,7 +1549,7 @@ static void dcn36_resource_destruct(struct dcn36_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
@@ -1565,7 +1565,7 @@ static void dcn36_resource_destruct(struct dcn36_resource_pool *pool)
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
@@ -1622,7 +1622,7 @@ static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1661,7 +1661,7 @@ static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -2010,7 +2010,7 @@ static bool dcn36_resource_construct(
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
@@ -2062,7 +2062,7 @@ static bool dcn36_resource_construct(
}
/* HUBPs, DPPs, OPPs and TGs */
- for (i = 0; i < pool->base.pipe_count; i++) {
+ for (i = 0; i < (int)pool->base.pipe_count; i++) {
pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
if (pool->base.hubps[i] == NULL) {
BREAK_TO_DEBUGGER();
@@ -2194,7 +2194,7 @@ static bool dcn36_resource_construct(
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index 6aa051154f5e..9498cbff2449 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -1427,7 +1427,7 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn401_dsc_destroy(&pool->base.dscs[i]);
}
@@ -1457,7 +1457,7 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1470,19 +1470,19 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
@@ -1505,7 +1505,7 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
@@ -1521,7 +1521,7 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool)
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
@@ -1547,7 +1547,7 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool)
static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t dwb_count = pool->res_cap->num_dwb;
for (i = 0; i < dwb_count; i++) {
@@ -1578,7 +1578,7 @@ static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *poo
static bool dcn401_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t dwb_count = pool->res_cap->num_dwb;
for (i = 0; i < dwb_count; i++) {
@@ -1796,11 +1796,11 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
pixel_clk_params->dio_se_pix_per_cycle = 2;
} else if (dc_is_dp_signal(stream->signal)) {
/* round up to nearest power of 2, or max at 8 pixels per cycle */
- if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
+ if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
pixel_clk_params->dio_se_pix_per_cycle = 8;
- } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
+ } else if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
pixel_clk_params->dio_se_pix_per_cycle = 4;
- } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
+ } else if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
pixel_clk_params->dio_se_pix_per_cycle = 2;
} else {
pixel_clk_params->dio_se_pix_per_cycle = 1;
@@ -1810,10 +1810,10 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
int dcn401_get_power_profile(const struct dc_state *context)
{
- int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000;
+ unsigned int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000;
int dpm_level = 0;
- for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {
+ for (unsigned int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {
if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 ||
uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
break;
@@ -2100,7 +2100,7 @@ static bool dcn401_resource_construct(
CLOCK_SOURCE_ID_DP_DTO,
&clk_src_regs[0], true);
- for (i = 0; i < pool->base.clk_src_count; i++) {
+ for (i = 0; i < (int)pool->base.clk_src_count; i++) {
if (pool->base.clock_sources[i] == NULL) {
dm_error("DC: failed to create clock sources!\n");
BREAK_TO_DEBUGGER();
@@ -2262,7 +2262,7 @@ static bool dcn401_resource_construct(
dc->caps.max_planes = pool->base.pipe_count;
- for (i = 0; i < dc->caps.max_planes; ++i)
+ for (i = 0; i < (int)dc->caps.max_planes; ++i)
dc->caps.planes[i] = plane_cap;
dc->caps.max_odm_combine_factor = 4;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
index c013a6483f5d..57c6e81280bc 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
@@ -1416,7 +1416,7 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
if (pool->base.dscs[i] != NULL)
dcn42_dsc_destroy(&pool->base.dscs[i]);
}
@@ -1445,7 +1445,7 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool)
dal_irq_service_destroy(&pool->base.irqs);
}
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
if (pool->base.engines[i] != NULL)
dce110_engine_destroy(&pool->base.engines[i]);
if (pool->base.hw_i2cs[i] != NULL) {
@@ -1458,19 +1458,19 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
if (pool->base.opps[i] != NULL)
pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.timing_generators[i] != NULL) {
kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
pool->base.timing_generators[i] = NULL;
}
}
- for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
if (pool->base.dwbc[i] != NULL) {
kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
pool->base.dwbc[i] = NULL;
@@ -1493,7 +1493,7 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool)
}
}
- for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
if (pool->base.mpc_lut[i] != NULL) {
dc_3dlut_func_release(pool->base.mpc_lut[i]);
pool->base.mpc_lut[i] = NULL;
@@ -1509,7 +1509,7 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool)
pool->base.dp_clock_source = NULL;
}
- for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
if (pool->base.multiple_abms[i] != NULL)
dce_abm_destroy(&pool->base.multiple_abms[i]);
}
@@ -1580,11 +1580,11 @@ static void dcn42_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
pixel_clk_params->dio_se_pix_per_cycle = 2;
} else if (dc_is_dp_signal(stream->signal)) {
/* round up to nearest power of 2, or max at 8 pixels per cycle */
- if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
+ if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
pixel_clk_params->dio_se_pix_per_cycle = 8;
- } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
+ } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
pixel_clk_params->dio_se_pix_per_cycle = 4;
- } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
+ } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
pixel_clk_params->dio_se_pix_per_cycle = 2;
} else {
pixel_clk_params->dio_se_pix_per_cycle = 1;
@@ -1594,7 +1594,7 @@ static void dcn42_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
static bool dcn42_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t dwb_count = pool->res_cap->num_dwb;
for (i = 0; i < dwb_count; i++) {
@@ -1631,7 +1631,7 @@ static void dcn42_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
static bool dcn42_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
- int i;
+ unsigned int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
for (i = 0; i < pipe_count; i++) {
@@ -1753,7 +1753,7 @@ static struct link_encoder *dcn42_link_enc_create_minimal(
{
struct dcn20_link_encoder *enc20;
- if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+ if ((unsigned int)(eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
return NULL;
enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
@@ -1831,7 +1831,7 @@ static bool dcn42_resource_construct(
struct dc *dc,
struct dcn42_resource_pool *pool)
{
- int i, j;
+ unsigned int i, j;
struct dc_context *ctx = dc->ctx;
struct irq_service_init_data init_data;
uint32_t pipe_fuses;
@@ -1867,7 +1867,7 @@ static bool dcn42_resource_construct(
num_pipes = pool->base.res_cap->num_dpp;
pipe_fuses = read_pipe_fuses(ctx);
- for (i = 0; i < pool->base.res_cap->num_dpp; i++)
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dpp; i++)
if (pipe_fuses & 1 << i)
num_pipes--;
@@ -2121,7 +2121,7 @@ static bool dcn42_resource_construct(
}
/* HUBPs, DPPs, OPPs, TGs, ABMs */
- for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+ for (i = 0, j = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
/* if pipe is disabled, skip instance of HW pipe,
* i.e, skip ASIC register instance
*/
@@ -2165,7 +2165,7 @@ static bool dcn42_resource_construct(
&abm_shift,
&abm_mask);
if (pool->base.multiple_abms[j] == NULL) {
- dm_error("DC: failed to create abm for pipe %d!\n", i);
+ dm_error("DC: failed to create abm for pipe %u!\n", i);
BREAK_TO_DEBUGGER();
goto create_fail;
}
@@ -2200,11 +2200,11 @@ static bool dcn42_resource_construct(
}
/* DSCs */
- for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
pool->base.dscs[i] = dcn42_dsc_create(ctx, i);
if (pool->base.dscs[i] == NULL) {
BREAK_TO_DEBUGGER();
- dm_error("DC: failed to create display stream compressor %d!\n", i);
+ dm_error("DC: failed to create display stream compressor %u!\n", i);
goto create_fail;
}
}
@@ -2224,7 +2224,7 @@ static bool dcn42_resource_construct(
}
/* AUX and I2C */
- for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+ for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
pool->base.engines[i] = dcn42_aux_engine_create(ctx, i);
if (pool->base.engines[i] == NULL) {
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 05/20] drm/amd/display: Fix compiler warnings in dml2
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (3 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 04/20] drm/amd/display: Fix signed/unsigned comparison mismatches James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 06/20] drm/amd/display: Fix multiple compiler warnings James Lin
` (15 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Gaghik Khachatrian,
Dillon Varone, James Lin
From: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
[Why & How]
In dml2_translation_helper.c, rename the inner loop index inside
dml2_init_soc_states() for several project cases
to avoid shadowing the outer function-scope index variable.
In display_mode_core.c, replace shift-based power-of-two expressions
used to compute dpte_row_height and dpte_row_height_linear with an
equivalent floating-point power function, consistent with existing
usage elsewhere in the file.
Behavior for valid inputs is preserved in both cases.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
index 16514f1e4ed9..241406e9e85a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
@@ -2626,18 +2626,18 @@ static dml_uint_t CalculateVMAndRowBytes(
*PixelPTEBytesPerRow_one_row_per_frame = (dml_uint_t)((dml_float_t) *dpte_row_width_ub_one_row_per_frame / (dml_float_t) *PixelPTEReqWidth * *PTERequestSize);
if (SurfaceTiling == dml_sw_linear) {
- *dpte_row_height = (dml_uint_t)(dml_min(128, 1 << (dml_uint_t) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)));
+ *dpte_row_height = (dml_uint_t)(dml_min(128, (dml_uint_t)dml_pow(2.0, (int)dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1))));
dml_print("DML::%s: dpte_row_height term 1 = %u\n", __func__, PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch);
dml_print("DML::%s: dpte_row_height term 2 = %f\n", __func__, dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch));
dml_print("DML::%s: dpte_row_height term 3 = %f\n", __func__, dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1));
- dml_print("DML::%s: dpte_row_height term 4 = %u\n", __func__, 1 << (dml_uint_t) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1));
+ dml_print("DML::%s: dpte_row_height term 4 = %u\n", __func__, (dml_uint_t)dml_pow(2.0, (int)dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)));
dml_print("DML::%s: dpte_row_height = %u\n", __func__, *dpte_row_height);
*dpte_row_width_ub = (dml_uint_t)(dml_ceil(((dml_float_t) Pitch * (dml_float_t) *dpte_row_height - 1), (dml_float_t) *PixelPTEReqWidth) + *PixelPTEReqWidth);
*PixelPTEBytesPerRow = (dml_uint_t)((dml_float_t) *dpte_row_width_ub / (dml_float_t) *PixelPTEReqWidth * *PTERequestSize);
// VBA_DELTA, VBA doesn't have programming value for pte row height linear.
- *dpte_row_height_linear = 1 << (dml_uint_t) dml_floor(dml_log2(PTEBufferSizeInRequests * PixelPTEReqWidth_linear / Pitch), 1);
+ *dpte_row_height_linear = (dml_uint_t)dml_pow(2.0, (int)dml_floor(dml_log2(PTEBufferSizeInRequests * PixelPTEReqWidth_linear / Pitch), 1));
if (*dpte_row_height_linear > 128)
*dpte_row_height_linear = 128;
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 06/20] drm/amd/display: Fix multiple compiler warnings
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (4 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 05/20] drm/amd/display: Fix compiler warnings in dml2 James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 07/20] drm/amd/display: Fix warnings James Lin
` (14 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Gaghik Khachatrian,
Dillon Varone, James Lin
From: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
[Why]
Unreachable Code;
Copy Constructor Deleted;
Local Declaration Hides Parameter;
Local Declaration Hides Outer Scope;
Uninitialized or Suspicious Memory Use.
[How]
- Removed or refactored unreachable code paths
- Ensured proper copy constructors in C++ classes
- Renamed local variables that shadowed function parameters
- Renamed inner loop/block variables to avoid shadowing outer scope
Fixed in 8 files across several FPU layers
Also fixed in color_gamma and cs_funcs modules
- Reordered guard conditions to validate pipe type before accessing stream
- Ensures safe memory access patterns in DC DMUB service layer
All changes maintain backward compatibility and preserve functional behavior.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +++---
.../gpu/drm/amd/display/dc/core/dc_state.c | 6 ++--
.../gpu/drm/amd/display/dc/core/dc_stream.c | 4 +--
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 3 +-
.../dc/dml/dcn21/display_mode_vba_21.c | 8 +++---
.../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 4 +--
.../amd/display/dc/dml/dcn314/dcn314_fpu.c | 10 +++----
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 13 +++++----
.../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 10 +++----
.../amd/display/dc/dml/dcn351/dcn351_fpu.c | 10 +++----
.../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 4 +--
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 3 ++
.../amd/display/modules/color/color_gamma.c | 28 +++++++++----------
13 files changed, 57 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1e178becf949..0e9ea06d7297 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -4976,7 +4976,7 @@ static void commit_planes_for_stream(struct dc *dc,
if (!pipe_ctx->top_pipe &&
!pipe_ctx->prev_odm_pipe &&
should_update_pipe_for_stream(context, pipe_ctx, stream)) {
- struct dc_stream_status *stream_status = NULL;
+ struct dc_stream_status *pipe_stream_status = NULL;
if (!pipe_ctx->plane_state)
continue;
@@ -4985,12 +4985,12 @@ static void commit_planes_for_stream(struct dc *dc,
if (update_type == UPDATE_TYPE_FAST)
continue;
- stream_status =
+ pipe_stream_status =
stream_get_status(context, pipe_ctx->stream);
- if (dc->hwss.apply_ctx_for_surface && stream_status)
+ if (dc->hwss.apply_ctx_for_surface && pipe_stream_status)
dc->hwss.apply_ctx_for_surface(
- dc, pipe_ctx->stream, stream_status->plane_count, context);
+ dc, pipe_ctx->stream, pipe_stream_status->plane_count, context);
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index 0cc26f750586..1f183ae85a3f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
@@ -218,13 +218,13 @@ struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *p
}
if (dc->caps.dcmode_power_limits_present) {
- bool status;
+ bool dc_power_status;
DC_FP_START();
- status = dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source);
+ dc_power_status = dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source);
DC_FP_END();
- if (!status) {
+ if (!dc_power_status) {
dc_state_release(state);
return NULL;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 438e6415db6d..d4c32c945606 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -602,7 +602,7 @@ bool dc_stream_add_writeback(struct dc *dc,
if (dc->hwss.enable_writeback) {
struct dc_stream_status *stream_status = dc_stream_get_status(stream);
- struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
+ dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
if (stream_status)
dwb->otg_inst = stream_status->primary_otg_inst;
}
@@ -614,7 +614,7 @@ bool dc_stream_add_writeback(struct dc *dc,
/* enable writeback */
if (dc->hwss.enable_writeback) {
- struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
+ dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
if (dwb->funcs->is_enabled(dwb)) {
/* writeback pipe already enabled, only need to update */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index af487fa0db03..ea0210216d9e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -488,12 +488,11 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru
for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
- if (!resource_is_pipe_type(pipe, OTG_MASTER))
+ if (!resource_is_pipe_type(pipe, OTG_MASTER) || !pipe->stream)
continue;
stream_status = dc_state_get_stream_status(context, pipe->stream);
if (stream_status && stream_status->fpo_in_use) {
- struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
uint8_t min_refresh_in_hz;
min_refresh_in_hz = (uint8_t)((pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index df23ced2ff5a..3ff71751db1e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -4809,14 +4809,14 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = 0.0;
mode_lib->vba.MaximumReadBandwidthWithPrefetch = 0.0;
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
- unsigned int m;
+ unsigned int cursor_idx;
locals->cursor_bw[k] = 0;
locals->cursor_bw_pre[k] = 0;
- for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) {
- locals->cursor_bw[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m]
+ for (cursor_idx = 0; cursor_idx < mode_lib->vba.NumberOfCursors[k]; cursor_idx++) {
+ locals->cursor_bw[k] = mode_lib->vba.CursorWidth[k][cursor_idx] * mode_lib->vba.CursorBPP[k][cursor_idx]
/ 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
- locals->cursor_bw_pre[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m]
+ locals->cursor_bw_pre[k] = mode_lib->vba.CursorWidth[k][cursor_idx] * mode_lib->vba.CursorBPP[k][cursor_idx]
/ 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPreY[i][j][k];
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
index 79c567b6806e..0ba388c6aec1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
@@ -721,9 +721,9 @@ void dcn3_fpu_build_wm_range_table(struct clk_mgr *base)
base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
}
-void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip)
+void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *soc_bb)
{
- (void)dcn3_0_ip;
+ (void)soc_bb;
dc_assert_fp_enabled();
if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
index 29334772408e..2f9ae79da731 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
@@ -410,15 +410,15 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c
context->bw_ctx.dml.ip.odm_combine_4to1_supported = true;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
- if (!pipe->stream)
+ if (!cur_pipe->stream)
continue;
- if (pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine &&
- pipe->stream->apply_seamless_boot_optimization) {
+ if (cur_pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine &&
+ cur_pipe->stream->apply_seamless_boot_optimization) {
- if (pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) {
+ if (cur_pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) {
context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1;
break;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index a97e38aa7fed..03e49d298a85 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -2216,7 +2216,7 @@ bool dcn32_internal_validate_bw(struct dc *dc,
if (repopulate_pipes) {
int flag_max_mpc_comb = vba->maxMpcComb;
int flag_vlevel = vlevel;
- int i;
+ int j;
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);
if (!dc->config.enable_windowed_mpo_odm)
@@ -2231,19 +2231,20 @@ bool dcn32_internal_validate_bw(struct dc *dc,
dm_prefetch_support_uclk_fclk_and_stutter_if_possible;
vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+ const int num_states = (int)context->bw_ctx.dml.soc.num_states;
- if (vlevel == context->bw_ctx.dml.soc.num_states) {
+ if (vlevel == num_states) {
/* failed after DET size changes */
goto validate_fail;
} else if (flag_max_mpc_comb == 0 &&
flag_max_mpc_comb != context->bw_ctx.dml.vba.maxMpcComb) {
/* check the context constructed with pipe split flags is still valid*/
bool flags_valid = false;
- for (i = flag_vlevel; i < (int)context->bw_ctx.dml.soc.num_states; i++) {
- if (vba->ModeSupport[i][flag_max_mpc_comb]) {
+ for (j = flag_vlevel; j < (int)context->bw_ctx.dml.soc.num_states; j++) {
+ if (vba->ModeSupport[j][flag_max_mpc_comb]) {
vba->maxMpcComb = flag_max_mpc_comb;
- vba->VoltageLevel = i;
- vlevel = i;
+ vba->VoltageLevel = j;
+ vlevel = j;
flags_valid = true;
break;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
index bef2b0bcfcf0..c15fbc18bfdf 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
@@ -551,16 +551,16 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,
}
for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
- if (!pipe->stream)
+ if (!cur_pipe->stream)
continue;
- if (pipe->stream->signal == SIGNAL_TYPE_EDP &&
+ if (cur_pipe->stream->signal == SIGNAL_TYPE_EDP &&
dc->debug.seamless_boot_odm_combine &&
- pipe->stream->apply_seamless_boot_optimization) {
+ cur_pipe->stream->apply_seamless_boot_optimization) {
- if (pipe->stream->apply_boot_odm_mode ==
+ if (cur_pipe->stream->apply_boot_odm_mode ==
dm_odm_combine_policy_2to1) {
context->bw_ctx.dml.vba.ODMCombinePolicy =
dm_odm_combine_policy_2to1;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
index 9545d946215b..6552b26de845 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
@@ -583,16 +583,16 @@ int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc,
}
for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
- if (!pipe->stream)
+ if (!cur_pipe->stream)
continue;
- if (pipe->stream->signal == SIGNAL_TYPE_EDP &&
+ if (cur_pipe->stream->signal == SIGNAL_TYPE_EDP &&
dc->debug.seamless_boot_odm_combine &&
- pipe->stream->apply_seamless_boot_optimization) {
+ cur_pipe->stream->apply_seamless_boot_optimization) {
- if (pipe->stream->apply_boot_odm_mode ==
+ if (cur_pipe->stream->apply_boot_odm_mode ==
dm_odm_combine_policy_2to1) {
context->bw_ctx.dml.vba.ODMCombinePolicy =
dm_odm_combine_policy_2to1;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 169f34ea75b1..2c2fa320df40 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -3636,8 +3636,8 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
if (dc->hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied) {
struct dce_hwseq *hwseq = dc->hwseq;
- struct timing_generator *tg = dc->res_pool->timing_generators[0];
- unsigned int cur_frame = tg->funcs->get_frame_count(tg);
+ struct timing_generator *wa_tg = dc->res_pool->timing_generators[0];
+ unsigned int cur_frame = wa_tg->funcs->get_frame_count(wa_tg);
if (cur_frame != hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame) {
struct hubbub *hubbub = dc->res_pool->hubbub;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 55a672b4e886..204f11b784bb 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1952,6 +1952,9 @@ void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx)
* This is meant to work around a known HW issue where VREADY will cancel the pending 3DLUT_ENABLE signal regardless
* of whether OTG lock is currently being held or not.
*/
+ if (!pipe_ctx)
+ return;
+
struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL };
struct pipe_ctx *odm_pipe, *mpc_pipe;
int i, wa_pipe_ct = 0;
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index b79ca7a2eedc..2ac01083de88 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -690,7 +690,7 @@ static bool find_software_points(
static bool build_custom_gamma_mapping_coefficients_worker(
const struct dc_gamma *ramp,
struct pixel_gamma_point *coeff,
- const struct hw_x_point *coordinates_x,
+ const struct hw_x_point *hw_coordinates_x,
const struct gamma_pixel *axis_x,
enum channel_name channel,
uint32_t number_of_points)
@@ -712,11 +712,11 @@ static bool build_custom_gamma_mapping_coefficients_worker(
struct fixed31_32 right_pos;
if (channel == CHANNEL_NAME_RED)
- coord_x = coordinates_x[i].regamma_y_red;
+ coord_x = hw_coordinates_x[i].regamma_y_red;
else if (channel == CHANNEL_NAME_GREEN)
- coord_x = coordinates_x[i].regamma_y_green;
+ coord_x = hw_coordinates_x[i].regamma_y_green;
else
- coord_x = coordinates_x[i].regamma_y_blue;
+ coord_x = hw_coordinates_x[i].regamma_y_blue;
if (!find_software_points(
ramp, axis_x, coord_x, channel,
@@ -1539,11 +1539,11 @@ static void build_evenly_distributed_points(
}
static inline void copy_rgb_regamma_to_coordinates_x(
- struct hw_x_point *coordinates_x,
+ struct hw_x_point *hw_coordinates_x,
uint32_t hw_points_num,
const struct pwl_float_data_ex *rgb_ex)
{
- struct hw_x_point *coords = coordinates_x;
+ struct hw_x_point *coords = hw_coordinates_x;
uint32_t i = 0;
const struct pwl_float_data_ex *rgb_regamma = rgb_ex;
@@ -1562,7 +1562,7 @@ static bool calculate_interpolated_hardware_curve(
const struct dc_gamma *ramp,
struct pixel_gamma_point *coeff128,
struct pwl_float_data *rgb_user,
- const struct hw_x_point *coordinates_x,
+ const struct hw_x_point *hw_coordinates_x,
const struct gamma_pixel *axis_x,
uint32_t number_of_points,
struct dc_transfer_func_distributed_points *tf_pts)
@@ -1575,7 +1575,7 @@ static bool calculate_interpolated_hardware_curve(
for (i = 0; i < 3; i++) {
if (!build_custom_gamma_mapping_coefficients_worker(
- ramp, coeff128, coordinates_x, axis_x, i,
+ ramp, coeff128, hw_coordinates_x, axis_x, i,
number_of_points))
return false;
}
@@ -1789,14 +1789,14 @@ bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps,
if (input_tf->tf == TRANSFER_FUNCTION_PQ) {
/* just copy current rgb_regamma into tf_pts */
struct pwl_float_data_ex *curvePt = curve;
- int i = 0;
+ int j = 0;
- while (i <= MAX_HW_POINTS) {
- tf_pts->red[i] = curvePt->r;
- tf_pts->green[i] = curvePt->g;
- tf_pts->blue[i] = curvePt->b;
+ while (j <= MAX_HW_POINTS) {
+ tf_pts->red[j] = curvePt->r;
+ tf_pts->green[j] = curvePt->g;
+ tf_pts->blue[j] = curvePt->b;
++curvePt;
- ++i;
+ ++j;
}
} else {
// clamps to 0-1
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 07/20] drm/amd/display: Fix warnings
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (5 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 06/20] drm/amd/display: Fix multiple compiler warnings James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 08/20] drm/amd/display: only call pmfw if smu present flags true James Lin
` (13 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Clay King, Dillon Varone,
James Lin
From: Clay King <clayking@amd.com>
[Why & How]
Fix various warnings related to unsigned/signed mismatches
- Consistently use the same signedness for a given value
- Explcitly cast between types when needed
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Clay King <clayking@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
.../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 6 +-
.../display/dc/clk_mgr/dce100/dce_clk_mgr.h | 2 +-
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 8 +-
.../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c | 4 +-
.../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h | 2 +-
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 2 +-
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.h | 4 +-
.../clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c | 4 +-
.../clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h | 2 +-
.../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +-
.../drm/amd/display/dc/core/dc_link_exports.c | 2 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 18 +-
.../drm/amd/display/dc/core/dc_vm_helper.c | 4 +-
drivers/gpu/drm/amd/display/dc/dc.h | 68 +--
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 2 +-
drivers/gpu/drm/amd/display/dc/dc_stream.h | 4 +-
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +-
.../amd/display/dc/dcn21/dcn21_link_encoder.c | 2 +-
.../display/dc/dio/dcn10/dcn10_link_encoder.c | 2 +-
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 4 +-
.../dc/dml/dcn21/display_mode_vba_21.c | 28 +-
.../dc/dml/dcn30/display_mode_vba_30.c | 342 +++++++--------
.../dc/dml/dcn31/display_mode_vba_31.c | 408 +++++++++---------
.../dc/dml/dcn314/display_mode_vba_314.c | 400 ++++++++---------
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +-
.../dc/dml/dcn32/display_mode_vba_util_32.c | 8 +-
.../dc/dml/dcn32/display_mode_vba_util_32.h | 8 +-
.../drm/amd/display/dc/dml/display_mode_vba.h | 12 +-
.../amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c | 2 +-
.../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 2 +-
.../amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c | 4 +-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2 +-
.../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 8 +-
.../drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c | 8 +-
.../amd/display/dc/dsc/dcn401/dcn401_dsc.c | 10 +-
.../amd/display/dc/hubp/dcn401/dcn401_hubp.c | 4 +-
.../amd/display/dc/hubp/dcn401/dcn401_hubp.h | 2 +-
.../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 6 +-
.../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 2 +-
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2 +-
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 4 +-
.../amd/display/dc/inc/hw/timing_generator.h | 8 +-
.../gpu/drm/amd/display/dc/inc/link_service.h | 2 +-
.../gpu/drm/amd/display/dc/inc/reg_helper.h | 72 ++--
.../drm/amd/display/dc/link/link_detection.c | 2 +-
.../drm/amd/display/dc/link/link_detection.h | 2 +-
.../link/protocols/link_edp_panel_control.c | 8 +-
.../drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c | 2 +-
.../drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c | 6 +-
.../drm/amd/display/dc/opp/dcn20/dcn20_opp.c | 2 +-
.../drm/amd/display/dc/opp/dcn20/dcn20_opp.h | 2 +-
.../amd/display/dc/optc/dcn32/dcn32_optc.c | 2 +-
.../gpu/drm/amd/display/include/fixed31_32.h | 6 +-
.../drm/amd/display/modules/hdcp/hdcp_log.c | 2 +-
59 files changed, 769 insertions(+), 767 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index 6d41df52d7c9..808e24f0e88f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -88,7 +88,7 @@ static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
/* ClocksStatePerformance */
{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 } };
-int dentist_get_divider_from_did(int did)
+unsigned int dentist_get_divider_from_did(unsigned int did)
{
if (did < DENTIST_BASE_DID_1)
did = DENTIST_BASE_DID_1;
@@ -155,8 +155,8 @@ static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
- int dprefclk_wdivider;
- int dprefclk_src_sel;
+ uint32_t dprefclk_wdivider;
+ uint32_t dprefclk_src_sel;
int dp_ref_clk_khz;
int target_div;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h
index f6622f58f62e..9ea1b0a9923d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h
@@ -54,6 +54,6 @@ int dce_set_clock(
void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr);
-int dentist_get_divider_from_did(int did);
+unsigned int dentist_get_divider_from_did(unsigned int did);
#endif /* _DCE_CLK_MGR_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index c0abbdd2cf5c..cbd989b6a3df 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -430,8 +430,8 @@ void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base)
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
uint32_t dispclk_wdivider;
uint32_t dppclk_wdivider;
- int disp_divider;
- int dpp_divider;
+ unsigned int disp_divider;
+ unsigned int dpp_divider;
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider);
@@ -534,8 +534,8 @@ void dcn20_clk_mgr_construct(
struct pp_smu_funcs *pp_smu,
struct dccg *dccg)
{
- int dprefclk_did;
- int target_div;
+ unsigned int dprefclk_did;
+ unsigned int target_div;
uint32_t pll_req_reg;
struct fixed31_32 pll_req;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
index 827bc2431d5d..e36233127b15 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
@@ -123,12 +123,12 @@ bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input)
return false;
}
-bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version)
+bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version)
{
smu_print("SMU Get SMU version\n");
if (dcn30_smu_send_msg_with_param(clk_mgr,
- DALSMC_MSG_GetSmuVersion, 0, version)) {
+ DALSMC_MSG_GetSmuVersion, 0, (uint32_t *)version)) {
smu_print("SMU version: %d\n", *version);
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h
index ca9f5296be94..67e93f9cac71 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h
@@ -31,7 +31,7 @@
struct clk_mgr_internal;
bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input);
-bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version);
+bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version);
bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index f78b33076e70..2dc244d5a55f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -475,7 +475,7 @@ static int dcn32_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
uint32_t dispclk_wdivider;
- int disp_divider;
+ unsigned int disp_divider;
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index 2654f4dacee3..7c2b716d5d2a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -1490,7 +1490,7 @@ static int dcn401_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
uint32_t dispclk_wdivider;
- int disp_divider;
+ unsigned int disp_divider;
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
index 97a1ce1e8a9e..370d2ddd6064 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
@@ -17,14 +17,14 @@ union dcn401_clk_mgr_block_sequence_params {
uint32_t ppclk;
uint16_t freq_mhz;
/* outputs */
- uint32_t *response;
+ int *response;
} update_hardmin_params;
struct {
/* inputs */
uint32_t ppclk;
int freq_khz;
/* outputs */
- uint32_t *response;
+ int *response;
} update_hardmin_optimized_params;
struct {
/* inputs */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
index 3a263840893e..82ccd9b407f4 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
@@ -143,12 +143,12 @@ static bool dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mg
return false;
}
-bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version)
+bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version)
{
smu_print("SMU Get SMU version\n");
if (dcn401_smu_send_msg_with_param(clk_mgr,
- DALSMC_MSG_GetSmuVersion, 0, version)) {
+ DALSMC_MSG_GetSmuVersion, 0, (uint32_t *)version)) {
smu_print("SMU version: %d\n", *version);
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
index 4f5ac603e822..1addbed1cb99 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h
@@ -10,7 +10,7 @@
struct clk_mgr_internal;
-bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version);
+bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version);
bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
index 41729426d08c..245a217894a7 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
@@ -879,7 +879,7 @@ int dcn42_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
(void)clk_mgr_base;
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
uint32_t dispclk_wdivider;
- int disp_divider;
+ unsigned int disp_divider;
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0e9ea06d7297..842a8b11b17a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -7006,7 +7006,7 @@ bool dc_can_clear_cursor_limit(const struct dc *dc)
return false;
}
-void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst,
+void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst,
struct dc_underflow_debug_data *out_data)
{
struct timing_generator *tg = NULL;
@@ -7024,7 +7024,7 @@ void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst,
dc->hwss.get_underflow_debug_data(dc, tg, out_data);
}
-void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst,
+void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst,
struct power_features *out_data)
{
(void)primary_otg_inst;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
index f4e99ca7918f..5ac5ad86bd01 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
@@ -282,7 +282,7 @@ unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link)
struct dc_sink *dc_link_add_remote_sink(
struct dc_link *link,
const uint8_t *edid,
- int len,
+ unsigned int len,
struct dc_sink_init_data *init_data)
{
return link->dc->link_srv->add_remote_sink(link, edid, len, init_data);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index ad377a991451..f57e9d85563e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -982,7 +982,7 @@ static struct rect calculate_mpc_slice_in_timing_active(
}
static void calculate_adjust_recout_for_visual_confirm(struct pipe_ctx *pipe_ctx,
- int *base_offset, int *dpp_offset)
+ unsigned int *base_offset, unsigned int *dpp_offset)
{
struct dc *dc = pipe_ctx->stream->ctx->dc;
*base_offset = 0;
@@ -1004,7 +1004,7 @@ static void calculate_adjust_recout_for_visual_confirm(struct pipe_ctx *pipe_ctx
static void reverse_adjust_recout_for_visual_confirm(struct rect *recout,
struct pipe_ctx *pipe_ctx)
{
- int dpp_offset, base_offset;
+ unsigned int dpp_offset, base_offset;
calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset,
&dpp_offset);
@@ -1015,7 +1015,7 @@ static void reverse_adjust_recout_for_visual_confirm(struct rect *recout,
static void adjust_recout_for_visual_confirm(struct rect *recout,
struct pipe_ctx *pipe_ctx)
{
- int dpp_offset, base_offset;
+ unsigned int dpp_offset, base_offset;
calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset,
&dpp_offset);
@@ -1692,7 +1692,7 @@ bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
struct pipe_ctx *test_pipe, *split_pipe;
struct rect r1 = pipe_ctx->plane_res.scl_data.recout;
int r1_right, r1_bottom;
- int cur_layer = pipe_ctx->plane_state->layer_index;
+ unsigned int cur_layer = pipe_ctx->plane_state->layer_index;
reverse_adjust_recout_for_visual_confirm(&r1, pipe_ctx);
r1_right = r1.x + r1.width;
@@ -4103,9 +4103,9 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
static bool planes_changed_for_existing_stream(struct dc_state *context,
struct dc_stream_state *stream,
const struct dc_validation_set set[],
- int set_count)
+ unsigned int set_count)
{
- int i, j;
+ unsigned int i, j;
struct dc_stream_status *stream_status = NULL;
for (i = 0; i < context->stream_count; i++) {
@@ -4141,10 +4141,10 @@ static bool add_all_planes_for_stream(
const struct dc *dc,
struct dc_stream_state *stream,
const struct dc_validation_set set[],
- int set_count,
+ unsigned int set_count,
struct dc_state *state)
{
- int i, j;
+ unsigned int i, j;
for (i = 0; i < set_count; i++)
if (set[i].stream == stream)
@@ -4182,7 +4182,7 @@ static bool add_all_planes_for_stream(
*/
enum dc_status dc_validate_with_context(struct dc *dc,
const struct dc_validation_set set[],
- int set_count,
+ unsigned int set_count,
struct dc_state *context,
enum dc_validate_mode validate_mode)
{
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
index d1e68dc57a2a..3743555133f6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
@@ -34,9 +34,9 @@ void vm_helper_mark_vmid_used(struct vm_helper *vm_helper, unsigned int pos, uin
vmids.vmid_usage[1] = 1 << pos;
}
-int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config)
+unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config)
{
- int num_vmids = 0;
+ unsigned int num_vmids = 0;
/* Call HWSS to setup HUBBUB for address config */
if (dc->hwss.init_sys_ctx) {
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 9bd4b0bb47df..e5933e3a8206 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -540,7 +540,7 @@ struct dc_config {
bool use_default_clock_table;
bool force_bios_enable_lttpr;
uint8_t force_bios_fixed_vs;
- int sdpif_request_limit_words_per_umc;
+ unsigned int sdpif_request_limit_words_per_umc;
bool dc_mode_clk_limit_support;
bool EnableMinDispClkODM;
bool enable_auto_dpm_test_logs;
@@ -944,20 +944,20 @@ struct dc_virtual_addr_space_config {
};
struct dc_bounding_box_overrides {
- int sr_exit_time_ns;
- int sr_enter_plus_exit_time_ns;
- int sr_exit_z8_time_ns;
- int sr_enter_plus_exit_z8_time_ns;
- int urgent_latency_ns;
- int percent_of_ideal_drambw;
- int dram_clock_change_latency_ns;
- int dummy_clock_change_latency_ns;
- int fclk_clock_change_latency_ns;
+ unsigned int sr_exit_time_ns;
+ unsigned int sr_enter_plus_exit_time_ns;
+ unsigned int sr_exit_z8_time_ns;
+ unsigned int sr_enter_plus_exit_z8_time_ns;
+ unsigned int urgent_latency_ns;
+ unsigned int percent_of_ideal_drambw;
+ unsigned int dram_clock_change_latency_ns;
+ unsigned int dummy_clock_change_latency_ns;
+ unsigned int fclk_clock_change_latency_ns;
/* This forces a hard min on the DCFCLK we use
* for DML. Unlike the debug option for forcing
* DCFCLK, this override affects watermark calculations
*/
- int min_dcfclk_mhz;
+ unsigned int min_dcfclk_mhz;
};
struct dc_qos_info {
@@ -990,7 +990,7 @@ struct link_service;
struct dc_debug_options {
bool disable_dsc;
enum visual_confirm visual_confirm;
- int visual_confirm_rect_height;
+ unsigned int visual_confirm_rect_height;
bool sanity_checks;
bool max_disp_clk;
@@ -1026,23 +1026,23 @@ struct dc_debug_options {
bool disable_io_clk_power_gate;
bool disable_mem_power_gate;
bool disable_dio_power_gate;
- int dsc_min_slice_height_override;
- int dsc_bpp_increment_div;
+ unsigned int dsc_min_slice_height_override;
+ unsigned int dsc_bpp_increment_div;
bool disable_pplib_wm_range;
enum wm_report_mode pplib_wm_report_mode;
unsigned int min_disp_clk_khz;
unsigned int min_dpp_clk_khz;
unsigned int min_dram_clk_khz;
- int sr_exit_time_dpm0_ns;
- int sr_enter_plus_exit_time_dpm0_ns;
- int sr_exit_time_ns;
- int sr_enter_plus_exit_time_ns;
- int sr_exit_z8_time_ns;
- int sr_enter_plus_exit_z8_time_ns;
- int urgent_latency_ns;
+ unsigned int sr_exit_time_dpm0_ns;
+ unsigned int sr_enter_plus_exit_time_dpm0_ns;
+ unsigned int sr_exit_time_ns;
+ unsigned int sr_enter_plus_exit_time_ns;
+ unsigned int sr_exit_z8_time_ns;
+ unsigned int sr_enter_plus_exit_z8_time_ns;
+ unsigned int urgent_latency_ns;
uint32_t underflow_assert_delay_us;
- int percent_of_ideal_drambw;
- int dram_clock_change_latency_ns;
+ unsigned int percent_of_ideal_drambw;
+ unsigned int dram_clock_change_latency_ns;
bool optimized_watermark;
int always_scale;
bool disable_pplib_clock_request;
@@ -1067,8 +1067,8 @@ struct dc_debug_options {
uint8_t seamless_boot_odm_combine;
uint8_t force_odm_combine_4to1; //bit vector based on otg inst
- int minimum_z8_residency_time;
- int minimum_z10_residency_time;
+ unsigned int minimum_z8_residency_time;
+ unsigned int minimum_z10_residency_time;
bool disable_z9_mpc;
unsigned int force_fclk_khz;
bool enable_tri_buf;
@@ -1117,7 +1117,7 @@ struct dc_debug_options {
uint8_t fec_enable_delay_in100us;
bool enable_driver_sequence_debug;
enum det_size crb_alloc_policy;
- int crb_alloc_policy_min_disp_count;
+ unsigned int crb_alloc_policy_min_disp_count;
bool disable_z10;
bool enable_z9_disable_interface;
bool psr_skip_crtc_disable;
@@ -1291,7 +1291,7 @@ void dc_hardware_init(struct dc *dc);
int dc_get_vmid_use_vector(struct dc *dc);
void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
/* Returns the number of vmids supported */
-int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
+unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
void dc_init_callbacks(struct dc *dc,
const struct dc_callback_init *init_params);
void dc_deinit_callbacks(struct dc *dc);
@@ -1520,7 +1520,7 @@ struct dc_plane_state {
bool visible;
bool flip_immediate;
bool horizontal_mirror;
- int layer_index;
+ unsigned int layer_index;
union surface_update_flags update_flags;
bool flip_int_enabled;
@@ -1550,7 +1550,7 @@ struct dc_plane_state {
struct dc_csc_transform cursor_csc_color_matrix;
bool adaptive_sharpness_en;
int adaptive_sharpness_policy;
- int sharpness_level;
+ unsigned int sharpness_level;
enum linear_light_scaling linear_light_scaling;
unsigned int sdr_white_level_nits;
struct cm_hist_control cm_hist_control;
@@ -1573,7 +1573,7 @@ struct dc_plane_info {
bool global_alpha;
int global_alpha_value;
bool input_csc_enabled;
- int layer_index;
+ unsigned int layer_index;
enum chroma_cositing cositing;
};
@@ -1965,7 +1965,7 @@ enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *pla
enum dc_status dc_validate_with_context(struct dc *dc,
const struct dc_validation_set set[],
- int set_count,
+ unsigned int set_count,
struct dc_state *context,
enum dc_validate_mode validate_mode);
@@ -2072,7 +2072,7 @@ struct dc_sink_init_data;
struct dc_sink *dc_link_add_remote_sink(
struct dc_link *dc_link,
const uint8_t *edid,
- int len,
+ unsigned int len,
struct dc_sink_init_data *init_data);
/* Remove remote sink from a link with dc_connection_mst_branch connection type.
@@ -2869,9 +2869,9 @@ bool dc_can_clear_cursor_limit(const struct dc *dc);
* including OTG underflow status, current read positions, frame count, and per-HUBP debug data.
* The results are stored in the provided out_data structure for further analysis or logging.
*/
-void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data);
+void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data);
-void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst, struct power_features *out_data);
+void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst, struct power_features *out_data);
/*
* Software state variables used to program register fields across the display pipeline
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index 101bce6b8de6..7cb34e2b44a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -92,7 +92,7 @@ uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,
uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps(
const struct dc_crtc_timing *timing,
- const int num_slices_h,
+ const uint32_t num_slices_h,
const bool is_dp);
void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc,
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 32f7c7c076c8..1649fbab08aa 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -159,8 +159,8 @@ struct luminance_data {
int luminance_millinits[LUMINANCE_DATA_TABLE_SIZE];
int flicker_criteria_milli_nits_GAMING;
int flicker_criteria_milli_nits_STATIC;
- int nominal_refresh_rate;
- int dm_max_decrease_from_nominal;
+ unsigned int nominal_refresh_rate;
+ unsigned int dm_max_decrease_from_nominal;
};
enum dc_drr_trigger_mode {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 12ce4a059231..3ec49f4e277f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -917,7 +917,7 @@ struct dsc_dec_dpcd_caps {
union dsc_slice_caps2 slice_caps2;
int32_t lb_bit_depth;
bool is_block_pred_supported;
- int32_t edp_max_bits_per_pixel; /* Valid only in eDP */
+ uint32_t edp_max_bits_per_pixel; /* Valid only in eDP */
union dsc_color_formats color_formats;
union dsc_color_depth color_depth;
int32_t throughput_mode_0_mps; /* In MPs */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
index 36456c9971c8..fcaa3884d705 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
@@ -205,7 +205,7 @@ static bool update_cfg_data(
static bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc)
{
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
- int value;
+ uint32_t value;
if (enc->features.flags.bits.DP_IS_USB_C) {
REG_GET(RDPCSTX_PHY_CNTL6,
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
index 872ea3646023..59b68422334d 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
@@ -450,7 +450,7 @@ static uint8_t get_frontend_source(
unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
{
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
- int32_t value;
+ uint32_t value;
enum engine_id result;
REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 71710d96ffe3..ed7c989a5b13 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1105,7 +1105,7 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc
}
static void dcn20_adjust_freesync_v_startup(
- const struct dc_crtc_timing *dc_crtc_timing, int *vstartup_start)
+ const struct dc_crtc_timing *dc_crtc_timing, unsigned int *vstartup_start)
{
struct dc_crtc_timing patched_crtc_timing;
uint32_t asic_blank_end = 0;
@@ -1253,7 +1253,7 @@ void dcn20_calculate_dlg_params(struct dc *dc,
static void swizzle_to_dml_params(
enum swizzle_mode_values swizzle,
- unsigned int *sw_mode)
+ int *sw_mode)
{
switch (swizzle) {
case DC_SW_LINEAR:
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index 3ff71751db1e..961b705acfa9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -296,7 +296,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
double UrgentOutOfOrderReturn,
double ReturnBW,
bool GPUVMEnable,
- int dpte_group_bytes[],
+ unsigned int dpte_group_bytes[],
unsigned int MetaChunkSize,
double UrgentLatency,
double ExtraLatency,
@@ -307,7 +307,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
double SRExitTime,
double SREnterPlusExitTime,
double DCFCLKDeepSleep,
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
bool DCCEnable[],
double DPPCLK[],
double SwathWidthSingleDPPY[],
@@ -346,7 +346,7 @@ static void CalculateDCFCLKDeepSleep(
double BytePerPixelDETC[],
double VRatio[],
double SwathWidthY[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double HRatio[],
double PixelClock[],
double PSCL_THROUGHPUT[],
@@ -390,7 +390,7 @@ static void CalculatePixelDeliveryTimes(
double VRatioPrefetchC[],
unsigned int swath_width_luma_ub[],
unsigned int swath_width_chroma_ub[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double HRatio[],
double PixelClock[],
double PSCL_THROUGHPUT[],
@@ -436,7 +436,7 @@ static void CalculateMetaAndPTETimes(
unsigned int meta_row_height[],
unsigned int meta_req_width[],
unsigned int meta_req_height[],
- int dpte_group_bytes[],
+ unsigned int dpte_group_bytes[],
unsigned int PTERequestSizeY[],
unsigned int PTERequestSizeC[],
unsigned int PixelPTEReqWidthY[],
@@ -477,8 +477,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
int HostVMMaxPageTableLevels,
@@ -5257,7 +5257,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
double UrgentOutOfOrderReturn,
double ReturnBW,
bool GPUVMEnable,
- int dpte_group_bytes[],
+ unsigned int dpte_group_bytes[],
unsigned int MetaChunkSize,
double UrgentLatency,
double ExtraLatency,
@@ -5268,7 +5268,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
double SRExitTime,
double SREnterPlusExitTime,
double DCFCLKDeepSleep,
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
bool DCCEnable[],
double DPPCLK[],
double SwathWidthSingleDPPY[],
@@ -5543,7 +5543,7 @@ static void CalculateDCFCLKDeepSleep(
double BytePerPixelDETC[],
double VRatio[],
double SwathWidthY[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double HRatio[],
double PixelClock[],
double PSCL_THROUGHPUT[],
@@ -5749,7 +5749,7 @@ static void CalculatePixelDeliveryTimes(
double VRatioPrefetchC[],
unsigned int swath_width_luma_ub[],
unsigned int swath_width_chroma_ub[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double HRatio[],
double PixelClock[],
double PSCL_THROUGHPUT[],
@@ -5870,7 +5870,7 @@ static void CalculateMetaAndPTETimes(
unsigned int meta_row_height[],
unsigned int meta_req_width[],
unsigned int meta_req_height[],
- int dpte_group_bytes[],
+ unsigned int dpte_group_bytes[],
unsigned int PTERequestSizeY[],
unsigned int PTERequestSizeC[],
unsigned int PixelPTEReqWidthY[],
@@ -6126,8 +6126,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
int HostVMMaxPageTableLevels,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 3c9040117cc4..f0b1bfb408f6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -285,8 +285,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
static void CalculateDCFCLKDeepSleep(
struct display_mode_lib *mode_lib,
unsigned int NumberOfActivePlanes,
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
double VRatio[],
double VRatioChroma[],
double SwathWidthY[],
@@ -327,7 +327,7 @@ static void CalculateUrgentBurstFactor(
static void UseMinimumDCFCLK(
struct display_mode_lib *mode_lib,
struct vba_vars_st *v,
- int MaxPrefetchMode,
+ unsigned int MaxPrefetchMode,
int ReorderingBytes);
static void CalculatePixelDeliveryTimes(
@@ -345,7 +345,7 @@ static void CalculatePixelDeliveryTimes(
double PSCL_THROUGHPUT[],
double PSCL_THROUGHPUT_CHROMA[],
double DPPCLK[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
unsigned int NumberOfCursors[],
unsigned int CursorWidth[][2],
@@ -370,35 +370,35 @@ static void CalculateMetaAndPTETimes(
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
- int HTotal[],
+ unsigned int HTotal[],
double VRatio[],
double VRatioChroma[],
double DestinationLinesToRequestRowInVBlank[],
double DestinationLinesToRequestRowInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
- int dpte_row_height[],
- int dpte_row_height_chroma[],
- int meta_row_width[],
- int meta_row_width_chroma[],
- int meta_row_height[],
- int meta_row_height_chroma[],
- int meta_req_width[],
- int meta_req_width_chroma[],
- int meta_req_height[],
- int meta_req_height_chroma[],
- int dpte_group_bytes[],
- int PTERequestSizeY[],
- int PTERequestSizeC[],
- int PixelPTEReqWidthY[],
- int PixelPTEReqHeightY[],
- int PixelPTEReqWidthC[],
- int PixelPTEReqHeightC[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
+ unsigned int dpte_row_height[],
+ unsigned int dpte_row_height_chroma[],
+ unsigned int meta_row_width[],
+ unsigned int meta_row_width_chroma[],
+ unsigned int meta_row_height[],
+ unsigned int meta_row_height_chroma[],
+ unsigned int meta_req_width[],
+ unsigned int meta_req_width_chroma[],
+ unsigned int meta_req_height[],
+ unsigned int meta_req_height_chroma[],
+ unsigned int dpte_group_bytes[],
+ unsigned int PTERequestSizeY[],
+ unsigned int PTERequestSizeC[],
+ unsigned int PixelPTEReqWidthY[],
+ unsigned int PixelPTEReqHeightY[],
+ unsigned int PixelPTEReqWidthC[],
+ unsigned int PixelPTEReqHeightC[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
double DST_Y_PER_PTE_ROW_NOM_L[],
double DST_Y_PER_PTE_ROW_NOM_C[],
double DST_Y_PER_META_ROW_NOM_L[],
@@ -421,18 +421,18 @@ static void CalculateVMGroupAndRequestTimes(
bool GPUVMEnable,
unsigned int GPUVMMaxPageTableLevels,
unsigned int HTotal[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
double DestinationLinesToRequestVMInVBlank[],
double DestinationLinesToRequestVMInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
- int vm_group_bytes[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
+ unsigned int vm_group_bytes[],
unsigned int dpde0_bytes_per_frame_ub_l[],
unsigned int dpde0_bytes_per_frame_ub_c[],
- int meta_pte_bytes_per_frame_ub_l[],
- int meta_pte_bytes_per_frame_ub_c[],
+ unsigned int meta_pte_bytes_per_frame_ub_l[],
+ unsigned int meta_pte_bytes_per_frame_ub_c[],
double TimePerVMGroupVBlank[],
double TimePerVMGroupFlip[],
double TimePerVMRequestVBlank[],
@@ -446,27 +446,27 @@ static void CalculateStutterEfficiency(
double ReturnBW,
double SRExitTime,
bool SynchronizedVBlank,
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
unsigned int DETBufferSizeY[],
- int BytePerPixelY[],
+ unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
double SwathWidthY[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
double DCCRateLuma[],
double DCCRateChroma[],
- int HTotal[],
- int VTotal[],
+ unsigned int HTotal[],
+ unsigned int VTotal[],
double PixelClock[],
double VRatio[],
enum scan_direction_class SourceScan[],
- int BlockHeight256BytesY[],
- int BlockWidth256BytesY[],
- int BlockHeight256BytesC[],
- int BlockWidth256BytesC[],
- int DCCYMaxUncompressedBlock[],
- int DCCCMaxUncompressedBlock[],
- int VActive[],
+ unsigned int BlockHeight256BytesY[],
+ unsigned int BlockWidth256BytesY[],
+ unsigned int BlockHeight256BytesC[],
+ unsigned int BlockWidth256BytesC[],
+ unsigned int DCCYMaxUncompressedBlock[],
+ unsigned int DCCCMaxUncompressedBlock[],
+ unsigned int VActive[],
bool DCCEnable[],
bool WritebackEnable[],
double ReadBandwidthPlaneLuma[],
@@ -486,32 +486,32 @@ static void CalculateSwathAndDETConfiguration(
enum scan_direction_class SourceScan[],
enum source_format_class SourcePixelFormat[],
enum dm_swizzle_mode SurfaceTiling[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BlendingAndTiming[],
- int BytePerPixY[],
- int BytePerPixC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
double BytePerPixDETY[],
double BytePerPixDETC[],
- int HActive[],
+ unsigned int HActive[],
double HRatio[],
double HRatioChroma[],
- int DPPPerPlane[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[],
+ unsigned int DPPPerPlane[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[],
double SwathWidth[],
double SwathWidthChroma[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
unsigned int DETBufferSizeY[],
unsigned int DETBufferSizeC[],
bool ViewportSizeSupportPerPlane[],
@@ -528,22 +528,22 @@ static void CalculateSwathWidth(
unsigned int SurfaceHeightY[],
unsigned int SurfaceHeightC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BytePerPixY[],
- int BytePerPixC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
- int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
+ unsigned int BlendingAndTiming[],
unsigned int HActive[],
double HRatio[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double SwathWidthSingleDPPY[],
double SwathWidthSingleDPPC[],
double SwathWidthY[],
double SwathWidthC[],
- int MaximumSwathHeightY[],
- int MaximumSwathHeightC[],
+ unsigned int MaximumSwathHeightY[],
+ unsigned int MaximumSwathHeightC[],
unsigned int swath_width_luma_ub[],
unsigned int swath_width_chroma_ub[]);
static double CalculateExtraLatency(
@@ -558,8 +558,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
double HostVMMinPageSize,
@@ -573,8 +573,8 @@ static double CalculateExtraLatencyBytes(
bool GPUVMEnable,
bool HostVMEnable,
unsigned int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
double HostVMMinPageSize,
@@ -2888,18 +2888,18 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
// Display Pipe Configuration
double BytePerPixDETY[DC__NUM_DPP__MAX] = { 0 };
double BytePerPixDETC[DC__NUM_DPP__MAX] = { 0 };
- int BytePerPixY[DC__NUM_DPP__MAX] = { 0 };
- int BytePerPixC[DC__NUM_DPP__MAX] = { 0 };
- int Read256BytesBlockHeightY[DC__NUM_DPP__MAX] = { 0 };
- int Read256BytesBlockHeightC[DC__NUM_DPP__MAX] = { 0 };
- int Read256BytesBlockWidthY[DC__NUM_DPP__MAX] = { 0 };
- int Read256BytesBlockWidthC[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int BytePerPixY[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int BytePerPixC[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int Read256BytesBlockHeightY[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int Read256BytesBlockHeightC[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int Read256BytesBlockWidthY[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int Read256BytesBlockWidthC[DC__NUM_DPP__MAX] = { 0 };
double dummy1[DC__NUM_DPP__MAX] = { 0 };
double dummy2[DC__NUM_DPP__MAX] = { 0 };
double dummy3[DC__NUM_DPP__MAX] = { 0 };
double dummy4[DC__NUM_DPP__MAX] = { 0 };
- int dummy5[DC__NUM_DPP__MAX] = { 0 };
- int dummy6[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int dummy5[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int dummy6[DC__NUM_DPP__MAX] = { 0 };
bool dummy7[DC__NUM_DPP__MAX] = { 0 };
bool dummysinglestring = 0;
unsigned int k;
@@ -3381,7 +3381,7 @@ static double TruncToValidBPP(
void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
{
struct vba_vars_st *v = &mode_lib->vba;
- int MinPrefetchMode, MaxPrefetchMode;
+ unsigned int MinPrefetchMode, MaxPrefetchMode;
int idx, start_state;
unsigned int i, j, k, m;
bool EnoughWritebackUnits = true;
@@ -4550,7 +4550,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
for (i = start_state; i < mode_lib->soc.num_states; ++i) {
for (j = 0; j <= 1; ++j) {
- int NextPrefetchModeState = MinPrefetchMode;
+ unsigned int NextPrefetchModeState = MinPrefetchMode;
v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j];
@@ -5153,8 +5153,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
static void CalculateDCFCLKDeepSleep(
struct display_mode_lib *mode_lib,
unsigned int NumberOfActivePlanes,
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
double VRatio[],
double VRatioChroma[],
double SwathWidthY[],
@@ -5306,7 +5306,7 @@ static void CalculatePixelDeliveryTimes(
double PSCL_THROUGHPUT[],
double PSCL_THROUGHPUT_CHROMA[],
double DPPCLK[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
unsigned int NumberOfCursors[],
unsigned int CursorWidth[][2],
@@ -5411,35 +5411,35 @@ static void CalculateMetaAndPTETimes(
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
- int HTotal[],
+ unsigned int HTotal[],
double VRatio[],
double VRatioChroma[],
double DestinationLinesToRequestRowInVBlank[],
double DestinationLinesToRequestRowInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
- int dpte_row_height[],
- int dpte_row_height_chroma[],
- int meta_row_width[],
- int meta_row_width_chroma[],
- int meta_row_height[],
- int meta_row_height_chroma[],
- int meta_req_width[],
- int meta_req_width_chroma[],
- int meta_req_height[],
- int meta_req_height_chroma[],
- int dpte_group_bytes[],
- int PTERequestSizeY[],
- int PTERequestSizeC[],
- int PixelPTEReqWidthY[],
- int PixelPTEReqHeightY[],
- int PixelPTEReqWidthC[],
- int PixelPTEReqHeightC[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
+ unsigned int dpte_row_height[],
+ unsigned int dpte_row_height_chroma[],
+ unsigned int meta_row_width[],
+ unsigned int meta_row_width_chroma[],
+ unsigned int meta_row_height[],
+ unsigned int meta_row_height_chroma[],
+ unsigned int meta_req_width[],
+ unsigned int meta_req_width_chroma[],
+ unsigned int meta_req_height[],
+ unsigned int meta_req_height_chroma[],
+ unsigned int dpte_group_bytes[],
+ unsigned int PTERequestSizeY[],
+ unsigned int PTERequestSizeC[],
+ unsigned int PixelPTEReqWidthY[],
+ unsigned int PixelPTEReqHeightY[],
+ unsigned int PixelPTEReqWidthC[],
+ unsigned int PixelPTEReqHeightC[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
double DST_Y_PER_PTE_ROW_NOM_L[],
double DST_Y_PER_PTE_ROW_NOM_C[],
double DST_Y_PER_META_ROW_NOM_L[],
@@ -5584,18 +5584,18 @@ static void CalculateVMGroupAndRequestTimes(
bool GPUVMEnable,
unsigned int GPUVMMaxPageTableLevels,
unsigned int HTotal[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
double DestinationLinesToRequestVMInVBlank[],
double DestinationLinesToRequestVMInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
- int vm_group_bytes[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
+ unsigned int vm_group_bytes[],
unsigned int dpde0_bytes_per_frame_ub_l[],
unsigned int dpde0_bytes_per_frame_ub_c[],
- int meta_pte_bytes_per_frame_ub_l[],
- int meta_pte_bytes_per_frame_ub_c[],
+ unsigned int meta_pte_bytes_per_frame_ub_l[],
+ unsigned int meta_pte_bytes_per_frame_ub_c[],
double TimePerVMGroupVBlank[],
double TimePerVMGroupFlip[],
double TimePerVMRequestVBlank[],
@@ -5700,27 +5700,27 @@ static void CalculateStutterEfficiency(
double ReturnBW,
double SRExitTime,
bool SynchronizedVBlank,
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
unsigned int DETBufferSizeY[],
- int BytePerPixelY[],
+ unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
double SwathWidthY[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
double DCCRateLuma[],
double DCCRateChroma[],
- int HTotal[],
- int VTotal[],
+ unsigned int HTotal[],
+ unsigned int VTotal[],
double PixelClock[],
double VRatio[],
enum scan_direction_class SourceScan[],
- int BlockHeight256BytesY[],
- int BlockWidth256BytesY[],
- int BlockHeight256BytesC[],
- int BlockWidth256BytesC[],
- int DCCYMaxUncompressedBlock[],
- int DCCCMaxUncompressedBlock[],
- int VActive[],
+ unsigned int BlockHeight256BytesY[],
+ unsigned int BlockWidth256BytesY[],
+ unsigned int BlockHeight256BytesC[],
+ unsigned int BlockWidth256BytesC[],
+ unsigned int DCCYMaxUncompressedBlock[],
+ unsigned int DCCCMaxUncompressedBlock[],
+ unsigned int VActive[],
bool DCCEnable[],
bool WritebackEnable[],
double ReadBandwidthPlaneLuma[],
@@ -5854,42 +5854,42 @@ static void CalculateSwathAndDETConfiguration(
enum scan_direction_class SourceScan[],
enum source_format_class SourcePixelFormat[],
enum dm_swizzle_mode SurfaceTiling[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BlendingAndTiming[],
- int BytePerPixY[],
- int BytePerPixC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
double BytePerPixDETY[],
double BytePerPixDETC[],
- int HActive[],
+ unsigned int HActive[],
double HRatio[],
double HRatioChroma[],
- int DPPPerPlane[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[],
+ unsigned int DPPPerPlane[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[],
double SwathWidth[],
double SwathWidthChroma[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
unsigned int DETBufferSizeY[],
unsigned int DETBufferSizeC[],
bool ViewportSizeSupportPerPlane[],
bool *ViewportSizeSupport)
{
(void)HRatioChroma;
- int MaximumSwathHeightY[DC__NUM_DPP__MAX] = { 0 };
- int MaximumSwathHeightC[DC__NUM_DPP__MAX] = { 0 };
- int MinimumSwathHeightY = 0;
- int MinimumSwathHeightC = 0;
+ unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int MinimumSwathHeightY = 0;
+ unsigned int MinimumSwathHeightC = 0;
long RoundedUpMaxSwathSizeBytesY = 0;
long RoundedUpMaxSwathSizeBytesC = 0;
long RoundedUpMinSwathSizeBytesY = 0;
@@ -6049,22 +6049,22 @@ static void CalculateSwathWidth(
unsigned int SurfaceHeightY[],
unsigned int SurfaceHeightC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BytePerPixY[],
- int BytePerPixC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
- int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
+ unsigned int BlendingAndTiming[],
unsigned int HActive[],
double HRatio[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double SwathWidthSingleDPPY[],
double SwathWidthSingleDPPC[],
double SwathWidthY[],
double SwathWidthC[],
- int MaximumSwathHeightY[],
- int MaximumSwathHeightC[],
+ unsigned int MaximumSwathHeightY[],
+ unsigned int MaximumSwathHeightC[],
unsigned int swath_width_luma_ub[],
unsigned int swath_width_chroma_ub[])
{
@@ -6157,8 +6157,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
double HostVMMinPageSize,
@@ -6193,8 +6193,8 @@ static double CalculateExtraLatencyBytes(
bool GPUVMEnable,
bool HostVMEnable,
unsigned int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
double HostVMMinPageSize,
@@ -6251,7 +6251,7 @@ static double CalculateUrgentLatency(
static noinline_for_stack void UseMinimumDCFCLK(
struct display_mode_lib *mode_lib,
struct vba_vars_st *v,
- int MaxPrefetchMode,
+ unsigned int MaxPrefetchMode,
int ReorderingBytes)
{
double NormalEfficiency = 0;
@@ -6276,7 +6276,7 @@ static noinline_for_stack void UseMinimumDCFCLK(
double ExtraLatencyBytes = 0;
double ExtraLatencyCycles = 0;
double DCFCLKRequiredForPeakBandwidth = 0;
- int NoOfDPPState[DC__NUM_DPP__MAX] = { 0 };
+ unsigned int NoOfDPPState[DC__NUM_DPP__MAX] = { 0 };
double MinimumTvmPlus2Tr0 = 0;
TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index 173251d738f2..f9224a433220 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -157,7 +157,7 @@ static bool CalculatePrefetchSchedule(
double *Tdmdl_vm,
double *Tdmdl,
double *TSetup,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix);
static double RoundToDFSGranularityUp(double Clock, double VCOSpeed);
@@ -218,19 +218,19 @@ static unsigned int CalculateVMAndRowBytes(
unsigned int *MetaRowByte,
unsigned int *PixelPTEBytesPerRow,
bool *PTEBufferSizeNotExceeded,
- int *dpte_row_width_ub,
+ unsigned int *dpte_row_width_ub,
unsigned int *dpte_row_height,
unsigned int *MetaRequestWidth,
unsigned int *MetaRequestHeight,
unsigned int *meta_row_width,
unsigned int *meta_row_height,
- int *vm_group_bytes,
+ unsigned int *vm_group_bytes,
unsigned int *dpte_group_bytes,
unsigned int *PixelPTEReqWidth,
unsigned int *PixelPTEReqHeight,
unsigned int *PTERequestSize,
- int *DPDE0BytesFrame,
- int *MetaPTEBytesFrame);
+ unsigned int *DPDE0BytesFrame,
+ unsigned int *MetaPTEBytesFrame);
static double CalculateTWait(unsigned int PrefetchMode, double DRAMClockChangeLatency, double UrgentLatency, double SREnterPlusExitTime);
static void CalculateRowBandwidth(
bool GPUVMEnable,
@@ -285,7 +285,7 @@ static void CalculateVupdateAndDynamicMetadataParameters(
double *Tdmbf,
double *Tdmec,
double *Tdmsks,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix);
@@ -318,8 +318,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
static void CalculateDCFCLKDeepSleep(
struct display_mode_lib *mode_lib,
unsigned int NumberOfActivePlanes,
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
double VRatio[],
double VRatioChroma[],
double SwathWidthY[],
@@ -377,7 +377,7 @@ static void CalculatePixelDeliveryTimes(
double PSCL_THROUGHPUT[],
double PSCL_THROUGHPUT_CHROMA[],
double DPPCLK[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
unsigned int NumberOfCursors[],
unsigned int CursorWidth[][DC__NUM_CURSOR__MAX],
@@ -402,35 +402,35 @@ static void CalculateMetaAndPTETimes(
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
- int HTotal[],
+ unsigned int HTotal[],
double VRatio[],
double VRatioChroma[],
double DestinationLinesToRequestRowInVBlank[],
double DestinationLinesToRequestRowInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
- int dpte_row_height[],
- int dpte_row_height_chroma[],
- int meta_row_width[],
- int meta_row_width_chroma[],
- int meta_row_height[],
- int meta_row_height_chroma[],
- int meta_req_width[],
- int meta_req_width_chroma[],
- int meta_req_height[],
- int meta_req_height_chroma[],
- int dpte_group_bytes[],
- int PTERequestSizeY[],
- int PTERequestSizeC[],
- int PixelPTEReqWidthY[],
- int PixelPTEReqHeightY[],
- int PixelPTEReqWidthC[],
- int PixelPTEReqHeightC[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
+ unsigned int dpte_row_height[],
+ unsigned int dpte_row_height_chroma[],
+ unsigned int meta_row_width[],
+ unsigned int meta_row_width_chroma[],
+ unsigned int meta_row_height[],
+ unsigned int meta_row_height_chroma[],
+ unsigned int meta_req_width[],
+ unsigned int meta_req_width_chroma[],
+ unsigned int meta_req_height[],
+ unsigned int meta_req_height_chroma[],
+ unsigned int dpte_group_bytes[],
+ unsigned int PTERequestSizeY[],
+ unsigned int PTERequestSizeC[],
+ unsigned int PixelPTEReqWidthY[],
+ unsigned int PixelPTEReqHeightY[],
+ unsigned int PixelPTEReqWidthC[],
+ unsigned int PixelPTEReqHeightC[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
double DST_Y_PER_PTE_ROW_NOM_L[],
double DST_Y_PER_PTE_ROW_NOM_C[],
double DST_Y_PER_META_ROW_NOM_L[],
@@ -453,18 +453,18 @@ static void CalculateVMGroupAndRequestTimes(
bool GPUVMEnable,
unsigned int GPUVMMaxPageTableLevels,
unsigned int HTotal[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
double DestinationLinesToRequestVMInVBlank[],
double DestinationLinesToRequestVMInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
- int vm_group_bytes[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
+ unsigned int vm_group_bytes[],
unsigned int dpde0_bytes_per_frame_ub_l[],
unsigned int dpde0_bytes_per_frame_ub_c[],
- int meta_pte_bytes_per_frame_ub_l[],
- int meta_pte_bytes_per_frame_ub_c[],
+ unsigned int meta_pte_bytes_per_frame_ub_l[],
+ unsigned int meta_pte_bytes_per_frame_ub_c[],
double TimePerVMGroupVBlank[],
double TimePerVMGroupFlip[],
double TimePerVMRequestVBlank[],
@@ -492,29 +492,29 @@ static void CalculateStutterEfficiency(
bool ProgressiveToInterlaceUnitInOPP,
bool Interlace[],
double MinTTUVBlank[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
unsigned int DETBufferSizeY[],
- int BytePerPixelY[],
+ unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
double SwathWidthY[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
double NetDCCRateLuma[],
double NetDCCRateChroma[],
double DCCFractionOfZeroSizeRequestsLuma[],
double DCCFractionOfZeroSizeRequestsChroma[],
- int HTotal[],
- int VTotal[],
+ unsigned int HTotal[],
+ unsigned int VTotal[],
double PixelClock[],
double VRatio[],
enum scan_direction_class SourceScan[],
- int BlockHeight256BytesY[],
- int BlockWidth256BytesY[],
- int BlockHeight256BytesC[],
- int BlockWidth256BytesC[],
- int DCCYMaxUncompressedBlock[],
- int DCCCMaxUncompressedBlock[],
- int VActive[],
+ unsigned int BlockHeight256BytesY[],
+ unsigned int BlockWidth256BytesY[],
+ unsigned int BlockHeight256BytesC[],
+ unsigned int BlockWidth256BytesC[],
+ unsigned int DCCYMaxUncompressedBlock[],
+ unsigned int DCCCMaxUncompressedBlock[],
+ unsigned int VActive[],
bool DCCEnable[],
bool WritebackEnable[],
double ReadBandwidthPlaneLuma[],
@@ -539,32 +539,32 @@ static void CalculateSwathAndDETConfiguration(
enum scan_direction_class SourceScan[],
enum source_format_class SourcePixelFormat[],
enum dm_swizzle_mode SurfaceTiling[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BlendingAndTiming[],
- int BytePerPixY[],
- int BytePerPixC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
double BytePerPixDETY[],
double BytePerPixDETC[],
- int HActive[],
+ unsigned int HActive[],
double HRatio[],
double HRatioChroma[],
- int DPPPerPlane[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[],
+ unsigned int DPPPerPlane[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[],
double SwathWidth[],
double SwathWidthChroma[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
unsigned int DETBufferSizeY[],
unsigned int DETBufferSizeC[],
bool ViewportSizeSupportPerPlane[],
@@ -574,31 +574,31 @@ static void CalculateSwathWidth(
int NumberOfActivePlanes,
enum source_format_class SourcePixelFormat[],
enum scan_direction_class SourceScan[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BytePerPixY[],
- int BytePerPixC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
- int BlendingAndTiming[],
- int HActive[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int HActive[],
double HRatio[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double SwathWidthSingleDPPY[],
double SwathWidthSingleDPPC[],
double SwathWidthY[],
double SwathWidthC[],
- int MaximumSwathHeightY[],
- int MaximumSwathHeightC[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[]);
+ unsigned int MaximumSwathHeightY[],
+ unsigned int MaximumSwathHeightC[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[]);
static double CalculateExtraLatency(
int RoundTripPingLatencyCycles,
@@ -612,8 +612,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels);
@@ -627,8 +627,8 @@ static double CalculateExtraLatencyBytes(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels);
@@ -652,7 +652,7 @@ static void CalculateUnboundedRequestAndCompressedBufferSize(
int CompressedBufferSegmentSizeInkByteFinal,
enum output_encoder_class *Output,
bool *UnboundedRequestEnabled,
- int *CompressedBufferSizeInkByte);
+ unsigned int *CompressedBufferSizeInkByte);
static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output);
@@ -869,7 +869,7 @@ static bool CalculatePrefetchSchedule(
double *Tdmdl_vm,
double *Tdmdl,
double *TSetup,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix)
{
@@ -1818,19 +1818,19 @@ static unsigned int CalculateVMAndRowBytes(
unsigned int *MetaRowByte,
unsigned int *PixelPTEBytesPerRow,
bool *PTEBufferSizeNotExceeded,
- int *dpte_row_width_ub,
+ unsigned int *dpte_row_width_ub,
unsigned int *dpte_row_height,
unsigned int *MetaRequestWidth,
unsigned int *MetaRequestHeight,
unsigned int *meta_row_width,
unsigned int *meta_row_height,
- int *vm_group_bytes,
+ unsigned int *vm_group_bytes,
unsigned int *dpte_group_bytes,
unsigned int *PixelPTEReqWidth,
unsigned int *PixelPTEReqHeight,
unsigned int *PTERequestSize,
- int *DPDE0BytesFrame,
- int *MetaPTEBytesFrame)
+ unsigned int *DPDE0BytesFrame,
+ unsigned int *MetaPTEBytesFrame)
{
(void)SourcePixelFormat;
struct vba_vars_st *v = &mode_lib->vba;
@@ -3278,18 +3278,18 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
// Display Pipe Configuration
double BytePerPixDETY[DC__NUM_DPP__MAX];
double BytePerPixDETC[DC__NUM_DPP__MAX];
- int BytePerPixY[DC__NUM_DPP__MAX];
- int BytePerPixC[DC__NUM_DPP__MAX];
- int Read256BytesBlockHeightY[DC__NUM_DPP__MAX];
- int Read256BytesBlockHeightC[DC__NUM_DPP__MAX];
- int Read256BytesBlockWidthY[DC__NUM_DPP__MAX];
- int Read256BytesBlockWidthC[DC__NUM_DPP__MAX];
+ unsigned int BytePerPixY[DC__NUM_DPP__MAX];
+ unsigned int BytePerPixC[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockHeightY[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockHeightC[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockWidthY[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockWidthC[DC__NUM_DPP__MAX];
double dummy1[DC__NUM_DPP__MAX];
double dummy2[DC__NUM_DPP__MAX];
double dummy3[DC__NUM_DPP__MAX];
double dummy4[DC__NUM_DPP__MAX];
- int dummy5[DC__NUM_DPP__MAX];
- int dummy6[DC__NUM_DPP__MAX];
+ unsigned int dummy5[DC__NUM_DPP__MAX];
+ unsigned int dummy6[DC__NUM_DPP__MAX];
bool dummy7[DC__NUM_DPP__MAX];
bool dummysinglestring;
@@ -3429,7 +3429,7 @@ static void CalculateVupdateAndDynamicMetadataParameters(
double *Tdmbf,
double *Tdmec,
double *Tdmsks,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix)
{
@@ -3783,7 +3783,7 @@ static noinline void CalculatePrefetchSchedulePerPlane(
&v->VReadyOffsetPix[k]);
}
-static void PatchDETBufferSizeInKByte(unsigned int NumberOfActivePlanes, int NoOfDPPThisState[], unsigned int config_return_buffer_size_in_kbytes, unsigned int DETBufferSizeInKByte[])
+static void PatchDETBufferSizeInKByte(unsigned int NumberOfActivePlanes, unsigned int NoOfDPPThisState[], unsigned int config_return_buffer_size_in_kbytes, unsigned int DETBufferSizeInKByte[])
{
int total_pipes = 0;
unsigned int i;
@@ -3804,7 +3804,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
int idx;
unsigned int i, j, k, m;
int ReorderingBytes;
- int MinPrefetchMode = 0, MaxPrefetchMode = 2;
+ unsigned int MinPrefetchMode = 0, MaxPrefetchMode = 2;
bool NoChroma = true;
bool EnoughWritebackUnits = true;
bool P2IWith420 = false;
@@ -5119,7 +5119,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
double HostVMInefficiencyFactor = 1;
int NextPrefetchModeState = MinPrefetchMode;
bool UnboundedRequestEnabledThisState = false;
- int CompressedBufferSizeInkByteThisState = 0;
+ unsigned int CompressedBufferSizeInkByteThisState = 0;
double dummy;
v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j];
@@ -5774,8 +5774,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
static void CalculateDCFCLKDeepSleep(
struct display_mode_lib *mode_lib,
unsigned int NumberOfActivePlanes,
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
double VRatio[],
double VRatioChroma[],
double SwathWidthY[],
@@ -5926,7 +5926,7 @@ static void CalculatePixelDeliveryTimes(
double PSCL_THROUGHPUT[],
double PSCL_THROUGHPUT_CHROMA[],
double DPPCLK[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
unsigned int NumberOfCursors[],
unsigned int CursorWidth[][DC__NUM_CURSOR__MAX],
@@ -6050,35 +6050,35 @@ static void CalculateMetaAndPTETimes(
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
- int HTotal[],
+ unsigned int HTotal[],
double VRatio[],
double VRatioChroma[],
double DestinationLinesToRequestRowInVBlank[],
double DestinationLinesToRequestRowInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
- int dpte_row_height[],
- int dpte_row_height_chroma[],
- int meta_row_width[],
- int meta_row_width_chroma[],
- int meta_row_height[],
- int meta_row_height_chroma[],
- int meta_req_width[],
- int meta_req_width_chroma[],
- int meta_req_height[],
- int meta_req_height_chroma[],
- int dpte_group_bytes[],
- int PTERequestSizeY[],
- int PTERequestSizeC[],
- int PixelPTEReqWidthY[],
- int PixelPTEReqHeightY[],
- int PixelPTEReqWidthC[],
- int PixelPTEReqHeightC[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
+ unsigned int dpte_row_height[],
+ unsigned int dpte_row_height_chroma[],
+ unsigned int meta_row_width[],
+ unsigned int meta_row_width_chroma[],
+ unsigned int meta_row_height[],
+ unsigned int meta_row_height_chroma[],
+ unsigned int meta_req_width[],
+ unsigned int meta_req_width_chroma[],
+ unsigned int meta_req_height[],
+ unsigned int meta_req_height_chroma[],
+ unsigned int dpte_group_bytes[],
+ unsigned int PTERequestSizeY[],
+ unsigned int PTERequestSizeC[],
+ unsigned int PixelPTEReqWidthY[],
+ unsigned int PixelPTEReqHeightY[],
+ unsigned int PixelPTEReqWidthC[],
+ unsigned int PixelPTEReqHeightC[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
double DST_Y_PER_PTE_ROW_NOM_L[],
double DST_Y_PER_PTE_ROW_NOM_C[],
double DST_Y_PER_META_ROW_NOM_L[],
@@ -6223,18 +6223,18 @@ static void CalculateVMGroupAndRequestTimes(
bool GPUVMEnable,
unsigned int GPUVMMaxPageTableLevels,
unsigned int HTotal[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
double DestinationLinesToRequestVMInVBlank[],
double DestinationLinesToRequestVMInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
- int vm_group_bytes[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
+ unsigned int vm_group_bytes[],
unsigned int dpde0_bytes_per_frame_ub_l[],
unsigned int dpde0_bytes_per_frame_ub_c[],
- int meta_pte_bytes_per_frame_ub_l[],
- int meta_pte_bytes_per_frame_ub_c[],
+ unsigned int meta_pte_bytes_per_frame_ub_l[],
+ unsigned int meta_pte_bytes_per_frame_ub_c[],
double TimePerVMGroupVBlank[],
double TimePerVMGroupFlip[],
double TimePerVMRequestVBlank[],
@@ -6342,29 +6342,29 @@ static void CalculateStutterEfficiency(
bool ProgressiveToInterlaceUnitInOPP,
bool Interlace[],
double MinTTUVBlank[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
unsigned int DETBufferSizeY[],
- int BytePerPixelY[],
+ unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
double SwathWidthY[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
double NetDCCRateLuma[],
double NetDCCRateChroma[],
double DCCFractionOfZeroSizeRequestsLuma[],
double DCCFractionOfZeroSizeRequestsChroma[],
- int HTotal[],
- int VTotal[],
+ unsigned int HTotal[],
+ unsigned int VTotal[],
double PixelClock[],
double VRatio[],
enum scan_direction_class SourceScan[],
- int BlockHeight256BytesY[],
- int BlockWidth256BytesY[],
- int BlockHeight256BytesC[],
- int BlockWidth256BytesC[],
- int DCCYMaxUncompressedBlock[],
- int DCCCMaxUncompressedBlock[],
- int VActive[],
+ unsigned int BlockHeight256BytesY[],
+ unsigned int BlockWidth256BytesY[],
+ unsigned int BlockHeight256BytesC[],
+ unsigned int BlockWidth256BytesC[],
+ unsigned int DCCYMaxUncompressedBlock[],
+ unsigned int DCCCMaxUncompressedBlock[],
+ unsigned int VActive[],
bool DCCEnable[],
bool WritebackEnable[],
double ReadBandwidthPlaneLuma[],
@@ -6649,42 +6649,42 @@ static void CalculateSwathAndDETConfiguration(
enum scan_direction_class SourceScan[],
enum source_format_class SourcePixelFormat[],
enum dm_swizzle_mode SurfaceTiling[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BlendingAndTiming[],
- int BytePerPixY[],
- int BytePerPixC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
double BytePerPixDETY[],
double BytePerPixDETC[],
- int HActive[],
+ unsigned int HActive[],
double HRatio[],
double HRatioChroma[],
- int DPPPerPlane[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[],
+ unsigned int DPPPerPlane[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[],
double SwathWidth[],
double SwathWidthChroma[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
unsigned int DETBufferSizeY[],
unsigned int DETBufferSizeC[],
bool ViewportSizeSupportPerPlane[],
bool *ViewportSizeSupport)
{
(void)HRatioChroma;
- int MaximumSwathHeightY[DC__NUM_DPP__MAX];
- int MaximumSwathHeightC[DC__NUM_DPP__MAX];
- int MinimumSwathHeightY;
- int MinimumSwathHeightC;
+ unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX];
+ unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX];
+ unsigned int MinimumSwathHeightY;
+ unsigned int MinimumSwathHeightC;
unsigned int RoundedUpMaxSwathSizeBytesY;
unsigned int RoundedUpMaxSwathSizeBytesC;
unsigned int RoundedUpMinSwathSizeBytesY;
@@ -6829,31 +6829,31 @@ static void CalculateSwathWidth(
int NumberOfActivePlanes,
enum source_format_class SourcePixelFormat[],
enum scan_direction_class SourceScan[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BytePerPixY[],
- int BytePerPixC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
- int BlendingAndTiming[],
- int HActive[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int HActive[],
double HRatio[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double SwathWidthSingleDPPY[],
double SwathWidthSingleDPPC[],
double SwathWidthY[],
double SwathWidthC[],
- int MaximumSwathHeightY[],
- int MaximumSwathHeightC[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[])
+ unsigned int MaximumSwathHeightY[],
+ unsigned int MaximumSwathHeightC[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[])
{
(void)BytePerPixY;
enum odm_combine_mode MainPlaneODMCombine;
@@ -6960,8 +6960,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels)
@@ -7006,8 +7006,8 @@ static double CalculateExtraLatencyBytes(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels)
@@ -7061,7 +7061,7 @@ static noinline_for_stack void UseMinimumDCFCLK(
int ReorderingBytes)
{
struct vba_vars_st *v = &mode_lib->vba;
- int dummy1;
+ unsigned int dummy1;
unsigned int j, k;
unsigned int i;
double NormalEfficiency, dummy2, dummy3;
@@ -7081,7 +7081,7 @@ static noinline_for_stack void UseMinimumDCFCLK(
double ExtraLatencyBytes;
double ExtraLatencyCycles;
double DCFCLKRequiredForPeakBandwidth;
- int NoOfDPPState[DC__NUM_DPP__MAX];
+ unsigned int NoOfDPPState[DC__NUM_DPP__MAX];
double MinimumTvmPlus2Tr0;
TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0;
@@ -7226,7 +7226,7 @@ static void CalculateUnboundedRequestAndCompressedBufferSize(
int CompressedBufferSegmentSizeInkByteFinal,
enum output_encoder_class *Output,
bool *UnboundedRequestEnabled,
- int *CompressedBufferSizeInkByte)
+ unsigned int *CompressedBufferSizeInkByte)
{
double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64);
@@ -7244,7 +7244,7 @@ static void CalculateUnboundedRequestAndCompressedBufferSize(
dml_print("DML::%s: UseUnboundedRequestingFinal = %d\n", __func__, UseUnboundedRequestingFinal);
dml_print("DML::%s: actDETBufferSizeInKByte = %f\n", __func__, actDETBufferSizeInKByte);
dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, *UnboundedRequestEnabled);
- dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, *CompressedBufferSizeInkByte);
+ dml_print("DML::%s: CompressedBufferSizeInkByte = %u\n", __func__, *CompressedBufferSizeInkByte);
#endif
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index d6dcebb1ab14..dd9dc0c8cb43 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -166,7 +166,7 @@ static bool CalculatePrefetchSchedule(
double *Tdmdl_vm,
double *Tdmdl,
double *TSetup,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix);
static double RoundToDFSGranularityUp(double Clock, double VCOSpeed);
@@ -227,19 +227,19 @@ static unsigned int CalculateVMAndRowBytes(
unsigned int *MetaRowByte,
unsigned int *PixelPTEBytesPerRow,
bool *PTEBufferSizeNotExceeded,
- int *dpte_row_width_ub,
+ unsigned int *dpte_row_width_ub,
unsigned int *dpte_row_height,
unsigned int *MetaRequestWidth,
unsigned int *MetaRequestHeight,
unsigned int *meta_row_width,
unsigned int *meta_row_height,
- int *vm_group_bytes,
+ unsigned int *vm_group_bytes,
unsigned int *dpte_group_bytes,
unsigned int *PixelPTEReqWidth,
unsigned int *PixelPTEReqHeight,
unsigned int *PTERequestSize,
- int *DPDE0BytesFrame,
- int *MetaPTEBytesFrame);
+ unsigned int *DPDE0BytesFrame,
+ unsigned int *MetaPTEBytesFrame);
static double CalculateTWait(unsigned int PrefetchMode, double DRAMClockChangeLatency, double UrgentLatency, double SREnterPlusExitTime);
static void CalculateRowBandwidth(
bool GPUVMEnable,
@@ -294,7 +294,7 @@ static void CalculateVupdateAndDynamicMetadataParameters(
double *Tdmbf,
double *Tdmec,
double *Tdmsks,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix);
@@ -327,8 +327,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
static void CalculateDCFCLKDeepSleep(
struct display_mode_lib *mode_lib,
unsigned int NumberOfActivePlanes,
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
double VRatio[],
double VRatioChroma[],
double SwathWidthY[],
@@ -386,7 +386,7 @@ static void CalculatePixelDeliveryTimes(
double PSCL_THROUGHPUT[],
double PSCL_THROUGHPUT_CHROMA[],
double DPPCLK[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
unsigned int NumberOfCursors[],
unsigned int CursorWidth[][DC__NUM_CURSOR__MAX],
@@ -411,35 +411,35 @@ static void CalculateMetaAndPTETimes(
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
- int HTotal[],
+ unsigned int HTotal[],
double VRatio[],
double VRatioChroma[],
double DestinationLinesToRequestRowInVBlank[],
double DestinationLinesToRequestRowInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
- int dpte_row_height[],
- int dpte_row_height_chroma[],
- int meta_row_width[],
- int meta_row_width_chroma[],
- int meta_row_height[],
- int meta_row_height_chroma[],
- int meta_req_width[],
- int meta_req_width_chroma[],
- int meta_req_height[],
- int meta_req_height_chroma[],
- int dpte_group_bytes[],
- int PTERequestSizeY[],
- int PTERequestSizeC[],
- int PixelPTEReqWidthY[],
- int PixelPTEReqHeightY[],
- int PixelPTEReqWidthC[],
- int PixelPTEReqHeightC[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
+ unsigned int dpte_row_height[],
+ unsigned int dpte_row_height_chroma[],
+ unsigned int meta_row_width[],
+ unsigned int meta_row_width_chroma[],
+ unsigned int meta_row_height[],
+ unsigned int meta_row_height_chroma[],
+ unsigned int meta_req_width[],
+ unsigned int meta_req_width_chroma[],
+ unsigned int meta_req_height[],
+ unsigned int meta_req_height_chroma[],
+ unsigned int dpte_group_bytes[],
+ unsigned int PTERequestSizeY[],
+ unsigned int PTERequestSizeC[],
+ unsigned int PixelPTEReqWidthY[],
+ unsigned int PixelPTEReqHeightY[],
+ unsigned int PixelPTEReqWidthC[],
+ unsigned int PixelPTEReqHeightC[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
double DST_Y_PER_PTE_ROW_NOM_L[],
double DST_Y_PER_PTE_ROW_NOM_C[],
double DST_Y_PER_META_ROW_NOM_L[],
@@ -462,18 +462,18 @@ static void CalculateVMGroupAndRequestTimes(
bool GPUVMEnable,
unsigned int GPUVMMaxPageTableLevels,
unsigned int HTotal[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
double DestinationLinesToRequestVMInVBlank[],
double DestinationLinesToRequestVMInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
- int vm_group_bytes[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
+ unsigned int vm_group_bytes[],
unsigned int dpde0_bytes_per_frame_ub_l[],
unsigned int dpde0_bytes_per_frame_ub_c[],
- int meta_pte_bytes_per_frame_ub_l[],
- int meta_pte_bytes_per_frame_ub_c[],
+ unsigned int meta_pte_bytes_per_frame_ub_l[],
+ unsigned int meta_pte_bytes_per_frame_ub_c[],
double TimePerVMGroupVBlank[],
double TimePerVMGroupFlip[],
double TimePerVMRequestVBlank[],
@@ -501,29 +501,29 @@ static void CalculateStutterEfficiency(
bool ProgressiveToInterlaceUnitInOPP,
bool Interlace[],
double MinTTUVBlank[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
unsigned int DETBufferSizeY[],
- int BytePerPixelY[],
+ unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
double SwathWidthY[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
double NetDCCRateLuma[],
double NetDCCRateChroma[],
double DCCFractionOfZeroSizeRequestsLuma[],
double DCCFractionOfZeroSizeRequestsChroma[],
- int HTotal[],
- int VTotal[],
+ unsigned int HTotal[],
+ unsigned int VTotal[],
double PixelClock[],
double VRatio[],
enum scan_direction_class SourceScan[],
- int BlockHeight256BytesY[],
- int BlockWidth256BytesY[],
- int BlockHeight256BytesC[],
- int BlockWidth256BytesC[],
- int DCCYMaxUncompressedBlock[],
- int DCCCMaxUncompressedBlock[],
- int VActive[],
+ unsigned int BlockHeight256BytesY[],
+ unsigned int BlockWidth256BytesY[],
+ unsigned int BlockHeight256BytesC[],
+ unsigned int BlockWidth256BytesC[],
+ unsigned int DCCYMaxUncompressedBlock[],
+ unsigned int DCCCMaxUncompressedBlock[],
+ unsigned int VActive[],
bool DCCEnable[],
bool WritebackEnable[],
double ReadBandwidthPlaneLuma[],
@@ -547,32 +547,32 @@ static void CalculateSwathAndDETConfiguration(
enum scan_direction_class SourceScan[],
enum source_format_class SourcePixelFormat[],
enum dm_swizzle_mode SurfaceTiling[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BlendingAndTiming[],
- int BytePerPixY[],
- int BytePerPixC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
double BytePerPixDETY[],
double BytePerPixDETC[],
- int HActive[],
+ unsigned int HActive[],
double HRatio[],
double HRatioChroma[],
- int DPPPerPlane[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[],
+ unsigned int DPPPerPlane[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[],
double SwathWidth[],
double SwathWidthChroma[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
unsigned int DETBufferSizeY[],
unsigned int DETBufferSizeC[],
bool ViewportSizeSupportPerPlane[],
@@ -582,31 +582,31 @@ static void CalculateSwathWidth(
int NumberOfActivePlanes,
enum source_format_class SourcePixelFormat[],
enum scan_direction_class SourceScan[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BytePerPixY[],
- int BytePerPixC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
- int BlendingAndTiming[],
- int HActive[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int HActive[],
double HRatio[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double SwathWidthSingleDPPY[],
double SwathWidthSingleDPPC[],
double SwathWidthY[],
double SwathWidthC[],
- int MaximumSwathHeightY[],
- int MaximumSwathHeightC[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[]);
+ unsigned int MaximumSwathHeightY[],
+ unsigned int MaximumSwathHeightC[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[]);
static double CalculateExtraLatency(
int RoundTripPingLatencyCycles,
@@ -620,8 +620,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels);
@@ -635,8 +635,8 @@ static double CalculateExtraLatencyBytes(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels);
@@ -660,7 +660,7 @@ static void CalculateUnboundedRequestAndCompressedBufferSize(
int CompressedBufferSegmentSizeInkByteFinal,
enum output_encoder_class *Output,
bool *UnboundedRequestEnabled,
- int *CompressedBufferSizeInkByte);
+ unsigned int *CompressedBufferSizeInkByte);
static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output);
static unsigned int CalculateMaxVStartup(
@@ -887,7 +887,7 @@ static bool CalculatePrefetchSchedule(
double *Tdmdl_vm,
double *Tdmdl,
double *TSetup,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix)
{
@@ -1835,19 +1835,19 @@ static unsigned int CalculateVMAndRowBytes(
unsigned int *MetaRowByte,
unsigned int *PixelPTEBytesPerRow,
bool *PTEBufferSizeNotExceeded,
- int *dpte_row_width_ub,
+ unsigned int *dpte_row_width_ub,
unsigned int *dpte_row_height,
unsigned int *MetaRequestWidth,
unsigned int *MetaRequestHeight,
unsigned int *meta_row_width,
unsigned int *meta_row_height,
- int *vm_group_bytes,
+ unsigned int *vm_group_bytes,
unsigned int *dpte_group_bytes,
unsigned int *PixelPTEReqWidth,
unsigned int *PixelPTEReqHeight,
unsigned int *PTERequestSize,
- int *DPDE0BytesFrame,
- int *MetaPTEBytesFrame)
+ unsigned int *DPDE0BytesFrame,
+ unsigned int *MetaPTEBytesFrame)
{
(void)SourcePixelFormat;
struct vba_vars_st *v = &mode_lib->vba;
@@ -3297,18 +3297,18 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
// Display Pipe Configuration
double BytePerPixDETY[DC__NUM_DPP__MAX];
double BytePerPixDETC[DC__NUM_DPP__MAX];
- int BytePerPixY[DC__NUM_DPP__MAX];
- int BytePerPixC[DC__NUM_DPP__MAX];
- int Read256BytesBlockHeightY[DC__NUM_DPP__MAX];
- int Read256BytesBlockHeightC[DC__NUM_DPP__MAX];
- int Read256BytesBlockWidthY[DC__NUM_DPP__MAX];
- int Read256BytesBlockWidthC[DC__NUM_DPP__MAX];
+ unsigned int BytePerPixY[DC__NUM_DPP__MAX];
+ unsigned int BytePerPixC[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockHeightY[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockHeightC[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockWidthY[DC__NUM_DPP__MAX];
+ unsigned int Read256BytesBlockWidthC[DC__NUM_DPP__MAX];
double dummy1[DC__NUM_DPP__MAX];
double dummy2[DC__NUM_DPP__MAX];
double dummy3[DC__NUM_DPP__MAX];
double dummy4[DC__NUM_DPP__MAX];
- int dummy5[DC__NUM_DPP__MAX];
- int dummy6[DC__NUM_DPP__MAX];
+ unsigned int dummy5[DC__NUM_DPP__MAX];
+ unsigned int dummy6[DC__NUM_DPP__MAX];
bool dummy7[DC__NUM_DPP__MAX];
bool dummysinglestring;
@@ -3535,7 +3535,7 @@ static void CalculateVupdateAndDynamicMetadataParameters(
double *Tdmbf,
double *Tdmec,
double *Tdmsks,
- int *VUpdateOffsetPix,
+ unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix)
{
@@ -3897,7 +3897,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_
unsigned int i;
unsigned int k, m;
int ReorderingBytes;
- int MinPrefetchMode = 0, MaxPrefetchMode = 2;
+ unsigned int MinPrefetchMode = 0, MaxPrefetchMode = 2;
bool NoChroma = true;
bool EnoughWritebackUnits = true;
bool P2IWith420 = false;
@@ -5205,7 +5205,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_
double HostVMInefficiencyFactor = 1;
int NextPrefetchModeState = MinPrefetchMode;
bool UnboundedRequestEnabledThisState = false;
- int CompressedBufferSizeInkByteThisState = 0;
+ unsigned int CompressedBufferSizeInkByteThisState = 0;
double dummy;
v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j];
@@ -5867,8 +5867,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
static void CalculateDCFCLKDeepSleep(
struct display_mode_lib *mode_lib,
unsigned int NumberOfActivePlanes,
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
double VRatio[],
double VRatioChroma[],
double SwathWidthY[],
@@ -6019,7 +6019,7 @@ static void CalculatePixelDeliveryTimes(
double PSCL_THROUGHPUT[],
double PSCL_THROUGHPUT_CHROMA[],
double DPPCLK[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
unsigned int NumberOfCursors[],
unsigned int CursorWidth[][DC__NUM_CURSOR__MAX],
@@ -6144,35 +6144,35 @@ static void CalculateMetaAndPTETimes(
bool GPUVMEnable,
int MetaChunkSize,
int MinMetaChunkSizeBytes,
- int HTotal[],
+ unsigned int HTotal[],
double VRatio[],
double VRatioChroma[],
double DestinationLinesToRequestRowInVBlank[],
double DestinationLinesToRequestRowInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int BytePerPixelY[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelY[],
+ unsigned int BytePerPixelC[],
enum scan_direction_class SourceScan[],
- int dpte_row_height[],
- int dpte_row_height_chroma[],
- int meta_row_width[],
- int meta_row_width_chroma[],
- int meta_row_height[],
- int meta_row_height_chroma[],
- int meta_req_width[],
- int meta_req_width_chroma[],
- int meta_req_height[],
- int meta_req_height_chroma[],
- int dpte_group_bytes[],
- int PTERequestSizeY[],
- int PTERequestSizeC[],
- int PixelPTEReqWidthY[],
- int PixelPTEReqHeightY[],
- int PixelPTEReqWidthC[],
- int PixelPTEReqHeightC[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
+ unsigned int dpte_row_height[],
+ unsigned int dpte_row_height_chroma[],
+ unsigned int meta_row_width[],
+ unsigned int meta_row_width_chroma[],
+ unsigned int meta_row_height[],
+ unsigned int meta_row_height_chroma[],
+ unsigned int meta_req_width[],
+ unsigned int meta_req_width_chroma[],
+ unsigned int meta_req_height[],
+ unsigned int meta_req_height_chroma[],
+ unsigned int dpte_group_bytes[],
+ unsigned int PTERequestSizeY[],
+ unsigned int PTERequestSizeC[],
+ unsigned int PixelPTEReqWidthY[],
+ unsigned int PixelPTEReqHeightY[],
+ unsigned int PixelPTEReqWidthC[],
+ unsigned int PixelPTEReqHeightC[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
double DST_Y_PER_PTE_ROW_NOM_L[],
double DST_Y_PER_PTE_ROW_NOM_C[],
double DST_Y_PER_META_ROW_NOM_L[],
@@ -6317,18 +6317,18 @@ static void CalculateVMGroupAndRequestTimes(
bool GPUVMEnable,
unsigned int GPUVMMaxPageTableLevels,
unsigned int HTotal[],
- int BytePerPixelC[],
+ unsigned int BytePerPixelC[],
double DestinationLinesToRequestVMInVBlank[],
double DestinationLinesToRequestVMInImmediateFlip[],
bool DCCEnable[],
double PixelClock[],
- int dpte_row_width_luma_ub[],
- int dpte_row_width_chroma_ub[],
- int vm_group_bytes[],
+ unsigned int dpte_row_width_luma_ub[],
+ unsigned int dpte_row_width_chroma_ub[],
+ unsigned int vm_group_bytes[],
unsigned int dpde0_bytes_per_frame_ub_l[],
unsigned int dpde0_bytes_per_frame_ub_c[],
- int meta_pte_bytes_per_frame_ub_l[],
- int meta_pte_bytes_per_frame_ub_c[],
+ unsigned int meta_pte_bytes_per_frame_ub_l[],
+ unsigned int meta_pte_bytes_per_frame_ub_c[],
double TimePerVMGroupVBlank[],
double TimePerVMGroupFlip[],
double TimePerVMRequestVBlank[],
@@ -6436,29 +6436,29 @@ static void CalculateStutterEfficiency(
bool ProgressiveToInterlaceUnitInOPP,
bool Interlace[],
double MinTTUVBlank[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
unsigned int DETBufferSizeY[],
- int BytePerPixelY[],
+ unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
double SwathWidthY[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
double NetDCCRateLuma[],
double NetDCCRateChroma[],
double DCCFractionOfZeroSizeRequestsLuma[],
double DCCFractionOfZeroSizeRequestsChroma[],
- int HTotal[],
- int VTotal[],
+ unsigned int HTotal[],
+ unsigned int VTotal[],
double PixelClock[],
double VRatio[],
enum scan_direction_class SourceScan[],
- int BlockHeight256BytesY[],
- int BlockWidth256BytesY[],
- int BlockHeight256BytesC[],
- int BlockWidth256BytesC[],
- int DCCYMaxUncompressedBlock[],
- int DCCCMaxUncompressedBlock[],
- int VActive[],
+ unsigned int BlockHeight256BytesY[],
+ unsigned int BlockWidth256BytesY[],
+ unsigned int BlockHeight256BytesC[],
+ unsigned int BlockWidth256BytesC[],
+ unsigned int DCCYMaxUncompressedBlock[],
+ unsigned int DCCCMaxUncompressedBlock[],
+ unsigned int VActive[],
bool DCCEnable[],
bool WritebackEnable[],
double ReadBandwidthPlaneLuma[],
@@ -6742,40 +6742,40 @@ static void CalculateSwathAndDETConfiguration(
enum scan_direction_class SourceScan[],
enum source_format_class SourcePixelFormat[],
enum dm_swizzle_mode SurfaceTiling[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BlendingAndTiming[],
- int BytePerPixY[],
- int BytePerPixC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
double BytePerPixDETY[],
double BytePerPixDETC[],
- int HActive[],
+ unsigned int HActive[],
double HRatio[],
double HRatioChroma[],
- int DPPPerPlane[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[],
+ unsigned int DPPPerPlane[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[],
double SwathWidth[],
double SwathWidthChroma[],
- int SwathHeightY[],
- int SwathHeightC[],
+ unsigned int SwathHeightY[],
+ unsigned int SwathHeightC[],
unsigned int DETBufferSizeY[],
unsigned int DETBufferSizeC[],
bool ViewportSizeSupportPerPlane[],
bool *ViewportSizeSupport)
{
(void)HRatioChroma;
- int MaximumSwathHeightY[DC__NUM_DPP__MAX];
- int MaximumSwathHeightC[DC__NUM_DPP__MAX];
+ unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX];
+ unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX];
int MinimumSwathHeightY;
int MinimumSwathHeightC;
unsigned int RoundedUpMaxSwathSizeBytesY;
@@ -6919,31 +6919,31 @@ static void CalculateSwathWidth(
int NumberOfActivePlanes,
enum source_format_class SourcePixelFormat[],
enum scan_direction_class SourceScan[],
- int ViewportWidth[],
- int ViewportHeight[],
- int SurfaceWidthY[],
- int SurfaceWidthC[],
- int SurfaceHeightY[],
- int SurfaceHeightC[],
+ unsigned int ViewportWidth[],
+ unsigned int ViewportHeight[],
+ unsigned int SurfaceWidthY[],
+ unsigned int SurfaceWidthC[],
+ unsigned int SurfaceHeightY[],
+ unsigned int SurfaceHeightC[],
enum odm_combine_mode ODMCombineEnabled[],
- int BytePerPixY[],
- int BytePerPixC[],
- int Read256BytesBlockHeightY[],
- int Read256BytesBlockHeightC[],
- int Read256BytesBlockWidthY[],
- int Read256BytesBlockWidthC[],
- int BlendingAndTiming[],
- int HActive[],
+ unsigned int BytePerPixY[],
+ unsigned int BytePerPixC[],
+ unsigned int Read256BytesBlockHeightY[],
+ unsigned int Read256BytesBlockHeightC[],
+ unsigned int Read256BytesBlockWidthY[],
+ unsigned int Read256BytesBlockWidthC[],
+ unsigned int BlendingAndTiming[],
+ unsigned int HActive[],
double HRatio[],
- int DPPPerPlane[],
+ unsigned int DPPPerPlane[],
double SwathWidthSingleDPPY[],
double SwathWidthSingleDPPC[],
double SwathWidthY[],
double SwathWidthC[],
- int MaximumSwathHeightY[],
- int MaximumSwathHeightC[],
- int swath_width_luma_ub[],
- int swath_width_chroma_ub[])
+ unsigned int MaximumSwathHeightY[],
+ unsigned int MaximumSwathHeightC[],
+ unsigned int swath_width_luma_ub[],
+ unsigned int swath_width_chroma_ub[])
{
(void)BytePerPixY;
enum odm_combine_mode MainPlaneODMCombine;
@@ -7049,8 +7049,8 @@ static double CalculateExtraLatency(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels)
@@ -7095,8 +7095,8 @@ static double CalculateExtraLatencyBytes(
bool GPUVMEnable,
bool HostVMEnable,
int NumberOfActivePlanes,
- int NumberOfDPP[],
- int dpte_group_bytes[],
+ unsigned int NumberOfDPP[],
+ unsigned int dpte_group_bytes[],
double HostVMInefficiencyFactor,
double HostVMMinPageSize,
int HostVMMaxNonCachedPageTableLevels)
@@ -7147,7 +7147,7 @@ static noinline_for_stack void UseMinimumDCFCLK(
int ReorderingBytes)
{
struct vba_vars_st *v = &mode_lib->vba;
- int dummy1, j;
+ unsigned int dummy1, j;
unsigned int i, k;
double NormalEfficiency, dummy2, dummy3;
double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];
@@ -7166,7 +7166,7 @@ static noinline_for_stack void UseMinimumDCFCLK(
double ExtraLatencyBytes;
double ExtraLatencyCycles;
double DCFCLKRequiredForPeakBandwidth;
- int NoOfDPPState[DC__NUM_DPP__MAX];
+ unsigned int NoOfDPPState[DC__NUM_DPP__MAX];
double MinimumTvmPlus2Tr0;
TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0;
@@ -7314,7 +7314,7 @@ static void CalculateUnboundedRequestAndCompressedBufferSize(
int CompressedBufferSegmentSizeInkByteFinal,
enum output_encoder_class *Output,
bool *UnboundedRequestEnabled,
- int *CompressedBufferSizeInkByte)
+ unsigned int *CompressedBufferSizeInkByte)
{
double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 03e49d298a85..1b1ab6a6d53a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1400,7 +1400,7 @@ static void try_odm_power_optimization_and_revalidate(
display_e2e_pipe_params_st *pipes,
int *split,
bool *merge,
- unsigned int *vlevel,
+ int *vlevel,
int pipe_cnt)
{
int i;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 8a2dbb4a2fbb..15f5248340a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -2954,7 +2954,7 @@ void dml32_UseMinimumDCFCLK(
unsigned int VTotal[],
unsigned int VActive[],
unsigned int DynamicMetadataTransmittedBytes[],
- unsigned int DynamicMetadataLinesBeforeActiveRequired[],
+ int DynamicMetadataLinesBeforeActiveRequired[],
bool Interlace[],
double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX],
double RequiredDISPCLK[][2],
@@ -5631,7 +5631,7 @@ void dml32_CalculateStutterEfficiency(
bool Interlace[],
double MinTTUVBlank[],
unsigned int DPPPerSurface[],
- unsigned int DETBufferSizeY[],
+ unsigned int DETBufferSizeY[],
unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
double SwathWidthY[],
@@ -5663,10 +5663,10 @@ void dml32_CalculateStutterEfficiency(
/* Output */
double *StutterEfficiencyNotIncludingVBlank,
double *StutterEfficiency,
- unsigned int *NumberOfStutterBurstsPerFrame,
+ int *NumberOfStutterBurstsPerFrame,
double *Z8StutterEfficiencyNotIncludingVBlank,
double *Z8StutterEfficiency,
- unsigned int *Z8NumberOfStutterBurstsPerFrame,
+ int *Z8NumberOfStutterBurstsPerFrame,
double *StutterPeriod,
bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
index 5d34735df83d..9ea36f3ff27c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
@@ -614,7 +614,7 @@ void dml32_UseMinimumDCFCLK(
unsigned int VTotal[],
unsigned int VActive[],
unsigned int DynamicMetadataTransmittedBytes[],
- unsigned int DynamicMetadataLinesBeforeActiveRequired[],
+ int DynamicMetadataLinesBeforeActiveRequired[],
bool Interlace[],
double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX],
double RequiredDISPCLK[][2],
@@ -1013,7 +1013,7 @@ void dml32_CalculateStutterEfficiency(
bool ProgressiveToInterlaceUnitInOPP,
bool Interlace[],
double MinTTUVBlank[],
- unsigned int DPPPerSurface[],
+ unsigned int DPPPerSurface[],
unsigned int DETBufferSizeY[],
unsigned int BytePerPixelY[],
double BytePerPixelDETY[],
@@ -1046,10 +1046,10 @@ void dml32_CalculateStutterEfficiency(
/* Output */
double *StutterEfficiencyNotIncludingVBlank,
double *StutterEfficiency,
- unsigned int *NumberOfStutterBurstsPerFrame,
+ int *NumberOfStutterBurstsPerFrame,
double *Z8StutterEfficiencyNotIncludingVBlank,
double *Z8StutterEfficiency,
- unsigned int *Z8NumberOfStutterBurstsPerFrame,
+ int *Z8NumberOfStutterBurstsPerFrame,
double *StutterPeriod,
bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 07993741f5e6..cde84dfb0953 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -472,7 +472,7 @@ struct vba_vars_st {
unsigned int VTotal[DC__NUM_DPP__MAX];
unsigned int VTotal_Max[DC__NUM_DPP__MAX];
unsigned int VTotal_Min[DC__NUM_DPP__MAX];
- int DPPPerPlane[DC__NUM_DPP__MAX];
+ unsigned int DPPPerPlane[DC__NUM_DPP__MAX];
double PixelClock[DC__NUM_DPP__MAX];
double PixelClockBackEnd[DC__NUM_DPP__MAX];
bool DCCEnable[DC__NUM_DPP__MAX];
@@ -739,7 +739,7 @@ struct vba_vars_st {
/* ms locals */
double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2];
unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
- int NoOfDPPThisState[DC__NUM_DPP__MAX];
+ unsigned int NoOfDPPThisState[DC__NUM_DPP__MAX];
enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
double SwathWidthYThisState[DC__NUM_DPP__MAX];
unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
@@ -900,7 +900,7 @@ struct vba_vars_st {
int PTEBufferSizeInRequestsForChroma;
// Missing from VBA
- int dpte_group_bytes_chroma;
+ unsigned int dpte_group_bytes_chroma;
unsigned int vm_group_bytes_chroma;
double dst_x_after_scaler;
double dst_y_after_scaler;
@@ -1100,8 +1100,8 @@ struct vba_vars_st {
unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX];
bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX];
bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
- int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX];
- int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX];
+ unsigned int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX];
+ unsigned int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX];
double UrgLatency[DC__VOLTAGE_STATES];
double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
@@ -1172,7 +1172,7 @@ struct vba_vars_st {
int ConfigReturnBufferSizeInKByte;
enum unbounded_requesting_policy UseUnboundedRequesting;
int CompressedBufferSegmentSizeInkByte;
- int CompressedBufferSizeInkByte;
+ unsigned int CompressedBufferSizeInkByte;
int MetaFIFOSizeInKEntries;
int ZeroSizeBufferEntries;
int COMPBUF_RESERVED_SPACE_64B;
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
index 2b8afe46ff1c..53b21adc6267 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
@@ -307,7 +307,7 @@ void dpp1_cm_set_output_csc_default(
{
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
const uint16_t *regval = NULL;
- int arr_size;
+ uint32_t arr_size;
regval = find_color_matrix(colorspace, &arr_size);
if (regval == NULL) {
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
index d24f02d201f4..8faffc2993b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
@@ -548,7 +548,7 @@ bool dpp3_get_optimal_number_of_taps(
static void dpp3_deferred_update(struct dpp *dpp_base)
{
- int bypass_state;
+ uint32_t bypass_state;
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
if (dpp_base->deferred_reg_writes.bits.disable_dscl) {
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
index 8170a86ad0ea..99581f35e54b 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
@@ -317,7 +317,7 @@ void dpp3_set_hdr_multiplier(
static void program_gamut_remap(
struct dcn3_dpp *dpp,
const uint16_t *regval,
- int select)
+ unsigned int select)
{
uint16_t selection = 0;
struct color_matrices_reg gam_regs;
@@ -379,7 +379,7 @@ void dpp3_cm_set_gamut_remap(
{
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
int i = 0;
- int gamut_mode;
+ uint32_t gamut_mode;
if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
/* Bypass if type is bypass or hw */
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 8dcdda46ee1e..9aa5adb15103 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -1336,7 +1336,7 @@ uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,
uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps(
const struct dc_crtc_timing *timing,
- const int num_slices_h,
+ const uint32_t num_slices_h,
const bool is_dp)
{
struct fixed31_32 max_dsc_overhead;
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
index 7ee31cae5959..cede9588bad8 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
@@ -228,9 +228,9 @@ bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc
void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
{
struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
- int dsc_clock_en;
- int dsc_fw_config;
- int enabled_opp_pipe;
+ uint32_t dsc_clock_en;
+ uint32_t dsc_fw_config;
+ uint32_t enabled_opp_pipe;
DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
@@ -253,7 +253,7 @@ void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
void dsc2_disable(struct display_stream_compressor *dsc)
{
struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
- int dsc_clock_en;
+ uint32_t dsc_clock_en;
DC_LOG_DSC("disable DSC %d", dsc->inst);
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
index 17acb64a9d80..d84c3399d386 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
@@ -79,9 +79,9 @@ void dsc35_construct(struct dcn20_dsc *dsc,
static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe)
{
struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
- int dsc_clock_en;
- int dsc_fw_config;
- int enabled_opp_pipe;
+ uint32_t dsc_clock_en;
+ uint32_t dsc_fw_config;
+ uint32_t enabled_opp_pipe;
DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
@@ -96,7 +96,7 @@ static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe)
REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
- DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
+ DC_LOG_DSC("ERROR: DSC %d at opp pipe %u already enabled!", dsc->inst, enabled_opp_pipe);
ASSERT(0);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
index 363e83ad21db..749547960046 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
@@ -145,16 +145,16 @@ void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_c
void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe)
{
struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
- int dsc_clock_en;
- int dsc_fw_config;
- int enabled_opp_pipe;
+ uint32_t dsc_clock_en;
+ uint32_t dsc_fw_config;
+ uint32_t enabled_opp_pipe;
DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
- DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
+ DC_LOG_DSC("ERROR: DSC %d at opp pipe %u already enabled!", dsc->inst, enabled_opp_pipe);
ASSERT(0);
}
@@ -170,7 +170,7 @@ void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe)
void dsc401_disable(struct display_stream_compressor *dsc)
{
struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
- int dsc_clock_en;
+ uint32_t dsc_clock_en;
DC_LOG_DSC("disable DSC %d", dsc->inst);
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
index 3c7a6569b692..302515128358 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
@@ -63,10 +63,10 @@ void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable)
REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, enable ? 1 : 0);
}
-int hubp401_get_3dlut_fl_done(struct hubp *hubp)
+uint32_t hubp401_get_3dlut_fl_done(struct hubp *hubp)
{
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
- int ret;
+ uint32_t ret;
REG_GET(HUBP_3DLUT_CONTROL, HUBP_3DLUT_DONE, &ret);
return ret;
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
index 4570b8016de5..4116834c552d 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
@@ -324,7 +324,7 @@ bool hubp401_construct(
void hubp401_init(struct hubp *hubp);
-int hubp401_get_3dlut_fl_done(struct hubp *hubp);
+uint32_t hubp401_get_3dlut_fl_done(struct hubp *hubp);
void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 2c2fa320df40..fc2587ca56ec 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -2485,7 +2485,8 @@ void dcn10_enable_vblanks_synchronization(
(void)group_index;
struct output_pixel_processor *opp;
struct timing_generator *tg;
- int i, width = 0, height = 0, master;
+ int i, master;
+ uint32_t width = 0, height = 0;
DC_LOGGER_INIT(dc->ctx);
@@ -2551,7 +2552,8 @@ void dcn10_enable_timing_synchronization(
(void)group_index;
struct output_pixel_processor *opp;
struct timing_generator *tg;
- int i, width = 0, height = 0;
+ int i;
+ uint32_t width = 0, height = 0;
DC_LOGGER_INIT(dc->ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
index 408d417318c2..09dfbb16dd29 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
@@ -147,7 +147,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
// Given any pipe_ctx, return the total ODM combine factor, and optionally return
// the OPPids which are used
-static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
+static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, int *opp_instances)
{
unsigned int opp_count = 1;
struct pipe_ctx *odm_pipe;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index fd42f0afc3a9..415b3f875f0d 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -1119,7 +1119,7 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
* Given any pipe_ctx, return the total ODM combine factor, and optionally return
* the OPPids which are used
* */
-static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
+static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, int *opp_instances)
{
unsigned int opp_count = 1;
struct pipe_ctx *odm_pipe;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index a094c8b40a85..1a0123338dfa 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -403,7 +403,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
// Given any pipe_ctx, return the total ODM combine factor, and optionally return
// the OPPids which are used
-static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
+static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, int *opp_instances)
{
unsigned int opp_count = 1;
struct pipe_ctx *odm_pipe;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
index d567d4bd585d..3fdd9a770334 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
@@ -126,7 +126,7 @@ static inline struct bw_fixed bw_div(const struct bw_fixed arg1, const struct bw
static inline struct bw_fixed bw_mod(const struct bw_fixed arg1, const struct bw_fixed arg2)
{
struct bw_fixed res;
- div64_u64_rem(arg1.value, arg2.value, (uint64_t *)&res.value);
+ div64_u64_rem((uint64_t)arg1.value, (uint64_t)arg2.value, (uint64_t *)&res.value);
return res;
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 0530b214c4b6..1c18898aa475 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -305,7 +305,7 @@ struct hubp_funcs {
enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g,
enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b,
enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r);
- int (*hubp_get_3dlut_fl_done)(struct hubp *hubp);
+ uint32_t (*hubp_get_3dlut_fl_done)(struct hubp *hubp);
void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg);
void (*hubp_clear_tiling)(struct hubp *hubp);
uint32_t (*hubp_get_current_read_line)(struct hubp *hubp);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index e1428a83ecbc..73cc34ea7726 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -356,8 +356,8 @@ struct opp_funcs {
void (*opp_program_dpg_dimensions)(
struct output_pixel_processor *opp,
- int width,
- int height);
+ uint32_t width,
+ uint32_t height);
bool (*dpg_is_blanked)(
struct output_pixel_processor *opp);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 2f70bb476c97..3a80369cde16 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -32,9 +32,9 @@ struct dc_bios;
/* Contains CRTC vertical/horizontal pixel counters */
struct crtc_position {
- int32_t vertical_count;
- int32_t horizontal_count;
- int32_t nominal_vcount;
+ uint32_t vertical_count;
+ uint32_t horizontal_count;
+ uint32_t nominal_vcount;
};
struct dcp_gsl_params {
@@ -321,7 +321,7 @@ struct timing_generator {
const struct timing_generator_funcs *funcs;
struct dc_bios *bp;
struct dc_context *ctx;
- int inst;
+ uint32_t inst;
};
struct dc_crtc_timing;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_service.h b/drivers/gpu/drm/amd/display/dc/inc/link_service.h
index 57bb82e94942..d0609443af49 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_service.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_service.h
@@ -110,7 +110,7 @@ struct link_service {
struct dc_sink *(*add_remote_sink)(
struct dc_link *link,
const uint8_t *edid,
- int len,
+ unsigned int len,
struct dc_sink_init_data *init_data);
void (*remove_remote_sink)(struct dc_link *link, struct dc_sink *sink);
bool (*get_hpd_state)(struct dc_link *link);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
index 26cb1459b743..7a1ecb8d986f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
@@ -155,63 +155,63 @@
* read given register and fill in field value in output parameter */
#define REG_GET(reg_name, field, val) \
generic_reg_get(CTX, REG(reg_name), \
- FN(reg_name, field), val)
+ FN(reg_name, field), (uint32_t *)val)
#define REG_GET_2(reg_name, f1, v1, f2, v2) \
generic_reg_get2(CTX, REG(reg_name), \
- FN(reg_name, f1), v1, \
- FN(reg_name, f2), v2)
+ FN(reg_name, f1), (uint32_t *)v1, \
+ FN(reg_name, f2), (uint32_t *)v2)
#define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \
generic_reg_get3(CTX, REG(reg_name), \
- FN(reg_name, f1), v1, \
- FN(reg_name, f2), v2, \
- FN(reg_name, f3), v3)
+ FN(reg_name, f1), (uint32_t *)v1, \
+ FN(reg_name, f2), (uint32_t *)v2, \
+ FN(reg_name, f3), (uint32_t *)v3)
#define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) \
generic_reg_get4(CTX, REG(reg_name), \
- FN(reg_name, f1), v1, \
- FN(reg_name, f2), v2, \
- FN(reg_name, f3), v3, \
- FN(reg_name, f4), v4)
+ FN(reg_name, f1), (uint32_t *)v1, \
+ FN(reg_name, f2), (uint32_t *)v2, \
+ FN(reg_name, f3), (uint32_t *)v3, \
+ FN(reg_name, f4), (uint32_t *)v4)
#define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
generic_reg_get5(CTX, REG(reg_name), \
- FN(reg_name, f1), v1, \
- FN(reg_name, f2), v2, \
- FN(reg_name, f3), v3, \
- FN(reg_name, f4), v4, \
- FN(reg_name, f5), v5)
+ FN(reg_name, f1), (uint32_t *)v1, \
+ FN(reg_name, f2), (uint32_t *)v2, \
+ FN(reg_name, f3), (uint32_t *)v3, \
+ FN(reg_name, f4), (uint32_t *)v4, \
+ FN(reg_name, f5), (uint32_t *)v5)
#define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
generic_reg_get6(CTX, REG(reg_name), \
- FN(reg_name, f1), v1, \
- FN(reg_name, f2), v2, \
- FN(reg_name, f3), v3, \
- FN(reg_name, f4), v4, \
- FN(reg_name, f5), v5, \
- FN(reg_name, f6), v6)
+ FN(reg_name, f1), (uint32_t *)v1, \
+ FN(reg_name, f2), (uint32_t *)v2, \
+ FN(reg_name, f3), (uint32_t *)v3, \
+ FN(reg_name, f4), (uint32_t *)v4, \
+ FN(reg_name, f5), (uint32_t *)v5, \
+ FN(reg_name, f6), (uint32_t *)v6)
#define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
generic_reg_get7(CTX, REG(reg_name), \
- FN(reg_name, f1), v1, \
- FN(reg_name, f2), v2, \
- FN(reg_name, f3), v3, \
- FN(reg_name, f4), v4, \
- FN(reg_name, f5), v5, \
- FN(reg_name, f6), v6, \
- FN(reg_name, f7), v7)
+ FN(reg_name, f1), (uint32_t *)v1, \
+ FN(reg_name, f2), (uint32_t *)v2, \
+ FN(reg_name, f3), (uint32_t *)v3, \
+ FN(reg_name, f4), (uint32_t *)v4, \
+ FN(reg_name, f5), (uint32_t *)v5, \
+ FN(reg_name, f6), (uint32_t *)v6, \
+ FN(reg_name, f7), (uint32_t *)v7)
#define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
generic_reg_get8(CTX, REG(reg_name), \
- FN(reg_name, f1), v1, \
- FN(reg_name, f2), v2, \
- FN(reg_name, f3), v3, \
- FN(reg_name, f4), v4, \
- FN(reg_name, f5), v5, \
- FN(reg_name, f6), v6, \
- FN(reg_name, f7), v7, \
- FN(reg_name, f8), v8)
+ FN(reg_name, f1), (uint32_t *)v1, \
+ FN(reg_name, f2), (uint32_t *)v2, \
+ FN(reg_name, f3), (uint32_t *)v3, \
+ FN(reg_name, f4), (uint32_t *)v4, \
+ FN(reg_name, f5), (uint32_t *)v5, \
+ FN(reg_name, f6), (uint32_t *)v6, \
+ FN(reg_name, f7), (uint32_t *)v7, \
+ FN(reg_name, f8), (uint32_t *)v8)
/* macro to poll and wait for a register field to read back given value */
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index 026c55ca0196..1ac6a22fecfe 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -1562,7 +1562,7 @@ static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink
struct dc_sink *link_add_remote_sink(
struct dc_link *link,
const uint8_t *edid,
- int len,
+ unsigned int len,
struct dc_sink_init_data *init_data)
{
struct dc_sink *dc_sink;
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.h b/drivers/gpu/drm/amd/display/dc/link/link_detection.h
index 1ab29476060b..e8d29fa1550d 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.h
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.h
@@ -32,7 +32,7 @@ bool link_detect_connection_type(struct dc_link *link,
struct dc_sink *link_add_remote_sink(
struct dc_link *link,
const uint8_t *edid,
- int len,
+ unsigned int len,
struct dc_sink_init_data *init_data);
void link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink);
bool link_reset_cur_dp_mst_topology(struct dc_link *link);
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index 6aa65815af22..72b5921227d2 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -47,9 +47,9 @@
#define DP_SINK_PR_ENABLE_AND_CONFIGURATION 0x37B
/* Travis */
-static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
+static const char DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
/* Nutmeg */
-static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
+static const char DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
{
@@ -1210,9 +1210,9 @@ int edp_get_backlight_level(const struct dc_link *link)
fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
- return panel_cntl->funcs->get_current_backlight(panel_cntl);
+ return (int)panel_cntl->funcs->get_current_backlight(panel_cntl);
else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
- return (int) abm->funcs->get_current_backlight(abm);
+ return (int)abm->funcs->get_current_backlight(abm);
else
return DC_ERROR_UNEXPECTED;
}
diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
index 0779db249765..0f2294bedcc3 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c
@@ -375,7 +375,7 @@ void mpc1_mpc_init(struct mpc *mpc)
void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)
{
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
- int opp_id;
+ uint32_t opp_id;
REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
index 4e91e9f6f11a..d7a07e29d23a 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
@@ -1067,7 +1067,7 @@ static void program_gamut_remap(
struct dcn30_mpc *mpc30,
int mpcc_id,
const uint16_t *regval,
- int select)
+ uint32_t select)
{
uint16_t selection = 0;
struct color_matrices_reg gam_regs;
@@ -1129,7 +1129,7 @@ void mpc3_set_gamut_remap(
{
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
int i = 0;
- int gamut_mode;
+ uint32_t gamut_mode;
if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
program_gamut_remap(mpc30, mpcc_id, NULL, GAMUT_REMAP_BYPASS);
@@ -1201,7 +1201,7 @@ void mpc3_get_gamut_remap(struct mpc *mpc,
{
struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
uint16_t arr_reg_val[12] = {0};
- int select;
+ uint32_t select;
read_gamut_remap(mpc30, mpcc_id, arr_reg_val, &select);
diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
index ce826a5be4c7..83730bbe26a8 100644
--- a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
@@ -293,7 +293,7 @@ void opp2_set_disp_pattern_generator(
void opp2_program_dpg_dimensions(
struct output_pixel_processor *opp,
- int width, int height)
+ uint32_t width, uint32_t height)
{
struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h
index fb0c047c1788..8944fa6c8f79 100644
--- a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h
@@ -156,7 +156,7 @@ void opp2_set_disp_pattern_generator(
void opp2_program_dpg_dimensions(
struct output_pixel_processor *opp,
- int width, int height);
+ uint32_t width, uint32_t height);
bool opp2_dpg_is_blanked(struct output_pixel_processor *opp);
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
index 60e546b69a05..07895d5f4dfa 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
@@ -101,7 +101,7 @@ static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, i
void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combine_segments)
{
struct optc *optc1 = DCN10TG_FROM_TG(tg);
- int segments;
+ uint32_t segments;
REG_GET(OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, &segments);
diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index 990fa1f19c22..109093311984 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -445,7 +445,7 @@ static inline struct fixed31_32 dc_fixpt_pow(struct fixed31_32 arg1, struct fixe
*/
static inline int dc_fixpt_floor(struct fixed31_32 arg)
{
- unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value;
+ unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value);
if (arg.value >= 0)
return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART);
@@ -459,7 +459,7 @@ static inline int dc_fixpt_floor(struct fixed31_32 arg)
*/
static inline int dc_fixpt_round(struct fixed31_32 arg)
{
- unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value;
+ unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value);
const long long summand = dc_fixpt_half.value;
@@ -479,7 +479,7 @@ static inline int dc_fixpt_round(struct fixed31_32 arg)
*/
static inline int dc_fixpt_ceil(struct fixed31_32 arg)
{
- unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value;
+ unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value);
const long long summand = dc_fixpt_one.value -
dc_fixpt_epsilon.value;
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
index 5cb979c2cf8c..1164fd96b714 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
@@ -44,7 +44,7 @@ void mod_hdcp_dump_binary_message(uint8_t *msg, uint32_t msg_size,
for (i = 0; i < msg_size; i++) {
if (i % bytes_per_line == 0)
buf[buf_pos++] = '\n';
- sprintf(&buf[buf_pos], "%02X ", msg[i]);
+ sprintf((char *)&buf[buf_pos], "%02X ", msg[i]);
buf_pos += byte_size;
}
buf[buf_pos++] = '\0';
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 08/20] drm/amd/display: only call pmfw if smu present flags true
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (6 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 07/20] drm/amd/display: Fix warnings James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 09/20] drm/amd/display: Refactor dc_link_aux_transfer_raw James Lin
` (12 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Charlene Liu, Alvin Lee,
James Lin
From: Charlene Liu <Charlene.Liu@amd.com>
[Why & How]
for fault safe case: only call pmfw if smu present flags true
and default to 2 channle for bios intergration info table error.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
index 245a217894a7..d856a7a807b1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
@@ -1078,10 +1078,11 @@ void dcn42_clk_mgr_construct(
dcn42_bw_params.vram_type = ctx->dc_bios->integrated_info->memory_type;
dcn42_bw_params.dram_channel_width_bytes = ctx->dc_bios->integrated_info->memory_type == 0x22 ? 8 : 4;
- dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 1;
- clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base);
- clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base);
-
+ dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 2;
+ if (clk_mgr->base.smu_present) {
+ clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base);
+ clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base);
+ }
clk_mgr->base.base.bw_params = &dcn42_bw_params;
if (clk_mgr->base.smu_present)
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 09/20] drm/amd/display: Refactor dc_link_aux_transfer_raw
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (7 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 08/20] drm/amd/display: only call pmfw if smu present flags true James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 10/20] drm/amd/display: always-true lower-bound assert James Lin
` (11 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Matthew Stewart,
Nevenko Stupar, Gabe Teeger, James Lin
From: Matthew Stewart <Matthew.Stewart2@amd.com>
[Why & How]
The logic for choosing between the dce_aux_transfer function variants is
moved into dce_aux.c rather than link_ddc.c.
The "dce_aux_transfer_with_retries" function now uses
dce_aux_transfer_raw in its implementation as the logic is equivalent.
Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com>
Reviewed-by: Gabe Teeger <gabe.teeger@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 20 ++++++++++++-------
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 4 ++++
.../amd/display/dc/link/protocols/link_ddc.c | 7 +------
3 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index eee58f946fae..181944ce77ab 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -559,6 +559,18 @@ static enum i2caux_transaction_action i2caux_action_from_payload(struct aux_payl
int dce_aux_transfer_raw(struct ddc_service *ddc,
struct aux_payload *payload,
enum aux_return_code_type *operation_result)
+{
+ if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc ||
+ !ddc->ddc_pin) {
+ return dce_aux_transfer_dmub_raw(ddc, payload, operation_result);
+ } else {
+ return dce_aux_transfer_raw_with_ddc_pin(ddc, payload, operation_result);
+ }
+}
+
+int dce_aux_transfer_raw_with_ddc_pin(struct ddc_service *ddc,
+ struct aux_payload *payload,
+ enum aux_return_code_type *operation_result)
{
struct ddc *ddc_pin = ddc->ddc_pin;
struct dce_aux *aux_engine;
@@ -740,13 +752,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
if (payload->write)
dce_aux_log_payload(" write", payload->data, payload->length, 16);
- /* Check whether aux to be processed via dmub or dcn directly */
- if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc
- || ddc->ddc_pin == NULL) {
- ret = dce_aux_transfer_dmub_raw(ddc, payload, &operation_result);
- } else {
- ret = dce_aux_transfer_raw(ddc, payload, &operation_result);
- }
+ ret = dce_aux_transfer_raw(ddc, payload, &operation_result);
DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
LOG_FLAG_I2cAux_DceAux,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
index c850ed49281f..8f4745694016 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
@@ -304,6 +304,10 @@ int dce_aux_transfer_raw(struct ddc_service *ddc,
struct aux_payload *cmd,
enum aux_return_code_type *operation_result);
+int dce_aux_transfer_raw_with_ddc_pin(struct ddc_service *ddc,
+ struct aux_payload *cmd,
+ enum aux_return_code_type *operation_result);
+
int dce_aux_transfer_dmub_raw(struct ddc_service *ddc,
struct aux_payload *payload,
enum aux_return_code_type *operation_result);
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c
index ef9306686b14..70f854cca029 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c
@@ -401,12 +401,7 @@ int link_aux_transfer_raw(struct ddc_service *ddc,
struct aux_payload *payload,
enum aux_return_code_type *operation_result)
{
- if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc ||
- !ddc->ddc_pin) {
- return dce_aux_transfer_dmub_raw(ddc, payload, operation_result);
- } else {
- return dce_aux_transfer_raw(ddc, payload, operation_result);
- }
+ return dce_aux_transfer_raw(ddc, payload, operation_result);
}
uint32_t link_get_fixed_vs_pe_retimer_write_address(struct dc_link *link)
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 10/20] drm/amd/display: always-true lower-bound assert
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (8 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 09/20] drm/amd/display: Refactor dc_link_aux_transfer_raw James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 11/20] drm/amd/display: Separate ABM functions into dedicated power_abm.c file James Lin
` (10 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Gaghik Khachatrian, Aric Cyr,
James Lin
From: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
[Why]
A recent type change made the lower-bound part of the OTG instance
assert redundant, which can trigger static-analysis noise and distract
from actionable diagnostics.
[How]
Kept the meaningful upper-bound range validation required for safe
narrowing to uint8_t. Removed the redundant non-negative portion of the
assert so the check matches current type semantics. Revalidated with the
latest debug build log: no warnings and no build-failure markers.
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
index 1bc81e26a11f..5ed14f694fb0 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
@@ -255,7 +255,7 @@ static void populate_pipe_ctx_dlg_params_from_dml(struct pipe_ctx *pipe_ctx, str
pipe_ctx->pipe_dlg_param.vupdate_width = dml_get_vupdate_width(mode_lib, pipe_idx);
pipe_ctx->pipe_dlg_param.vready_offset = dml_get_vready_offset(mode_lib, pipe_idx);
- ASSERT(pipe_ctx->stream_res.tg->inst >= 0 && pipe_ctx->stream_res.tg->inst <= 0xFF);
+ ASSERT(pipe_ctx->stream_res.tg->inst <= 0xFF);
pipe_ctx->pipe_dlg_param.otg_inst = (unsigned char)pipe_ctx->stream_res.tg->inst;
pipe_ctx->pipe_dlg_param.hactive = hactive;
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 11/20] drm/amd/display: Separate ABM functions into dedicated power_abm.c file
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (9 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 10/20] drm/amd/display: always-true lower-bound assert James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 12/20] drm/amd/display: Add additional IPS entry/exit for PSR/Replay James Lin
` (9 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Lohita Mudimela, Martin Leung,
James Lin
From: Lohita Mudimela <lohita.mudimela@amd.com>
[Why]
Improves code organization by separating Adaptive Backlight
Modulation functionality from general power management.
This modular approach enhances maintainability and makes the
codebase easier to navigate.
[How]
Create new power_abm.c file containing all ABM-related functions moved from power.c.
Remove static qualifier from shared functions to enable cross-file access:
- initialize_backlight_caps: Initialize backlight capabilities
- validate_ext_backlight_caps: Validate external backlight capabilities
- backlight_millipercent_to_pwm: Convert brightness percent to PWM
- backlight_millipercent_to_millinit: Convert brightness percent to nits
- fill_backlight_level_params: Populate backlight level parametersAdd function
declarations to mod_power.h header. Update CMakeLists.txt to include power_abm.c in build.
Maintain forward declaration of struct core_power for type compatibility.
Rename struct core_power field from 'public' to 'mod_public'.
Move internal structures (backlight_state, backlight_properties,
dmcu_varibright_cached_properties, core_power) to power_helpers.h to
ensure consistent memory layouts across compilation units.
Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Lohita Mudimela <lohita.mudimela@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
.../drm/amd/display/modules/inc/mod_power.h | 25 +
.../drm/amd/display/modules/power/Makefile | 2 +-
.../gpu/drm/amd/display/modules/power/power.c | 1323 +---------
.../drm/amd/display/modules/power/power_abm.c | 2160 +++++++++++++++++
.../amd/display/modules/power/power_helpers.c | 815 -------
.../amd/display/modules/power/power_helpers.h | 1 +
6 files changed, 2251 insertions(+), 2075 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/modules/power/power_abm.c
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_power.h b/drivers/gpu/drm/amd/display/modules/inc/mod_power.h
index 89037f7b7961..440e4284b6f0 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_power.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_power.h
@@ -5,6 +5,8 @@
#include "dm_services.h"
+struct core_power;
+
struct mod_power_init_params {
bool disable_fractional_pwm;
@@ -412,4 +414,27 @@ bool mod_power_backlight_nits_to_percent(struct mod_power *mod_power,
unsigned int backlight_millinit,
unsigned int *backlight_millipercent);
+void initialize_backlight_caps(struct core_power *core_power, unsigned int inst);
+
+unsigned int backlight_millipercent_to_pwm(
+ struct core_power *core_power, unsigned int millipercent, unsigned int inst);
+
+unsigned int backlight_millipercent_to_millinit(
+ struct core_power *core_power, unsigned int millipercent, unsigned int inst);
+
+void fill_backlight_level_params(struct core_power *core_power,
+ struct set_backlight_level_params *backlight_level_params,
+ int panel_inst, uint8_t aux_inst, unsigned int backlight_pwm,
+ enum backlight_control_type backlight_control_type,
+ unsigned int backlight_millinit, unsigned int transition_time_millisec,
+ bool is_hdr);
+
+bool mod_power_hw_init_backlight(struct mod_power *mod_power);
+
+void mod_power_update_backlight_on_mode_change(
+ struct core_power *core_power,
+ struct dc_link *link,
+ unsigned int panel_inst,
+ uint8_t aux_inst,
+ bool is_hdr);
#endif /* MODULES_INC_MOD_POWER_H_ */
diff --git a/drivers/gpu/drm/amd/display/modules/power/Makefile b/drivers/gpu/drm/amd/display/modules/power/Makefile
index b27a1ff3d86b..dd11f7d5617d 100644
--- a/drivers/gpu/drm/amd/display/modules/power/Makefile
+++ b/drivers/gpu/drm/amd/display/modules/power/Makefile
@@ -23,7 +23,7 @@
# Makefile for the 'power' sub-module of DAL.
#
-MOD_POWER = power_helpers.o power.o
+MOD_POWER = power_helpers.o power.o power_abm.o
AMD_DAL_MOD_POWER = $(addprefix $(AMDDALPATH)/modules/power/,$(MOD_POWER))
#$(info ************ DAL POWER MODULE MAKEFILE ************)
diff --git a/drivers/gpu/drm/amd/display/modules/power/power.c b/drivers/gpu/drm/amd/display/modules/power/power.c
index 1ee671119ddd..f8a0b252c745 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power.c
@@ -114,7 +114,7 @@ struct dmcu_varibright_cached_properties {
};
struct core_power {
- struct mod_power public;
+ struct mod_power mod_public;
struct dc *dc;
struct power_entity *map;
struct dmcu_varibright_cached_properties varibright_prop;
@@ -153,7 +153,7 @@ static const unsigned int default_ac_backlight_percent = 100;
static const unsigned int default_dc_backlight_percent = 70;
#define MOD_POWER_TO_CORE(mod_power)\
- container_of(mod_power, struct core_power, public)
+ container_of(mod_power, struct core_power, mod_public)
static unsigned int calc_psr_num_static_frames(unsigned int vsync_rate_hz)
{
@@ -199,467 +199,12 @@ static unsigned int map_index_from_stream(struct core_power *core_power,
return 0;
}
-static uint16_t backlight_8_to_16(unsigned int backlight_8bit)
-{
- return (uint16_t)(backlight_8bit * 0x101);
-}
-
-
-static unsigned int backlight_millipercent_to_millinit(
- struct core_power *core_power, unsigned int millipercent, unsigned int inst)
-{
- unsigned int millinit = 0;
- unsigned long long numerator = 0;
-
- if (core_power == NULL)
- return 0;
-
- numerator = ((unsigned long long)millipercent) *
- core_power->bl_prop[inst].nits_range;
- millinit = ((unsigned int)div_u64(numerator, 100000)) +
- core_power->bl_prop[inst].min_brightness_millinits;
-
- return millinit;
-}
-
-static unsigned int backlight_millinit_to_millipercent(
- struct core_power *core_power, unsigned int millinit, unsigned int inst)
-{
- unsigned int millipercent = 0;
- unsigned long long numerator = 0;
-
- if (core_power == NULL)
- return 0;
-
- if (millinit <= core_power->bl_prop[inst].min_brightness_millinits)
- return 0;
-
- if (millinit >= core_power->bl_prop[inst].max_brightness_millinits)
- return (100 * 1000);
-
- numerator = (((unsigned long long)millinit) -
- core_power->bl_prop[inst].min_brightness_millinits) * 100000;
- millipercent = ((unsigned int)div_u64(numerator,
- core_power->bl_prop[inst].nits_range));
-
- return millipercent;
-}
-
-static unsigned int backlight_pwm_to_millipercent(
- struct core_power *core_power, unsigned int pwm, unsigned int inst)
-{
- unsigned int millipercent = 0;
- unsigned int max_index = 0;
-
- if (core_power == NULL)
- return 0;
-
- if (!core_power->bl_prop[inst].backlight_caps_valid)
- return 0;
-
- /* Doesn't really make sense to have one single backlight level
- * possible...
- */
- if (core_power->bl_prop[inst].num_backlight_levels < 2)
- return 0;
-
- max_index = core_power->bl_prop[inst].num_backlight_levels - 1;
-
- if (pwm <= core_power->bl_prop[inst].backlight_lut[0])
- return 0;
-
- if (pwm > core_power->bl_prop[inst].backlight_lut[max_index])
- return (100 * 1000);
-
- /* We need to do a binary search over the array for where the pwm level
- * is in the lut. Based on the index we can determine percentage.
- */
- unsigned int min = 0;
- unsigned int max = max_index;
- unsigned int mid = 0;
-
- while (max >= min) {
- mid = (min + max) / 2; /* floor of half range */
-
- if (core_power->bl_prop[inst].backlight_lut[mid] < pwm)
- min = mid + 1;
- else if (core_power->bl_prop[inst].backlight_lut[mid] > pwm)
- max = mid - 1;
- else
- break;
- }
-
- /* In this case, exact match is not found. Check if mid/min/max
- * value is actually closer.
- */
- if (max < min) {
- unsigned int min_delta;
- unsigned int mid_delta;
- unsigned int max_delta;
-
- min_delta = (core_power->bl_prop[inst].backlight_lut[min] > pwm) ?
- core_power->bl_prop[inst].backlight_lut[min] - pwm :
- pwm - core_power->bl_prop[inst].backlight_lut[min];
-
- mid_delta = (core_power->bl_prop[inst].backlight_lut[mid] > pwm) ?
- core_power->bl_prop[inst].backlight_lut[mid] - pwm :
- pwm - core_power->bl_prop[inst].backlight_lut[mid];
-
- max_delta = (core_power->bl_prop[inst].backlight_lut[max] > pwm) ?
- core_power->bl_prop[inst].backlight_lut[max] - pwm :
- pwm - core_power->bl_prop[inst].backlight_lut[max];
-
- if ((min_delta < mid_delta) && (min_delta < max_delta))
- mid = min;
-
- if ((max_delta < mid_delta) && (max_delta < min_delta))
- mid = max;
- }
-
- /* No interpolation, just take closest index */
- millipercent = 1000 * 100 * mid / max_index;
-
- return millipercent;
-}
-
-static unsigned int backlight_pwm_to_millinit(
- struct core_power *core_power, unsigned int pwm, unsigned int inst)
-{
- unsigned int millinit = 0;
-
- if (core_power == NULL)
- return 0;
-
- if (pwm <= core_power->bl_prop[inst].min_backlight_pwm)
- return core_power->bl_prop[inst].min_brightness_millinits;
-
- if (pwm >= core_power->bl_prop[inst].max_backlight_pwm)
- return core_power->bl_prop[inst].max_brightness_millinits;
-
- millinit = ((unsigned int)div_u64(((unsigned long long)pwm -
- core_power->bl_prop[inst].min_backlight_pwm) *
- core_power->bl_prop[inst].nits_range,
- core_power->bl_prop[inst].backlight_range));
-
- millinit += core_power->bl_prop[inst].min_brightness_millinits;
-
- if (millinit > core_power->bl_prop[inst].max_brightness_millinits)
- millinit = core_power->bl_prop[inst].max_brightness_millinits;
-
- return millinit;
-}
-
-static unsigned int backlight_millipercent_to_pwm(
- struct core_power *core_power, unsigned int millipercent, unsigned int inst)
-{
- unsigned int pwm = (unsigned int)-1;
- unsigned int index = 0;
-
- if (core_power == NULL)
- return 0;
-
- // Bypass the brightness mapping LUT
- if (core_power->bl_prop->use_linear_backlight_curve) {
- pwm = core_power->bl_prop[inst].min_backlight_pwm +
- (unsigned int) div_u64((unsigned long long) millipercent *
- core_power->bl_prop[inst].backlight_range,
- 100000);
-
- if (pwm > core_power->bl_prop[inst].max_backlight_pwm)
- pwm = core_power->bl_prop[inst].max_backlight_pwm;
-
- return pwm;
- }
-
- if (millipercent >= (100 * 1000))
- return core_power->bl_prop[inst].backlight_lut[core_power->bl_prop[inst].num_backlight_levels - 1];
-
- /* This will give the floor index. */
- index = ((core_power->bl_prop[inst].num_backlight_levels - 1) *
- millipercent) / 100000;
- /* Null check otherwise eDP doesn't lightup when connected to DP1 */
- if (core_power->bl_prop[inst].backlight_lut == NULL)
- return pwm;
-
- pwm = core_power->bl_prop[inst].backlight_lut[index];
-
- return pwm;
-}
-
-static unsigned int backlight_millinit_to_pwm(
- struct core_power *core_power, unsigned int millinit, unsigned int inst)
-{
- unsigned int pwm = 0;
-
- if (core_power == NULL)
- return 0;
-
- /* For nits based brightness, the signal will be a value
- * between the minimum and maximum value.
- */
- if (millinit >= core_power->bl_prop[inst].max_brightness_millinits)
- return core_power->bl_prop[inst].max_backlight_pwm;
- else if (millinit <= core_power->bl_prop[inst].min_brightness_millinits)
- return core_power->bl_prop[inst].min_backlight_pwm;
-
- pwm = ((unsigned int)div_u64(((unsigned long long)millinit -
- core_power->bl_prop[inst].min_brightness_millinits) *
- core_power->bl_prop[inst].backlight_range,
- core_power->bl_prop[inst].nits_range));
-
- pwm += core_power->bl_prop[inst].min_backlight_pwm;
-
- if (pwm > core_power->bl_prop[inst].max_backlight_pwm)
- pwm = core_power->bl_prop[inst].max_backlight_pwm;
-
- return pwm;
-}
-
-static bool validate_ext_backlight_caps(
- struct dm_acpi_atif_backlight_caps *ext_backlight_caps)
-{
- unsigned int i;
- unsigned int num_of_data_points = 0;
- unsigned int last_signal_level = 0;
- unsigned int last_luminance = 0;
-
- num_of_data_points = ext_backlight_caps->num_data_points;
-
- /* Validation rules:
- * 1. BIOS should carry customized data points and
- * the number of data points should not be larger than 99.
- * 2. The max_input_signal should be larger than min_input_signal.
- * 3. For each data point:
- * a. luminance should be in ascending order and
- * should not be 0 or 100 since the corresponding signal_level
- * are assigned by min_input_signal and max_input_signal.
- * b. signal_level should be in ascending order and
- * be within the range of min/max_input_signal.
- */
- if (num_of_data_points > BL_DATA_POINTS)
- return false;
-
- if (ext_backlight_caps->min_input_signal >= ext_backlight_caps->max_input_signal)
- return false;
-
- last_signal_level = ext_backlight_caps->min_input_signal;
- for (i = 0; i < num_of_data_points; i++) {
- unsigned int luminance = ext_backlight_caps->data_points[i].luminance;
- unsigned int signal_level = ext_backlight_caps->data_points[i].signal_level;
-
- if ((luminance <= last_luminance) || (luminance > BL_DATA_POINTS))
- return false;
-
- if ((signal_level <= last_signal_level) || (signal_level >= ext_backlight_caps->max_input_signal))
- return false;
-
- last_signal_level = signal_level;
- last_luminance = luminance;
- }
-
- return true;
-}
-
-/* hard coded to default backlight curve. */
-static void initialize_backlight_caps(struct core_power *core_power, unsigned int inst)
-{
- unsigned int i;
- struct dm_acpi_atif_backlight_caps *ext_backlight_caps = NULL;
- bool custom_curve_present = false;
- unsigned int num_levels = 0;
- struct dc *dc = NULL;
- enum dm_acpi_display_type acpi_display_type =
- (inst == 0) ? AcpiDisplayType_LCD1 : AcpiDisplayType_LCD2;
-
- if (core_power == NULL)
- return;
- dc = core_power->dc;
-
- num_levels = core_power->bl_prop[inst].num_backlight_levels;
-
- /* Allocate memory for ATIF output
- * (do not want to use 256 bytes on the stack)
- */
- ext_backlight_caps = (struct dm_acpi_atif_backlight_caps *)
- (kzalloc(sizeof(struct dm_acpi_atif_backlight_caps),
- GFP_KERNEL));
-
- if (ext_backlight_caps == NULL)
- return;
-
- /* Retrieve ACPI extended brightness caps */
- if (dm_query_extended_brightness_caps
- (dc->ctx, acpi_display_type, ext_backlight_caps)) {
- custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps);
- }
-
- if (core_power->bl_prop[inst].use_custom_backlight_caps &&
- fill_custom_backlight_caps(
- core_power->bl_prop[inst].custom_backlight_caps_config_no,
- ext_backlight_caps)) {
- custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps);
- }
-
- if (custom_curve_present) {
- unsigned int index = 1;
- unsigned int num_of_data_points = ext_backlight_caps->num_data_points;
-
- core_power->bl_prop[inst].ac_backlight_percent =
- ext_backlight_caps->ac_level_percentage;
- core_power->bl_prop[inst].dc_backlight_percent =
- ext_backlight_caps->dc_level_percentage;
- core_power->bl_prop[inst].backlight_lut[0] =
- backlight_8_to_16(
- ext_backlight_caps->min_input_signal);
- core_power->bl_prop[inst].backlight_lut[num_levels - 1] =
- backlight_8_to_16(
- ext_backlight_caps->max_input_signal);
-
- /* Filling translation table from data points -
- * between every two provided data points we
- * lineary interpolate missing values
- */
- for (i = 0; i < num_of_data_points; i++) {
- unsigned int luminance =
- ext_backlight_caps->data_points[i].luminance;
- unsigned int signal_level =
- backlight_8_to_16(
- ext_backlight_caps->data_points[i].signal_level);
-
- /* Since luminance is a percentage, scale it by num_levels*/
- luminance = (luminance * num_levels) / 101;
-
- /* Lineary interpolate missing values */
- if (index < luminance) {
- unsigned int base_value =
- core_power->bl_prop[inst].backlight_lut[index-1];
- unsigned int delta_signal =
- signal_level - base_value;
- unsigned int delta_luma =
- luminance - index + 1;
- unsigned int step = delta_signal;
-
- for (; index < luminance; index++) {
- core_power->bl_prop[inst].backlight_lut[index] =
- base_value + (step / delta_luma);
- step += delta_signal;
- }
- }
-
- /* Now [index == luminance],
- * so we can add data point to the translation table
- */
- core_power->bl_prop[inst].backlight_lut[index++] = signal_level;
- }
-
- /* Complete the final segment of interpolation -
- * between last datapoint and maximum value
- */
- if (index < num_levels - 1) {
- unsigned int base_value =
- core_power->bl_prop[inst].backlight_lut[index-1];
- unsigned int delta_signal =
- core_power->bl_prop[inst].backlight_lut[num_levels - 1] -
- base_value;
- unsigned int delta_luma = num_levels - index;
- unsigned int step = delta_signal;
-
- for (; index < num_levels - 1; index++) {
- core_power->bl_prop[inst].backlight_lut[index] =
- base_value + (step / delta_luma);
- step += delta_signal;
- }
- }
- /* Build backlight translation table based on default curve */
- } else {
- /* Defines default backlight curve F(x) = A(x*x) + Bx + C.
- *
- * Backlight curve should always satisfy:
- * F(0) = min, F(100) = max,
- * So polynom coefficients are:
- * A is 0.0255 - B/100 - min/10000 - (255-max)/10000 =
- * (max - min)/10000 - B/100
- * B is adjustable factor to modify the curve.
- * Bigger B results in less concave curve.
- * B range is [0..(max-min)/100]
- * C is backlight minimum
- */
- unsigned int backlight_curve_coeff_a_factor =
- num_levels * num_levels;
- unsigned int backlight_curve_coeff_b = num_levels;
- unsigned int delta =
- core_power->bl_prop[inst].backlight_lut[num_levels - 1] -
- core_power->bl_prop[inst].backlight_lut[0];
- unsigned int coeffC = core_power->bl_prop[inst].backlight_lut[0];
- unsigned int coeffB =
- (backlight_curve_coeff_b < delta ?
- backlight_curve_coeff_b : delta);
- unsigned long long coeffA = delta - coeffB; /* coeffB is B*100 */
-
- for (i = 1; i < num_levels - 1; i++) {
- uint64_t lut_val = div_u64(coeffA * i * i, backlight_curve_coeff_a_factor) +
- div_u64((uint64_t)coeffB * i, backlight_curve_coeff_b) + coeffC;
-
- ASSERT(lut_val <= 0xFFFFFFFF);
- core_power->bl_prop[inst].backlight_lut[i] = (unsigned int)lut_val;
- }
- }
-
- if (ext_backlight_caps != NULL)
- kfree(ext_backlight_caps);
-
- /* Successfully initialized */
- core_power->bl_prop[inst].backlight_caps_valid = true;
-}
-
-static void varibright_set_level(struct core_power *core_power)
-{
- if (!core_power->varibright_prop.varibright_active ||
- !core_power->varibright_prop.varibright_user_enable)
- core_power->varibright_prop.varibright_hw_level = 0;
- else
- core_power->varibright_prop.varibright_hw_level =
- core_power->varibright_prop.varibright_level;
-}
-
bool mod_power_hw_init(struct mod_power *mod_power)
{
- struct core_power *core_power = NULL;
- struct dc *dc = NULL;
- struct dmcu *dmcu = NULL;
- struct dmcu_iram_parameters params;
- unsigned int i;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
- dc = core_power->dc;
+ /* Call backlight initialization */
+ return mod_power_hw_init_backlight(mod_power);
- for (i = 0; i < core_power->edp_num; i++) {
- params.set = core_power->varibright_prop.varibright_config_setting;
- params.backlight_ramping_override = core_power->bl_prop[i].backlight_ramping_override;
- params.backlight_ramping_reduction = core_power->bl_prop[i].backlight_ramping_reduction;
- params.backlight_ramping_start = core_power->bl_prop[i].backlight_ramping_start;
- params.backlight_lut_array = core_power->bl_prop[i].backlight_lut;
- params.backlight_lut_array_size = core_power->bl_prop[i].num_backlight_levels;
- params.min_abm_backlight = core_power->bl_prop[i].min_abm_backlight;
-
- dmcu = dc->res_pool->dmcu;
-
- // In the case where abm is implemented on dmcub,
- // dmcu object will be null.
- // ABM 2.4 and up are implemented on dmcub.
- if (dmcu) {
- //DMCU does not support multiple eDP
- return dmcu_load_iram(dmcu, params);
- } else if (dc->ctx->dmub_srv) {
- if (!dmub_init_abm_config(dc->res_pool, params, i))
- return false;
- } else
- return false;
- }
- return true;
+ /* Future: Add other HW init here */
}
struct mod_power *mod_power_create(struct dc *dc,
@@ -829,7 +374,7 @@ struct mod_power *mod_power_create(struct dc *dc,
core_power->bl_state[inst].backlight_millipercent, inst);
}
- return &core_power->public;
+ return &core_power->mod_public;
fail_bad_brightness_range:
fail_alloc_backlight_array:
@@ -1020,831 +565,91 @@ bool mod_power_replace_stream(struct mod_power *mod_power,
return true;
}
-static bool set_backlight_millinits_aux(struct core_power *core_power,
- struct dc_stream_state *stream,
- unsigned int backlight_millinits,
- unsigned int transition_time_millisec,
- unsigned int inst)
+bool mod_power_notify_mode_change(struct mod_power *mod_power,
+ const struct dc_stream_state *stream,
+ bool is_hdr)
{
+ unsigned int stream_index = 0;
+ struct core_power *core_power = NULL;
struct dc_link *link = NULL;
+ struct psr_config psr_config = {0};
+ struct psr_context psr_context = {0};
+ struct dc *dc = NULL;
+ unsigned int panel_inst = 0;
+ int active_psr_events = 0;
+ int active_replay_events = 0;
- if (core_power == NULL)
+ if ((mod_power == NULL) || (stream == NULL))
return false;
- if (stream == NULL)
- return true;
-
- link = dc_stream_get_link(stream);
-
- return dc_link_set_backlight_level_nits(link, core_power->bl_state[inst].isHDR,
- backlight_millinits, transition_time_millisec);
-}
-
-static bool set_backlight(struct core_power *core_power,
- struct dc_stream_state *stream,
- struct set_backlight_level_params *backlight_level_params,
- unsigned int inst)
-{
- bool retv = false;
- unsigned int frame_ramp = 0;
- unsigned int vsync_rate_hz;
- union dmcu_abm_set_bl_params params;
- const struct dc_link *link = NULL;
- unsigned int backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16;
- unsigned int transition_time_millisec = backlight_level_params->transition_time_in_ms;
+ core_power = MOD_POWER_TO_CORE(mod_power);
- if (core_power == NULL)
+ if (core_power->num_entities == 0)
return false;
- core_power->bl_state[inst].backlight_pwm = backlight_pwm_u16_16;
-
- if (stream == NULL)
- return true;
+ stream_index = map_index_from_stream(core_power, stream);
- if (stream->link->connector_signal != SIGNAL_TYPE_EDP)
+ if (stream_index >= core_power->num_entities)
return false;
- if (transition_time_millisec != 0) {
- unsigned int v_total =
- (stream->adjust.v_total_max == 0) ? stream->timing.v_total : stream->adjust.v_total_max;
-
- vsync_rate_hz = (unsigned int)div_u64(div_u64((stream->
- timing.pix_clk_100hz * 100),
- v_total),
- stream->timing.h_total);
-
- if (core_power->bl_state[inst].smooth_brightness_enabled)
- frame_ramp = ((vsync_rate_hz *
- transition_time_millisec) + 500) / 1000;
- }
-
- core_power->bl_state[inst].frame_ramp = frame_ramp;
- params.u32All = 0;
- params.bits.gradual_change = (frame_ramp > 0);
- params.bits.frame_ramp = frame_ramp;
+ dc = core_power->dc;
link = dc_stream_get_link(stream);
+ active_psr_events = core_power->map[stream_index].psr_events;
+ active_replay_events = core_power->map[stream_index].replay_events;
+ if (link != NULL && dc_get_edp_link_panel_inst(dc, link, &panel_inst)) {
+ ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF);
+ uint8_t aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel;
- mod_power_set_psr_event(&core_power->public, stream, true, psr_event_hw_programming, true);
- mod_power_set_replay_event(&core_power->public, stream, true, replay_event_hw_programming, true);
+ mod_power_update_backlight_on_mode_change(core_power, link, panel_inst, aux_inst, is_hdr);
- backlight_level_params->frame_ramp = params.u32All;
- retv = dc_link_set_backlight_level(link, backlight_level_params);
+ mod_power_calc_psr_configs(&psr_config, link, stream);
- mod_power_set_psr_event(&core_power->public, stream, false, psr_event_hw_programming, false);
- mod_power_set_replay_event(&core_power->public, stream, false, replay_event_hw_programming, false);
+ psr_config.psr_exit_link_training_required = core_power->map[stream_index].caps->psr_exit_link_training_required;
- return retv;
-}
+ if (dc->ctx->asic_id.chip_family >= AMDGPU_FAMILY_GC_11_0_1)
+ psr_config.allow_smu_optimizations =
+ core_power->psr_smu_optimizations_support && dc_is_embedded_signal(stream->signal);
+ else
+ psr_config.allow_smu_optimizations =
+ core_power->psr_smu_optimizations_support && mod_power_only_edp(dc->current_state, stream);
-static void fill_backlight_level_params(struct core_power *core_power,
- struct set_backlight_level_params *backlight_level_params,
- int panel_inst, uint8_t aux_inst, unsigned int backlight_pwm,
- enum backlight_control_type backlight_control_type,
- unsigned int backlight_millinit, unsigned int transition_time_millisec,
- bool is_hdr)
-{
- struct pwr_backlight_properties *bl_prop = &core_power->bl_prop[panel_inst];
-
- backlight_level_params->aux_inst = aux_inst;
- backlight_level_params->backlight_pwm_u16_16 = backlight_pwm;
- backlight_level_params->control_type = backlight_control_type;
- backlight_level_params->backlight_millinits = backlight_millinit;
- backlight_level_params->transition_time_in_ms = transition_time_millisec;
- backlight_level_params->min_luminance = bl_prop->min_brightness_millinits;
- backlight_level_params->max_luminance = bl_prop->max_brightness_millinits;
- backlight_level_params->min_backlight_pwm = bl_prop->min_backlight_pwm;
- backlight_level_params->max_backlight_pwm = bl_prop->max_backlight_pwm;
-
- if (backlight_control_type == BACKLIGHT_CONTROL_AMD_AUX && !is_hdr)
- backlight_level_params->control_type = BACKLIGHT_CONTROL_PWM;
-}
+ psr_config.allow_multi_disp_optimizations = core_power->multi_disp_optimizations_support;
-bool mod_power_set_backlight_nits(struct mod_power *mod_power,
- struct dc_stream_state *stream,
- unsigned int backlight_millinit,
- unsigned int transition_time_millisec,
- bool skip_aux,
- bool is_hdr)
-{
- struct core_power *core_power = NULL;
- unsigned int backlight_pwm;
- unsigned int panel_inst = 0;
- struct set_backlight_level_params backlight_level_params = { 0 };
- const struct dc_link *link = NULL;
- uint8_t aux_inst = 0;
+ psr_config.rate_control_caps = core_power->map[stream_index].caps->rate_control_caps;
- if (mod_power == NULL)
- return false;
+ if (active_psr_events & psr_event_os_request_force_ffu) {
+ psr_config.os_request_force_ffu = true;
+ }
+ /*
+ * DSC support:
+ * DSC slice height value must be 'mod' by su_y_granularity.
+ * According to Panel Vendor, there might be varied conditions to fulfill.
+ * Right now, DSC slice height value must be multiple of su_y_granularity.
+ *
+ * The value of DSC slice height is determined in DSC Driver but it does not
+ * propagated out here, so we need to calculate it as below 'slice_height'.
+ */
+ psr_su_set_dsc_slice_height(dc, link,
+ (struct dc_stream_state *) stream,
+ &psr_config);
- core_power = MOD_POWER_TO_CORE(mod_power);
- link = dc_stream_get_link(stream);
+ dc_link_setup_psr(link, stream, &psr_config, &psr_context);
- ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF);
- aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel;
+ link->replay_settings.replay_smu_opt_enable =
+ (link->replay_settings.config.replay_smu_opt_supported &&
+ mod_power_only_edp(dc->current_state, stream));
- if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst))
- return false;
+ if (active_replay_events & replay_event_os_request_force_ffu) {
+ link->replay_settings.config.os_request_force_ffu = true;
+ }
- if (!skip_aux) {
- if (!set_backlight_millinits_aux(core_power, stream,
- backlight_millinit, transition_time_millisec, panel_inst))
- return false;
+ if (dc_is_embedded_signal(stream->signal))
+ dc->link_srv->dp_setup_replay(link, stream);
}
-// always send both AUX (above) and PWM (below)
- core_power->bl_state[panel_inst].backlight_millinit = backlight_millinit;
-
- core_power->bl_state[panel_inst].backlight_millipercent =
- backlight_millinit_to_millipercent(
- core_power, backlight_millinit, panel_inst);
- backlight_pwm = backlight_millinit_to_pwm(
- core_power, backlight_millinit, panel_inst);
-
- fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, aux_inst, backlight_pwm,
- link->backlight_control_type, backlight_millinit, transition_time_millisec, is_hdr);
-
- return set_backlight(core_power, stream,
- &backlight_level_params, panel_inst);
+ return true;
}
-
-bool mod_power_backlight_percent_to_nits(struct mod_power *mod_power,
- struct dc_stream_state *stream,
- unsigned int backlight_millipercent,
- unsigned int *backlight_millinit)
-{
- struct core_power *core_power = NULL;
- unsigned int inst = 0;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
- return false;
-
- *backlight_millinit = backlight_millipercent_to_millinit(
- core_power, backlight_millipercent, inst);
- return true;
-}
-
-bool mod_power_backlight_nits_to_percent(struct mod_power *mod_power,
- struct dc_stream_state *stream,
- unsigned int backlight_millinit,
- unsigned int *backlight_millipercent)
-{
- struct core_power *core_power = NULL;
- unsigned int inst = 0;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
- return false;
-
- *backlight_millipercent = backlight_millinit_to_millipercent(
- core_power, backlight_millinit, inst);
- return true;
-}
-
-bool mod_power_set_backlight_percent(struct mod_power *mod_power,
- struct dc_stream_state *stream,
- unsigned int backlight_millipercent,
- unsigned int transition_time_millisec,
- bool is_hdr)
-{
- struct core_power *core_power = NULL;
- struct set_backlight_level_params backlight_level_params = { 0 };
- const struct dc_link *link = NULL;
- unsigned int backlight_pwm;
- unsigned int panel_inst = 0;
- uint8_t aux_inst = 0;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
- link = dc_stream_get_link(stream);
- ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF);
- aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel;
-
- if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst))
- return false;
- core_power->bl_state[panel_inst].backlight_millipercent = backlight_millipercent;
-
- core_power->bl_state[panel_inst].backlight_millinit =
- backlight_millipercent_to_millinit(
- core_power, backlight_millipercent, panel_inst);
-
- backlight_pwm = backlight_millipercent_to_pwm(
- core_power, backlight_millipercent, panel_inst);
-
- fill_backlight_level_params(core_power, &backlight_level_params, panel_inst,
- aux_inst, backlight_pwm, link->backlight_control_type,
- core_power->bl_state[panel_inst].backlight_millinit, transition_time_millisec, is_hdr);
-
- return set_backlight(core_power, stream,
- &backlight_level_params, panel_inst);
-}
-
-void mod_power_update_backlight(struct mod_power *mod_power,
- struct dc_stream_state *stream,
- unsigned int backlight_millipercent)
-{
- struct core_power *core_power = NULL;
- unsigned int inst = 0;
-
- if (mod_power == NULL)
- return;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
- return;
- core_power->bl_state[inst].backlight_millipercent = backlight_millipercent;
-
- core_power->bl_state[inst].backlight_millinit =
- backlight_millipercent_to_millinit(
- core_power, backlight_millipercent, inst);
-
- core_power->bl_state[inst].backlight_pwm = backlight_millipercent_to_pwm(
- core_power, backlight_millipercent, inst);
-}
-
-void mod_power_update_backlight_nits(struct mod_power *mod_power,
- struct dc_stream_state *stream,
- unsigned int backlight_millinit)
-{
- struct core_power *core_power = NULL;
- unsigned int inst = 0;
-
- if (mod_power == NULL)
- return;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
- return;
-
- core_power->bl_state[inst].backlight_millinit = backlight_millinit;
-
- core_power->bl_state[inst].backlight_millipercent = backlight_millinit_to_millipercent(
- core_power, backlight_millinit, inst);
- core_power->bl_state[inst].backlight_pwm = backlight_millinit_to_pwm(
- core_power, backlight_millinit, inst);
-}
-
-bool mod_power_get_backlight_pwm(struct mod_power *mod_power,
- unsigned int *backlight_pwm,
- unsigned int inst)
-{
- struct core_power *core_power = NULL;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- *backlight_pwm = core_power->bl_state[inst].backlight_pwm;
-
- return true;
-}
-
-bool mod_power_get_backlight_nits(struct mod_power *mod_power,
- unsigned int *backlight_millinit,
- unsigned int inst)
-{
- struct core_power *core_power = NULL;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- *backlight_millinit = core_power->bl_state[inst].backlight_millinit;
-
- return true;
-}
-
-bool mod_power_get_backlight_percent(struct mod_power *mod_power,
- unsigned int *backlight_millipercent,
- unsigned int inst)
-{
- struct core_power *core_power = NULL;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- *backlight_millipercent = core_power->bl_state[inst].backlight_millipercent;
-
- return true;
-}
-
-bool mod_power_get_hw_target_backlight_pwm_nits(struct mod_power *mod_power,
- const struct dc_link *link,
- unsigned int *backlight_millinit,
- unsigned int inst)
-{
- struct core_power *core_power = NULL;
- unsigned int backlight_u16_16 = 0;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- if (mod_power_get_hw_target_backlight_pwm(mod_power, link,
- &backlight_u16_16)) {
- *backlight_millinit =
- backlight_pwm_to_millinit(core_power,
- backlight_u16_16, inst);
- return true;
- }
- return false;
-}
-
-bool mod_power_get_hw_target_backlight_pwm_percent(struct mod_power *mod_power,
- const struct dc_link *link,
- unsigned int *backlight_millipercent,
- unsigned int inst)
-{
- struct core_power *core_power = NULL;
- unsigned int backlight_u16_16 = 0;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- if (mod_power_get_hw_target_backlight_pwm(mod_power, link,
- &backlight_u16_16)) {
- *backlight_millipercent =
- backlight_pwm_to_millipercent(core_power,
- backlight_u16_16, inst);
- return true;
- }
- return false;
-}
-
-bool mod_power_get_hw_target_backlight_pwm(struct mod_power *mod_power,
- const struct dc_link *link,
- unsigned int *backlight_u16_16)
-{
- if (mod_power == NULL)
- return false;
-
- *backlight_u16_16 = dc_link_get_target_backlight_pwm(link);
-
- return true;
-}
-
-bool mod_power_get_hw_backlight_pwm_nits(struct mod_power *mod_power,
- const struct dc_link *link,
- unsigned int *backlight_millinit,
- unsigned int inst)
-{
- struct core_power *core_power = NULL;
- unsigned int backlight_u16_16 = 0;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- if (mod_power_get_hw_backlight_pwm(mod_power, link, &backlight_u16_16)) {
- *backlight_millinit =
- backlight_pwm_to_millinit(core_power,
- backlight_u16_16, inst);
- return true;
- }
- return false;
-}
-
-bool mod_power_get_hw_backlight_aux_nits(struct mod_power *mod_power,
- struct dc_stream_state **streams, int num_streams,
- unsigned int *backlight_millinit_avg,
- unsigned int *backlight_millinit_peak)
-{
- struct core_power *core_power = NULL;
- struct dc_link *link = NULL;
- int stream_index;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- if (core_power == NULL)
- return false;
-
- if (num_streams < 1)
- return true;
-
- for (stream_index = 0; stream_index < num_streams; stream_index++)
- if (streams[stream_index]->link->connector_signal == SIGNAL_TYPE_EDP ||
- streams[stream_index]->link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT)
- break;
-
- if (stream_index == num_streams)
- return false;
-
- link = dc_stream_get_link(streams[stream_index]);
- if (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 0)
- return false;
-
- return dc_link_get_backlight_level_nits(link, backlight_millinit_avg,
- backlight_millinit_peak);
-}
-
-bool mod_power_get_hw_backlight_pwm_percent(struct mod_power *mod_power,
- const struct dc_link *link,
- unsigned int *backlight_millipercent,
- unsigned int inst)
-{
- struct core_power *core_power = NULL;
- unsigned int backlight_u16_16 = 0;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- if (mod_power_get_hw_backlight_pwm(mod_power, link, &backlight_u16_16)) {
- *backlight_millipercent =
- backlight_pwm_to_millipercent(core_power,
- backlight_u16_16, inst);
- return true;
- }
- return false;
-}
-
-bool mod_power_get_hw_backlight_pwm(struct mod_power *mod_power,
- const struct dc_link *link,
- unsigned int *backlight_u16_16)
-{
- if (mod_power == NULL)
- return false;
-
- *backlight_u16_16 = dc_link_get_backlight_level(link);
-
- return true;
-}
-
-bool mod_power_get_panel_backlight_boundaries(
- struct mod_power *mod_power,
- unsigned int *out_min_backlight,
- unsigned int *out_max_backlight,
- unsigned int *out_ac_backlight_percent,
- unsigned int *out_dc_backlight_percent,
- unsigned int inst)
-{
- struct core_power *core_power = NULL;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- /* If cache was successfully updated,
- * copy the values to output structure and return success
- */
- if (core_power->bl_prop[inst].backlight_caps_valid) {
- *out_min_backlight = core_power->bl_prop[inst].backlight_lut[0];
- *out_max_backlight =
- core_power->bl_prop[inst].backlight_lut[
- core_power->bl_prop[inst].num_backlight_levels - 1];
- *out_ac_backlight_percent =
- core_power->bl_prop[inst].ac_backlight_percent;
- *out_dc_backlight_percent =
- core_power->bl_prop[inst].dc_backlight_percent;
-
- return true;
- }
-
- return false;
-}
-
-bool mod_power_set_smooth_brightness(struct mod_power *mod_power,
- bool enable_brightness,
- unsigned int inst)
-{
- struct core_power *core_power = NULL;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- core_power->bl_state[inst].smooth_brightness_enabled = enable_brightness;
-
- return true;
-}
-
-bool mod_power_notify_mode_change(struct mod_power *mod_power,
- const struct dc_stream_state *stream,
- bool is_hdr)
-{
- unsigned int stream_index = 0;
- struct core_power *core_power = NULL;
- struct dc_link *link = NULL;
- struct psr_config psr_config = {0};
- struct psr_context psr_context = {0};
- struct dc *dc = NULL;
- unsigned int panel_inst = 0;
- int active_psr_events = 0;
- int active_replay_events = 0;
-
- if ((mod_power == NULL) || (stream == NULL))
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- if (core_power->num_entities == 0)
- return false;
-
- stream_index = map_index_from_stream(core_power, stream);
-
- if (stream_index >= core_power->num_entities)
- return false;
-
- dc = core_power->dc;
- link = dc_stream_get_link(stream);
- active_psr_events = core_power->map[stream_index].psr_events;
- active_replay_events = core_power->map[stream_index].replay_events;
- if (link != NULL && dc_get_edp_link_panel_inst(dc, link, &panel_inst)) {
- struct set_backlight_level_params backlight_level_params = { 0 };
-
- ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF);
- uint8_t aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel;
-
- if (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
- link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
- dc_link_set_backlight_level_nits(link, core_power->bl_state[panel_inst].isHDR,
- core_power->bl_state[panel_inst].backlight_millinit, 0);
-
- backlight_level_params.frame_ramp = 0;
-
- fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, aux_inst,
- core_power->bl_state[panel_inst].backlight_pwm, link->backlight_control_type,
- core_power->bl_state[panel_inst].backlight_millinit, 0, is_hdr);
-
- dc_link_set_backlight_level(link, &backlight_level_params);
-
- mod_power_calc_psr_configs(&psr_config, link, stream);
-
- psr_config.psr_exit_link_training_required = core_power->map[stream_index].caps->psr_exit_link_training_required;
-
- if (dc->ctx->asic_id.chip_family >= AMDGPU_FAMILY_GC_11_0_1)
- psr_config.allow_smu_optimizations =
- core_power->psr_smu_optimizations_support && dc_is_embedded_signal(stream->signal);
- else
- psr_config.allow_smu_optimizations =
- core_power->psr_smu_optimizations_support && mod_power_only_edp(dc->current_state, stream);
-
- psr_config.allow_multi_disp_optimizations = core_power->multi_disp_optimizations_support;
-
- psr_config.rate_control_caps = core_power->map[stream_index].caps->rate_control_caps;
-
- if (active_psr_events & psr_event_os_request_force_ffu) {
- psr_config.os_request_force_ffu = true;
- }
- /*
- * DSC support:
- * DSC slice height value must be 'mod' by su_y_granularity.
- * According to Panel Vendor, there might be varied conditions to fulfill.
- * Right now, DSC slice height value must be multiple of su_y_granularity.
- *
- * The value of DSC slice height is determined in DSC Driver but it does not
- * propagated out here, so we need to calculate it as below 'slice_height'.
- */
- psr_su_set_dsc_slice_height(dc, link,
- (struct dc_stream_state *) stream,
- &psr_config);
-
- dc_link_setup_psr(link, stream, &psr_config, &psr_context);
-
- link->replay_settings.replay_smu_opt_enable =
- (link->replay_settings.config.replay_smu_opt_supported &&
- mod_power_only_edp(dc->current_state, stream));
-
- if (active_replay_events & replay_event_os_request_force_ffu) {
- link->replay_settings.config.os_request_force_ffu = true;
- }
-
- if (dc_is_embedded_signal(stream->signal))
- dc->link_srv->dp_setup_replay(link, stream);
- }
-
- return true;
-}
-
-bool mod_power_varibright_feature_enable(struct mod_power *mod_power, bool enable,
- struct dc_stream_update *stream_update)
-{
- struct core_power *core_power = NULL;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
- core_power->varibright_prop.varibright_user_enable = enable;
-
- /* find abm hw level to program, and save in stream update */
- varibright_set_level(core_power);
- *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level;
-
- DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
- WPP_BIT_FLAG_Backlight_ABM,
- ">ABM feature enable: enable=%u su->varibright_level=%u varibright_hw_level=%u",
- (unsigned int) enable,
- *stream_update->abm_level,
- core_power->varibright_prop.varibright_hw_level);
- return true;
-}
-
-bool mod_power_varibright_activate(struct mod_power *mod_power,
- bool activate,
- struct dc_stream_update *stream_update)
-{
- struct core_power *core_power = NULL;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
- core_power->varibright_prop.varibright_active = activate;
-
- /* find abm hw level to program, and save in stream update */
- varibright_set_level(core_power);
- *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level;
-
- DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
- WPP_BIT_FLAG_Backlight_ABM,
- ">ABM activate: activate=%u su->varibright_level=%u",
- (unsigned int) activate,
- *stream_update->abm_level);
- return true;
-}
-bool mod_power_varibright_set_level(struct mod_power *mod_power, unsigned int level,
- struct dc_stream_update *stream_update)
-{
- struct core_power *core_power = NULL;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
- core_power->varibright_prop.varibright_level = level;
- core_power->varibright_prop.varibright_hw_level = level;
-
- /* find abm hw level to program, and save in stream update */
- varibright_set_level(core_power);
- *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level;
-
- DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
- WPP_BIT_FLAG_Backlight_ABM,
- ">ABM set level: level=%u -> (varibright_level=%u varibright_hw_level=%u) -> su->varibright_level=%u",
- level,
- core_power->varibright_prop.varibright_level,
- core_power->varibright_prop.varibright_hw_level,
- *stream_update->abm_level);
- return true;
-}
-
-bool mod_power_varibright_set_hw_level(struct mod_power *mod_power, unsigned int level,
- struct dc_stream_update *stream_update)
-{
- struct core_power *core_power = NULL;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- if (level == 0 || level == ABM_LEVEL_IMMEDIATE_DISABLE)
- core_power->varibright_prop.varibright_active = 0;
- else
- core_power->varibright_prop.varibright_active = 1;
- core_power->varibright_prop.varibright_hw_level = level;
- *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level;
-
- DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
- WPP_BIT_FLAG_Backlight_ABM,
- ">ABM set level: level=%u -> (varibright_level=%u varibright_hw_level=%u) -> su->varibright_level=%u",
- level,
- core_power->varibright_prop.varibright_level,
- core_power->varibright_prop.varibright_hw_level,
- *stream_update->abm_level);
- return true;
-}
-
-bool mod_power_get_varibright_level(struct mod_power *mod_power,
- unsigned int *varibright_level)
-{
- struct core_power *core_power = NULL;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- *varibright_level = core_power->varibright_prop.varibright_level;
-
- DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
- WPP_BIT_FLAG_Backlight_ABM,
- ">get varibright level: cp->varibright_level=%u",
- *varibright_level);
- return true;
-
-}
-
-bool mod_power_get_varibright_hw_level(struct mod_power *mod_power,
- unsigned int *varibright_level)
-{
- struct core_power *core_power = NULL;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- *varibright_level = core_power->varibright_prop.varibright_hw_level;
- DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
- WPP_BIT_FLAG_Backlight_ABM,
- ">get varibright HW level: hw_level=%u",
- *varibright_level);
- return true;
-}
-
-bool mod_power_get_varibright_default_level(struct mod_power *mod_power,
- unsigned int *varibright_level)
-{
- struct core_power *core_power = NULL;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- *varibright_level = core_power->varibright_prop.def_varibright_level;
- DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
- WPP_BIT_FLAG_Backlight_ABM,
- ">get varibright default level: def_varibright_level=%u",
- *varibright_level);
- return true;
-}
-
-bool mod_power_get_varibright_enable(struct mod_power *mod_power,
- bool *varibright_enable)
-{
- struct core_power *core_power = NULL;
-
- if (mod_power == NULL)
- return false;
-
- core_power = MOD_POWER_TO_CORE(mod_power);
-
- *varibright_enable = core_power->varibright_prop.varibright_user_enable;
- DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
- WPP_BIT_FLAG_Backlight_ABM,
- ">get varibright enable state: varibright_user_enable=%u",
- (unsigned int) (*varibright_enable));
- return true;
-}
-
-bool mod_power_is_abm_active(struct mod_power *mod_power,
- const struct dc_link *link,
- unsigned int inst)
-{
- unsigned int user_backlight = 0;
- unsigned int current_backlight = 0;
- bool is_active = false;
-
- if (mod_power == NULL)
- return false;
-
- mod_power_get_backlight_pwm(mod_power, &user_backlight, inst);
- mod_power_get_hw_backlight_pwm(mod_power, link, ¤t_backlight);
-
- if (user_backlight != current_backlight)
- is_active = true;
- else
- is_active = false;
- DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
- WPP_BIT_FLAG_Backlight_ABM,
- ">get ABM active state: is_active=%u (user_backlight_pwm=%u, current_backlight_pwm=%u)",
- (unsigned int)is_active,
- user_backlight,
- current_backlight);
- return is_active;
-}
-
-
static void mod_power_psr_set_power_opt(struct mod_power *mod_power,
struct dc_stream_state *stream,
unsigned int active_psr_events,
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_abm.c b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
new file mode 100644
index 000000000000..c41ace406519
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
@@ -0,0 +1,2160 @@
+// SPDX-License-Identifier: MIT
+//
+// Copyright 2026 Advanced Micro Devices, Inc.
+
+#include "dm_services.h"
+#include "dc.h"
+#include "mod_power.h"
+#include "core_types.h"
+#include "dmcu.h"
+#include "abm.h"
+#include "power_helpers.h"
+#include "dce/dmub_psr.h"
+#include "dal_asic_id.h"
+#include "link_service.h"
+#include <linux/math.h>
+
+#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
+#define DC_TRACE_LEVEL_MESSAGEP(...) /* do nothing */
+
+#define DIV_ROUNDUP(a, b) (((a)+((b)/2))/(b))
+#define bswap16_based_on_endian(big_endian, value) \
+ ((big_endian) ? cpu_to_be16(value) : cpu_to_le16(value))
+
+/* Possible Min Reduction config from least aggressive to most aggressive
+ * 0 1 2 3 4 5 6 7 8 9 10 11 12
+ * 100 98.0 94.1 94.1 85.1 80.3 75.3 69.4 60.0 57.6 50.2 49.8 40.0 %
+ */
+static const unsigned char min_reduction_table[13] = {
+0xff, 0xfa, 0xf0, 0xf0, 0xd9, 0xcd, 0xc0, 0xb1, 0x99, 0x93, 0x80, 0x82, 0x66};
+
+/* Possible Max Reduction configs from least aggressive to most aggressive
+ * 0 1 2 3 4 5 6 7 8 9 10 11 12
+ * 96.1 89.8 85.1 80.3 69.4 64.7 64.7 50.2 39.6 30.2 30.2 30.2 19.6 %
+ */
+static const unsigned char max_reduction_table[13] = {
+0xf5, 0xe5, 0xd9, 0xcd, 0xb1, 0xa5, 0xa5, 0x80, 0x65, 0x4d, 0x4d, 0x4d, 0x32};
+
+/* Possible ABM 2.2 Min Reduction configs from least aggressive to most aggressive
+ * 0 1 2 3 4 5 6 7 8 9 10 11 12
+ * 100 100 100 100 100 100 100 100 100 92.2 83.1 75.3 75.3 %
+ */
+static const unsigned char min_reduction_table_v_2_2[13] = {
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0xd4, 0xc0, 0xc0};
+
+/* Possible ABM 2.2 Max Reduction configs from least aggressive to most aggressive
+ * 0 1 2 3 4 5 6 7 8 9 10 11 12
+ * 96.1 89.8 74.9 69.4 64.7 52.2 48.6 39.6 30.2 25.1 19.6 12.5 12.5 %
+ */
+static const unsigned char max_reduction_table_v_2_2[13] = {
+0xf5, 0xe5, 0xbf, 0xb1, 0xa5, 0x85, 0x7c, 0x65, 0x4d, 0x40, 0x32, 0x20, 0x20};
+
+/* Predefined ABM configuration sets. We may have different configuration sets
+ * in order to satisfy different power/quality requirements.
+ */
+static const unsigned char abm_config[abm_defines_max_config][abm_defines_max_level] = {
+/* ABM Level 1, ABM Level 2, ABM Level 3, ABM Level 4 */
+{ 2, 5, 7, 8 }, /* Default - Medium aggressiveness */
+{ 2, 5, 8, 11 }, /* Alt #1 - Increased aggressiveness */
+{ 0, 2, 4, 8 }, /* Alt #2 - Minimal aggressiveness */
+{ 3, 6, 10, 12 }, /* Alt #3 - Super aggressiveness */
+};
+
+struct abm_parameters {
+ unsigned char min_reduction;
+ unsigned char max_reduction;
+ unsigned char bright_pos_gain;
+ unsigned char dark_pos_gain;
+ unsigned char brightness_gain;
+ unsigned char contrast_factor;
+ unsigned char deviation_gain;
+ unsigned char min_knee;
+ unsigned char max_knee;
+ unsigned short blRampReduction;
+ unsigned short blRampStart;
+};
+
+static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = {
+// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart
+ {0xff, 0xbf, 0x20, 0x00, 0xff, 0x99, 0xb3, 0x40, 0xe0, 0xf777, 0xcccc},
+ {0xde, 0x85, 0x20, 0x00, 0xe0, 0x90, 0xa8, 0x40, 0xc8, 0xf777, 0xcccc},
+ {0xb0, 0x50, 0x20, 0x00, 0xc0, 0x88, 0x78, 0x70, 0xa0, 0xeeee, 0x9999},
+ {0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xe333, 0xb333},
+};
+
+static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = {
+// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart
+ {0xf0, 0xd9, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
+ {0xcd, 0xa5, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
+ {0x99, 0x65, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
+ {0x82, 0x4d, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
+};
+
+static const struct abm_parameters abm_settings_config2[abm_defines_max_level] = {
+// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart
+ {0xf0, 0xbf, 0x20, 0x00, 0x88, 0x99, 0xb3, 0x40, 0xe0, 0x0000, 0xcccc},
+ {0xd8, 0x85, 0x20, 0x00, 0x70, 0x90, 0xa8, 0x40, 0xc8, 0x0700, 0xb333},
+ {0xb8, 0x58, 0x20, 0x00, 0x64, 0x88, 0x78, 0x70, 0xa0, 0x7000, 0x9999},
+ {0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xc333, 0xb333},
+};
+
+static const struct abm_parameters * const abm_settings[] = {
+ abm_settings_config0,
+ abm_settings_config1,
+ abm_settings_config2,
+};
+
+static const struct dm_bl_data_point custom_backlight_curve0[] = {
+ {2, 14}, {4, 16}, {6, 18}, {8, 21}, {10, 23}, {12, 26}, {14, 29}, {16, 32}, {18, 35},
+ {20, 38}, {22, 41}, {24, 44}, {26, 48}, {28, 52}, {30, 55}, {32, 59}, {34, 62},
+ {36, 67}, {38, 71}, {40, 75}, {42, 80}, {44, 84}, {46, 88}, {48, 93}, {50, 98},
+ {52, 103}, {54, 108}, {56, 113}, {58, 118}, {60, 123}, {62, 129}, {64, 135}, {66, 140},
+ {68, 146}, {70, 152}, {72, 158}, {74, 164}, {76, 171}, {78, 177}, {80, 183}, {82, 190},
+ {84, 197}, {86, 204}, {88, 211}, {90, 218}, {92, 225}, {94, 232}, {96, 240}, {98, 247}};
+
+struct custom_backlight_profile {
+ uint8_t ac_level_percentage;
+ uint8_t dc_level_percentage;
+ uint8_t min_input_signal;
+ uint8_t max_input_signal;
+ uint8_t num_data_points;
+ const struct dm_bl_data_point *data_points;
+};
+
+static const struct custom_backlight_profile custom_backlight_profiles[] = {
+ {100, 32, 12, 255, ARRAY_SIZE(custom_backlight_curve0), custom_backlight_curve0},
+};
+
+#define NUM_AMBI_LEVEL 5
+#define NUM_AGGR_LEVEL 4
+#define NUM_POWER_FN_SEGS 8
+#define NUM_BL_CURVE_SEGS 16
+#define IRAM_SIZE 256
+
+#define IRAM_RESERVE_AREA_START_V2 0xF0 // reserve 0xF0~0xF6 are write by DMCU only
+#define IRAM_RESERVE_AREA_END_V2 0xF6 // reserve 0xF0~0xF6 are write by DMCU only
+
+#define IRAM_RESERVE_AREA_START_V2_2 0xF0 // reserve 0xF0~0xFF are write by DMCU only
+#define IRAM_RESERVE_AREA_END_V2_2 0xFF // reserve 0xF0~0xFF are write by DMCU only
+
+#pragma pack(push, 1)
+/* NOTE: iRAM is 256B in size */
+struct iram_table_v_2 {
+ /* flags */
+ uint16_t min_abm_backlight; /* 0x00 U16 */
+
+ /* parameters for ABM2.0 algorithm */
+ uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */
+ uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */
+ uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */
+ uint8_t bright_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */
+ uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x52 U2.6 */
+ uint8_t dark_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x66 U2.6 */
+ uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x7a U0.8 */
+ uint8_t deviation_gain; /* 0x7f U0.8 */
+
+ /* parameters for crgb conversion */
+ uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */
+ uint16_t crgb_offset[NUM_POWER_FN_SEGS]; /* 0x90 U1.15 */
+ uint16_t crgb_slope[NUM_POWER_FN_SEGS]; /* 0xa0 U4.12 */
+
+ /* parameters for custom curve */
+ /* thresholds for brightness --> backlight */
+ uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; /* 0xb0 U16.0 */
+ /* offsets for brightness --> backlight */
+ uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; /* 0xd0 U16.0 */
+
+ /* For reading PSR State directly from IRAM */
+ uint8_t psr_state; /* 0xf0 */
+ uint8_t dmcu_mcp_interface_version; /* 0xf1 */
+ uint8_t dmcu_abm_feature_version; /* 0xf2 */
+ uint8_t dmcu_psr_feature_version; /* 0xf3 */
+ uint16_t dmcu_version; /* 0xf4 */
+ uint8_t dmcu_state; /* 0xf6 */
+
+ uint16_t blRampReduction; /* 0xf7 */
+ uint16_t blRampStart; /* 0xf9 */
+ uint8_t dummy5; /* 0xfb */
+ uint8_t dummy6; /* 0xfc */
+ uint8_t dummy7; /* 0xfd */
+ uint8_t dummy8; /* 0xfe */
+ uint8_t dummy9; /* 0xff */
+};
+
+struct iram_table_v_2_2 {
+ /* flags */
+ uint16_t flags; /* 0x00 U16 */
+
+ /* parameters for ABM2.2 algorithm */
+ uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */
+ uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */
+ uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */
+ uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */
+ uint8_t hybrid_factor[NUM_AGGR_LEVEL]; /* 0x52 U0.8 */
+ uint8_t contrast_factor[NUM_AGGR_LEVEL]; /* 0x56 U0.8 */
+ uint8_t deviation_gain[NUM_AGGR_LEVEL]; /* 0x5a U0.8 */
+ uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x5e U0.8 */
+ uint8_t min_knee[NUM_AGGR_LEVEL]; /* 0x63 U0.8 */
+ uint8_t max_knee[NUM_AGGR_LEVEL]; /* 0x67 U0.8 */
+ uint16_t min_abm_backlight; /* 0x6b U16 */
+ uint8_t pad[19]; /* 0x6d U0.8 */
+
+ /* parameters for crgb conversion */
+ uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */
+ uint16_t crgb_offset[NUM_POWER_FN_SEGS]; /* 0x90 U1.15 */
+ uint16_t crgb_slope[NUM_POWER_FN_SEGS]; /* 0xa0 U4.12 */
+
+ /* parameters for custom curve */
+ /* thresholds for brightness --> backlight */
+ uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; /* 0xb0 U16.0 */
+ /* offsets for brightness --> backlight */
+ uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; /* 0xd0 U16.0 */
+
+ /* For reading PSR State directly from IRAM */
+ uint8_t psr_state; /* 0xf0 */
+ uint8_t dmcu_mcp_interface_version; /* 0xf1 */
+ uint8_t dmcu_abm_feature_version; /* 0xf2 */
+ uint8_t dmcu_psr_feature_version; /* 0xf3 */
+ uint16_t dmcu_version; /* 0xf4 */
+ uint8_t dmcu_state; /* 0xf6 */
+
+ uint8_t dummy1; /* 0xf7 */
+ uint8_t dummy2; /* 0xf8 */
+ uint8_t dummy3; /* 0xf9 */
+ uint8_t dummy4; /* 0xfa */
+ uint8_t dummy5; /* 0xfb */
+ uint8_t dummy6; /* 0xfc */
+ uint8_t dummy7; /* 0xfd */
+ uint8_t dummy8; /* 0xfe */
+ uint8_t dummy9; /* 0xff */
+};
+#pragma pack(pop)
+
+#define MOD_POWER_MAX_CONCURRENT_STREAMS 32
+#define SMOOTH_BRIGHTNESS_ADJUSTMENT_TIME_IN_MS 500
+
+
+
+struct backlight_state {
+ /* HW uses u16.16 format for backlight PWM */
+ unsigned int backlight_pwm;
+ /* DM may call power module to set backlight
+ * targeting percent brightness
+ */
+ unsigned int backlight_millipercent;
+ /* DM may call power module to set backlight based on an explicit
+ * nits value.
+ */
+ unsigned int backlight_millinit;
+ unsigned int frame_ramp;
+ bool smooth_brightness_enabled;
+ bool isHDR;
+};
+struct power_entity {
+ struct dc_stream_state *stream;
+ struct psr_caps *caps;
+ struct mod_power_psr_context *psr_context;
+
+ /*PSR cached properties*/
+ bool psr_enabled;
+ unsigned int psr_events;
+ unsigned int psr_power_opt;
+ unsigned int replay_events;
+};
+
+struct pwr_backlight_properties {
+ bool use_nits_based_brightness;
+ bool disable_fractional_pwm;
+
+ unsigned int min_abm_backlight;
+ unsigned int num_backlight_levels;
+
+ bool backlight_ramping_override;
+ unsigned int backlight_ramping_reduction;
+ unsigned int backlight_ramping_start;
+
+ /* Backlight cached properties */
+ unsigned int ac_backlight_percent;
+ unsigned int dc_backlight_percent;
+
+ /* backlight LUT stored in HW u16.16 format*/
+ unsigned int *backlight_lut;
+ unsigned int min_backlight_pwm;
+ unsigned int max_backlight_pwm;
+ unsigned int backlight_range;
+
+ /* Describes the panel's min and max luminance in millinits measured
+ * on full white screen, in min and max backlight settings.
+ */
+ unsigned int min_brightness_millinits;
+ unsigned int max_brightness_millinits;
+ unsigned int nits_range;
+
+ bool backlight_caps_valid;
+ bool use_custom_backlight_caps;
+ unsigned int custom_backlight_caps_config_no;
+ bool use_linear_backlight_curve;
+};
+
+struct dmcu_varibright_cached_properties {
+ unsigned int varibright_config_setting;
+ unsigned int varibright_level;
+ unsigned int varibright_hw_level;
+ unsigned int def_varibright_level;
+ bool varibright_user_enable;
+ bool varibright_active;
+};
+
+struct core_power {
+ struct mod_power mod_public;
+ struct dc *dc;
+ struct power_entity *map;
+ struct dmcu_varibright_cached_properties varibright_prop;
+ struct pwr_backlight_properties bl_prop[MAX_NUM_EDP];
+ struct backlight_state bl_state[MAX_NUM_EDP];
+ unsigned int edp_num;
+
+ bool psr_smu_optimizations_support;
+ bool multi_disp_optimizations_support;
+
+ unsigned int num_entities;
+};
+
+union dmcu_abm_set_bl_params {
+ struct {
+ unsigned int gradual_change : 1; /* [0:0] */
+ unsigned int reserved : 15; /* [15:1] */
+ unsigned int frame_ramp : 16; /* [31:16] */
+ } bits;
+ unsigned int u32All;
+};
+
+/* If system or panel does not report some sort of brightness percent to nits
+ * mapping, we will use following default values so backlight control using
+ * nits based interfaces will still work, but might not describe panel
+ * correctly. In this case percentage based backlight control should ideally
+ * be used.
+ * Min = 5 nits
+ * Max = 300 nits
+ */
+
+#define MOD_POWER_TO_CORE(mod_power)\
+ container_of(mod_power, struct core_power, mod_public)
+
+
+
+static uint16_t backlight_8_to_16(unsigned int backlight_8bit)
+{
+ return (uint16_t)(backlight_8bit * 0x101);
+}
+
+unsigned int backlight_millipercent_to_millinit(
+ struct core_power *core_power, unsigned int millipercent, unsigned int inst)
+{
+ unsigned int millinit = 0;
+ unsigned long long numerator = 0;
+
+ if (core_power == NULL)
+ return 0;
+
+ numerator = ((unsigned long long)millipercent) *
+ core_power->bl_prop[inst].nits_range;
+ millinit = ((unsigned int)div_u64(numerator, 100000)) +
+ core_power->bl_prop[inst].min_brightness_millinits;
+
+ return millinit;
+}
+
+static unsigned int backlight_millinit_to_millipercent(
+ struct core_power *core_power, unsigned int millinit, unsigned int inst)
+{
+ unsigned int millipercent = 0;
+ unsigned long long numerator = 0;
+
+ if (core_power == NULL)
+ return 0;
+
+ if (millinit <= core_power->bl_prop[inst].min_brightness_millinits)
+ return 0;
+
+ if (millinit >= core_power->bl_prop[inst].max_brightness_millinits)
+ return (100 * 1000);
+
+ numerator = (((unsigned long long)millinit) -
+ core_power->bl_prop[inst].min_brightness_millinits) * 100000;
+ millipercent = ((unsigned int)div_u64(numerator,
+ core_power->bl_prop[inst].nits_range));
+
+ return millipercent;
+}
+
+static unsigned int backlight_pwm_to_millipercent(
+ struct core_power *core_power, unsigned int pwm, unsigned int inst)
+{
+ unsigned int millipercent = 0;
+ unsigned int max_index = 0;
+
+ if (core_power == NULL)
+ return 0;
+
+ if (!core_power->bl_prop[inst].backlight_caps_valid)
+ return 0;
+
+ /* Doesn't really make sense to have one single backlight level
+ * possible...
+ */
+ if (core_power->bl_prop[inst].num_backlight_levels < 2)
+ return 0;
+
+ max_index = core_power->bl_prop[inst].num_backlight_levels - 1;
+
+ if (pwm <= core_power->bl_prop[inst].backlight_lut[0])
+ return 0;
+
+ if (pwm > core_power->bl_prop[inst].backlight_lut[max_index])
+ return (100 * 1000);
+
+ /* We need to do a binary search over the array for where the pwm level
+ * is in the lut. Based on the index we can determine percentage.
+ */
+ unsigned int min = 0;
+ unsigned int max = max_index;
+ unsigned int mid = 0;
+
+ while (max >= min) {
+ mid = (min + max) / 2; /* floor of half range */
+
+ if (core_power->bl_prop[inst].backlight_lut[mid] < pwm)
+ min = mid + 1;
+ else if (core_power->bl_prop[inst].backlight_lut[mid] > pwm)
+ max = mid - 1;
+ else
+ break;
+ }
+
+ /* In this case, exact match is not found. Check if mid/min/max
+ * value is actually closer.
+ */
+ if (max < min) {
+ unsigned int min_delta;
+ unsigned int mid_delta;
+ unsigned int max_delta;
+
+ min_delta = (core_power->bl_prop[inst].backlight_lut[min] > pwm) ?
+ core_power->bl_prop[inst].backlight_lut[min] - pwm :
+ pwm - core_power->bl_prop[inst].backlight_lut[min];
+
+ mid_delta = (core_power->bl_prop[inst].backlight_lut[mid] > pwm) ?
+ core_power->bl_prop[inst].backlight_lut[mid] - pwm :
+ pwm - core_power->bl_prop[inst].backlight_lut[mid];
+
+ max_delta = (core_power->bl_prop[inst].backlight_lut[max] > pwm) ?
+ core_power->bl_prop[inst].backlight_lut[max] - pwm :
+ pwm - core_power->bl_prop[inst].backlight_lut[max];
+
+ if ((min_delta < mid_delta) && (min_delta < max_delta))
+ mid = min;
+
+ if ((max_delta < mid_delta) && (max_delta < min_delta))
+ mid = max;
+ }
+
+ /* No interpolation, just take closest index */
+ millipercent = 1000 * 100 * mid / max_index;
+
+ return millipercent;
+}
+
+static unsigned int backlight_pwm_to_millinit(
+ struct core_power *core_power, unsigned int pwm, unsigned int inst)
+{
+ unsigned int millinit = 0;
+
+ if (core_power == NULL)
+ return 0;
+
+ if (pwm <= core_power->bl_prop[inst].min_backlight_pwm)
+ return core_power->bl_prop[inst].min_brightness_millinits;
+
+ if (pwm >= core_power->bl_prop[inst].max_backlight_pwm)
+ return core_power->bl_prop[inst].max_brightness_millinits;
+
+ millinit = ((unsigned int)div_u64(((unsigned long long)pwm -
+ core_power->bl_prop[inst].min_backlight_pwm) *
+ core_power->bl_prop[inst].nits_range,
+ core_power->bl_prop[inst].backlight_range));
+
+ millinit += core_power->bl_prop[inst].min_brightness_millinits;
+
+ if (millinit > core_power->bl_prop[inst].max_brightness_millinits)
+ millinit = core_power->bl_prop[inst].max_brightness_millinits;
+
+ return millinit;
+}
+
+unsigned int backlight_millipercent_to_pwm(
+ struct core_power *core_power, unsigned int millipercent, unsigned int inst)
+{
+ unsigned int pwm = (unsigned int)-1;
+ unsigned int index = 0;
+
+ if (core_power == NULL)
+ return 0;
+
+ // Bypass the brightness mapping LUT
+ if (core_power->bl_prop->use_linear_backlight_curve) {
+ pwm = core_power->bl_prop[inst].min_backlight_pwm +
+ (unsigned int) div_u64((unsigned long long) millipercent *
+ core_power->bl_prop[inst].backlight_range,
+ 100000);
+
+ if (pwm > core_power->bl_prop[inst].max_backlight_pwm)
+ pwm = core_power->bl_prop[inst].max_backlight_pwm;
+
+ return pwm;
+ }
+
+ if (millipercent >= (100 * 1000))
+ return core_power->bl_prop[inst].backlight_lut[core_power->bl_prop[inst].num_backlight_levels - 1];
+
+ /* This will give the floor index. */
+ index = ((core_power->bl_prop[inst].num_backlight_levels - 1) *
+ millipercent) / 100000;
+ /* Null check otherwise eDP doesn't lightup when connected to DP1 */
+ if (core_power->bl_prop[inst].backlight_lut == NULL)
+ return pwm;
+
+ pwm = core_power->bl_prop[inst].backlight_lut[index];
+
+ return pwm;
+}
+
+static unsigned int backlight_millinit_to_pwm(
+ struct core_power *core_power, unsigned int millinit, unsigned int inst)
+{
+ unsigned int pwm = 0;
+
+ if (core_power == NULL)
+ return 0;
+
+ /* For nits based brightness, the signal will be a value
+ * between the minimum and maximum value.
+ */
+ if (millinit >= core_power->bl_prop[inst].max_brightness_millinits)
+ return core_power->bl_prop[inst].max_backlight_pwm;
+ else if (millinit <= core_power->bl_prop[inst].min_brightness_millinits)
+ return core_power->bl_prop[inst].min_backlight_pwm;
+
+ pwm = ((unsigned int)div_u64(((unsigned long long)millinit -
+ core_power->bl_prop[inst].min_brightness_millinits) *
+ core_power->bl_prop[inst].backlight_range,
+ core_power->bl_prop[inst].nits_range));
+
+ pwm += core_power->bl_prop[inst].min_backlight_pwm;
+
+ if (pwm > core_power->bl_prop[inst].max_backlight_pwm)
+ pwm = core_power->bl_prop[inst].max_backlight_pwm;
+
+ return pwm;
+}
+
+static bool validate_ext_backlight_caps(
+ struct dm_acpi_atif_backlight_caps *ext_backlight_caps)
+{
+ unsigned int i;
+ unsigned int num_of_data_points = 0;
+ unsigned int last_signal_level = 0;
+ unsigned int last_luminance = 0;
+
+ num_of_data_points = ext_backlight_caps->num_data_points;
+
+ /* Validation rules:
+ * 1. BIOS should carry customized data points and
+ * the number of data points should not be larger than 99.
+ * 2. The max_input_signal should be larger than min_input_signal.
+ * 3. For each data point:
+ * a. luminance should be in ascending order and
+ * should not be 0 or 100 since the corresponding signal_level
+ * are assigned by min_input_signal and max_input_signal.
+ * b. signal_level should be in ascending order and
+ * be within the range of min/max_input_signal.
+ */
+ if (num_of_data_points > BL_DATA_POINTS)
+ return false;
+
+ if (ext_backlight_caps->min_input_signal >= ext_backlight_caps->max_input_signal)
+ return false;
+
+ last_signal_level = ext_backlight_caps->min_input_signal;
+ for (i = 0; i < num_of_data_points; i++) {
+ unsigned int luminance = ext_backlight_caps->data_points[i].luminance;
+ unsigned int signal_level = ext_backlight_caps->data_points[i].signal_level;
+
+ if ((luminance <= last_luminance) || (luminance > BL_DATA_POINTS))
+ return false;
+
+ if ((signal_level <= last_signal_level) || (signal_level >= ext_backlight_caps->max_input_signal))
+ return false;
+
+ last_signal_level = signal_level;
+ last_luminance = luminance;
+ }
+
+ return true;
+}
+
+/* hard coded to default backlight curve. */
+void initialize_backlight_caps(struct core_power *core_power, unsigned int inst)
+{
+ unsigned int i;
+ struct dm_acpi_atif_backlight_caps *ext_backlight_caps = NULL;
+ bool custom_curve_present = false;
+ unsigned int num_levels = 0;
+ struct dc *dc = NULL;
+ enum dm_acpi_display_type acpi_display_type =
+ (inst == 0) ? AcpiDisplayType_LCD1 : AcpiDisplayType_LCD2;
+
+ if (core_power == NULL)
+ return;
+ dc = core_power->dc;
+
+ num_levels = core_power->bl_prop[inst].num_backlight_levels;
+
+ /* Allocate memory for ATIF output
+ * (do not want to use 256 bytes on the stack)
+ */
+ ext_backlight_caps = (struct dm_acpi_atif_backlight_caps *)
+ (kzalloc(sizeof(struct dm_acpi_atif_backlight_caps),
+ GFP_KERNEL));
+
+ if (ext_backlight_caps == NULL)
+ return;
+
+ /* Retrieve ACPI extended brightness caps */
+ if (dm_query_extended_brightness_caps
+ (dc->ctx, acpi_display_type, ext_backlight_caps)) {
+ custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps);
+ }
+
+ if (core_power->bl_prop[inst].use_custom_backlight_caps &&
+ fill_custom_backlight_caps(
+ core_power->bl_prop[inst].custom_backlight_caps_config_no,
+ ext_backlight_caps)) {
+ custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps);
+ }
+
+ if (custom_curve_present) {
+ unsigned int index = 1;
+ unsigned int num_of_data_points = ext_backlight_caps->num_data_points;
+
+ core_power->bl_prop[inst].ac_backlight_percent =
+ ext_backlight_caps->ac_level_percentage;
+ core_power->bl_prop[inst].dc_backlight_percent =
+ ext_backlight_caps->dc_level_percentage;
+ core_power->bl_prop[inst].backlight_lut[0] =
+ backlight_8_to_16(
+ ext_backlight_caps->min_input_signal);
+ core_power->bl_prop[inst].backlight_lut[num_levels - 1] =
+ backlight_8_to_16(
+ ext_backlight_caps->max_input_signal);
+
+ /* Filling translation table from data points -
+ * between every two provided data points we
+ * lineary interpolate missing values
+ */
+ for (i = 0; i < num_of_data_points; i++) {
+ unsigned int luminance =
+ ext_backlight_caps->data_points[i].luminance;
+ unsigned int signal_level =
+ backlight_8_to_16(
+ ext_backlight_caps->data_points[i].signal_level);
+
+ /* Since luminance is a percentage, scale it by num_levels*/
+ luminance = (luminance * num_levels) / 101;
+
+ /* Lineary interpolate missing values */
+ if (index < luminance) {
+ unsigned int base_value =
+ core_power->bl_prop[inst].backlight_lut[index-1];
+ unsigned int delta_signal =
+ signal_level - base_value;
+ unsigned int delta_luma =
+ luminance - index + 1;
+ unsigned int step = delta_signal;
+
+ for (; index < luminance; index++) {
+ core_power->bl_prop[inst].backlight_lut[index] =
+ base_value + (step / delta_luma);
+ step += delta_signal;
+ }
+ }
+
+ /* Now [index == luminance],
+ * so we can add data point to the translation table
+ */
+ core_power->bl_prop[inst].backlight_lut[index++] = signal_level;
+ }
+
+ /* Complete the final segment of interpolation -
+ * between last datapoint and maximum value
+ */
+ if (index < num_levels - 1) {
+ unsigned int base_value =
+ core_power->bl_prop[inst].backlight_lut[index-1];
+ unsigned int delta_signal =
+ core_power->bl_prop[inst].backlight_lut[num_levels - 1] -
+ base_value;
+ unsigned int delta_luma = num_levels - index;
+ unsigned int step = delta_signal;
+
+ for (; index < num_levels - 1; index++) {
+ core_power->bl_prop[inst].backlight_lut[index] =
+ base_value + (step / delta_luma);
+ step += delta_signal;
+ }
+ }
+ /* Build backlight translation table based on default curve */
+ } else {
+ /* Defines default backlight curve F(x) = A(x*x) + Bx + C.
+ *
+ * Backlight curve should always satisfy:
+ * F(0) = min, F(100) = max,
+ * So polynom coefficients are:
+ * A is 0.0255 - B/100 - min/10000 - (255-max)/10000 =
+ * (max - min)/10000 - B/100
+ * B is adjustable factor to modify the curve.
+ * Bigger B results in less concave curve.
+ * B range is [0..(max-min)/100]
+ * C is backlight minimum
+ */
+ unsigned int backlight_curve_coeff_a_factor =
+ num_levels * num_levels;
+ unsigned int backlight_curve_coeff_b = num_levels;
+ unsigned int delta =
+ core_power->bl_prop[inst].backlight_lut[num_levels - 1] -
+ core_power->bl_prop[inst].backlight_lut[0];
+ unsigned int coeffC = core_power->bl_prop[inst].backlight_lut[0];
+ unsigned int coeffB =
+ (backlight_curve_coeff_b < delta ?
+ backlight_curve_coeff_b : delta);
+ unsigned long long coeffA = delta - coeffB; /* coeffB is B*100 */
+
+ for (i = 1; i < num_levels - 1; i++) {
+ uint64_t lut_val = div_u64(coeffA * i * i, backlight_curve_coeff_a_factor) +
+ div_u64((uint64_t)coeffB * i, backlight_curve_coeff_b) + coeffC;
+
+ ASSERT(lut_val <= 0xFFFFFFFF);
+ core_power->bl_prop[inst].backlight_lut[i] = (unsigned int)lut_val;
+ }
+ }
+
+ if (ext_backlight_caps != NULL)
+ kfree(ext_backlight_caps);
+
+ /* Successfully initialized */
+ core_power->bl_prop[inst].backlight_caps_valid = true;
+}
+
+static void varibright_set_level(struct core_power *core_power)
+{
+ if (!core_power->varibright_prop.varibright_active ||
+ !core_power->varibright_prop.varibright_user_enable)
+ core_power->varibright_prop.varibright_hw_level = 0;
+ else
+ core_power->varibright_prop.varibright_hw_level =
+ core_power->varibright_prop.varibright_level;
+}
+
+bool mod_power_hw_init_backlight(struct mod_power *mod_power)
+{
+ struct core_power *core_power = NULL;
+ struct dc *dc = NULL;
+ struct dmcu *dmcu = NULL;
+ struct dmcu_iram_parameters params;
+ unsigned int i;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+ dc = core_power->dc;
+
+ for (i = 0; i < core_power->edp_num; i++) {
+ params.set = core_power->varibright_prop.varibright_config_setting;
+ params.backlight_ramping_override = core_power->bl_prop[i].backlight_ramping_override;
+ params.backlight_ramping_reduction = core_power->bl_prop[i].backlight_ramping_reduction;
+ params.backlight_ramping_start = core_power->bl_prop[i].backlight_ramping_start;
+ params.backlight_lut_array = core_power->bl_prop[i].backlight_lut;
+ params.backlight_lut_array_size = core_power->bl_prop[i].num_backlight_levels;
+ params.min_abm_backlight = core_power->bl_prop[i].min_abm_backlight;
+
+ dmcu = dc->res_pool->dmcu;
+
+ // In the case where abm is implemented on dmcub,
+ // dmcu object will be null.
+ // ABM 2.4 and up are implemented on dmcub.
+ if (dmcu) {
+ //DMCU does not support multiple eDP
+ return dmcu_load_iram(dmcu, params);
+ } else if (dc->ctx->dmub_srv) {
+ if (!dmub_init_abm_config(dc->res_pool, params, i))
+ return false;
+ } else
+ return false;
+ }
+ return true;
+}
+
+void mod_power_update_backlight_on_mode_change(
+ struct core_power *core_power,
+ struct dc_link *link,
+ unsigned int panel_inst,
+ uint8_t aux_inst,
+ bool is_hdr)
+{
+ struct set_backlight_level_params backlight_level_params = { 0 };
+
+ if (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
+ link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
+ dc_link_set_backlight_level_nits(link, core_power->bl_state[panel_inst].isHDR,
+ core_power->bl_state[panel_inst].backlight_millinit, 0);
+
+ backlight_level_params.frame_ramp = 0;
+
+ fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, aux_inst,
+ core_power->bl_state[panel_inst].backlight_pwm, link->backlight_control_type,
+ core_power->bl_state[panel_inst].backlight_millinit, 0, is_hdr);
+
+ dc_link_set_backlight_level(link, &backlight_level_params);
+}
+
+static bool set_backlight_millinits_aux(struct core_power *core_power,
+ struct dc_stream_state *stream,
+ unsigned int backlight_millinits,
+ unsigned int transition_time_millisec,
+ unsigned int inst)
+{
+ struct dc_link *link = NULL;
+
+ if (core_power == NULL)
+ return false;
+
+ if (stream == NULL)
+ return true;
+
+ link = dc_stream_get_link(stream);
+
+ return dc_link_set_backlight_level_nits(link, core_power->bl_state[inst].isHDR,
+ backlight_millinits, transition_time_millisec);
+}
+
+static bool set_backlight(struct core_power *core_power,
+ struct dc_stream_state *stream,
+ struct set_backlight_level_params *backlight_level_params,
+ unsigned int inst)
+{
+ bool retv = false;
+ unsigned int frame_ramp = 0;
+ unsigned int vsync_rate_hz;
+ union dmcu_abm_set_bl_params params;
+ const struct dc_link *link = NULL;
+ unsigned int backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16;
+ unsigned int transition_time_millisec = backlight_level_params->transition_time_in_ms;
+
+ if (core_power == NULL)
+ return false;
+
+ core_power->bl_state[inst].backlight_pwm = backlight_pwm_u16_16;
+
+ if (stream == NULL)
+ return true;
+
+ if (stream->link->connector_signal != SIGNAL_TYPE_EDP)
+ return false;
+
+ if (transition_time_millisec != 0) {
+ unsigned int v_total =
+ (stream->adjust.v_total_max == 0) ? stream->timing.v_total : stream->adjust.v_total_max;
+
+ vsync_rate_hz = (unsigned int)div_u64(div_u64((stream->
+ timing.pix_clk_100hz * 100),
+ v_total),
+ stream->timing.h_total);
+
+ if (core_power->bl_state[inst].smooth_brightness_enabled)
+ frame_ramp = ((vsync_rate_hz *
+ transition_time_millisec) + 500) / 1000;
+ }
+
+ core_power->bl_state[inst].frame_ramp = frame_ramp;
+ params.u32All = 0;
+ params.bits.gradual_change = (frame_ramp > 0);
+ params.bits.frame_ramp = frame_ramp;
+ link = dc_stream_get_link(stream);
+
+ mod_power_set_psr_event(&core_power->mod_public, stream, true, psr_event_hw_programming, true);
+ mod_power_set_replay_event(&core_power->mod_public, stream, true, replay_event_hw_programming, true);
+
+ backlight_level_params->frame_ramp = params.u32All;
+ retv = dc_link_set_backlight_level(link, backlight_level_params);
+
+ mod_power_set_psr_event(&core_power->mod_public, stream, false, psr_event_hw_programming, false);
+ mod_power_set_replay_event(&core_power->mod_public, stream, false, replay_event_hw_programming, false);
+
+ return retv;
+}
+
+void fill_backlight_level_params(struct core_power *core_power,
+ struct set_backlight_level_params *backlight_level_params,
+ int panel_inst, uint8_t aux_inst, unsigned int backlight_pwm,
+ enum backlight_control_type backlight_control_type,
+ unsigned int backlight_millinit, unsigned int transition_time_millisec,
+ bool is_hdr)
+{
+ struct pwr_backlight_properties *bl_prop = &core_power->bl_prop[panel_inst];
+
+ backlight_level_params->aux_inst = aux_inst;
+ backlight_level_params->backlight_pwm_u16_16 = backlight_pwm;
+ backlight_level_params->control_type = backlight_control_type;
+ backlight_level_params->backlight_millinits = backlight_millinit;
+ backlight_level_params->transition_time_in_ms = transition_time_millisec;
+ backlight_level_params->min_luminance = bl_prop->min_brightness_millinits;
+ backlight_level_params->max_luminance = bl_prop->max_brightness_millinits;
+ backlight_level_params->min_backlight_pwm = bl_prop->min_backlight_pwm;
+ backlight_level_params->max_backlight_pwm = bl_prop->max_backlight_pwm;
+
+ if (backlight_control_type == BACKLIGHT_CONTROL_AMD_AUX && !is_hdr)
+ backlight_level_params->control_type = BACKLIGHT_CONTROL_PWM;
+}
+
+bool mod_power_set_backlight_nits(struct mod_power *mod_power,
+ struct dc_stream_state *stream,
+ unsigned int backlight_millinit,
+ unsigned int transition_time_millisec,
+ bool skip_aux,
+ bool is_hdr)
+{
+ struct core_power *core_power = NULL;
+ unsigned int backlight_pwm;
+ unsigned int panel_inst = 0;
+ struct set_backlight_level_params backlight_level_params = { 0 };
+ const struct dc_link *link = NULL;
+ uint8_t aux_inst = 0;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+ link = dc_stream_get_link(stream);
+
+ ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF);
+ aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel;
+
+ if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst))
+ return false;
+
+ if (!skip_aux) {
+ if (!set_backlight_millinits_aux(core_power, stream,
+ backlight_millinit, transition_time_millisec, panel_inst))
+ return false;
+ }
+// always send both AUX (above) and PWM (below)
+ core_power->bl_state[panel_inst].backlight_millinit = backlight_millinit;
+
+ core_power->bl_state[panel_inst].backlight_millipercent =
+ backlight_millinit_to_millipercent(
+ core_power, backlight_millinit, panel_inst);
+
+ backlight_pwm = backlight_millinit_to_pwm(
+ core_power, backlight_millinit, panel_inst);
+
+ fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, aux_inst, backlight_pwm,
+ link->backlight_control_type, backlight_millinit, transition_time_millisec, is_hdr);
+
+ return set_backlight(core_power, stream,
+ &backlight_level_params, panel_inst);
+}
+
+bool mod_power_backlight_percent_to_nits(struct mod_power *mod_power,
+ struct dc_stream_state *stream,
+ unsigned int backlight_millipercent,
+ unsigned int *backlight_millinit)
+{
+ struct core_power *core_power = NULL;
+ unsigned int inst = 0;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
+ return false;
+
+ *backlight_millinit = backlight_millipercent_to_millinit(
+ core_power, backlight_millipercent, inst);
+ return true;
+}
+
+bool mod_power_backlight_nits_to_percent(struct mod_power *mod_power,
+ struct dc_stream_state *stream,
+ unsigned int backlight_millinit,
+ unsigned int *backlight_millipercent)
+{
+ struct core_power *core_power = NULL;
+ unsigned int inst = 0;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
+ return false;
+
+ *backlight_millipercent = backlight_millinit_to_millipercent(
+ core_power, backlight_millinit, inst);
+ return true;
+}
+
+bool mod_power_set_backlight_percent(struct mod_power *mod_power,
+ struct dc_stream_state *stream,
+ unsigned int backlight_millipercent,
+ unsigned int transition_time_millisec,
+ bool is_hdr)
+{
+ struct core_power *core_power = NULL;
+ struct set_backlight_level_params backlight_level_params = { 0 };
+ const struct dc_link *link = NULL;
+ unsigned int backlight_pwm;
+ unsigned int panel_inst = 0;
+ uint8_t aux_inst = 0;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+ link = dc_stream_get_link(stream);
+ ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF);
+ aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel;
+
+ if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst))
+ return false;
+ core_power->bl_state[panel_inst].backlight_millipercent = backlight_millipercent;
+
+ core_power->bl_state[panel_inst].backlight_millinit =
+ backlight_millipercent_to_millinit(
+ core_power, backlight_millipercent, panel_inst);
+
+ backlight_pwm = backlight_millipercent_to_pwm(
+ core_power, backlight_millipercent, panel_inst);
+
+ fill_backlight_level_params(core_power, &backlight_level_params, panel_inst,
+ aux_inst, backlight_pwm, link->backlight_control_type,
+ core_power->bl_state[panel_inst].backlight_millinit, transition_time_millisec, is_hdr);
+
+ return set_backlight(core_power, stream,
+ &backlight_level_params, panel_inst);
+}
+
+void mod_power_update_backlight(struct mod_power *mod_power,
+ struct dc_stream_state *stream,
+ unsigned int backlight_millipercent)
+{
+ struct core_power *core_power = NULL;
+ unsigned int inst = 0;
+
+ if (mod_power == NULL)
+ return;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
+ return;
+ core_power->bl_state[inst].backlight_millipercent = backlight_millipercent;
+
+ core_power->bl_state[inst].backlight_millinit =
+ backlight_millipercent_to_millinit(
+ core_power, backlight_millipercent, inst);
+
+ core_power->bl_state[inst].backlight_pwm = backlight_millipercent_to_pwm(
+ core_power, backlight_millipercent, inst);
+}
+
+void mod_power_update_backlight_nits(struct mod_power *mod_power,
+ struct dc_stream_state *stream,
+ unsigned int backlight_millinit)
+{
+ struct core_power *core_power = NULL;
+ unsigned int inst = 0;
+
+ if (mod_power == NULL)
+ return;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
+ return;
+
+ core_power->bl_state[inst].backlight_millinit = backlight_millinit;
+
+ core_power->bl_state[inst].backlight_millipercent = backlight_millinit_to_millipercent(
+ core_power, backlight_millinit, inst);
+ core_power->bl_state[inst].backlight_pwm = backlight_millinit_to_pwm(
+ core_power, backlight_millinit, inst);
+}
+
+bool mod_power_get_backlight_pwm(struct mod_power *mod_power,
+ unsigned int *backlight_pwm,
+ unsigned int inst)
+{
+ struct core_power *core_power = NULL;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ *backlight_pwm = core_power->bl_state[inst].backlight_pwm;
+
+ return true;
+}
+
+bool mod_power_get_backlight_nits(struct mod_power *mod_power,
+ unsigned int *backlight_millinit,
+ unsigned int inst)
+{
+ struct core_power *core_power = NULL;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ *backlight_millinit = core_power->bl_state[inst].backlight_millinit;
+
+ return true;
+}
+
+bool mod_power_get_backlight_percent(struct mod_power *mod_power,
+ unsigned int *backlight_millipercent,
+ unsigned int inst)
+{
+ struct core_power *core_power = NULL;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ *backlight_millipercent = core_power->bl_state[inst].backlight_millipercent;
+
+ return true;
+}
+
+bool mod_power_get_hw_target_backlight_pwm_nits(struct mod_power *mod_power,
+ const struct dc_link *link,
+ unsigned int *backlight_millinit,
+ unsigned int inst)
+{
+ struct core_power *core_power = NULL;
+ unsigned int backlight_u16_16 = 0;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ if (mod_power_get_hw_target_backlight_pwm(mod_power, link,
+ &backlight_u16_16)) {
+ *backlight_millinit =
+ backlight_pwm_to_millinit(core_power,
+ backlight_u16_16, inst);
+ return true;
+ }
+ return false;
+}
+
+bool mod_power_get_hw_target_backlight_pwm_percent(struct mod_power *mod_power,
+ const struct dc_link *link,
+ unsigned int *backlight_millipercent,
+ unsigned int inst)
+{
+ struct core_power *core_power = NULL;
+ unsigned int backlight_u16_16 = 0;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ if (mod_power_get_hw_target_backlight_pwm(mod_power, link,
+ &backlight_u16_16)) {
+ *backlight_millipercent =
+ backlight_pwm_to_millipercent(core_power,
+ backlight_u16_16, inst);
+ return true;
+ }
+ return false;
+}
+
+bool mod_power_get_hw_target_backlight_pwm(struct mod_power *mod_power,
+ const struct dc_link *link,
+ unsigned int *backlight_u16_16)
+{
+ if (mod_power == NULL)
+ return false;
+
+ *backlight_u16_16 = dc_link_get_target_backlight_pwm(link);
+
+ return true;
+}
+
+bool mod_power_get_hw_backlight_pwm_nits(struct mod_power *mod_power,
+ const struct dc_link *link,
+ unsigned int *backlight_millinit,
+ unsigned int inst)
+{
+ struct core_power *core_power = NULL;
+ unsigned int backlight_u16_16 = 0;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ if (mod_power_get_hw_backlight_pwm(mod_power, link, &backlight_u16_16)) {
+ *backlight_millinit =
+ backlight_pwm_to_millinit(core_power,
+ backlight_u16_16, inst);
+ return true;
+ }
+ return false;
+}
+
+bool mod_power_get_hw_backlight_aux_nits(struct mod_power *mod_power,
+ struct dc_stream_state **streams, int num_streams,
+ unsigned int *backlight_millinit_avg,
+ unsigned int *backlight_millinit_peak)
+{
+ struct core_power *core_power = NULL;
+ struct dc_link *link = NULL;
+ int stream_index;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ if (core_power == NULL)
+ return false;
+
+ if (num_streams < 1)
+ return true;
+
+ for (stream_index = 0; stream_index < num_streams; stream_index++)
+ if (streams[stream_index]->link->connector_signal == SIGNAL_TYPE_EDP ||
+ streams[stream_index]->link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT)
+ break;
+
+ if (stream_index == num_streams)
+ return false;
+
+ link = dc_stream_get_link(streams[stream_index]);
+ if (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 0)
+ return false;
+
+ return dc_link_get_backlight_level_nits(link, backlight_millinit_avg,
+ backlight_millinit_peak);
+}
+
+bool mod_power_get_hw_backlight_pwm_percent(struct mod_power *mod_power,
+ const struct dc_link *link,
+ unsigned int *backlight_millipercent,
+ unsigned int inst)
+{
+ struct core_power *core_power = NULL;
+ unsigned int backlight_u16_16 = 0;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ if (mod_power_get_hw_backlight_pwm(mod_power, link, &backlight_u16_16)) {
+ *backlight_millipercent =
+ backlight_pwm_to_millipercent(core_power,
+ backlight_u16_16, inst);
+ return true;
+ }
+ return false;
+}
+
+bool mod_power_get_hw_backlight_pwm(struct mod_power *mod_power,
+ const struct dc_link *link,
+ unsigned int *backlight_u16_16)
+{
+ if (mod_power == NULL)
+ return false;
+
+ *backlight_u16_16 = dc_link_get_backlight_level(link);
+
+ return true;
+}
+
+bool mod_power_get_panel_backlight_boundaries(
+ struct mod_power *mod_power,
+ unsigned int *out_min_backlight,
+ unsigned int *out_max_backlight,
+ unsigned int *out_ac_backlight_percent,
+ unsigned int *out_dc_backlight_percent,
+ unsigned int inst)
+{
+ struct core_power *core_power = NULL;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ /* If cache was successfully updated,
+ * copy the values to output structure and return success
+ */
+ if (core_power->bl_prop[inst].backlight_caps_valid) {
+ *out_min_backlight = core_power->bl_prop[inst].backlight_lut[0];
+ *out_max_backlight =
+ core_power->bl_prop[inst].backlight_lut[
+ core_power->bl_prop[inst].num_backlight_levels - 1];
+ *out_ac_backlight_percent =
+ core_power->bl_prop[inst].ac_backlight_percent;
+ *out_dc_backlight_percent =
+ core_power->bl_prop[inst].dc_backlight_percent;
+
+ return true;
+ }
+
+ return false;
+}
+
+bool mod_power_set_smooth_brightness(struct mod_power *mod_power,
+ bool enable_brightness,
+ unsigned int inst)
+{
+ struct core_power *core_power = NULL;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ core_power->bl_state[inst].smooth_brightness_enabled = enable_brightness;
+
+ return true;
+}
+
+bool mod_power_varibright_feature_enable(struct mod_power *mod_power, bool enable,
+ struct dc_stream_update *stream_update)
+{
+ struct core_power *core_power = NULL;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+ core_power->varibright_prop.varibright_user_enable = enable;
+
+ /* find abm hw level to program, and save in stream update */
+ varibright_set_level(core_power);
+ *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level;
+
+ DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+ WPP_BIT_FLAG_Backlight_ABM,
+ ">ABM feature enable: enable=%u su->varibright_level=%u varibright_hw_level=%u",
+ (unsigned int) enable,
+ *stream_update->abm_level,
+ core_power->varibright_prop.varibright_hw_level);
+ return true;
+}
+
+bool mod_power_varibright_activate(struct mod_power *mod_power,
+ bool activate,
+ struct dc_stream_update *stream_update)
+{
+ struct core_power *core_power = NULL;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+ core_power->varibright_prop.varibright_active = activate;
+
+ /* find abm hw level to program, and save in stream update */
+ varibright_set_level(core_power);
+ *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level;
+
+ DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+ WPP_BIT_FLAG_Backlight_ABM,
+ ">ABM activate: activate=%u su->varibright_level=%u",
+ (unsigned int) activate,
+ *stream_update->abm_level);
+ return true;
+}
+bool mod_power_varibright_set_level(struct mod_power *mod_power, unsigned int level,
+ struct dc_stream_update *stream_update)
+{
+ struct core_power *core_power = NULL;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+ core_power->varibright_prop.varibright_level = level;
+ core_power->varibright_prop.varibright_hw_level = level;
+
+ /* find abm hw level to program, and save in stream update */
+ varibright_set_level(core_power);
+ *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level;
+
+ DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+ WPP_BIT_FLAG_Backlight_ABM,
+ ">ABM set level: level=%u -> (varibright_level=%u varibright_hw_level=%u) -> su->varibright_level=%u",
+ level,
+ core_power->varibright_prop.varibright_level,
+ core_power->varibright_prop.varibright_hw_level,
+ *stream_update->abm_level);
+ return true;
+}
+
+bool mod_power_varibright_set_hw_level(struct mod_power *mod_power, unsigned int level,
+ struct dc_stream_update *stream_update)
+{
+ struct core_power *core_power = NULL;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ if (level == 0 || level == ABM_LEVEL_IMMEDIATE_DISABLE)
+ core_power->varibright_prop.varibright_active = 0;
+ else
+ core_power->varibright_prop.varibright_active = 1;
+ core_power->varibright_prop.varibright_hw_level = level;
+ *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level;
+
+ DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+ WPP_BIT_FLAG_Backlight_ABM,
+ ">ABM set level: level=%u -> (varibright_level=%u varibright_hw_level=%u) -> su->varibright_level=%u",
+ level,
+ core_power->varibright_prop.varibright_level,
+ core_power->varibright_prop.varibright_hw_level,
+ *stream_update->abm_level);
+ return true;
+}
+
+bool mod_power_get_varibright_level(struct mod_power *mod_power,
+ unsigned int *varibright_level)
+{
+ struct core_power *core_power = NULL;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ *varibright_level = core_power->varibright_prop.varibright_level;
+
+ DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+ WPP_BIT_FLAG_Backlight_ABM,
+ ">get varibright level: cp->varibright_level=%u",
+ *varibright_level);
+ return true;
+
+}
+
+bool mod_power_get_varibright_hw_level(struct mod_power *mod_power,
+ unsigned int *varibright_level)
+{
+ struct core_power *core_power = NULL;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ *varibright_level = core_power->varibright_prop.varibright_hw_level;
+ DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+ WPP_BIT_FLAG_Backlight_ABM,
+ ">get varibright HW level: hw_level=%u",
+ *varibright_level);
+ return true;
+}
+
+bool mod_power_get_varibright_default_level(struct mod_power *mod_power,
+ unsigned int *varibright_level)
+{
+ struct core_power *core_power = NULL;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ *varibright_level = core_power->varibright_prop.def_varibright_level;
+ DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+ WPP_BIT_FLAG_Backlight_ABM,
+ ">get varibright default level: def_varibright_level=%u",
+ *varibright_level);
+ return true;
+}
+
+bool mod_power_get_varibright_enable(struct mod_power *mod_power,
+ bool *varibright_enable)
+{
+ struct core_power *core_power = NULL;
+
+ if (mod_power == NULL)
+ return false;
+
+ core_power = MOD_POWER_TO_CORE(mod_power);
+
+ *varibright_enable = core_power->varibright_prop.varibright_user_enable;
+ DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+ WPP_BIT_FLAG_Backlight_ABM,
+ ">get varibright enable state: varibright_user_enable=%u",
+ (unsigned int) (*varibright_enable));
+ return true;
+}
+
+bool mod_power_is_abm_active(struct mod_power *mod_power,
+ const struct dc_link *link,
+ unsigned int inst)
+{
+ unsigned int user_backlight = 0;
+ unsigned int current_backlight = 0;
+ bool is_active = false;
+
+ if (mod_power == NULL)
+ return false;
+
+ mod_power_get_backlight_pwm(mod_power, &user_backlight, inst);
+ mod_power_get_hw_backlight_pwm(mod_power, link, ¤t_backlight);
+
+ if (user_backlight != current_backlight)
+ is_active = true;
+ else
+ is_active = false;
+ DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+ WPP_BIT_FLAG_Backlight_ABM,
+ ">get ABM active state: is_active=%u (user_backlight_pwm=%u, current_backlight_pwm=%u)",
+ (unsigned int)is_active,
+ user_backlight,
+ current_backlight);
+ return is_active;
+}
+
+static void fill_backlight_transform_table(struct dmcu_iram_parameters params,
+ struct iram_table_v_2 *table)
+{
+ unsigned int i;
+ unsigned int num_entries = NUM_BL_CURVE_SEGS;
+ unsigned int lut_index;
+
+ table->backlight_thresholds[0] = 0;
+ ASSERT(params.backlight_lut_array[0] <= 0xFFFF);
+ table->backlight_offsets[0] = (uint16_t)params.backlight_lut_array[0];
+ table->backlight_thresholds[num_entries-1] = 0xFFFF;
+ ASSERT(params.backlight_lut_array[params.backlight_lut_array_size - 1] <= 0xFFFF);
+ table->backlight_offsets[num_entries-1] =
+ (uint16_t)params.backlight_lut_array[params.backlight_lut_array_size - 1];
+
+ /* Setup all brightness levels between 0% and 100% exclusive
+ * Fills brightness-to-backlight transform table. Backlight custom curve
+ * describes transform from brightness to backlight. It will be defined
+ * as set of thresholds and set of offsets, together, implying
+ * extrapolation of custom curve into 16 uniformly spanned linear
+ * segments. Each threshold/offset represented by 16 bit entry in
+ * format U4.10.
+ */
+ for (i = 1; i+1 < num_entries; i++) {
+ lut_index = (params.backlight_lut_array_size - 1) * i / (num_entries - 1);
+
+ ASSERT(lut_index < params.backlight_lut_array_size);
+
+ unsigned int threshold_val = DIV_ROUNDUP((i * 65536), num_entries);
+ unsigned int offset_val = params.backlight_lut_array[lut_index];
+
+ ASSERT(threshold_val <= 0xFFFF);
+ ASSERT(offset_val <= 0xFFFF);
+
+ table->backlight_thresholds[i] = cpu_to_be16((uint16_t)threshold_val);
+ table->backlight_offsets[i] = cpu_to_be16((uint16_t)offset_val);
+ }
+}
+
+static void fill_backlight_transform_table_v_2_2(struct dmcu_iram_parameters params,
+ struct iram_table_v_2_2 *table, bool big_endian)
+{
+ unsigned int i;
+ unsigned int num_entries = NUM_BL_CURVE_SEGS;
+ unsigned int lut_index;
+
+ table->backlight_thresholds[0] = 0;
+ ASSERT(params.backlight_lut_array[0] <= 0xFFFF);
+ table->backlight_offsets[0] = (uint16_t)params.backlight_lut_array[0];
+ table->backlight_thresholds[num_entries-1] = 0xFFFF;
+ ASSERT(params.backlight_lut_array[params.backlight_lut_array_size - 1] <= 0xFFFF);
+ table->backlight_offsets[num_entries-1] =
+ (uint16_t)params.backlight_lut_array[params.backlight_lut_array_size - 1];
+
+ /* Setup all brightness levels between 0% and 100% exclusive
+ * Fills brightness-to-backlight transform table. Backlight custom curve
+ * describes transform from brightness to backlight. It will be defined
+ * as set of thresholds and set of offsets, together, implying
+ * extrapolation of custom curve into 16 uniformly spanned linear
+ * segments. Each threshold/offset represented by 16 bit entry in
+ * format U4.10.
+ */
+ for (i = 1; i+1 < num_entries; i++) {
+ lut_index = DIV_ROUNDUP((i * params.backlight_lut_array_size), num_entries);
+ ASSERT(lut_index < params.backlight_lut_array_size);
+
+ unsigned int threshold_val = DIV_ROUNDUP((i * 65536), num_entries);
+ unsigned int offset_val = params.backlight_lut_array[lut_index];
+
+ ASSERT(threshold_val <= 0xFFFF);
+ ASSERT(offset_val <= 0xFFFF);
+
+ table->backlight_thresholds[i] = (big_endian) ?
+ cpu_to_be16((uint16_t)threshold_val) : cpu_to_le16((uint16_t)threshold_val);
+ table->backlight_offsets[i] = (big_endian) ?
+ cpu_to_be16((uint16_t)offset_val) : cpu_to_le16((uint16_t)offset_val);
+ }
+}
+
+static void fill_iram_v_2(struct iram_table_v_2 *ram_table, struct dmcu_iram_parameters params)
+{
+ unsigned int set = params.set;
+
+ ram_table->min_abm_backlight =
+ cpu_to_be16(params.min_abm_backlight);
+ ram_table->deviation_gain = 0xb3;
+
+ ram_table->blRampReduction =
+ cpu_to_be16(params.backlight_ramping_reduction);
+ ram_table->blRampStart =
+ cpu_to_be16(params.backlight_ramping_start);
+
+ ram_table->min_reduction[0][0] = min_reduction_table[abm_config[set][0]];
+ ram_table->min_reduction[1][0] = min_reduction_table[abm_config[set][0]];
+ ram_table->min_reduction[2][0] = min_reduction_table[abm_config[set][0]];
+ ram_table->min_reduction[3][0] = min_reduction_table[abm_config[set][0]];
+ ram_table->min_reduction[4][0] = min_reduction_table[abm_config[set][0]];
+ ram_table->max_reduction[0][0] = max_reduction_table[abm_config[set][0]];
+ ram_table->max_reduction[1][0] = max_reduction_table[abm_config[set][0]];
+ ram_table->max_reduction[2][0] = max_reduction_table[abm_config[set][0]];
+ ram_table->max_reduction[3][0] = max_reduction_table[abm_config[set][0]];
+ ram_table->max_reduction[4][0] = max_reduction_table[abm_config[set][0]];
+
+ ram_table->min_reduction[0][1] = min_reduction_table[abm_config[set][1]];
+ ram_table->min_reduction[1][1] = min_reduction_table[abm_config[set][1]];
+ ram_table->min_reduction[2][1] = min_reduction_table[abm_config[set][1]];
+ ram_table->min_reduction[3][1] = min_reduction_table[abm_config[set][1]];
+ ram_table->min_reduction[4][1] = min_reduction_table[abm_config[set][1]];
+ ram_table->max_reduction[0][1] = max_reduction_table[abm_config[set][1]];
+ ram_table->max_reduction[1][1] = max_reduction_table[abm_config[set][1]];
+ ram_table->max_reduction[2][1] = max_reduction_table[abm_config[set][1]];
+ ram_table->max_reduction[3][1] = max_reduction_table[abm_config[set][1]];
+ ram_table->max_reduction[4][1] = max_reduction_table[abm_config[set][1]];
+
+ ram_table->min_reduction[0][2] = min_reduction_table[abm_config[set][2]];
+ ram_table->min_reduction[1][2] = min_reduction_table[abm_config[set][2]];
+ ram_table->min_reduction[2][2] = min_reduction_table[abm_config[set][2]];
+ ram_table->min_reduction[3][2] = min_reduction_table[abm_config[set][2]];
+ ram_table->min_reduction[4][2] = min_reduction_table[abm_config[set][2]];
+ ram_table->max_reduction[0][2] = max_reduction_table[abm_config[set][2]];
+ ram_table->max_reduction[1][2] = max_reduction_table[abm_config[set][2]];
+ ram_table->max_reduction[2][2] = max_reduction_table[abm_config[set][2]];
+ ram_table->max_reduction[3][2] = max_reduction_table[abm_config[set][2]];
+ ram_table->max_reduction[4][2] = max_reduction_table[abm_config[set][2]];
+
+ ram_table->min_reduction[0][3] = min_reduction_table[abm_config[set][3]];
+ ram_table->min_reduction[1][3] = min_reduction_table[abm_config[set][3]];
+ ram_table->min_reduction[2][3] = min_reduction_table[abm_config[set][3]];
+ ram_table->min_reduction[3][3] = min_reduction_table[abm_config[set][3]];
+ ram_table->min_reduction[4][3] = min_reduction_table[abm_config[set][3]];
+ ram_table->max_reduction[0][3] = max_reduction_table[abm_config[set][3]];
+ ram_table->max_reduction[1][3] = max_reduction_table[abm_config[set][3]];
+ ram_table->max_reduction[2][3] = max_reduction_table[abm_config[set][3]];
+ ram_table->max_reduction[3][3] = max_reduction_table[abm_config[set][3]];
+ ram_table->max_reduction[4][3] = max_reduction_table[abm_config[set][3]];
+
+ ram_table->bright_pos_gain[0][0] = 0x20;
+ ram_table->bright_pos_gain[0][1] = 0x20;
+ ram_table->bright_pos_gain[0][2] = 0x20;
+ ram_table->bright_pos_gain[0][3] = 0x20;
+ ram_table->bright_pos_gain[1][0] = 0x20;
+ ram_table->bright_pos_gain[1][1] = 0x20;
+ ram_table->bright_pos_gain[1][2] = 0x20;
+ ram_table->bright_pos_gain[1][3] = 0x20;
+ ram_table->bright_pos_gain[2][0] = 0x20;
+ ram_table->bright_pos_gain[2][1] = 0x20;
+ ram_table->bright_pos_gain[2][2] = 0x20;
+ ram_table->bright_pos_gain[2][3] = 0x20;
+ ram_table->bright_pos_gain[3][0] = 0x20;
+ ram_table->bright_pos_gain[3][1] = 0x20;
+ ram_table->bright_pos_gain[3][2] = 0x20;
+ ram_table->bright_pos_gain[3][3] = 0x20;
+ ram_table->bright_pos_gain[4][0] = 0x20;
+ ram_table->bright_pos_gain[4][1] = 0x20;
+ ram_table->bright_pos_gain[4][2] = 0x20;
+ ram_table->bright_pos_gain[4][3] = 0x20;
+ ram_table->bright_neg_gain[0][0] = 0x00;
+ ram_table->bright_neg_gain[0][1] = 0x00;
+ ram_table->bright_neg_gain[0][2] = 0x00;
+ ram_table->bright_neg_gain[0][3] = 0x00;
+ ram_table->bright_neg_gain[1][0] = 0x00;
+ ram_table->bright_neg_gain[1][1] = 0x00;
+ ram_table->bright_neg_gain[1][2] = 0x00;
+ ram_table->bright_neg_gain[1][3] = 0x00;
+ ram_table->bright_neg_gain[2][0] = 0x00;
+ ram_table->bright_neg_gain[2][1] = 0x00;
+ ram_table->bright_neg_gain[2][2] = 0x00;
+ ram_table->bright_neg_gain[2][3] = 0x00;
+ ram_table->bright_neg_gain[3][0] = 0x00;
+ ram_table->bright_neg_gain[3][1] = 0x00;
+ ram_table->bright_neg_gain[3][2] = 0x00;
+ ram_table->bright_neg_gain[3][3] = 0x00;
+ ram_table->bright_neg_gain[4][0] = 0x00;
+ ram_table->bright_neg_gain[4][1] = 0x00;
+ ram_table->bright_neg_gain[4][2] = 0x00;
+ ram_table->bright_neg_gain[4][3] = 0x00;
+ ram_table->dark_pos_gain[0][0] = 0x00;
+ ram_table->dark_pos_gain[0][1] = 0x00;
+ ram_table->dark_pos_gain[0][2] = 0x00;
+ ram_table->dark_pos_gain[0][3] = 0x00;
+ ram_table->dark_pos_gain[1][0] = 0x00;
+ ram_table->dark_pos_gain[1][1] = 0x00;
+ ram_table->dark_pos_gain[1][2] = 0x00;
+ ram_table->dark_pos_gain[1][3] = 0x00;
+ ram_table->dark_pos_gain[2][0] = 0x00;
+ ram_table->dark_pos_gain[2][1] = 0x00;
+ ram_table->dark_pos_gain[2][2] = 0x00;
+ ram_table->dark_pos_gain[2][3] = 0x00;
+ ram_table->dark_pos_gain[3][0] = 0x00;
+ ram_table->dark_pos_gain[3][1] = 0x00;
+ ram_table->dark_pos_gain[3][2] = 0x00;
+ ram_table->dark_pos_gain[3][3] = 0x00;
+ ram_table->dark_pos_gain[4][0] = 0x00;
+ ram_table->dark_pos_gain[4][1] = 0x00;
+ ram_table->dark_pos_gain[4][2] = 0x00;
+ ram_table->dark_pos_gain[4][3] = 0x00;
+ ram_table->dark_neg_gain[0][0] = 0x00;
+ ram_table->dark_neg_gain[0][1] = 0x00;
+ ram_table->dark_neg_gain[0][2] = 0x00;
+ ram_table->dark_neg_gain[0][3] = 0x00;
+ ram_table->dark_neg_gain[1][0] = 0x00;
+ ram_table->dark_neg_gain[1][1] = 0x00;
+ ram_table->dark_neg_gain[1][2] = 0x00;
+ ram_table->dark_neg_gain[1][3] = 0x00;
+ ram_table->dark_neg_gain[2][0] = 0x00;
+ ram_table->dark_neg_gain[2][1] = 0x00;
+ ram_table->dark_neg_gain[2][2] = 0x00;
+ ram_table->dark_neg_gain[2][3] = 0x00;
+ ram_table->dark_neg_gain[3][0] = 0x00;
+ ram_table->dark_neg_gain[3][1] = 0x00;
+ ram_table->dark_neg_gain[3][2] = 0x00;
+ ram_table->dark_neg_gain[3][3] = 0x00;
+ ram_table->dark_neg_gain[4][0] = 0x00;
+ ram_table->dark_neg_gain[4][1] = 0x00;
+ ram_table->dark_neg_gain[4][2] = 0x00;
+ ram_table->dark_neg_gain[4][3] = 0x00;
+
+ ram_table->iir_curve[0] = 0x65;
+ ram_table->iir_curve[1] = 0x65;
+ ram_table->iir_curve[2] = 0x65;
+ ram_table->iir_curve[3] = 0x65;
+ ram_table->iir_curve[4] = 0x65;
+
+ //Gamma 2.4
+ ram_table->crgb_thresh[0] = cpu_to_be16(0x13b6);
+ ram_table->crgb_thresh[1] = cpu_to_be16(0x1648);
+ ram_table->crgb_thresh[2] = cpu_to_be16(0x18e3);
+ ram_table->crgb_thresh[3] = cpu_to_be16(0x1b41);
+ ram_table->crgb_thresh[4] = cpu_to_be16(0x1d46);
+ ram_table->crgb_thresh[5] = cpu_to_be16(0x1f21);
+ ram_table->crgb_thresh[6] = cpu_to_be16(0x2167);
+ ram_table->crgb_thresh[7] = cpu_to_be16(0x2384);
+ ram_table->crgb_offset[0] = cpu_to_be16(0x2999);
+ ram_table->crgb_offset[1] = cpu_to_be16(0x3999);
+ ram_table->crgb_offset[2] = cpu_to_be16(0x4666);
+ ram_table->crgb_offset[3] = cpu_to_be16(0x5999);
+ ram_table->crgb_offset[4] = cpu_to_be16(0x6333);
+ ram_table->crgb_offset[5] = cpu_to_be16(0x7800);
+ ram_table->crgb_offset[6] = cpu_to_be16(0x8c00);
+ ram_table->crgb_offset[7] = cpu_to_be16(0xa000);
+ ram_table->crgb_slope[0] = cpu_to_be16(0x3147);
+ ram_table->crgb_slope[1] = cpu_to_be16(0x2978);
+ ram_table->crgb_slope[2] = cpu_to_be16(0x23a2);
+ ram_table->crgb_slope[3] = cpu_to_be16(0x1f55);
+ ram_table->crgb_slope[4] = cpu_to_be16(0x1c63);
+ ram_table->crgb_slope[5] = cpu_to_be16(0x1a0f);
+ ram_table->crgb_slope[6] = cpu_to_be16(0x178d);
+ ram_table->crgb_slope[7] = cpu_to_be16(0x15ab);
+
+ fill_backlight_transform_table(
+ params, ram_table);
+}
+
+static void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params)
+{
+ unsigned int set = params.set;
+
+ ram_table->flags = 0x0;
+
+ ram_table->min_abm_backlight =
+ cpu_to_be16(params.min_abm_backlight);
+
+ ram_table->deviation_gain[0] = 0xb3;
+ ram_table->deviation_gain[1] = 0xa8;
+ ram_table->deviation_gain[2] = 0x98;
+ ram_table->deviation_gain[3] = 0x68;
+
+ ram_table->min_reduction[0][0] = min_reduction_table_v_2_2[abm_config[set][0]];
+ ram_table->min_reduction[1][0] = min_reduction_table_v_2_2[abm_config[set][0]];
+ ram_table->min_reduction[2][0] = min_reduction_table_v_2_2[abm_config[set][0]];
+ ram_table->min_reduction[3][0] = min_reduction_table_v_2_2[abm_config[set][0]];
+ ram_table->min_reduction[4][0] = min_reduction_table_v_2_2[abm_config[set][0]];
+ ram_table->max_reduction[0][0] = max_reduction_table_v_2_2[abm_config[set][0]];
+ ram_table->max_reduction[1][0] = max_reduction_table_v_2_2[abm_config[set][0]];
+ ram_table->max_reduction[2][0] = max_reduction_table_v_2_2[abm_config[set][0]];
+ ram_table->max_reduction[3][0] = max_reduction_table_v_2_2[abm_config[set][0]];
+ ram_table->max_reduction[4][0] = max_reduction_table_v_2_2[abm_config[set][0]];
+
+ ram_table->min_reduction[0][1] = min_reduction_table_v_2_2[abm_config[set][1]];
+ ram_table->min_reduction[1][1] = min_reduction_table_v_2_2[abm_config[set][1]];
+ ram_table->min_reduction[2][1] = min_reduction_table_v_2_2[abm_config[set][1]];
+ ram_table->min_reduction[3][1] = min_reduction_table_v_2_2[abm_config[set][1]];
+ ram_table->min_reduction[4][1] = min_reduction_table_v_2_2[abm_config[set][1]];
+ ram_table->max_reduction[0][1] = max_reduction_table_v_2_2[abm_config[set][1]];
+ ram_table->max_reduction[1][1] = max_reduction_table_v_2_2[abm_config[set][1]];
+ ram_table->max_reduction[2][1] = max_reduction_table_v_2_2[abm_config[set][1]];
+ ram_table->max_reduction[3][1] = max_reduction_table_v_2_2[abm_config[set][1]];
+ ram_table->max_reduction[4][1] = max_reduction_table_v_2_2[abm_config[set][1]];
+
+ ram_table->min_reduction[0][2] = min_reduction_table_v_2_2[abm_config[set][2]];
+ ram_table->min_reduction[1][2] = min_reduction_table_v_2_2[abm_config[set][2]];
+ ram_table->min_reduction[2][2] = min_reduction_table_v_2_2[abm_config[set][2]];
+ ram_table->min_reduction[3][2] = min_reduction_table_v_2_2[abm_config[set][2]];
+ ram_table->min_reduction[4][2] = min_reduction_table_v_2_2[abm_config[set][2]];
+ ram_table->max_reduction[0][2] = max_reduction_table_v_2_2[abm_config[set][2]];
+ ram_table->max_reduction[1][2] = max_reduction_table_v_2_2[abm_config[set][2]];
+ ram_table->max_reduction[2][2] = max_reduction_table_v_2_2[abm_config[set][2]];
+ ram_table->max_reduction[3][2] = max_reduction_table_v_2_2[abm_config[set][2]];
+ ram_table->max_reduction[4][2] = max_reduction_table_v_2_2[abm_config[set][2]];
+
+ ram_table->min_reduction[0][3] = min_reduction_table_v_2_2[abm_config[set][3]];
+ ram_table->min_reduction[1][3] = min_reduction_table_v_2_2[abm_config[set][3]];
+ ram_table->min_reduction[2][3] = min_reduction_table_v_2_2[abm_config[set][3]];
+ ram_table->min_reduction[3][3] = min_reduction_table_v_2_2[abm_config[set][3]];
+ ram_table->min_reduction[4][3] = min_reduction_table_v_2_2[abm_config[set][3]];
+ ram_table->max_reduction[0][3] = max_reduction_table_v_2_2[abm_config[set][3]];
+ ram_table->max_reduction[1][3] = max_reduction_table_v_2_2[abm_config[set][3]];
+ ram_table->max_reduction[2][3] = max_reduction_table_v_2_2[abm_config[set][3]];
+ ram_table->max_reduction[3][3] = max_reduction_table_v_2_2[abm_config[set][3]];
+ ram_table->max_reduction[4][3] = max_reduction_table_v_2_2[abm_config[set][3]];
+
+ ram_table->bright_pos_gain[0][0] = 0x20;
+ ram_table->bright_pos_gain[0][1] = 0x20;
+ ram_table->bright_pos_gain[0][2] = 0x20;
+ ram_table->bright_pos_gain[0][3] = 0x20;
+ ram_table->bright_pos_gain[1][0] = 0x20;
+ ram_table->bright_pos_gain[1][1] = 0x20;
+ ram_table->bright_pos_gain[1][2] = 0x20;
+ ram_table->bright_pos_gain[1][3] = 0x20;
+ ram_table->bright_pos_gain[2][0] = 0x20;
+ ram_table->bright_pos_gain[2][1] = 0x20;
+ ram_table->bright_pos_gain[2][2] = 0x20;
+ ram_table->bright_pos_gain[2][3] = 0x20;
+ ram_table->bright_pos_gain[3][0] = 0x20;
+ ram_table->bright_pos_gain[3][1] = 0x20;
+ ram_table->bright_pos_gain[3][2] = 0x20;
+ ram_table->bright_pos_gain[3][3] = 0x20;
+ ram_table->bright_pos_gain[4][0] = 0x20;
+ ram_table->bright_pos_gain[4][1] = 0x20;
+ ram_table->bright_pos_gain[4][2] = 0x20;
+ ram_table->bright_pos_gain[4][3] = 0x20;
+
+ ram_table->dark_pos_gain[0][0] = 0x00;
+ ram_table->dark_pos_gain[0][1] = 0x00;
+ ram_table->dark_pos_gain[0][2] = 0x00;
+ ram_table->dark_pos_gain[0][3] = 0x00;
+ ram_table->dark_pos_gain[1][0] = 0x00;
+ ram_table->dark_pos_gain[1][1] = 0x00;
+ ram_table->dark_pos_gain[1][2] = 0x00;
+ ram_table->dark_pos_gain[1][3] = 0x00;
+ ram_table->dark_pos_gain[2][0] = 0x00;
+ ram_table->dark_pos_gain[2][1] = 0x00;
+ ram_table->dark_pos_gain[2][2] = 0x00;
+ ram_table->dark_pos_gain[2][3] = 0x00;
+ ram_table->dark_pos_gain[3][0] = 0x00;
+ ram_table->dark_pos_gain[3][1] = 0x00;
+ ram_table->dark_pos_gain[3][2] = 0x00;
+ ram_table->dark_pos_gain[3][3] = 0x00;
+ ram_table->dark_pos_gain[4][0] = 0x00;
+ ram_table->dark_pos_gain[4][1] = 0x00;
+ ram_table->dark_pos_gain[4][2] = 0x00;
+ ram_table->dark_pos_gain[4][3] = 0x00;
+
+ ram_table->hybrid_factor[0] = 0xff;
+ ram_table->hybrid_factor[1] = 0xff;
+ ram_table->hybrid_factor[2] = 0xff;
+ ram_table->hybrid_factor[3] = 0xc0;
+
+ ram_table->contrast_factor[0] = 0x99;
+ ram_table->contrast_factor[1] = 0x99;
+ ram_table->contrast_factor[2] = 0x90;
+ ram_table->contrast_factor[3] = 0x80;
+
+ ram_table->iir_curve[0] = 0x65;
+ ram_table->iir_curve[1] = 0x65;
+ ram_table->iir_curve[2] = 0x65;
+ ram_table->iir_curve[3] = 0x65;
+ ram_table->iir_curve[4] = 0x65;
+
+ //Gamma 2.2
+ ram_table->crgb_thresh[0] = cpu_to_be16(0x127c);
+ ram_table->crgb_thresh[1] = cpu_to_be16(0x151b);
+ ram_table->crgb_thresh[2] = cpu_to_be16(0x17d5);
+ ram_table->crgb_thresh[3] = cpu_to_be16(0x1a56);
+ ram_table->crgb_thresh[4] = cpu_to_be16(0x1c83);
+ ram_table->crgb_thresh[5] = cpu_to_be16(0x1e72);
+ ram_table->crgb_thresh[6] = cpu_to_be16(0x20f0);
+ ram_table->crgb_thresh[7] = cpu_to_be16(0x232b);
+ ram_table->crgb_offset[0] = cpu_to_be16(0x2999);
+ ram_table->crgb_offset[1] = cpu_to_be16(0x3999);
+ ram_table->crgb_offset[2] = cpu_to_be16(0x4666);
+ ram_table->crgb_offset[3] = cpu_to_be16(0x5999);
+ ram_table->crgb_offset[4] = cpu_to_be16(0x6333);
+ ram_table->crgb_offset[5] = cpu_to_be16(0x7800);
+ ram_table->crgb_offset[6] = cpu_to_be16(0x8c00);
+ ram_table->crgb_offset[7] = cpu_to_be16(0xa000);
+ ram_table->crgb_slope[0] = cpu_to_be16(0x3609);
+ ram_table->crgb_slope[1] = cpu_to_be16(0x2dfa);
+ ram_table->crgb_slope[2] = cpu_to_be16(0x27ea);
+ ram_table->crgb_slope[3] = cpu_to_be16(0x235d);
+ ram_table->crgb_slope[4] = cpu_to_be16(0x2042);
+ ram_table->crgb_slope[5] = cpu_to_be16(0x1dc3);
+ ram_table->crgb_slope[6] = cpu_to_be16(0x1b1a);
+ ram_table->crgb_slope[7] = cpu_to_be16(0x1910);
+
+ fill_backlight_transform_table_v_2_2(
+ params, ram_table, true);
+}
+
+static void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params, bool big_endian)
+{
+ unsigned int i, j;
+ unsigned int set = params.set;
+
+ ram_table->flags = 0x0;
+ ram_table->min_abm_backlight = (uint16_t)((big_endian) ?
+ cpu_to_be16(params.min_abm_backlight) :
+ cpu_to_le16(params.min_abm_backlight));
+
+ for (i = 0; i < NUM_AGGR_LEVEL; i++) {
+ ram_table->hybrid_factor[i] = (uint8_t)abm_settings[set][i].brightness_gain;
+ ram_table->contrast_factor[i] = abm_settings[set][i].contrast_factor;
+ ram_table->deviation_gain[i] = abm_settings[set][i].deviation_gain;
+ ram_table->min_knee[i] = abm_settings[set][i].min_knee;
+ ram_table->max_knee[i] = abm_settings[set][i].max_knee;
+
+ for (j = 0; j < NUM_AMBI_LEVEL; j++) {
+ ram_table->min_reduction[j][i] = abm_settings[set][i].min_reduction;
+ ram_table->max_reduction[j][i] = abm_settings[set][i].max_reduction;
+ ram_table->bright_pos_gain[j][i] = abm_settings[set][i].bright_pos_gain;
+ ram_table->dark_pos_gain[j][i] = abm_settings[set][i].dark_pos_gain;
+ }
+ }
+
+ ram_table->iir_curve[0] = 0x65;
+ ram_table->iir_curve[1] = 0x65;
+ ram_table->iir_curve[2] = 0x65;
+ ram_table->iir_curve[3] = 0x65;
+ ram_table->iir_curve[4] = 0x65;
+
+ //Gamma 2.2
+ ram_table->crgb_thresh[0] = bswap16_based_on_endian(big_endian, 0x127c);
+ ram_table->crgb_thresh[1] = bswap16_based_on_endian(big_endian, 0x151b);
+ ram_table->crgb_thresh[2] = bswap16_based_on_endian(big_endian, 0x17d5);
+ ram_table->crgb_thresh[3] = bswap16_based_on_endian(big_endian, 0x1a56);
+ ram_table->crgb_thresh[4] = bswap16_based_on_endian(big_endian, 0x1c83);
+ ram_table->crgb_thresh[5] = bswap16_based_on_endian(big_endian, 0x1e72);
+ ram_table->crgb_thresh[6] = bswap16_based_on_endian(big_endian, 0x20f0);
+ ram_table->crgb_thresh[7] = bswap16_based_on_endian(big_endian, 0x232b);
+ ram_table->crgb_offset[0] = bswap16_based_on_endian(big_endian, 0x2999);
+ ram_table->crgb_offset[1] = bswap16_based_on_endian(big_endian, 0x3999);
+ ram_table->crgb_offset[2] = bswap16_based_on_endian(big_endian, 0x4666);
+ ram_table->crgb_offset[3] = bswap16_based_on_endian(big_endian, 0x5999);
+ ram_table->crgb_offset[4] = bswap16_based_on_endian(big_endian, 0x6333);
+ ram_table->crgb_offset[5] = bswap16_based_on_endian(big_endian, 0x7800);
+ ram_table->crgb_offset[6] = bswap16_based_on_endian(big_endian, 0x8c00);
+ ram_table->crgb_offset[7] = bswap16_based_on_endian(big_endian, 0xa000);
+ ram_table->crgb_slope[0] = bswap16_based_on_endian(big_endian, 0x3609);
+ ram_table->crgb_slope[1] = bswap16_based_on_endian(big_endian, 0x2dfa);
+ ram_table->crgb_slope[2] = bswap16_based_on_endian(big_endian, 0x27ea);
+ ram_table->crgb_slope[3] = bswap16_based_on_endian(big_endian, 0x235d);
+ ram_table->crgb_slope[4] = bswap16_based_on_endian(big_endian, 0x2042);
+ ram_table->crgb_slope[5] = bswap16_based_on_endian(big_endian, 0x1dc3);
+ ram_table->crgb_slope[6] = bswap16_based_on_endian(big_endian, 0x1b1a);
+ ram_table->crgb_slope[7] = bswap16_based_on_endian(big_endian, 0x1910);
+
+ fill_backlight_transform_table_v_2_2(
+ params, ram_table, big_endian);
+}
+
+bool dmub_init_abm_config(struct resource_pool *res_pool,
+ struct dmcu_iram_parameters params,
+ unsigned int inst)
+{
+ struct iram_table_v_2_2 ram_table;
+ struct abm_config_table config;
+ unsigned int set = params.set;
+ bool result = false;
+ uint32_t i, j = 0;
+
+ if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
+ return false;
+
+ memset(&ram_table, 0, sizeof(ram_table));
+ memset(&config, 0, sizeof(config));
+
+ fill_iram_v_2_3(&ram_table, params, false);
+
+ // We must copy to structure that is aligned to 32-bit
+ for (i = 0; i < NUM_POWER_FN_SEGS; i++) {
+ config.crgb_thresh[i] = ram_table.crgb_thresh[i];
+ config.crgb_offset[i] = ram_table.crgb_offset[i];
+ config.crgb_slope[i] = ram_table.crgb_slope[i];
+ }
+
+ for (i = 0; i < NUM_BL_CURVE_SEGS; i++) {
+ config.backlight_thresholds[i] = ram_table.backlight_thresholds[i];
+ config.backlight_offsets[i] = ram_table.backlight_offsets[i];
+ }
+
+ for (i = 0; i < NUM_AMBI_LEVEL; i++)
+ config.iir_curve[i] = ram_table.iir_curve[i];
+
+ for (i = 0; i < NUM_AMBI_LEVEL; i++) {
+ for (j = 0; j < NUM_AGGR_LEVEL; j++) {
+ config.min_reduction[i][j] = ram_table.min_reduction[i][j];
+ config.max_reduction[i][j] = ram_table.max_reduction[i][j];
+ config.bright_pos_gain[i][j] = ram_table.bright_pos_gain[i][j];
+ config.dark_pos_gain[i][j] = ram_table.dark_pos_gain[i][j];
+ }
+ }
+
+ for (i = 0; i < NUM_AGGR_LEVEL; i++) {
+ config.hybrid_factor[i] = ram_table.hybrid_factor[i];
+ config.contrast_factor[i] = ram_table.contrast_factor[i];
+ config.deviation_gain[i] = ram_table.deviation_gain[i];
+ config.min_knee[i] = ram_table.min_knee[i];
+ config.max_knee[i] = ram_table.max_knee[i];
+ }
+
+ if (params.backlight_ramping_override) {
+
+ ASSERT(params.backlight_ramping_reduction <= 0xFFFF);
+ ASSERT(params.backlight_ramping_start <= 0xFFFF);
+ for (i = 0; i < NUM_AGGR_LEVEL; i++) {
+ config.blRampReduction[i] = (uint16_t)params.backlight_ramping_reduction;
+ config.blRampStart[i] = (uint16_t)params.backlight_ramping_start;
+ }
+ } else {
+ for (i = 0; i < NUM_AGGR_LEVEL; i++) {
+ config.blRampReduction[i] = abm_settings[set][i].blRampReduction;
+ config.blRampStart[i] = abm_settings[set][i].blRampStart;
+ }
+ }
+
+ config.min_abm_backlight = ram_table.min_abm_backlight;
+
+ if (res_pool->multiple_abms[inst]) {
+ result = res_pool->multiple_abms[inst]->funcs->init_abm_config(
+ res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst);
+ } else
+ result = res_pool->abm->funcs->init_abm_config(
+ res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0);
+
+ return result;
+}
+
+bool dmcu_load_iram(struct dmcu *dmcu,
+ struct dmcu_iram_parameters params)
+{
+ unsigned char ram_table[IRAM_SIZE];
+ bool result = false;
+
+ if (dmcu == NULL)
+ return false;
+
+ if (dmcu && !dmcu->funcs->is_dmcu_initialized(dmcu))
+ return true;
+
+ memset(&ram_table, 0, sizeof(ram_table));
+
+ if (dmcu->dmcu_version.abm_version == 0x24) {
+ fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true);
+ result = dmcu->funcs->load_iram(dmcu, 0, (char *)(&ram_table),
+ IRAM_RESERVE_AREA_START_V2_2);
+ } else if (dmcu->dmcu_version.abm_version == 0x23) {
+ fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true);
+
+ result = dmcu->funcs->load_iram(
+ dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
+ } else if (dmcu->dmcu_version.abm_version == 0x22) {
+ fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params);
+
+ result = dmcu->funcs->load_iram(
+ dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
+ } else {
+ fill_iram_v_2((struct iram_table_v_2 *)ram_table, params);
+
+ result = dmcu->funcs->load_iram(
+ dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2);
+
+ if (result)
+ result = dmcu->funcs->load_iram(
+ dmcu, IRAM_RESERVE_AREA_END_V2 + 1,
+ (char *)(&ram_table) + IRAM_RESERVE_AREA_END_V2 + 1,
+ sizeof(ram_table) - IRAM_RESERVE_AREA_END_V2 - 1);
+ }
+
+ return result;
+}
+
+bool fill_custom_backlight_caps(unsigned int config_no, struct dm_acpi_atif_backlight_caps *caps)
+{
+ unsigned int data_points_size;
+ uint64_t caps_size;
+
+ if (config_no >= ARRAY_SIZE(custom_backlight_profiles))
+ return false;
+
+ data_points_size = custom_backlight_profiles[config_no].num_data_points
+ * sizeof(custom_backlight_profiles[config_no].data_points[0]);
+
+ caps_size = sizeof(struct dm_acpi_atif_backlight_caps) - sizeof(caps->data_points) + data_points_size;
+ ASSERT(caps_size <= 0xFFFF);
+ caps->size = (uint16_t)caps_size;
+ caps->flags = 0;
+ caps->error_code = 0;
+ caps->ac_level_percentage = custom_backlight_profiles[config_no].ac_level_percentage;
+ caps->dc_level_percentage = custom_backlight_profiles[config_no].dc_level_percentage;
+ caps->min_input_signal = custom_backlight_profiles[config_no].min_input_signal;
+ caps->max_input_signal = custom_backlight_profiles[config_no].max_input_signal;
+ caps->num_data_points = (uint8_t)custom_backlight_profiles[config_no].num_data_points;
+ memcpy(caps->data_points, custom_backlight_profiles[config_no].data_points, data_points_size);
+ return true;
+}
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index f55c15199fb4..1046fc35f8f9 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -33,796 +33,6 @@
#define bswap16_based_on_endian(big_endian, value) \
((big_endian) ? cpu_to_be16(value) : cpu_to_le16(value))
-/* Possible Min Reduction config from least aggressive to most aggressive
- * 0 1 2 3 4 5 6 7 8 9 10 11 12
- * 100 98.0 94.1 94.1 85.1 80.3 75.3 69.4 60.0 57.6 50.2 49.8 40.0 %
- */
-static const unsigned char min_reduction_table[13] = {
-0xff, 0xfa, 0xf0, 0xf0, 0xd9, 0xcd, 0xc0, 0xb1, 0x99, 0x93, 0x80, 0x82, 0x66};
-
-/* Possible Max Reduction configs from least aggressive to most aggressive
- * 0 1 2 3 4 5 6 7 8 9 10 11 12
- * 96.1 89.8 85.1 80.3 69.4 64.7 64.7 50.2 39.6 30.2 30.2 30.2 19.6 %
- */
-static const unsigned char max_reduction_table[13] = {
-0xf5, 0xe5, 0xd9, 0xcd, 0xb1, 0xa5, 0xa5, 0x80, 0x65, 0x4d, 0x4d, 0x4d, 0x32};
-
-/* Possible ABM 2.2 Min Reduction configs from least aggressive to most aggressive
- * 0 1 2 3 4 5 6 7 8 9 10 11 12
- * 100 100 100 100 100 100 100 100 100 92.2 83.1 75.3 75.3 %
- */
-static const unsigned char min_reduction_table_v_2_2[13] = {
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0xd4, 0xc0, 0xc0};
-
-/* Possible ABM 2.2 Max Reduction configs from least aggressive to most aggressive
- * 0 1 2 3 4 5 6 7 8 9 10 11 12
- * 96.1 89.8 74.9 69.4 64.7 52.2 48.6 39.6 30.2 25.1 19.6 12.5 12.5 %
- */
-static const unsigned char max_reduction_table_v_2_2[13] = {
-0xf5, 0xe5, 0xbf, 0xb1, 0xa5, 0x85, 0x7c, 0x65, 0x4d, 0x40, 0x32, 0x20, 0x20};
-
-/* Predefined ABM configuration sets. We may have different configuration sets
- * in order to satisfy different power/quality requirements.
- */
-static const unsigned char abm_config[abm_defines_max_config][abm_defines_max_level] = {
-/* ABM Level 1, ABM Level 2, ABM Level 3, ABM Level 4 */
-{ 2, 5, 7, 8 }, /* Default - Medium aggressiveness */
-{ 2, 5, 8, 11 }, /* Alt #1 - Increased aggressiveness */
-{ 0, 2, 4, 8 }, /* Alt #2 - Minimal aggressiveness */
-{ 3, 6, 10, 12 }, /* Alt #3 - Super aggressiveness */
-};
-
-struct abm_parameters {
- unsigned char min_reduction;
- unsigned char max_reduction;
- unsigned char bright_pos_gain;
- unsigned char dark_pos_gain;
- unsigned char brightness_gain;
- unsigned char contrast_factor;
- unsigned char deviation_gain;
- unsigned char min_knee;
- unsigned char max_knee;
- unsigned short blRampReduction;
- unsigned short blRampStart;
-};
-
-static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = {
-// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart
- {0xff, 0xbf, 0x20, 0x00, 0xff, 0x99, 0xb3, 0x40, 0xe0, 0xf777, 0xcccc},
- {0xde, 0x85, 0x20, 0x00, 0xe0, 0x90, 0xa8, 0x40, 0xc8, 0xf777, 0xcccc},
- {0xb0, 0x50, 0x20, 0x00, 0xc0, 0x88, 0x78, 0x70, 0xa0, 0xeeee, 0x9999},
- {0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xe333, 0xb333},
-};
-
-static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = {
-// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart
- {0xf0, 0xd9, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
- {0xcd, 0xa5, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
- {0x99, 0x65, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
- {0x82, 0x4d, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
-};
-
-static const struct abm_parameters abm_settings_config2[abm_defines_max_level] = {
-// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart
- {0xf0, 0xbf, 0x20, 0x00, 0x88, 0x99, 0xb3, 0x40, 0xe0, 0x0000, 0xcccc},
- {0xd8, 0x85, 0x20, 0x00, 0x70, 0x90, 0xa8, 0x40, 0xc8, 0x0700, 0xb333},
- {0xb8, 0x58, 0x20, 0x00, 0x64, 0x88, 0x78, 0x70, 0xa0, 0x7000, 0x9999},
- {0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xc333, 0xb333},
-};
-
-static const struct abm_parameters * const abm_settings[] = {
- abm_settings_config0,
- abm_settings_config1,
- abm_settings_config2,
-};
-
-static const struct dm_bl_data_point custom_backlight_curve0[] = {
- {2, 14}, {4, 16}, {6, 18}, {8, 21}, {10, 23}, {12, 26}, {14, 29}, {16, 32}, {18, 35},
- {20, 38}, {22, 41}, {24, 44}, {26, 48}, {28, 52}, {30, 55}, {32, 59}, {34, 62},
- {36, 67}, {38, 71}, {40, 75}, {42, 80}, {44, 84}, {46, 88}, {48, 93}, {50, 98},
- {52, 103}, {54, 108}, {56, 113}, {58, 118}, {60, 123}, {62, 129}, {64, 135}, {66, 140},
- {68, 146}, {70, 152}, {72, 158}, {74, 164}, {76, 171}, {78, 177}, {80, 183}, {82, 190},
- {84, 197}, {86, 204}, {88, 211}, {90, 218}, {92, 225}, {94, 232}, {96, 240}, {98, 247}};
-
-struct custom_backlight_profile {
- uint8_t ac_level_percentage;
- uint8_t dc_level_percentage;
- uint8_t min_input_signal;
- uint8_t max_input_signal;
- uint8_t num_data_points;
- const struct dm_bl_data_point *data_points;
-};
-
-static const struct custom_backlight_profile custom_backlight_profiles[] = {
- {100, 32, 12, 255, ARRAY_SIZE(custom_backlight_curve0), custom_backlight_curve0},
-};
-
-#define NUM_AMBI_LEVEL 5
-#define NUM_AGGR_LEVEL 4
-#define NUM_POWER_FN_SEGS 8
-#define NUM_BL_CURVE_SEGS 16
-#define IRAM_SIZE 256
-
-#define IRAM_RESERVE_AREA_START_V2 0xF0 // reserve 0xF0~0xF6 are write by DMCU only
-#define IRAM_RESERVE_AREA_END_V2 0xF6 // reserve 0xF0~0xF6 are write by DMCU only
-
-#define IRAM_RESERVE_AREA_START_V2_2 0xF0 // reserve 0xF0~0xFF are write by DMCU only
-#define IRAM_RESERVE_AREA_END_V2_2 0xFF // reserve 0xF0~0xFF are write by DMCU only
-
-#pragma pack(push, 1)
-/* NOTE: iRAM is 256B in size */
-struct iram_table_v_2 {
- /* flags */
- uint16_t min_abm_backlight; /* 0x00 U16 */
-
- /* parameters for ABM2.0 algorithm */
- uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */
- uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */
- uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */
- uint8_t bright_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */
- uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x52 U2.6 */
- uint8_t dark_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x66 U2.6 */
- uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x7a U0.8 */
- uint8_t deviation_gain; /* 0x7f U0.8 */
-
- /* parameters for crgb conversion */
- uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */
- uint16_t crgb_offset[NUM_POWER_FN_SEGS]; /* 0x90 U1.15 */
- uint16_t crgb_slope[NUM_POWER_FN_SEGS]; /* 0xa0 U4.12 */
-
- /* parameters for custom curve */
- /* thresholds for brightness --> backlight */
- uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; /* 0xb0 U16.0 */
- /* offsets for brightness --> backlight */
- uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; /* 0xd0 U16.0 */
-
- /* For reading PSR State directly from IRAM */
- uint8_t psr_state; /* 0xf0 */
- uint8_t dmcu_mcp_interface_version; /* 0xf1 */
- uint8_t dmcu_abm_feature_version; /* 0xf2 */
- uint8_t dmcu_psr_feature_version; /* 0xf3 */
- uint16_t dmcu_version; /* 0xf4 */
- uint8_t dmcu_state; /* 0xf6 */
-
- uint16_t blRampReduction; /* 0xf7 */
- uint16_t blRampStart; /* 0xf9 */
- uint8_t dummy5; /* 0xfb */
- uint8_t dummy6; /* 0xfc */
- uint8_t dummy7; /* 0xfd */
- uint8_t dummy8; /* 0xfe */
- uint8_t dummy9; /* 0xff */
-};
-
-struct iram_table_v_2_2 {
- /* flags */
- uint16_t flags; /* 0x00 U16 */
-
- /* parameters for ABM2.2 algorithm */
- uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */
- uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */
- uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */
- uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */
- uint8_t hybrid_factor[NUM_AGGR_LEVEL]; /* 0x52 U0.8 */
- uint8_t contrast_factor[NUM_AGGR_LEVEL]; /* 0x56 U0.8 */
- uint8_t deviation_gain[NUM_AGGR_LEVEL]; /* 0x5a U0.8 */
- uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x5e U0.8 */
- uint8_t min_knee[NUM_AGGR_LEVEL]; /* 0x63 U0.8 */
- uint8_t max_knee[NUM_AGGR_LEVEL]; /* 0x67 U0.8 */
- uint16_t min_abm_backlight; /* 0x6b U16 */
- uint8_t pad[19]; /* 0x6d U0.8 */
-
- /* parameters for crgb conversion */
- uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */
- uint16_t crgb_offset[NUM_POWER_FN_SEGS]; /* 0x90 U1.15 */
- uint16_t crgb_slope[NUM_POWER_FN_SEGS]; /* 0xa0 U4.12 */
-
- /* parameters for custom curve */
- /* thresholds for brightness --> backlight */
- uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; /* 0xb0 U16.0 */
- /* offsets for brightness --> backlight */
- uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; /* 0xd0 U16.0 */
-
- /* For reading PSR State directly from IRAM */
- uint8_t psr_state; /* 0xf0 */
- uint8_t dmcu_mcp_interface_version; /* 0xf1 */
- uint8_t dmcu_abm_feature_version; /* 0xf2 */
- uint8_t dmcu_psr_feature_version; /* 0xf3 */
- uint16_t dmcu_version; /* 0xf4 */
- uint8_t dmcu_state; /* 0xf6 */
-
- uint8_t dummy1; /* 0xf7 */
- uint8_t dummy2; /* 0xf8 */
- uint8_t dummy3; /* 0xf9 */
- uint8_t dummy4; /* 0xfa */
- uint8_t dummy5; /* 0xfb */
- uint8_t dummy6; /* 0xfc */
- uint8_t dummy7; /* 0xfd */
- uint8_t dummy8; /* 0xfe */
- uint8_t dummy9; /* 0xff */
-};
-#pragma pack(pop)
-
-static void fill_backlight_transform_table(struct dmcu_iram_parameters params,
- struct iram_table_v_2 *table)
-{
- unsigned int i;
- unsigned int num_entries = NUM_BL_CURVE_SEGS;
- unsigned int lut_index;
-
- table->backlight_thresholds[0] = 0;
- ASSERT(params.backlight_lut_array[0] <= 0xFFFF);
- table->backlight_offsets[0] = (uint16_t)params.backlight_lut_array[0];
- table->backlight_thresholds[num_entries-1] = 0xFFFF;
- ASSERT(params.backlight_lut_array[params.backlight_lut_array_size - 1] <= 0xFFFF);
- table->backlight_offsets[num_entries-1] =
- (uint16_t)params.backlight_lut_array[params.backlight_lut_array_size - 1];
-
- /* Setup all brightness levels between 0% and 100% exclusive
- * Fills brightness-to-backlight transform table. Backlight custom curve
- * describes transform from brightness to backlight. It will be defined
- * as set of thresholds and set of offsets, together, implying
- * extrapolation of custom curve into 16 uniformly spanned linear
- * segments. Each threshold/offset represented by 16 bit entry in
- * format U4.10.
- */
- for (i = 1; i+1 < num_entries; i++) {
- lut_index = (params.backlight_lut_array_size - 1) * i / (num_entries - 1);
-
- ASSERT(lut_index < params.backlight_lut_array_size);
-
- unsigned int threshold_val = DIV_ROUNDUP((i * 65536), num_entries);
- unsigned int offset_val = params.backlight_lut_array[lut_index];
-
- ASSERT(threshold_val <= 0xFFFF);
- ASSERT(offset_val <= 0xFFFF);
-
- table->backlight_thresholds[i] = cpu_to_be16((uint16_t)threshold_val);
- table->backlight_offsets[i] = cpu_to_be16((uint16_t)offset_val);
- }
-}
-
-static void fill_backlight_transform_table_v_2_2(struct dmcu_iram_parameters params,
- struct iram_table_v_2_2 *table, bool big_endian)
-{
- unsigned int i;
- unsigned int num_entries = NUM_BL_CURVE_SEGS;
- unsigned int lut_index;
-
- table->backlight_thresholds[0] = 0;
- ASSERT(params.backlight_lut_array[0] <= 0xFFFF);
- table->backlight_offsets[0] = (uint16_t)params.backlight_lut_array[0];
- table->backlight_thresholds[num_entries-1] = 0xFFFF;
- ASSERT(params.backlight_lut_array[params.backlight_lut_array_size - 1] <= 0xFFFF);
- table->backlight_offsets[num_entries-1] =
- (uint16_t)params.backlight_lut_array[params.backlight_lut_array_size - 1];
-
- /* Setup all brightness levels between 0% and 100% exclusive
- * Fills brightness-to-backlight transform table. Backlight custom curve
- * describes transform from brightness to backlight. It will be defined
- * as set of thresholds and set of offsets, together, implying
- * extrapolation of custom curve into 16 uniformly spanned linear
- * segments. Each threshold/offset represented by 16 bit entry in
- * format U4.10.
- */
- for (i = 1; i+1 < num_entries; i++) {
- lut_index = DIV_ROUNDUP((i * params.backlight_lut_array_size), num_entries);
- ASSERT(lut_index < params.backlight_lut_array_size);
-
- unsigned int threshold_val = DIV_ROUNDUP((i * 65536), num_entries);
- unsigned int offset_val = params.backlight_lut_array[lut_index];
-
- ASSERT(threshold_val <= 0xFFFF);
- ASSERT(offset_val <= 0xFFFF);
-
- table->backlight_thresholds[i] = (big_endian) ?
- cpu_to_be16((uint16_t)threshold_val) : cpu_to_le16((uint16_t)threshold_val);
- table->backlight_offsets[i] = (big_endian) ?
- cpu_to_be16((uint16_t)offset_val) : cpu_to_le16((uint16_t)offset_val);
- }
-}
-
-static void fill_iram_v_2(struct iram_table_v_2 *ram_table, struct dmcu_iram_parameters params)
-{
- unsigned int set = params.set;
-
- ram_table->min_abm_backlight =
- cpu_to_be16(params.min_abm_backlight);
- ram_table->deviation_gain = 0xb3;
-
- ram_table->blRampReduction =
- cpu_to_be16(params.backlight_ramping_reduction);
- ram_table->blRampStart =
- cpu_to_be16(params.backlight_ramping_start);
-
- ram_table->min_reduction[0][0] = min_reduction_table[abm_config[set][0]];
- ram_table->min_reduction[1][0] = min_reduction_table[abm_config[set][0]];
- ram_table->min_reduction[2][0] = min_reduction_table[abm_config[set][0]];
- ram_table->min_reduction[3][0] = min_reduction_table[abm_config[set][0]];
- ram_table->min_reduction[4][0] = min_reduction_table[abm_config[set][0]];
- ram_table->max_reduction[0][0] = max_reduction_table[abm_config[set][0]];
- ram_table->max_reduction[1][0] = max_reduction_table[abm_config[set][0]];
- ram_table->max_reduction[2][0] = max_reduction_table[abm_config[set][0]];
- ram_table->max_reduction[3][0] = max_reduction_table[abm_config[set][0]];
- ram_table->max_reduction[4][0] = max_reduction_table[abm_config[set][0]];
-
- ram_table->min_reduction[0][1] = min_reduction_table[abm_config[set][1]];
- ram_table->min_reduction[1][1] = min_reduction_table[abm_config[set][1]];
- ram_table->min_reduction[2][1] = min_reduction_table[abm_config[set][1]];
- ram_table->min_reduction[3][1] = min_reduction_table[abm_config[set][1]];
- ram_table->min_reduction[4][1] = min_reduction_table[abm_config[set][1]];
- ram_table->max_reduction[0][1] = max_reduction_table[abm_config[set][1]];
- ram_table->max_reduction[1][1] = max_reduction_table[abm_config[set][1]];
- ram_table->max_reduction[2][1] = max_reduction_table[abm_config[set][1]];
- ram_table->max_reduction[3][1] = max_reduction_table[abm_config[set][1]];
- ram_table->max_reduction[4][1] = max_reduction_table[abm_config[set][1]];
-
- ram_table->min_reduction[0][2] = min_reduction_table[abm_config[set][2]];
- ram_table->min_reduction[1][2] = min_reduction_table[abm_config[set][2]];
- ram_table->min_reduction[2][2] = min_reduction_table[abm_config[set][2]];
- ram_table->min_reduction[3][2] = min_reduction_table[abm_config[set][2]];
- ram_table->min_reduction[4][2] = min_reduction_table[abm_config[set][2]];
- ram_table->max_reduction[0][2] = max_reduction_table[abm_config[set][2]];
- ram_table->max_reduction[1][2] = max_reduction_table[abm_config[set][2]];
- ram_table->max_reduction[2][2] = max_reduction_table[abm_config[set][2]];
- ram_table->max_reduction[3][2] = max_reduction_table[abm_config[set][2]];
- ram_table->max_reduction[4][2] = max_reduction_table[abm_config[set][2]];
-
- ram_table->min_reduction[0][3] = min_reduction_table[abm_config[set][3]];
- ram_table->min_reduction[1][3] = min_reduction_table[abm_config[set][3]];
- ram_table->min_reduction[2][3] = min_reduction_table[abm_config[set][3]];
- ram_table->min_reduction[3][3] = min_reduction_table[abm_config[set][3]];
- ram_table->min_reduction[4][3] = min_reduction_table[abm_config[set][3]];
- ram_table->max_reduction[0][3] = max_reduction_table[abm_config[set][3]];
- ram_table->max_reduction[1][3] = max_reduction_table[abm_config[set][3]];
- ram_table->max_reduction[2][3] = max_reduction_table[abm_config[set][3]];
- ram_table->max_reduction[3][3] = max_reduction_table[abm_config[set][3]];
- ram_table->max_reduction[4][3] = max_reduction_table[abm_config[set][3]];
-
- ram_table->bright_pos_gain[0][0] = 0x20;
- ram_table->bright_pos_gain[0][1] = 0x20;
- ram_table->bright_pos_gain[0][2] = 0x20;
- ram_table->bright_pos_gain[0][3] = 0x20;
- ram_table->bright_pos_gain[1][0] = 0x20;
- ram_table->bright_pos_gain[1][1] = 0x20;
- ram_table->bright_pos_gain[1][2] = 0x20;
- ram_table->bright_pos_gain[1][3] = 0x20;
- ram_table->bright_pos_gain[2][0] = 0x20;
- ram_table->bright_pos_gain[2][1] = 0x20;
- ram_table->bright_pos_gain[2][2] = 0x20;
- ram_table->bright_pos_gain[2][3] = 0x20;
- ram_table->bright_pos_gain[3][0] = 0x20;
- ram_table->bright_pos_gain[3][1] = 0x20;
- ram_table->bright_pos_gain[3][2] = 0x20;
- ram_table->bright_pos_gain[3][3] = 0x20;
- ram_table->bright_pos_gain[4][0] = 0x20;
- ram_table->bright_pos_gain[4][1] = 0x20;
- ram_table->bright_pos_gain[4][2] = 0x20;
- ram_table->bright_pos_gain[4][3] = 0x20;
- ram_table->bright_neg_gain[0][0] = 0x00;
- ram_table->bright_neg_gain[0][1] = 0x00;
- ram_table->bright_neg_gain[0][2] = 0x00;
- ram_table->bright_neg_gain[0][3] = 0x00;
- ram_table->bright_neg_gain[1][0] = 0x00;
- ram_table->bright_neg_gain[1][1] = 0x00;
- ram_table->bright_neg_gain[1][2] = 0x00;
- ram_table->bright_neg_gain[1][3] = 0x00;
- ram_table->bright_neg_gain[2][0] = 0x00;
- ram_table->bright_neg_gain[2][1] = 0x00;
- ram_table->bright_neg_gain[2][2] = 0x00;
- ram_table->bright_neg_gain[2][3] = 0x00;
- ram_table->bright_neg_gain[3][0] = 0x00;
- ram_table->bright_neg_gain[3][1] = 0x00;
- ram_table->bright_neg_gain[3][2] = 0x00;
- ram_table->bright_neg_gain[3][3] = 0x00;
- ram_table->bright_neg_gain[4][0] = 0x00;
- ram_table->bright_neg_gain[4][1] = 0x00;
- ram_table->bright_neg_gain[4][2] = 0x00;
- ram_table->bright_neg_gain[4][3] = 0x00;
- ram_table->dark_pos_gain[0][0] = 0x00;
- ram_table->dark_pos_gain[0][1] = 0x00;
- ram_table->dark_pos_gain[0][2] = 0x00;
- ram_table->dark_pos_gain[0][3] = 0x00;
- ram_table->dark_pos_gain[1][0] = 0x00;
- ram_table->dark_pos_gain[1][1] = 0x00;
- ram_table->dark_pos_gain[1][2] = 0x00;
- ram_table->dark_pos_gain[1][3] = 0x00;
- ram_table->dark_pos_gain[2][0] = 0x00;
- ram_table->dark_pos_gain[2][1] = 0x00;
- ram_table->dark_pos_gain[2][2] = 0x00;
- ram_table->dark_pos_gain[2][3] = 0x00;
- ram_table->dark_pos_gain[3][0] = 0x00;
- ram_table->dark_pos_gain[3][1] = 0x00;
- ram_table->dark_pos_gain[3][2] = 0x00;
- ram_table->dark_pos_gain[3][3] = 0x00;
- ram_table->dark_pos_gain[4][0] = 0x00;
- ram_table->dark_pos_gain[4][1] = 0x00;
- ram_table->dark_pos_gain[4][2] = 0x00;
- ram_table->dark_pos_gain[4][3] = 0x00;
- ram_table->dark_neg_gain[0][0] = 0x00;
- ram_table->dark_neg_gain[0][1] = 0x00;
- ram_table->dark_neg_gain[0][2] = 0x00;
- ram_table->dark_neg_gain[0][3] = 0x00;
- ram_table->dark_neg_gain[1][0] = 0x00;
- ram_table->dark_neg_gain[1][1] = 0x00;
- ram_table->dark_neg_gain[1][2] = 0x00;
- ram_table->dark_neg_gain[1][3] = 0x00;
- ram_table->dark_neg_gain[2][0] = 0x00;
- ram_table->dark_neg_gain[2][1] = 0x00;
- ram_table->dark_neg_gain[2][2] = 0x00;
- ram_table->dark_neg_gain[2][3] = 0x00;
- ram_table->dark_neg_gain[3][0] = 0x00;
- ram_table->dark_neg_gain[3][1] = 0x00;
- ram_table->dark_neg_gain[3][2] = 0x00;
- ram_table->dark_neg_gain[3][3] = 0x00;
- ram_table->dark_neg_gain[4][0] = 0x00;
- ram_table->dark_neg_gain[4][1] = 0x00;
- ram_table->dark_neg_gain[4][2] = 0x00;
- ram_table->dark_neg_gain[4][3] = 0x00;
-
- ram_table->iir_curve[0] = 0x65;
- ram_table->iir_curve[1] = 0x65;
- ram_table->iir_curve[2] = 0x65;
- ram_table->iir_curve[3] = 0x65;
- ram_table->iir_curve[4] = 0x65;
-
- //Gamma 2.4
- ram_table->crgb_thresh[0] = cpu_to_be16(0x13b6);
- ram_table->crgb_thresh[1] = cpu_to_be16(0x1648);
- ram_table->crgb_thresh[2] = cpu_to_be16(0x18e3);
- ram_table->crgb_thresh[3] = cpu_to_be16(0x1b41);
- ram_table->crgb_thresh[4] = cpu_to_be16(0x1d46);
- ram_table->crgb_thresh[5] = cpu_to_be16(0x1f21);
- ram_table->crgb_thresh[6] = cpu_to_be16(0x2167);
- ram_table->crgb_thresh[7] = cpu_to_be16(0x2384);
- ram_table->crgb_offset[0] = cpu_to_be16(0x2999);
- ram_table->crgb_offset[1] = cpu_to_be16(0x3999);
- ram_table->crgb_offset[2] = cpu_to_be16(0x4666);
- ram_table->crgb_offset[3] = cpu_to_be16(0x5999);
- ram_table->crgb_offset[4] = cpu_to_be16(0x6333);
- ram_table->crgb_offset[5] = cpu_to_be16(0x7800);
- ram_table->crgb_offset[6] = cpu_to_be16(0x8c00);
- ram_table->crgb_offset[7] = cpu_to_be16(0xa000);
- ram_table->crgb_slope[0] = cpu_to_be16(0x3147);
- ram_table->crgb_slope[1] = cpu_to_be16(0x2978);
- ram_table->crgb_slope[2] = cpu_to_be16(0x23a2);
- ram_table->crgb_slope[3] = cpu_to_be16(0x1f55);
- ram_table->crgb_slope[4] = cpu_to_be16(0x1c63);
- ram_table->crgb_slope[5] = cpu_to_be16(0x1a0f);
- ram_table->crgb_slope[6] = cpu_to_be16(0x178d);
- ram_table->crgb_slope[7] = cpu_to_be16(0x15ab);
-
- fill_backlight_transform_table(
- params, ram_table);
-}
-
-static void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params)
-{
- unsigned int set = params.set;
-
- ram_table->flags = 0x0;
-
- ram_table->min_abm_backlight =
- cpu_to_be16(params.min_abm_backlight);
-
- ram_table->deviation_gain[0] = 0xb3;
- ram_table->deviation_gain[1] = 0xa8;
- ram_table->deviation_gain[2] = 0x98;
- ram_table->deviation_gain[3] = 0x68;
-
- ram_table->min_reduction[0][0] = min_reduction_table_v_2_2[abm_config[set][0]];
- ram_table->min_reduction[1][0] = min_reduction_table_v_2_2[abm_config[set][0]];
- ram_table->min_reduction[2][0] = min_reduction_table_v_2_2[abm_config[set][0]];
- ram_table->min_reduction[3][0] = min_reduction_table_v_2_2[abm_config[set][0]];
- ram_table->min_reduction[4][0] = min_reduction_table_v_2_2[abm_config[set][0]];
- ram_table->max_reduction[0][0] = max_reduction_table_v_2_2[abm_config[set][0]];
- ram_table->max_reduction[1][0] = max_reduction_table_v_2_2[abm_config[set][0]];
- ram_table->max_reduction[2][0] = max_reduction_table_v_2_2[abm_config[set][0]];
- ram_table->max_reduction[3][0] = max_reduction_table_v_2_2[abm_config[set][0]];
- ram_table->max_reduction[4][0] = max_reduction_table_v_2_2[abm_config[set][0]];
-
- ram_table->min_reduction[0][1] = min_reduction_table_v_2_2[abm_config[set][1]];
- ram_table->min_reduction[1][1] = min_reduction_table_v_2_2[abm_config[set][1]];
- ram_table->min_reduction[2][1] = min_reduction_table_v_2_2[abm_config[set][1]];
- ram_table->min_reduction[3][1] = min_reduction_table_v_2_2[abm_config[set][1]];
- ram_table->min_reduction[4][1] = min_reduction_table_v_2_2[abm_config[set][1]];
- ram_table->max_reduction[0][1] = max_reduction_table_v_2_2[abm_config[set][1]];
- ram_table->max_reduction[1][1] = max_reduction_table_v_2_2[abm_config[set][1]];
- ram_table->max_reduction[2][1] = max_reduction_table_v_2_2[abm_config[set][1]];
- ram_table->max_reduction[3][1] = max_reduction_table_v_2_2[abm_config[set][1]];
- ram_table->max_reduction[4][1] = max_reduction_table_v_2_2[abm_config[set][1]];
-
- ram_table->min_reduction[0][2] = min_reduction_table_v_2_2[abm_config[set][2]];
- ram_table->min_reduction[1][2] = min_reduction_table_v_2_2[abm_config[set][2]];
- ram_table->min_reduction[2][2] = min_reduction_table_v_2_2[abm_config[set][2]];
- ram_table->min_reduction[3][2] = min_reduction_table_v_2_2[abm_config[set][2]];
- ram_table->min_reduction[4][2] = min_reduction_table_v_2_2[abm_config[set][2]];
- ram_table->max_reduction[0][2] = max_reduction_table_v_2_2[abm_config[set][2]];
- ram_table->max_reduction[1][2] = max_reduction_table_v_2_2[abm_config[set][2]];
- ram_table->max_reduction[2][2] = max_reduction_table_v_2_2[abm_config[set][2]];
- ram_table->max_reduction[3][2] = max_reduction_table_v_2_2[abm_config[set][2]];
- ram_table->max_reduction[4][2] = max_reduction_table_v_2_2[abm_config[set][2]];
-
- ram_table->min_reduction[0][3] = min_reduction_table_v_2_2[abm_config[set][3]];
- ram_table->min_reduction[1][3] = min_reduction_table_v_2_2[abm_config[set][3]];
- ram_table->min_reduction[2][3] = min_reduction_table_v_2_2[abm_config[set][3]];
- ram_table->min_reduction[3][3] = min_reduction_table_v_2_2[abm_config[set][3]];
- ram_table->min_reduction[4][3] = min_reduction_table_v_2_2[abm_config[set][3]];
- ram_table->max_reduction[0][3] = max_reduction_table_v_2_2[abm_config[set][3]];
- ram_table->max_reduction[1][3] = max_reduction_table_v_2_2[abm_config[set][3]];
- ram_table->max_reduction[2][3] = max_reduction_table_v_2_2[abm_config[set][3]];
- ram_table->max_reduction[3][3] = max_reduction_table_v_2_2[abm_config[set][3]];
- ram_table->max_reduction[4][3] = max_reduction_table_v_2_2[abm_config[set][3]];
-
- ram_table->bright_pos_gain[0][0] = 0x20;
- ram_table->bright_pos_gain[0][1] = 0x20;
- ram_table->bright_pos_gain[0][2] = 0x20;
- ram_table->bright_pos_gain[0][3] = 0x20;
- ram_table->bright_pos_gain[1][0] = 0x20;
- ram_table->bright_pos_gain[1][1] = 0x20;
- ram_table->bright_pos_gain[1][2] = 0x20;
- ram_table->bright_pos_gain[1][3] = 0x20;
- ram_table->bright_pos_gain[2][0] = 0x20;
- ram_table->bright_pos_gain[2][1] = 0x20;
- ram_table->bright_pos_gain[2][2] = 0x20;
- ram_table->bright_pos_gain[2][3] = 0x20;
- ram_table->bright_pos_gain[3][0] = 0x20;
- ram_table->bright_pos_gain[3][1] = 0x20;
- ram_table->bright_pos_gain[3][2] = 0x20;
- ram_table->bright_pos_gain[3][3] = 0x20;
- ram_table->bright_pos_gain[4][0] = 0x20;
- ram_table->bright_pos_gain[4][1] = 0x20;
- ram_table->bright_pos_gain[4][2] = 0x20;
- ram_table->bright_pos_gain[4][3] = 0x20;
-
- ram_table->dark_pos_gain[0][0] = 0x00;
- ram_table->dark_pos_gain[0][1] = 0x00;
- ram_table->dark_pos_gain[0][2] = 0x00;
- ram_table->dark_pos_gain[0][3] = 0x00;
- ram_table->dark_pos_gain[1][0] = 0x00;
- ram_table->dark_pos_gain[1][1] = 0x00;
- ram_table->dark_pos_gain[1][2] = 0x00;
- ram_table->dark_pos_gain[1][3] = 0x00;
- ram_table->dark_pos_gain[2][0] = 0x00;
- ram_table->dark_pos_gain[2][1] = 0x00;
- ram_table->dark_pos_gain[2][2] = 0x00;
- ram_table->dark_pos_gain[2][3] = 0x00;
- ram_table->dark_pos_gain[3][0] = 0x00;
- ram_table->dark_pos_gain[3][1] = 0x00;
- ram_table->dark_pos_gain[3][2] = 0x00;
- ram_table->dark_pos_gain[3][3] = 0x00;
- ram_table->dark_pos_gain[4][0] = 0x00;
- ram_table->dark_pos_gain[4][1] = 0x00;
- ram_table->dark_pos_gain[4][2] = 0x00;
- ram_table->dark_pos_gain[4][3] = 0x00;
-
- ram_table->hybrid_factor[0] = 0xff;
- ram_table->hybrid_factor[1] = 0xff;
- ram_table->hybrid_factor[2] = 0xff;
- ram_table->hybrid_factor[3] = 0xc0;
-
- ram_table->contrast_factor[0] = 0x99;
- ram_table->contrast_factor[1] = 0x99;
- ram_table->contrast_factor[2] = 0x90;
- ram_table->contrast_factor[3] = 0x80;
-
- ram_table->iir_curve[0] = 0x65;
- ram_table->iir_curve[1] = 0x65;
- ram_table->iir_curve[2] = 0x65;
- ram_table->iir_curve[3] = 0x65;
- ram_table->iir_curve[4] = 0x65;
-
- //Gamma 2.2
- ram_table->crgb_thresh[0] = cpu_to_be16(0x127c);
- ram_table->crgb_thresh[1] = cpu_to_be16(0x151b);
- ram_table->crgb_thresh[2] = cpu_to_be16(0x17d5);
- ram_table->crgb_thresh[3] = cpu_to_be16(0x1a56);
- ram_table->crgb_thresh[4] = cpu_to_be16(0x1c83);
- ram_table->crgb_thresh[5] = cpu_to_be16(0x1e72);
- ram_table->crgb_thresh[6] = cpu_to_be16(0x20f0);
- ram_table->crgb_thresh[7] = cpu_to_be16(0x232b);
- ram_table->crgb_offset[0] = cpu_to_be16(0x2999);
- ram_table->crgb_offset[1] = cpu_to_be16(0x3999);
- ram_table->crgb_offset[2] = cpu_to_be16(0x4666);
- ram_table->crgb_offset[3] = cpu_to_be16(0x5999);
- ram_table->crgb_offset[4] = cpu_to_be16(0x6333);
- ram_table->crgb_offset[5] = cpu_to_be16(0x7800);
- ram_table->crgb_offset[6] = cpu_to_be16(0x8c00);
- ram_table->crgb_offset[7] = cpu_to_be16(0xa000);
- ram_table->crgb_slope[0] = cpu_to_be16(0x3609);
- ram_table->crgb_slope[1] = cpu_to_be16(0x2dfa);
- ram_table->crgb_slope[2] = cpu_to_be16(0x27ea);
- ram_table->crgb_slope[3] = cpu_to_be16(0x235d);
- ram_table->crgb_slope[4] = cpu_to_be16(0x2042);
- ram_table->crgb_slope[5] = cpu_to_be16(0x1dc3);
- ram_table->crgb_slope[6] = cpu_to_be16(0x1b1a);
- ram_table->crgb_slope[7] = cpu_to_be16(0x1910);
-
- fill_backlight_transform_table_v_2_2(
- params, ram_table, true);
-}
-
-static void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params, bool big_endian)
-{
- unsigned int i, j;
- unsigned int set = params.set;
-
- ram_table->flags = 0x0;
- ram_table->min_abm_backlight = (uint16_t)((big_endian) ?
- cpu_to_be16(params.min_abm_backlight) :
- cpu_to_le16(params.min_abm_backlight));
-
- for (i = 0; i < NUM_AGGR_LEVEL; i++) {
- ram_table->hybrid_factor[i] = (uint8_t)abm_settings[set][i].brightness_gain;
- ram_table->contrast_factor[i] = abm_settings[set][i].contrast_factor;
- ram_table->deviation_gain[i] = abm_settings[set][i].deviation_gain;
- ram_table->min_knee[i] = abm_settings[set][i].min_knee;
- ram_table->max_knee[i] = abm_settings[set][i].max_knee;
-
- for (j = 0; j < NUM_AMBI_LEVEL; j++) {
- ram_table->min_reduction[j][i] = abm_settings[set][i].min_reduction;
- ram_table->max_reduction[j][i] = abm_settings[set][i].max_reduction;
- ram_table->bright_pos_gain[j][i] = abm_settings[set][i].bright_pos_gain;
- ram_table->dark_pos_gain[j][i] = abm_settings[set][i].dark_pos_gain;
- }
- }
-
- ram_table->iir_curve[0] = 0x65;
- ram_table->iir_curve[1] = 0x65;
- ram_table->iir_curve[2] = 0x65;
- ram_table->iir_curve[3] = 0x65;
- ram_table->iir_curve[4] = 0x65;
-
- //Gamma 2.2
- ram_table->crgb_thresh[0] = bswap16_based_on_endian(big_endian, 0x127c);
- ram_table->crgb_thresh[1] = bswap16_based_on_endian(big_endian, 0x151b);
- ram_table->crgb_thresh[2] = bswap16_based_on_endian(big_endian, 0x17d5);
- ram_table->crgb_thresh[3] = bswap16_based_on_endian(big_endian, 0x1a56);
- ram_table->crgb_thresh[4] = bswap16_based_on_endian(big_endian, 0x1c83);
- ram_table->crgb_thresh[5] = bswap16_based_on_endian(big_endian, 0x1e72);
- ram_table->crgb_thresh[6] = bswap16_based_on_endian(big_endian, 0x20f0);
- ram_table->crgb_thresh[7] = bswap16_based_on_endian(big_endian, 0x232b);
- ram_table->crgb_offset[0] = bswap16_based_on_endian(big_endian, 0x2999);
- ram_table->crgb_offset[1] = bswap16_based_on_endian(big_endian, 0x3999);
- ram_table->crgb_offset[2] = bswap16_based_on_endian(big_endian, 0x4666);
- ram_table->crgb_offset[3] = bswap16_based_on_endian(big_endian, 0x5999);
- ram_table->crgb_offset[4] = bswap16_based_on_endian(big_endian, 0x6333);
- ram_table->crgb_offset[5] = bswap16_based_on_endian(big_endian, 0x7800);
- ram_table->crgb_offset[6] = bswap16_based_on_endian(big_endian, 0x8c00);
- ram_table->crgb_offset[7] = bswap16_based_on_endian(big_endian, 0xa000);
- ram_table->crgb_slope[0] = bswap16_based_on_endian(big_endian, 0x3609);
- ram_table->crgb_slope[1] = bswap16_based_on_endian(big_endian, 0x2dfa);
- ram_table->crgb_slope[2] = bswap16_based_on_endian(big_endian, 0x27ea);
- ram_table->crgb_slope[3] = bswap16_based_on_endian(big_endian, 0x235d);
- ram_table->crgb_slope[4] = bswap16_based_on_endian(big_endian, 0x2042);
- ram_table->crgb_slope[5] = bswap16_based_on_endian(big_endian, 0x1dc3);
- ram_table->crgb_slope[6] = bswap16_based_on_endian(big_endian, 0x1b1a);
- ram_table->crgb_slope[7] = bswap16_based_on_endian(big_endian, 0x1910);
-
- fill_backlight_transform_table_v_2_2(
- params, ram_table, big_endian);
-}
-
-bool dmub_init_abm_config(struct resource_pool *res_pool,
- struct dmcu_iram_parameters params,
- unsigned int inst)
-{
- struct iram_table_v_2_2 ram_table;
- struct abm_config_table config;
- unsigned int set = params.set;
- bool result = false;
- uint32_t i, j = 0;
-
- if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
- return false;
-
- memset(&ram_table, 0, sizeof(ram_table));
- memset(&config, 0, sizeof(config));
-
- fill_iram_v_2_3(&ram_table, params, false);
-
- // We must copy to structure that is aligned to 32-bit
- for (i = 0; i < NUM_POWER_FN_SEGS; i++) {
- config.crgb_thresh[i] = ram_table.crgb_thresh[i];
- config.crgb_offset[i] = ram_table.crgb_offset[i];
- config.crgb_slope[i] = ram_table.crgb_slope[i];
- }
-
- for (i = 0; i < NUM_BL_CURVE_SEGS; i++) {
- config.backlight_thresholds[i] = ram_table.backlight_thresholds[i];
- config.backlight_offsets[i] = ram_table.backlight_offsets[i];
- }
-
- for (i = 0; i < NUM_AMBI_LEVEL; i++)
- config.iir_curve[i] = ram_table.iir_curve[i];
-
- for (i = 0; i < NUM_AMBI_LEVEL; i++) {
- for (j = 0; j < NUM_AGGR_LEVEL; j++) {
- config.min_reduction[i][j] = ram_table.min_reduction[i][j];
- config.max_reduction[i][j] = ram_table.max_reduction[i][j];
- config.bright_pos_gain[i][j] = ram_table.bright_pos_gain[i][j];
- config.dark_pos_gain[i][j] = ram_table.dark_pos_gain[i][j];
- }
- }
-
- for (i = 0; i < NUM_AGGR_LEVEL; i++) {
- config.hybrid_factor[i] = ram_table.hybrid_factor[i];
- config.contrast_factor[i] = ram_table.contrast_factor[i];
- config.deviation_gain[i] = ram_table.deviation_gain[i];
- config.min_knee[i] = ram_table.min_knee[i];
- config.max_knee[i] = ram_table.max_knee[i];
- }
-
- if (params.backlight_ramping_override) {
-
- ASSERT(params.backlight_ramping_reduction <= 0xFFFF);
- ASSERT(params.backlight_ramping_start <= 0xFFFF);
- for (i = 0; i < NUM_AGGR_LEVEL; i++) {
- config.blRampReduction[i] = (uint16_t)params.backlight_ramping_reduction;
- config.blRampStart[i] = (uint16_t)params.backlight_ramping_start;
- }
- } else {
- for (i = 0; i < NUM_AGGR_LEVEL; i++) {
- config.blRampReduction[i] = abm_settings[set][i].blRampReduction;
- config.blRampStart[i] = abm_settings[set][i].blRampStart;
- }
- }
-
- config.min_abm_backlight = ram_table.min_abm_backlight;
-
- if (res_pool->multiple_abms[inst]) {
- result = res_pool->multiple_abms[inst]->funcs->init_abm_config(
- res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst);
- } else
- result = res_pool->abm->funcs->init_abm_config(
- res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0);
-
- return result;
-}
-
-bool dmcu_load_iram(struct dmcu *dmcu,
- struct dmcu_iram_parameters params)
-{
- unsigned char ram_table[IRAM_SIZE];
- bool result = false;
-
- if (dmcu == NULL)
- return false;
-
- if (dmcu && !dmcu->funcs->is_dmcu_initialized(dmcu))
- return true;
-
- memset(&ram_table, 0, sizeof(ram_table));
-
- if (dmcu->dmcu_version.abm_version == 0x24) {
- fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true);
- result = dmcu->funcs->load_iram(dmcu, 0, (char *)(&ram_table),
- IRAM_RESERVE_AREA_START_V2_2);
- } else if (dmcu->dmcu_version.abm_version == 0x23) {
- fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true);
-
- result = dmcu->funcs->load_iram(
- dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
- } else if (dmcu->dmcu_version.abm_version == 0x22) {
- fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params);
-
- result = dmcu->funcs->load_iram(
- dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
- } else {
- fill_iram_v_2((struct iram_table_v_2 *)ram_table, params);
-
- result = dmcu->funcs->load_iram(
- dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2);
-
- if (result)
- result = dmcu->funcs->load_iram(
- dmcu, IRAM_RESERVE_AREA_END_V2 + 1,
- (char *)(&ram_table) + IRAM_RESERVE_AREA_END_V2 + 1,
- sizeof(ram_table) - IRAM_RESERVE_AREA_END_V2 - 1);
- }
-
- return result;
-}
-
/*
* is_psr_su_specific_panel() - check if sink is AMD vendor-specific PSR-SU
* supported eDP device.
@@ -1073,31 +283,6 @@ void calculate_replay_link_off_frame_count(struct dc_link *link,
link->replay_settings.link_off_frame_count = max_link_off_frame_count;
}
-bool fill_custom_backlight_caps(unsigned int config_no, struct dm_acpi_atif_backlight_caps *caps)
-{
- unsigned int data_points_size;
- uint64_t caps_size;
-
- if (config_no >= ARRAY_SIZE(custom_backlight_profiles))
- return false;
-
- data_points_size = custom_backlight_profiles[config_no].num_data_points
- * sizeof(custom_backlight_profiles[config_no].data_points[0]);
-
- caps_size = sizeof(struct dm_acpi_atif_backlight_caps) - sizeof(caps->data_points) + data_points_size;
- ASSERT(caps_size <= 0xFFFF);
- caps->size = (uint16_t)caps_size;
- caps->flags = 0;
- caps->error_code = 0;
- caps->ac_level_percentage = custom_backlight_profiles[config_no].ac_level_percentage;
- caps->dc_level_percentage = custom_backlight_profiles[config_no].dc_level_percentage;
- caps->min_input_signal = custom_backlight_profiles[config_no].min_input_signal;
- caps->max_input_signal = custom_backlight_profiles[config_no].max_input_signal;
- caps->num_data_points = (uint8_t)custom_backlight_profiles[config_no].num_data_points;
- memcpy(caps->data_points, custom_backlight_profiles[config_no].data_points, data_points_size);
- return true;
-}
-
void reset_replay_dsync_error_count(struct dc_link *link)
{
link->replay_settings.replay_desync_error_fail_count = 0;
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
index 87d31d9dce5a..94d2521355ce 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
@@ -28,6 +28,7 @@
#include "dc/inc/hw/dmcu.h"
#include "dc/inc/hw/abm.h"
#include "dc/inc/core_types.h"
+#include "mod_power.h"
struct resource_pool;
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 12/20] drm/amd/display: Add additional IPS entry/exit for PSR/Replay
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (10 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 11/20] drm/amd/display: Separate ABM functions into dedicated power_abm.c file James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 13/20] drm/amd/display: Enable IPS on DCN42 James Lin
` (8 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, James Lin
From: Ivan Lipski <ivan.lipski@amd.com>
[Why]
Multiple paths issue DMUB commands without managing IPS state, causing
dc_wake_and_execute_gpint/dmub_cmd to internally wake from IPS and
reallow idle. This flips idle_allowed back to true while
idle_optimizations_allowed remains false during in-flight commits,
desynchronizing the two flags.
Affected paths:
- amdgpu_dm_psr_set_event() and amdgpu_dm_replay_set_event() calls from
amdgpu_dm_handle_vrr_transition(), amdgpu_dm_commit_planes() and
amdgpu_dm_mod_power_update_streams(), that are invoked on atomic commits.
- debugfs psr_get(), psr_read_residency(), replay_get_state(),
replay_set_residency() access hardware without holding dc_lock or
disabling IPS.
[How]
- Explicitly exit IPS before PSR/Replay set_event w/ hw_programming,
called within atomic commit.
- Wrap debugfs PSR/Replay state getters and setters with IPS exit/entry +
dc_lock.
Reviewed-by: Sunpeng Li <sunpeng.li@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 77 +++++++++++++++++++
2 files changed, 81 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7ff1af3528dd..4e9b4fd505c2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9937,6 +9937,7 @@ static void amdgpu_dm_handle_vrr_transition(struct amdgpu_display_manager *dm,
__func__, new_state->base.crtc->base.id);
scoped_guard(mutex, &dm->dc_lock) {
+ dc_exit_ips_for_hw_access(dm->dc);
amdgpu_dm_psr_set_event(dm, new_state->stream, true,
psr_event_vrr_transition, true);
amdgpu_dm_replay_set_event(dm, new_state->stream, true,
@@ -9952,6 +9953,7 @@ static void amdgpu_dm_handle_vrr_transition(struct amdgpu_display_manager *dm,
__func__, new_state->base.crtc->base.id);
scoped_guard(mutex, &dm->dc_lock) {
+ dc_exit_ips_for_hw_access(dm->dc);
amdgpu_dm_psr_set_event(dm, new_state->stream, false,
psr_event_vrr_transition, false);
amdgpu_dm_replay_set_event(dm, new_state->stream, false,
@@ -10253,6 +10255,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
mutex_lock(&dm->dc_lock);
acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
timestamp_ns;
+ dc_exit_ips_for_hw_access(dm->dc);
amdgpu_dm_psr_set_event(dm, acrtc_state->stream, true,
psr_event_hw_programming, true);
mutex_unlock(&dm->dc_lock);
@@ -10610,6 +10613,7 @@ static void amdgpu_dm_mod_power_update_streams(struct drm_atomic_state *state,
*/
if (old_crtc_state->active) {
scoped_guard(mutex, &dm->dc_lock) {
+ dc_exit_ips_for_hw_access(dm->dc);
amdgpu_dm_psr_set_event(dm, dm_old_crtc_state->stream, true,
psr_event_hw_programming, true);
amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, true,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 49226d6d0311..4e68a3541639 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -3163,10 +3163,25 @@ static int replay_get_state(void *data, u64 *val)
{
struct amdgpu_dm_connector *connector = data;
struct dc_link *link = connector->dc_link;
+ struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
+ struct dc *dc = adev->dm.dc;
uint64_t state = REPLAY_STATE_INVALID;
+ bool reallow_idle = false;
+
+ mutex_lock(&adev->dm.dc_lock);
+
+ if (dc->idle_optimizations_allowed) {
+ dc_allow_idle_optimizations(dc, false);
+ reallow_idle = true;
+ }
dc_link_get_replay_state(link, &state);
+ if (reallow_idle)
+ dc_allow_idle_optimizations(dc, true);
+
+ mutex_unlock(&adev->dm.dc_lock);
+
*val = state;
return 0;
@@ -3179,10 +3194,26 @@ static int replay_set_residency(void *data, u64 val)
{
struct amdgpu_dm_connector *connector = data;
struct dc_link *link = connector->dc_link;
+ struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
+ struct dc *dc = adev->dm.dc;
bool is_start = (val != 0);
u32 residency = 0;
+ bool reallow_idle = false;
+
+ mutex_lock(&adev->dm.dc_lock);
+
+ if (dc->idle_optimizations_allowed) {
+ dc_allow_idle_optimizations(dc, false);
+ reallow_idle = true;
+ }
link->dc->link_srv->edp_replay_residency(link, &residency, is_start, PR_RESIDENCY_MODE_PHY);
+
+ if (reallow_idle)
+ dc_allow_idle_optimizations(dc, true);
+
+ mutex_unlock(&adev->dm.dc_lock);
+
return 0;
}
@@ -3193,9 +3224,25 @@ static int replay_get_residency(void *data, u64 *val)
{
struct amdgpu_dm_connector *connector = data;
struct dc_link *link = connector->dc_link;
+ struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
+ struct dc *dc = adev->dm.dc;
u32 residency = 0;
+ bool reallow_idle = false;
+
+ mutex_lock(&adev->dm.dc_lock);
+
+ if (dc->idle_optimizations_allowed) {
+ dc_allow_idle_optimizations(dc, false);
+ reallow_idle = true;
+ }
link->dc->link_srv->edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY);
+
+ if (reallow_idle)
+ dc_allow_idle_optimizations(dc, true);
+
+ mutex_unlock(&adev->dm.dc_lock);
+
*val = (u64)residency;
return 0;
@@ -3208,10 +3255,25 @@ static int psr_get(void *data, u64 *val)
{
struct amdgpu_dm_connector *connector = data;
struct dc_link *link = connector->dc_link;
+ struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
+ struct dc *dc = adev->dm.dc;
enum dc_psr_state state = PSR_STATE0;
+ bool reallow_idle = false;
+
+ mutex_lock(&adev->dm.dc_lock);
+
+ if (dc->idle_optimizations_allowed) {
+ dc_allow_idle_optimizations(dc, false);
+ reallow_idle = true;
+ }
dc_link_get_psr_state(link, &state);
+ if (reallow_idle)
+ dc_allow_idle_optimizations(dc, true);
+
+ mutex_unlock(&adev->dm.dc_lock);
+
*val = state;
return 0;
@@ -3224,10 +3286,25 @@ static int psr_read_residency(void *data, u64 *val)
{
struct amdgpu_dm_connector *connector = data;
struct dc_link *link = connector->dc_link;
+ struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
+ struct dc *dc = adev->dm.dc;
u32 residency = 0;
+ bool reallow_idle = false;
+
+ mutex_lock(&adev->dm.dc_lock);
+
+ if (dc->idle_optimizations_allowed) {
+ dc_allow_idle_optimizations(dc, false);
+ reallow_idle = true;
+ }
link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY);
+ if (reallow_idle)
+ dc_allow_idle_optimizations(dc, true);
+
+ mutex_unlock(&adev->dm.dc_lock);
+
*val = (u64)residency;
return 0;
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 13/20] drm/amd/display: Enable IPS on DCN42
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (11 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 12/20] drm/amd/display: Add additional IPS entry/exit for PSR/Replay James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 14/20] drm/amd/display: Fix enum decl warnings James Lin
` (7 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, James Lin
From: Ivan Lipski <ivan.lipski@amd.com>
[Why & How]
Fully enable IPS to achieve higher power savings.
Reviewed-by: Sunpeng Li <sunpeng.li@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4e9b4fd505c2..c41f017fe8f2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1867,7 +1867,7 @@ static enum dmub_ips_disable_type dm_get_default_ips_mode(
ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
break;
case IP_VERSION(4, 2, 0):
- ret = DMUB_IPS_DISABLE_ALL;
+ ret = DMUB_IPS_ENABLE;
break;
default:
/* ASICs older than DCN35 do not have IPSs */
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 14/20] drm/amd/display: Fix enum decl warnings
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (12 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 13/20] drm/amd/display: Enable IPS on DCN42 James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 15/20] drm/amd/display: enable ODM 2:1 on single eDP based on pixel clock James Lin
` (6 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Gaghik Khachatrian, Aric Cyr,
James Lin
From: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
[Why]
warnings were triggered by enum forward declarations that are not
valid in C++ without an explicit underlying type.
[How]
- Replace problematic enum forward declarations with C++-safe forms where
applicable.
- Use plain integer types for interface-only declarations that do not
require strong enum typing.
- Update dependent winterface signatures and related type usage
consistently.
- Add required include and type-visibility fixes to avoid follow-on parse
and type-resolution issues.
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
drivers/gpu/drm/amd/display/dc/dm_helpers.h | 1 +
.../amd/display/modules/inc/mod_color_types.h | 47 +++++++++++++++++++
.../amd/display/modules/inc/mod_info_packet.h | 9 +---
.../modules/inc/mod_info_packet_types.h | 37 +++++++++++++++
4 files changed, 86 insertions(+), 8 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h
create mode 100644 drivers/gpu/drm/amd/display/modules/inc/mod_info_packet_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
index 107aec6a1265..63704d21a0b5 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
@@ -30,6 +30,7 @@
#ifndef __DM_HELPERS__
#define __DM_HELPERS__
+#include "modules/inc/mod_info_packet_types.h"
#include "dc_types.h"
#include "dc.h"
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h b/drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h
new file mode 100644
index 000000000000..bf7313df585b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef MOD_COLOR_TYPES_H_
+#define MOD_COLOR_TYPES_H_
+
+enum predefined_gamut_type {
+ gamut_type_bt709,
+ gamut_type_bt601,
+ gamut_type_adobe_rgb,
+ gamut_type_srgb,
+ gamut_type_bt2020,
+ gamut_type_dcip3,
+ gamut_type_unknown,
+};
+
+enum predefined_white_point_type {
+ white_point_type_5000k_horizon,
+ white_point_type_6500k_noon,
+ white_point_type_7500k_north_sky,
+ white_point_type_9300k,
+ white_point_type_unknown,
+};
+
+#endif /* MOD_COLOR_TYPES_H_ */
\ No newline at end of file
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
index ddd64b7e4c04..11b127eb13d8 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
@@ -27,6 +27,7 @@
#define MOD_INFO_PACKET_H_
#include "dm_services.h"
+#include "mod_info_packet_types.h"
#include "mod_shared.h"
//Forward Declarations
struct dc_stream_state;
@@ -47,14 +48,6 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream,
struct dc_info_packet *info_packet);
-enum adaptive_sync_type {
- ADAPTIVE_SYNC_TYPE_NONE = 0,
- ADAPTIVE_SYNC_TYPE_DP = 1,
- FREESYNC_TYPE_PCON_IN_WHITELIST = 2,
- FREESYNC_TYPE_PCON_NOT_IN_WHITELIST = 3,
- ADAPTIVE_SYNC_TYPE_EDP = 4,
-};
-
enum adaptive_sync_sdp_version {
AS_SDP_VER_0 = 0x0,
AS_SDP_VER_1 = 0x1,
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet_types.h b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet_types.h
new file mode 100644
index 000000000000..30a5259ef36b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet_types.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef MOD_INFO_PACKET_TYPES_H_
+#define MOD_INFO_PACKET_TYPES_H_
+
+enum adaptive_sync_type {
+ ADAPTIVE_SYNC_TYPE_NONE = 0,
+ ADAPTIVE_SYNC_TYPE_DP = 1,
+ FREESYNC_TYPE_PCON_IN_WHITELIST = 2,
+ FREESYNC_TYPE_PCON_NOT_IN_WHITELIST = 3,
+ ADAPTIVE_SYNC_TYPE_EDP = 4,
+};
+
+#endif /* MOD_INFO_PACKET_TYPES_H_ */
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 15/20] drm/amd/display: enable ODM 2:1 on single eDP based on pixel clock
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (13 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 14/20] drm/amd/display: Fix enum decl warnings James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 16/20] drm/amd/display: Revert "Unify fast update classification paths" James Lin
` (5 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Charlene Liu, Dillon Varone,
James Lin
From: Charlene Liu <Charlene.Liu@amd.com>
[Why & How]
this is to force ODM 2:1 on single eDP to lower dispclk/dppclk.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../dc/resource/dcn42/dcn42_resource.c | 4 ++++
.../dc/resource/dcn42/dcn42_resource_fpu.c | 22 +++++++++++++++++++
.../dc/resource/dcn42/dcn42_resource_fpu.h | 2 +-
4 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e5933e3a8206..30ff7f1b9513 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1219,6 +1219,7 @@ struct dc_debug_options {
unsigned int force_vmin_threshold;
bool enable_otg_frame_sync_pwa;
unsigned int min_deep_sleep_dcfclk_khz;
+ unsigned int force_odm2to1_for_edp_pixclk_mhz;
};
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
index 57c6e81280bc..01a7639da80b 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
@@ -765,6 +765,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.min_deep_sleep_dcfclk_khz = 8000,
.replay_skip_crtc_disabled = true,
.psr_skip_crtc_disable = true,
+ .force_odm2to1_for_edp_pixclk_mhz = 550, // Force ODM 2to1 for eDP when pixel clock is above 550MHz
};
static const struct dc_check_config config_defaults = {
@@ -1721,9 +1722,12 @@ enum dc_status dcn42_validate_bandwidth(struct dc *dc,
DC_FP_START();
+ dcn42_decide_odm_override(dc, context);
+
out = dml2_validate(dc, context, context->bw_ctx.dml2,
validate_mode);
+
if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) {
/*not required for mode enumeration*/
dcn42_decide_zstate_support(dc, context);
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c
index 33b9775420d3..ee330559c233 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c
@@ -45,3 +45,25 @@ void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context)
context->bw_ctx.bw.dcn.clk.zstate_support = support;
}
+
+bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context)
+{
+ bool odm_override = false;
+
+ DC_LOGGER_INIT(dc->ctx->logger);
+ if (dc->ctx->dce_environment == DCE_ENV_DIAG)
+ return false;
+
+ if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
+
+ if (dc->debug.force_odm2to1_for_edp_pixclk_mhz != 0 &&
+ context->streams[0]->timing.pix_clk_100hz > dc->debug.force_odm2to1_for_edp_pixclk_mhz * 10000) {
+ odm_override = true;
+ context->streams[0]->debug.force_odm_combine_segments = 2;
+ }
+ DC_LOG_SMU("odm_override: %d, eDP pixelclock: %d, force_odm2to1_for_edp_pixclk_mhz: %d\n",
+ odm_override, context->streams[0]->timing.pix_clk_100hz / 10000, dc->debug.force_odm2to1_for_edp_pixclk_mhz);
+ }
+ return odm_override;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h
index e32103220507..aff7be777681 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h
@@ -29,5 +29,5 @@
#include "core_types.h"
void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context);
-
+bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context);
#endif /* _DCN42_RESOURCE_FPU_H_ */
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 16/20] drm/amd/display: Revert "Unify fast update classification paths"
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (14 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 15/20] drm/amd/display: enable ODM 2:1 on single eDP based on pixel clock James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 17/20] drm/amd/display: Revert "Enable HUBP/OPTC/DPP power gating" James Lin
` (4 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Ovidiu Bunea, Aric Cyr,
James Lin
From: Ovidiu Bunea <ovidiu.bunea@amd.com>
[why & how]
This change causes regressions in ACPI and display off/on testing.
Revert the change to unblock testing.
This reverts commit e8d5c0ef03bb7a3fea8495908e0c47d3ef31f1bf.
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 242 ++++++++++++++++--
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 12 -
drivers/gpu/drm/amd/display/dc/dc.h | 34 ++-
drivers/gpu/drm/amd/display/dc/dc_stream.h | 3 -
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 2 -
5 files changed, 252 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 842a8b11b17a..48d32adb9eb3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3012,8 +3012,7 @@ static struct surface_update_descriptor det_surface_update(
update_flags->bits.gamut_remap_change ||
update_flags->bits.input_csc_change ||
update_flags->bits.cm_hist_change ||
- update_flags->bits.coeff_reduction_change ||
- update_flags->bits.cursor_csc_color_matrix_change)) {
+ update_flags->bits.coeff_reduction_change)) {
elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
}
return overall_type;
@@ -3103,10 +3102,8 @@ static struct surface_update_descriptor check_update_surfaces_for_stream(
stream_update->vrr_active_variable || stream_update->vrr_active_fixed))
su_flags->bits.fams_changed = 1;
- if (stream_update->scaler_sharpener_update) {
+ if (stream_update->scaler_sharpener_update)
su_flags->bits.scaler_sharpener = 1;
- elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM);
- }
if (stream_update->sharpening_required)
su_flags->bits.sharpening_required = 1;
@@ -3171,16 +3168,6 @@ static struct surface_update_descriptor check_update_surfaces_for_stream(
su_flags->bits.cursor_pos = 1;
elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
}
-
- if (stream_update->func_shaper) {
- su_flags->bits.func_shaper = 1;
- elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM);
- }
-
- if (stream_update->lut3d_func) {
- su_flags->bits.lut3d_func = 1;
- elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM);
- }
}
for (int i = 0 ; i < surface_count; i++) {
@@ -4550,7 +4537,7 @@ static void build_dmub_update_dirty_rect(
}
}
-bool dc_check_address_only_update(union surface_update_flags update_flags)
+static bool check_address_only_update(union surface_update_flags update_flags)
{
union surface_update_flags addr_only_update_flags;
addr_only_update_flags.raw = 0;
@@ -4656,7 +4643,7 @@ static void commit_planes_for_stream_fast(struct dc *dc,
for (i = 0; i < surface_count; i++) {
if (srf_updates[i].surface &&
srf_updates[i].surface->update_flags.raw &&
- !dc_check_address_only_update(srf_updates[i].surface->update_flags)) {
+ !check_address_only_update(srf_updates[i].surface->update_flags)) {
/* more than address update, need to acquire FAMS2 lock */
should_offload_fams2_flip = false;
break;
@@ -5624,6 +5611,127 @@ static bool commit_minimal_transition_state(struct dc *dc,
return true;
}
+void populate_fast_updates(struct dc_fast_update *fast_update,
+ struct dc_surface_update *srf_updates,
+ int surface_count,
+ struct dc_stream_update *stream_update)
+{
+ int i = 0;
+
+ if (stream_update) {
+ fast_update[0].out_transfer_func = stream_update->out_transfer_func;
+ fast_update[0].output_csc_transform = stream_update->output_csc_transform;
+ fast_update[0].cursor_attributes = stream_update->cursor_attributes;
+ fast_update[0].cursor_position = stream_update->cursor_position;
+ fast_update[0].periodic_interrupt = stream_update->periodic_interrupt;
+ fast_update[0].dither_option = stream_update->dither_option;
+ fast_update[0].gamut_remap = stream_update->gamut_remap;
+ fast_update[0].vrr_infopacket = stream_update->vrr_infopacket;
+ fast_update[0].vsc_infopacket = stream_update->vsc_infopacket;
+ fast_update[0].vsp_infopacket = stream_update->vsp_infopacket;
+ fast_update[0].hfvsif_infopacket = stream_update->hfvsif_infopacket;
+ fast_update[0].vtem_infopacket = stream_update->vtem_infopacket;
+ fast_update[0].adaptive_sync_infopacket = stream_update->adaptive_sync_infopacket;
+ fast_update[0].avi_infopacket = stream_update->avi_infopacket;
+ fast_update[0].hdr_static_metadata = stream_update->hdr_static_metadata;
+ } else {
+ fast_update[0].out_transfer_func = NULL;
+ fast_update[0].output_csc_transform = NULL;
+ fast_update[0].cursor_attributes = NULL;
+ fast_update[0].cursor_position = NULL;
+ fast_update[0].periodic_interrupt = NULL;
+ fast_update[0].dither_option = NULL;
+ fast_update[0].gamut_remap = NULL;
+ fast_update[0].vrr_infopacket = NULL;
+ fast_update[0].vsc_infopacket = NULL;
+ fast_update[0].vsp_infopacket = NULL;
+ fast_update[0].hfvsif_infopacket = NULL;
+ fast_update[0].vtem_infopacket = NULL;
+ fast_update[0].adaptive_sync_infopacket = NULL;
+ fast_update[0].avi_infopacket = NULL;
+ fast_update[0].hdr_static_metadata = NULL;
+ }
+
+ for (i = 0; i < surface_count; i++) {
+ fast_update[i].flip_addr = srf_updates[i].flip_addr;
+ fast_update[i].gamma = srf_updates[i].gamma;
+ fast_update[i].gamut_remap_matrix = srf_updates[i].gamut_remap_matrix;
+ fast_update[i].input_csc_color_matrix = srf_updates[i].input_csc_color_matrix;
+ fast_update[i].coeff_reduction_factor = srf_updates[i].coeff_reduction_factor;
+ fast_update[i].cursor_csc_color_matrix = srf_updates[i].cursor_csc_color_matrix;
+ fast_update[i].cm_hist_control = srf_updates[i].cm_hist_control;
+ }
+}
+
+static bool fast_updates_exist(const struct dc_fast_update *fast_update, int surface_count)
+{
+ int i;
+
+ if (fast_update[0].out_transfer_func ||
+ fast_update[0].output_csc_transform ||
+ fast_update[0].cursor_attributes ||
+ fast_update[0].cursor_position ||
+ fast_update[0].periodic_interrupt ||
+ fast_update[0].dither_option ||
+ fast_update[0].gamut_remap ||
+ fast_update[0].vrr_infopacket ||
+ fast_update[0].vsc_infopacket ||
+ fast_update[0].vsp_infopacket ||
+ fast_update[0].hfvsif_infopacket ||
+ fast_update[0].vtem_infopacket ||
+ fast_update[0].adaptive_sync_infopacket ||
+ fast_update[0].avi_infopacket ||
+ fast_update[0].hdr_static_metadata)
+ return true;
+
+ for (i = 0; i < surface_count; i++) {
+ if (fast_update[i].flip_addr ||
+ fast_update[i].gamma ||
+ fast_update[i].gamut_remap_matrix ||
+ fast_update[i].input_csc_color_matrix ||
+ fast_update[i].cursor_csc_color_matrix ||
+ fast_update[i].cm_hist_control ||
+ fast_update[i].coeff_reduction_factor)
+ return true;
+ }
+
+ return false;
+}
+
+bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count)
+{
+ int i;
+
+ if (fast_update[0].out_transfer_func ||
+ fast_update[0].output_csc_transform ||
+ fast_update[0].gamut_remap ||
+ fast_update[0].cursor_attributes ||
+ fast_update[0].cursor_position ||
+ fast_update[0].periodic_interrupt ||
+ fast_update[0].dither_option ||
+ fast_update[0].vrr_infopacket ||
+ fast_update[0].vsc_infopacket ||
+ fast_update[0].vsp_infopacket ||
+ fast_update[0].hfvsif_infopacket ||
+ fast_update[0].vtem_infopacket ||
+ fast_update[0].adaptive_sync_infopacket ||
+ fast_update[0].avi_infopacket ||
+ fast_update[0].hdr_static_metadata)
+ return true;
+
+ for (i = 0; i < surface_count; i++) {
+ if (fast_update[i].input_csc_color_matrix ||
+ fast_update[i].gamma ||
+ fast_update[i].gamut_remap_matrix ||
+ fast_update[i].coeff_reduction_factor ||
+ fast_update[i].cm_hist_control ||
+ fast_update[i].cursor_csc_color_matrix)
+ return true;
+ }
+
+ return false;
+}
+
static bool full_update_required_weak(
const struct dc *dc,
const struct dc_surface_update *srf_updates,
@@ -5652,6 +5760,72 @@ static bool full_update_required_weak(
return false;
}
+static bool full_update_required(
+ const struct dc *dc,
+ const struct dc_surface_update *srf_updates,
+ int surface_count,
+ const struct dc_stream_update *stream_update,
+ const struct dc_stream_state *stream)
+{
+ if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream))
+ return true;
+
+ for (int i = 0; i < surface_count; i++) {
+ if (srf_updates &&
+ (srf_updates[i].plane_info ||
+ srf_updates[i].scaling_info ||
+ (srf_updates[i].hdr_mult.value &&
+ srf_updates[i].hdr_mult.value != srf_updates->surface->hdr_mult.value) ||
+ (srf_updates[i].sdr_white_level_nits &&
+ srf_updates[i].sdr_white_level_nits != srf_updates->surface->sdr_white_level_nits) ||
+ srf_updates[i].in_transfer_func ||
+ srf_updates[i].func_shaper ||
+ srf_updates[i].lut3d_func ||
+ srf_updates[i].surface->force_full_update ||
+ (srf_updates[i].flip_addr &&
+ srf_updates[i].flip_addr->address.tmz_surface != srf_updates[i].surface->address.tmz_surface) ||
+ (srf_updates[i].cm2_params &&
+ (srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting != srf_updates[i].surface->mcm_shaper_3dlut_setting ||
+ srf_updates[i].cm2_params->component_settings.lut1d_enable != srf_updates[i].surface->mcm_lut1d_enable))))
+ return true;
+ }
+
+ if (stream_update &&
+ (((stream_update->src.height != 0 && stream_update->src.width != 0) ||
+ (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
+ stream_update->integer_scaling_update) ||
+ stream_update->abm_level ||
+ stream_update->dpms_off ||
+ stream_update->allow_freesync ||
+ stream_update->vrr_active_variable ||
+ stream_update->vrr_active_fixed ||
+ stream_update->output_color_space ||
+ stream_update->wb_update ||
+ stream_update->dsc_config ||
+ stream_update->mst_bw_update ||
+ stream_update->func_shaper ||
+ stream_update->lut3d_func ||
+ stream_update->pending_test_pattern ||
+ stream_update->crtc_timing_adjust ||
+ stream_update->scaler_sharpener_update ||
+ stream_update->hw_cursor_req))
+ return true;
+
+ return false;
+}
+
+static bool fast_update_only(
+ const struct dc *dc,
+ const struct dc_fast_update *fast_update,
+ const struct dc_surface_update *srf_updates,
+ int surface_count,
+ const struct dc_stream_update *stream_update,
+ const struct dc_stream_state *stream)
+{
+ return fast_updates_exist(fast_update, surface_count)
+ && !full_update_required(dc, srf_updates, surface_count, stream_update, stream);
+}
+
static bool update_planes_and_stream_v2(struct dc *dc,
struct dc_surface_update *srf_updates, int surface_count,
struct dc_stream_state *stream,
@@ -5659,6 +5833,7 @@ static bool update_planes_and_stream_v2(struct dc *dc,
{
struct dc_state *context;
enum surface_update_type update_type;
+ struct dc_fast_update fast_update[MAX_SURFACES] = {0};
/* In cases where MPO and split or ODM are used transitions can
* cause underflow. Apply stream configuration with minimal pipe
@@ -5666,7 +5841,11 @@ static bool update_planes_and_stream_v2(struct dc *dc,
*/
bool force_minimal_pipe_splitting = 0;
bool is_plane_addition = 0;
+ bool is_fast_update_only;
+ populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);
+ is_fast_update_only = fast_update_only(dc, fast_update, srf_updates,
+ surface_count, stream_update, stream);
force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes(
dc,
stream,
@@ -5704,7 +5883,7 @@ static bool update_planes_and_stream_v2(struct dc *dc,
commit_minimal_transition_state_in_dc_update(dc, context, stream,
srf_updates, surface_count);
- if (update_type == UPDATE_TYPE_FAST && !dc->check_config.enable_legacy_fast_update) {
+ if (is_fast_update_only && !dc->check_config.enable_legacy_fast_update) {
commit_planes_for_stream_fast(dc,
srf_updates,
surface_count,
@@ -5740,8 +5919,13 @@ static void commit_planes_and_stream_update_on_current_context(struct dc *dc,
struct dc_stream_update *stream_update,
enum surface_update_type update_type)
{
+ struct dc_fast_update fast_update[MAX_SURFACES] = {0};
+
ASSERT(update_type < UPDATE_TYPE_FULL);
- if (update_type == UPDATE_TYPE_FAST &&
+ populate_fast_updates(fast_update, srf_updates, surface_count,
+ stream_update);
+ if (fast_update_only(dc, fast_update, srf_updates, surface_count,
+ stream_update, stream) &&
!dc->check_config.enable_legacy_fast_update)
commit_planes_for_stream_fast(dc,
srf_updates,
@@ -7744,6 +7928,23 @@ static bool update_planes_and_stream_prepare_v3(
ASSERT(scratch->flow == UPDATE_V3_FLOW_INVALID);
dc_exit_ips_for_hw_access(scratch->dc);
+ /* HWSS path determination needs to be done prior to updating the surface and stream states. */
+ struct dc_fast_update fast_update[MAX_SURFACES] = { 0 };
+
+ populate_fast_updates(fast_update,
+ scratch->surface_updates,
+ scratch->surface_count,
+ scratch->stream_update);
+
+ const bool is_hwss_fast_path_only =
+ fast_update_only(scratch->dc,
+ fast_update,
+ scratch->surface_updates,
+ scratch->surface_count,
+ scratch->stream_update,
+ scratch->stream) &&
+ !scratch->dc->check_config.enable_legacy_fast_update;
+
if (!update_planes_and_stream_state(
scratch->dc,
scratch->surface_updates,
@@ -7759,8 +7960,7 @@ static bool update_planes_and_stream_prepare_v3(
if (scratch->new_context == scratch->dc->current_state) {
ASSERT(scratch->update_type < UPDATE_TYPE_FULL);
- scratch->flow = (scratch->update_type == UPDATE_TYPE_FAST &&
- !scratch->dc->check_config.enable_legacy_fast_update)
+ scratch->flow = is_hwss_fast_path_only
? UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST
: UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FULL;
return true;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index ffa3130853c2..1916aa3ebaea 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -1057,18 +1057,6 @@ void hwss_build_fast_sequence(struct dc *dc,
(*num_steps)++;
}
- if (current_mpc_pipe->plane_state->update_flags.bits.lut_3d &&
- current_mpc_pipe->plane_state->mcm_luts.lut3d_data.lut3d_src ==
- DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM &&
- current_mpc_pipe->plane_state->mcm_shaper_3dlut_setting ==
- DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT &&
- current_mpc_pipe->plane_res.hubp->funcs->hubp_enable_3dlut_fl) {
- block_sequence[*num_steps].params.hubp_enable_3dlut_fl_params.hubp =
- current_mpc_pipe->plane_res.hubp;
- block_sequence[*num_steps].func = HUBP_ENABLE_3DLUT_FL;
- (*num_steps)++;
- }
-
if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) {
block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;
block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 30ff7f1b9513..d87bf8f4f56e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1467,14 +1467,11 @@ union surface_update_flags {
uint32_t full_update:1;
uint32_t sdr_white_level_nits:1;
uint32_t cm_hist_change:1;
- uint32_t reserved:2; /* adjust when adding new flags */
} bits;
uint32_t raw;
};
-bool dc_check_address_only_update(union surface_update_flags update_flags);
-
#define DC_REMOVE_PLANE_POINTERS 1
struct dc_plane_state {
@@ -1854,6 +1851,32 @@ struct dc_scaling_info {
struct scaling_taps scaling_quality;
};
+struct dc_fast_update {
+ const struct dc_flip_addrs *flip_addr;
+ const struct dc_gamma *gamma;
+ const struct colorspace_transform *gamut_remap_matrix;
+ const struct dc_csc_transform *input_csc_color_matrix;
+ const struct fixed31_32 *coeff_reduction_factor;
+ struct dc_transfer_func *out_transfer_func;
+ struct dc_csc_transform *output_csc_transform;
+ const struct dc_csc_transform *cursor_csc_color_matrix;
+ struct cm_hist_control *cm_hist_control;
+ /* stream-level fast updates */
+ const struct colorspace_transform *gamut_remap;
+ const struct dc_cursor_attributes *cursor_attributes;
+ const struct dc_cursor_position *cursor_position;
+ const struct periodic_interrupt_config *periodic_interrupt;
+ const enum dc_dither_option *dither_option;
+ struct dc_info_packet *vrr_infopacket;
+ struct dc_info_packet *vsc_infopacket;
+ struct dc_info_packet *vsp_infopacket;
+ struct dc_info_packet *hfvsif_infopacket;
+ struct dc_info_packet *vtem_infopacket;
+ struct dc_info_packet *adaptive_sync_infopacket;
+ struct dc_info_packet *avi_infopacket;
+ struct dc_info_packet *hdr_static_metadata;
+};
+
struct dc_surface_update {
struct dc_plane_state *surface;
@@ -1988,6 +2011,11 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
void get_audio_check(struct audio_info *aud_modes,
struct audio_check *aud_chk);
+bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count);
+void populate_fast_updates(struct dc_fast_update *fast_update,
+ struct dc_surface_update *srf_updates,
+ int surface_count,
+ struct dc_stream_update *stream_update);
/*
* Set up streams and links associated to drive sinks
* The streams parameter is an absolute set of all active streams.
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 1649fbab08aa..4154cd059562 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -123,9 +123,6 @@ union stream_update_flags {
uint32_t info_frame : 1;
uint32_t dmdata : 1;
uint32_t dither : 1;
- uint32_t func_shaper : 1;
- uint32_t lut3d_func : 1;
- uint32_t reserved : 11; /* adjust when adding new flags */
} bits;
uint32_t raw;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 204f11b784bb..124a1ccec741 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -493,12 +493,10 @@ void dcn401_populate_mcm_luts(struct dc *dc,
break;
case DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM:
switch (mcm_luts.lut3d_data.gpu_mem_params.size) {
-#if defined(CONFIG_DRM_AMD_DC_DCN4_2)
case DC_CM2_GPU_MEM_SIZE_333333:
if (dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33)
width = hubp_3dlut_fl_width_33;
break;
-#endif
case DC_CM2_GPU_MEM_SIZE_171717:
width = hubp_3dlut_fl_width_17;
break;
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 17/20] drm/amd/display: Revert "Enable HUBP/OPTC/DPP power gating"
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (15 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 16/20] drm/amd/display: Revert "Unify fast update classification paths" James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 18/20] drm/amd/display: Wrap DCN32 phantom-plane allocation in DC_RUN_WITH_PREEMPTION_ENABLED James Lin
` (3 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Leo Chen, Ovidiu Bunea,
James Lin
From: Leo Chen <leo.chen@amd.com>
[why & how]
Pipe power gating is causing regressions.
Revert to unblock testing and promotion
This reverts commit 265d90d95554555d18350e623ab823f3164bd462.
Reviewed-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
.../gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
index 01a7639da80b..52a1996a654f 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
@@ -694,9 +694,9 @@ static const struct dc_debug_options debug_defaults_drv = {
.clock_trace = true,
.disable_pplib_clock_request = false,
.ignore_pg = false,
- .disable_dpp_power_gate = false,
- .disable_hubp_power_gate = false,
- .disable_optc_power_gate = false,
+ .disable_dpp_power_gate = true,
+ .disable_hubp_power_gate = true,
+ .disable_optc_power_gate = true,
.disable_dsc_power_gate = false,
.disable_dio_power_gate = true,
.disable_hpo_power_gate = true,
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 18/20] drm/amd/display: Wrap DCN32 phantom-plane allocation in DC_RUN_WITH_PREEMPTION_ENABLED
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (16 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 17/20] drm/amd/display: Revert "Enable HUBP/OPTC/DPP power gating" James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 19/20] drm/amd/display: [FW Promotion] Release 0.1.59.0 James Lin
` (2 subsequent siblings)
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Mikhail Gavrilov, James Lin
From: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
[Why]
dcn32_validate_bandwidth() wraps dcn32_internal_validate_bw() with
DC_FP_START()/DC_FP_END(). In x86 non-RT, DC_FP_START takes fpregs_lock(),
which disables local softirqs.
The DML1 path through dcn32_enable_phantom_plane() calls kvzalloc() to
allocate ~335 KiB for dc_plane_state. This triggers the vmalloc path,
which calls BUG_ON(in_interrupt()) because it's invoked within the
FPU-enabled (softirq disabled) region, leading to a kernel crash.
[How]
Wrap the dc_state_create_phantom_plane() call with the
DC_RUN_WITH_PREEMPTION_ENABLED() macro to allow preemption during
this memory allocation.
Fixes: 235c67634230 ("drm/amd/display: add DCN32/321 specific files for Display Core")
Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/4470
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
.../drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index 28d21dd30106..1bdb4ffd2921 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -92,9 +92,14 @@
#include "dml/dcn32/dcn32_fpu.h"
#include "dc_state_priv.h"
+#include "dc_fpu.h"
#include "dml2_0/dml2_wrapper.h"
+#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED)
+#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code
+#endif
+
#define DC_LOGGER_INIT(logger)
enum dcn32_clk_src_array_id {
@@ -1688,7 +1693,8 @@ static void dcn32_enable_phantom_plane(struct dc *dc,
if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state)
phantom_plane = prev_phantom_plane;
else
- phantom_plane = dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state);
+ DC_RUN_WITH_PREEMPTION_ENABLED(phantom_plane =
+ dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state));
if (!phantom_plane)
continue;
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 19/20] drm/amd/display: [FW Promotion] Release 0.1.59.0
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (17 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 18/20] drm/amd/display: Wrap DCN32 phantom-plane allocation in DC_RUN_WITH_PREEMPTION_ENABLED James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-06 4:31 ` [PATCH 20/20] drm/amd/display: Promote DC to 3.2.382 James Lin
2026-05-11 13:05 ` [PATCH 00/20] DC Patches May 11 2026 Wheeler, Daniel
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Taimur Hassan, James Lin
From: Taimur Hassan <Syed.Hassan@amd.com>
[Why & How]
Update DMUB related command structure.
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 32 +++++++++++--------
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 300bbfe3c98d..c1becd664cb9 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -2378,24 +2378,24 @@ struct dmub_cmd_lsdma_data {
uint32_t dst_mip_max : 5;
uint32_t dst_swizzle_mode : 5;
uint32_t dst_mip_id : 5;
- uint32_t tmz : 1;
uint32_t dcc : 1;
+ uint32_t padding1 : 1;
uint32_t data_format : 6;
- uint32_t padding1 : 4;
+ uint32_t tmz : 4;
uint32_t dst_element_size : 3;
uint32_t num_type : 3;
uint32_t src_element_size : 3;
uint32_t write_compress : 2;
- uint32_t cache_policy_dst : 2;
- uint32_t cache_policy_src : 2;
+ uint32_t cache_policy_dst : 3;
+ uint32_t cache_policy_src : 3;
uint32_t read_compress : 2;
- uint32_t src_dim : 2;
- uint32_t dst_dim : 2;
+ uint32_t max_com : 2;
uint32_t max_uncom : 1;
- uint32_t max_com : 2;
- uint32_t padding : 30;
+ uint32_t dst_dim : 2;
+ uint32_t src_dim : 2;
+ uint32_t padding : 28;
} tiled_copy_data;
struct lsdma_linear_copy_data {
uint32_t src_lo;
@@ -2405,11 +2405,13 @@ struct dmub_cmd_lsdma_data {
uint32_t dst_hi;
uint32_t count : 30;
- uint32_t cache_policy_dst : 2;
+ uint32_t pad0 : 2;
- uint32_t tmz : 1;
- uint32_t cache_policy_src : 2;
- uint32_t padding : 29;
+ uint32_t tmz : 4;
+ uint32_t cache_policy_src : 3;
+ uint32_t cache_policy_dst : 3;
+ uint32_t pad1 : 22;
+ // DCC fields not included because linear mode on display does not support DCC
} linear_copy_data;
struct lsdma_linear_sub_window_copy_data {
uint32_t src_lo;
@@ -2433,11 +2435,13 @@ struct dmub_cmd_lsdma_data {
uint32_t src_slice_pitch;
uint32_t dst_slice_pitch;
- uint32_t tmz : 1;
+ uint32_t tmz : 4;
uint32_t element_size : 3;
uint32_t src_cache_policy : 3;
uint32_t dst_cache_policy : 3;
- uint32_t reserved0 : 22;
+ uint32_t reserved0 : 19;
+ // Linear mode on display does not support compression so DCC related fields are not included.
+ // The DCC fields in the command packet will be zero'd at the time of constructing the packet.
} linear_sub_window_copy_data;
struct lsdma_reg_write_data {
uint32_t reg_addr;
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 20/20] drm/amd/display: Promote DC to 3.2.382
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (18 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 19/20] drm/amd/display: [FW Promotion] Release 0.1.59.0 James Lin
@ 2026-05-06 4:31 ` James Lin
2026-05-11 13:05 ` [PATCH 00/20] DC Patches May 11 2026 Wheeler, Daniel
20 siblings, 0 replies; 22+ messages in thread
From: James Lin @ 2026-05-06 4:31 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, James Lin, Chenyu Chen, Taimur Hassan, James Lin
From: Taimur Hassan <Syed.Hassan@amd.com>
This version brings along following update:
-Revert "Enable HUBP/OPTC/DPP power gating"
-Revert "Unify fast update classification paths"
-enable ODM 2:1 on single eDP based on pixel clock
-Enable IPS on DCN42
-Add additional IPS entry/exit for PSR/Replay
-Separate ABM functions into dedicated power_abm.c file
-Fix always-true lower-bound assert
-Refactor dc_link_aux_transfer_raw
-only call pmfw if smu present flags true
-Fix multiple compiler warnings
-Fix CRC open failure during active rendering
-Fix white screen on boot with OLED panel
-Fix refresh rate round up case
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index d87bf8f4f56e..d0b6fad65bc0 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -63,7 +63,7 @@ struct dcn_dsc_reg_state;
struct dcn_optc_reg_state;
struct dcn_dccg_reg_state;
-#define DC_VER "3.2.381"
+#define DC_VER "3.2.382"
/**
* MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* RE: [PATCH 00/20] DC Patches May 11 2026
2026-05-06 4:30 [PATCH 00/20] DC Patches May 11 2026 James Lin
` (19 preceding siblings ...)
2026-05-06 4:31 ` [PATCH 20/20] drm/amd/display: Promote DC to 3.2.382 James Lin
@ 2026-05-11 13:05 ` Wheeler, Daniel
20 siblings, 0 replies; 22+ messages in thread
From: Wheeler, Daniel @ 2026-05-11 13:05 UTC (permalink / raw)
To: Lin, Ping Lei, amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry, Li, Sun peng (Leo), Pillai, Aurabindo, Li, Roman,
Lin, Wayne, Chung, ChiaHsuan (Tom), Zuo, Jerry, Wu, Ray,
LIPSKI, IVAN, Hung, Alex, Lin, Ping Lei, Chen, Chen-Yu
Public
Hi all,
This week this patchset was tested on 4 systems, two dGPU and two APU based, and tested across multiple display and connection types.
APU
* Single Display eDP -> 1080p 60hz, 1920x1200 165hz, 3840x2400 60hz
* Single Display DP (SST DSC) -> 4k144hz, 4k240hz
* Multi display -> eDP + DP/HDMI/USB-C -> 1080p 60hz eDP + 4k 144hz, 4k 240hz (Includes USB-C to DP/HDMI adapters)
* Thunderbolt -> LG Ultrafine 5k
* MST DSC -> Cable Matters 101075 (DP to 3x DP) with 3x 4k60hz displays, HP Hook G2 with 2x 4k60hz displays
* USB 4 -> HP Hook G4, Lenovo Thunderbolt Dock, both with 2x 4k60hz DP and 1x 4k60hz HDMI displays
* SST PCON -> Club3D CAC-1085 + 1x 4k 144hz, FRL3, at a max resolution supported by the dongle of 4k 120hz YUV420 12bpc.
* MST PCON -> 1x 4k 144hz, FRL3, at a max resolution supported by the adapter of 4k 120hz RGB 8bpc.
DGPU
* Single Display DP (SST DSC) -> 4k144hz, 4k240hz
* Multiple Display DP -> 4k240hz + 4k144hz
* MST (Startech MST14DP123DP [DP to 3x DP] and 2x 4k 60hz displays)
* MST DSC (with Cable Matters 101075 [DP to 3x DP] with 3x 4k60hz displays)
The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to)
* Changing display configurations and settings
* Video/Audio playback
* Benchmark testing
* Suspend/Resume testing
* Feature testing (Freesync, HDCP, etc.)
Automated testing includes (but is not limited to)
* Script testing (scripts to automate some of the manual checks)
* IGT testing
The testing is mainly tested on the following displays, but occasionally there are tests with other displays
* Samsung G8 Neo 4k240hz
* Samsung QN55QN95B 4k 120hz
* Acer XV322QKKV 4k144hz
* HP U27 4k Wireless 4k60hz
* LG 27UD58B 4k60hz
* LG 32UN650WA 4k60hz
* LG Ultrafine 5k 5k60hz
* AU Optronics B140HAN01.1 1080p 60hz eDP
* AU Optronics B160UAN01.J 1920x1200 165hz eDP
* Samsung ATNA60YV02-0 3840x2400 60Hz OLED eDP
The patchset consists of the amd-staging-drm-next branch (3abbc6894f696de837f4238a0fc24b236892861a -> drm/amd/display: Promote DC to 3.2.381) with new patches added on top of it.
Tested on Ubuntu 24.04.4, on Wayland and X11, using Gnome.
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Thank you,
Dan Wheeler
Sr. Technologist | AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
amd.com
-----Original Message-----
From: James Lin <PingLei.Lin@amd.com>
Sent: Wednesday, May 6, 2026 12:31 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry <Harry.Wentland@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Li, Roman <Roman.Li@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Chung, ChiaHsuan (Tom) <ChiaHsuan.Chung@amd.com>; Zuo, Jerry <Jerry.Zuo@amd.com>; Wheeler, Daniel <Daniel.Wheeler@amd.com>; Wu, Ray <Ray.Wu@amd.com>; LIPSKI, IVAN <IVAN.LIPSKI@amd.com>; Hung, Alex <Alex.Hung@amd.com>; Lin, Ping Lei <PingLei.Lin@amd.com>; Chen, Chen-Yu <Chen-Yu.Chen@amd.com>
Subject: [PATCH 00/20] DC Patches May 11 2026
Start from:
6ee9f5160ad6e0bf672329f7680398e718fc56f5
SWDEV-114487 - modules: [BACKPORT] drm/amd/display: Fix divide by zero in calc_psr_num_static_frames
Stopped at:
5e7f507891f430f50c71004b73c5ef4c13224f1a
SWDEV-2 - dc: Promote DC to 3.2.382
This version brings along following update:
-Revert "Enable HUBP/OPTC/DPP power gating" -Revert "Unify fast update classification paths" -enable ODM 2:1 on single eDP based on pixel clock -Enable IPS on DCN42 -Add additional IPS entry/exit for PSR/Replay -Separate ABM functions into dedicated power_abm.c file -Fix always-true lower-bound assert -Refactor dc_link_aux_transfer_raw -only call pmfw if smu present flags true -Fix multiple compiler warnings -Fix CRC open failure during active rendering -Fix white screen on boot with OLED panel -Fix refresh rate round up case
Charlene Liu (2):
drm/amd/display: only call pmfw if smu present flags true
drm/amd/display: enable ODM 2:1 on single eDP based on pixel clock
ChunTao Tso (1):
drm/amd/display: Fix refresh rate round up case
Clay King (1):
drm/amd/display: Fix warnings
Gaghik Khachatrian (5):
drm/amd/display: Fix signed/unsigned comparison mismatches
drm/amd/display: Fix compiler warnings in dml2
drm/amd/display: Fix multiple compiler warnings
drm/amd/display: always-true lower-bound assert
drm/amd/display: Fix enum decl warnings
Ivan Lipski (2):
drm/amd/display: Add additional IPS entry/exit for PSR/Replay
drm/amd/display: Enable IPS on DCN42
Leo Chen (1):
drm/amd/display: Revert "Enable HUBP/OPTC/DPP power gating"
Lohita Mudimela (1):
drm/amd/display: Separate ABM functions into dedicated power_abm.c
file
Matthew Stewart (1):
drm/amd/display: Refactor dc_link_aux_transfer_raw
Mikhail Gavrilov (1):
drm/amd/display: Wrap DCN32 phantom-plane allocation in
DC_RUN_WITH_PREEMPTION_ENABLED
Ovidiu Bunea (1):
drm/amd/display: Revert "Unify fast update classification paths"
Ray Wu (1):
drm/amd/display: Fix white screen on boot with OLED panel
Taimur Hassan (2):
drm/amd/display: [FW Promotion] Release 0.1.59.0
drm/amd/display: Promote DC to 3.2.382
Tom Chung (1):
drm/amd/display: Fix CRC open failure during active rendering
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 7 +-
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 77 +
.../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 6 +-
.../display/dc/clk_mgr/dce100/dce_clk_mgr.h | 2 +-
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 8 +-
.../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c | 4 +-
.../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h | 2 +-
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +-
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 2 +-
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.h | 4 +-
.../clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c | 4 +-
.../clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h | 2 +-
.../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 11 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 260 +-
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 12 -
.../drm/amd/display/dc/core/dc_link_exports.c | 2 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 18 +-
.../gpu/drm/amd/display/dc/core/dc_state.c | 6 +-
.../gpu/drm/amd/display/dc/core/dc_stream.c | 4 +-
.../drm/amd/display/dc/core/dc_vm_helper.c | 4 +-
drivers/gpu/drm/amd/display/dc/dc.h | 105 +-
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 3 +-
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 2 +-
drivers/gpu/drm/amd/display/dc/dc_stream.h | 7 +-
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +-
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 20 +-
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 4 +
.../amd/display/dc/dcn21/dcn21_link_encoder.c | 2 +-
.../display/dc/dio/dcn10/dcn10_link_encoder.c | 2 +-
drivers/gpu/drm/amd/display/dc/dm_helpers.h | 1 +
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 6 +-
.../dc/dml/dcn21/display_mode_vba_21.c | 36 +-
.../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 4 +-
.../dc/dml/dcn30/display_mode_vba_30.c | 342 +--
.../amd/display/dc/dml/dcn301/dcn301_fpu.c | 2 +-
.../dc/dml/dcn31/display_mode_vba_31.c | 408 ++--
.../amd/display/dc/dml/dcn314/dcn314_fpu.c | 10 +-
.../dc/dml/dcn314/display_mode_vba_314.c | 400 +--
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 15 +-
.../dc/dml/dcn32/display_mode_vba_util_32.c | 8 +-
.../dc/dml/dcn32/display_mode_vba_util_32.h | 8 +-
.../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 10 +-
.../amd/display/dc/dml/dcn351/dcn351_fpu.c | 10 +-
.../drm/amd/display/dc/dml/display_mode_vba.h | 12 +-
.../amd/display/dc/dml2_0/display_mode_core.c | 6 +-
.../drm/amd/display/dc/dml2_0/dml2_utils.c | 2 +-
.../amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c | 2 +-
.../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 2 +-
.../amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c | 4 +-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2 +-
.../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 8 +-
.../drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c | 8 +-
.../amd/display/dc/dsc/dcn401/dcn401_dsc.c | 10 +-
.../amd/display/dc/hubp/dcn401/dcn401_hubp.c | 4 +-
.../amd/display/dc/hubp/dcn401/dcn401_hubp.h | 2 +-
.../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 10 +-
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 8 +-
.../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 2 +-
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2 +-
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 +-
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 5 +-
drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 4 +-
.../amd/display/dc/inc/hw/timing_generator.h | 8 +-
.../gpu/drm/amd/display/dc/inc/link_service.h | 2 +-
.../gpu/drm/amd/display/dc/inc/reg_helper.h | 72 +-
.../drm/amd/display/dc/link/link_detection.c | 2 +-
.../drm/amd/display/dc/link/link_detection.h | 2 +-
.../amd/display/dc/link/protocols/link_ddc.c | 7 +-
.../link/protocols/link_edp_panel_control.c | 8 +-
.../drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c | 2 +-
.../drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c | 6 +-
.../drm/amd/display/dc/opp/dcn20/dcn20_opp.c | 2 +-
.../drm/amd/display/dc/opp/dcn20/dcn20_opp.h | 2 +-
.../amd/display/dc/optc/dcn32/dcn32_optc.c | 2 +-
.../dc/resource/dce100/dce100_resource.c | 10 +-
.../dc/resource/dce110/dce110_resource.c | 8 +-
.../dc/resource/dce112/dce112_resource.c | 4 +-
.../dc/resource/dce120/dce120_resource.c | 6 +-
.../dc/resource/dce80/dce80_resource.c | 8 +-
.../dc/resource/dcn10/dcn10_resource.c | 15 +-
.../dc/resource/dcn20/dcn20_resource.c | 60 +-
.../dc/resource/dcn21/dcn21_resource.c | 26 +-
.../dc/resource/dcn30/dcn30_resource.c | 63 +-
.../dc/resource/dcn301/dcn301_resource.c | 31 +-
.../dc/resource/dcn302/dcn302_resource.c | 22 +-
.../dc/resource/dcn303/dcn303_resource.c | 22 +-
.../dc/resource/dcn31/dcn31_resource.c | 30 +-
.../dc/resource/dcn314/dcn314_resource.c | 26 +-
.../dc/resource/dcn315/dcn315_resource.c | 37 +-
.../dc/resource/dcn316/dcn316_resource.c | 29 +-
.../dc/resource/dcn32/dcn32_resource.c | 33 +-
.../resource/dcn32/dcn32_resource_helpers.c | 6 +-
.../dc/resource/dcn321/dcn321_resource.c | 22 +-
.../dc/resource/dcn35/dcn35_resource.c | 26 +-
.../dc/resource/dcn351/dcn351_resource.c | 26 +-
.../dc/resource/dcn36/dcn36_resource.c | 26 +-
.../dc/resource/dcn401/dcn401_resource.c | 32 +-
.../dc/resource/dcn42/dcn42_resource.c | 50 +-
.../dc/resource/dcn42/dcn42_resource_fpu.c | 22 +
.../dc/resource/dcn42/dcn42_resource_fpu.h | 2 +-
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 32 +-
.../gpu/drm/amd/display/include/fixed31_32.h | 6 +-
.../amd/display/modules/color/color_gamma.c | 28 +-
.../drm/amd/display/modules/hdcp/hdcp_log.c | 2 +-
.../amd/display/modules/inc/mod_color_types.h | 47 +
.../amd/display/modules/inc/mod_info_packet.h | 9 +-
.../modules/inc/mod_info_packet_types.h | 37 +
.../drm/amd/display/modules/inc/mod_power.h | 25 +
.../drm/amd/display/modules/power/Makefile | 2 +-
.../gpu/drm/amd/display/modules/power/power.c | 1323 +--------- .../drm/amd/display/modules/power/power_abm.c | 2160 +++++++++++++++++ .../amd/display/modules/power/power_helpers.c | 823 +------
.../amd/display/modules/power/power_helpers.h | 1 +
116 files changed, 3922 insertions(+), 3295 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h
create mode 100644 drivers/gpu/drm/amd/display/modules/inc/mod_info_packet_types.h
create mode 100644 drivers/gpu/drm/amd/display/modules/power/power_abm.c
--
2.43.0
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