[PATCH 01/21] drm/amdgpu: wire up emit_wreg for gfx v6

[PATCH 01/21] drm/amdgpu: wire up emit_wreg for gfx v6

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 39acafbc84d6..e72f3e5d24b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2402,6 +2402,18 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 	}
 }
 
+static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
+				    uint32_t reg, uint32_t val)
+{
+	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+
+	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
+				 WRITE_DATA_DST_SEL(0)));
+	amdgpu_ring_write(ring, reg);
+	amdgpu_ring_write(ring, 0);
+	amdgpu_ring_write(ring, val);
+}
 
 static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
 {
@@ -3529,6 +3541,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
 	.test_ib = gfx_v6_0_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
 	.emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
+	.emit_wreg = gfx_v6_0_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
-- 
2.14.1

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[PATCH 02/21] drm/amdgpu: wire up emit_wreg for gfx v7

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index e29c22a72764..a8899ecd9387 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3290,6 +3290,19 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 	}
 }
 
+static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
+				    uint32_t reg, uint32_t val)
+{
+	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+
+	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
+				 WRITE_DATA_DST_SEL(0)));
+	amdgpu_ring_write(ring, reg);
+	amdgpu_ring_write(ring, 0);
+	amdgpu_ring_write(ring, val);
+}
+
 /*
  * RLC
  * The RLC is a multi-purpose microengine that handles a
@@ -5134,6 +5147,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
 	.insert_nop = amdgpu_ring_insert_nop,
 	.pad_ib = amdgpu_ring_generic_pad_ib,
 	.emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
+	.emit_wreg = gfx_v7_0_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
-- 
2.14.1

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[PATCH 03/21] drm/amdgpu: wire up emit_wreg for gfx v8

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 3fd7eb2a9a7b..ebec33f87fb1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6618,8 +6618,22 @@ static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
 static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
 				  uint32_t val)
 {
+	uint32_t cmd;
+
+	switch (ring->funcs->type) {
+	case AMDGPU_RING_TYPE_GFX:
+		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
+		break;
+	case AMDGPU_RING_TYPE_KIQ:
+		cmd = 1 << 16; /* no inc addr */
+		break;
+	default:
+		cmd = WR_CONFIRM;
+		break;
+	}
+
 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
+	amdgpu_ring_write(ring, cmd);
 	amdgpu_ring_write(ring, reg);
 	amdgpu_ring_write(ring, 0);
 	amdgpu_ring_write(ring, val);
@@ -6903,6 +6917,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
 	.emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
 	.init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
 	.patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
+	.emit_wreg = gfx_v8_0_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
-- 
2.14.1

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[PATCH 04/21] drm/amdgpu: wire up emit_wreg for gfx v9

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 1f580328f571..b69bbd2d7df1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4004,10 +4004,23 @@ static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
 }
 
 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
-				  uint32_t val)
+				    uint32_t val)
 {
+	uint32_t cmd = 0;
+
+	switch (ring->funcs->type) {
+	case AMDGPU_RING_TYPE_GFX:
+		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
+		break;
+	case AMDGPU_RING_TYPE_KIQ:
+		cmd = (1 << 16); /* no inc addr */
+		break;
+	default:
+		cmd = WR_CONFIRM;
+		break;
+	}
 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
+	amdgpu_ring_write(ring, cmd);
 	amdgpu_ring_write(ring, reg);
 	amdgpu_ring_write(ring, 0);
 	amdgpu_ring_write(ring, val);
@@ -4331,6 +4344,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
 	.init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
 	.patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
 	.emit_tmz = gfx_v9_0_ring_emit_tmz,
+	.emit_wreg = gfx_v9_0_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
@@ -4362,6 +4376,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
 	.insert_nop = amdgpu_ring_insert_nop,
 	.pad_ib = amdgpu_ring_generic_pad_ib,
 	.set_priority = gfx_v9_0_ring_set_priority_compute,
+	.emit_wreg = gfx_v9_0_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
-- 
2.14.1

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[PATCH 05/21] drm/amdgpu: wire up emit_wreg for SI DMA

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dma.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 697475a25749..c70e1d35975c 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -497,6 +497,14 @@ static void si_dma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 	amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */
 }
 
+static void si_dma_ring_emit_wreg(struct amdgpu_ring *ring,
+				  uint32_t reg, uint32_t val)
+{
+	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
+	amdgpu_ring_write(ring, (0xf << 16) | reg);
+	amdgpu_ring_write(ring, val);
+}
+
 static int si_dma_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -789,6 +797,7 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
 	.test_ib = si_dma_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
 	.pad_ib = si_dma_ring_pad_ib,
+	.emit_wreg = si_dma_ring_emit_wreg,
 };
 
 static void si_dma_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.14.1

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[PATCH 06/21] drm/amdgpu: wire up emit_wreg for CIK SDMA

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 66d9b5f85d6e..fbbac8498044 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -907,6 +907,14 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 	amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 }
 
+static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring,
+				    uint32_t reg, uint32_t val)
+{
+	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
+	amdgpu_ring_write(ring, reg);
+	amdgpu_ring_write(ring, val);
+}
+
 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 				 bool enable)
 {
@@ -1295,6 +1303,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
 	.test_ib = cik_sdma_ring_test_ib,
 	.insert_nop = cik_sdma_ring_insert_nop,
 	.pad_ib = cik_sdma_ring_pad_ib,
+	.emit_wreg = cik_sdma_ring_emit_wreg,
 };
 
 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.14.1

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[PATCH 07/21] drm/amdgpu: wire up emit_wreg for SDMA v2.4

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index c4de1c18bf77..0fb4b4409ef1 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -889,6 +889,15 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 }
 
+static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring,
+				     uint32_t reg, uint32_t val)
+{
+	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+	amdgpu_ring_write(ring, reg);
+	amdgpu_ring_write(ring, val);
+}
+
 static int sdma_v2_4_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1219,6 +1228,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
 	.test_ib = sdma_v2_4_ring_test_ib,
 	.insert_nop = sdma_v2_4_ring_insert_nop,
 	.pad_ib = sdma_v2_4_ring_pad_ib,
+	.emit_wreg = sdma_v2_4_ring_emit_wreg,
 };
 
 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.14.1

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[PATCH 08/21] drm/amdgpu: wire up emit_wreg for SDMA v3

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 3e22ae4c3802..935c3a8b6629 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1155,6 +1155,15 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 }
 
+static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring,
+				     uint32_t reg, uint32_t val)
+{
+	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+	amdgpu_ring_write(ring, reg);
+	amdgpu_ring_write(ring, val);
+}
+
 static int sdma_v3_0_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1653,6 +1662,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
 	.test_ib = sdma_v3_0_ring_test_ib,
 	.insert_nop = sdma_v3_0_ring_insert_nop,
 	.pad_ib = sdma_v3_0_ring_pad_ib,
+	.emit_wreg = sdma_v3_0_ring_emit_wreg,
 };
 
 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.14.1

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[PATCH 09/21] drm/amdgpu: wire up emit_wreg for SDMA v4

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index f0b10cb63940..282b402d93ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1172,6 +1172,15 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
 }
 
+static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
+				     uint32_t reg, uint32_t val)
+{
+	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+	amdgpu_ring_write(ring, reg);
+	amdgpu_ring_write(ring, val);
+}
+
 static int sdma_v4_0_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1608,6 +1617,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
 	.test_ib = sdma_v4_0_ring_test_ib,
 	.insert_nop = sdma_v4_0_ring_insert_nop,
 	.pad_ib = sdma_v4_0_ring_pad_ib,
+	.emit_wreg = sdma_v4_0_ring_emit_wreg,
 };
 
 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.14.1

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[PATCH 10/21] drm/amdgpu: wire up emit_wreg for UVD v6

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index c6e22eff89e7..b48b843c66ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1059,6 +1059,17 @@ static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
 	amdgpu_ring_write(ring, ib->length_dw);
 }
 
+static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
+				    uint32_t reg, uint32_t val)
+{
+	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
+	amdgpu_ring_write(ring, reg << 2);
+	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
+	amdgpu_ring_write(ring, val);
+	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
+	amdgpu_ring_write(ring, 0x8);
+}
+
 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 					unsigned vmid, unsigned pasid,
 					uint64_t pd_addr)
@@ -1595,6 +1606,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
 	.pad_ib = amdgpu_ring_generic_pad_ib,
 	.begin_use = amdgpu_uvd_ring_begin_use,
 	.end_use = amdgpu_uvd_ring_end_use,
+	.emit_wreg = uvd_v6_0_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
-- 
2.14.1

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[PATCH 11/21] drm/amdgpu: wire up emit_wreg for UVD v7

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 24 +++++++++++++++++-------
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 44f1a3dde4d6..42c4296909e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1255,17 +1255,17 @@ static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
 	amdgpu_ring_write(ring, ib->length_dw);
 }
 
-static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring,
-				uint32_t data0, uint32_t data1)
+static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
+				    uint32_t reg, uint32_t val)
 {
 	struct amdgpu_device *adev = ring->adev;
 
 	amdgpu_ring_write(ring,
 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
-	amdgpu_ring_write(ring, data0);
+	amdgpu_ring_write(ring, reg << 2);
 	amdgpu_ring_write(ring,
 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
-	amdgpu_ring_write(ring, data1);
+	amdgpu_ring_write(ring, val);
 	amdgpu_ring_write(ring,
 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
 	amdgpu_ring_write(ring, 8);
@@ -1305,11 +1305,11 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 
 	data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
 	data1 = upper_32_bits(pd_addr);
-	uvd_v7_0_vm_reg_write(ring, data0, data1);
+	uvd_v7_0_ring_emit_wreg(ring, data0, data1);
 
 	data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
 	data1 = lower_32_bits(pd_addr);
-	uvd_v7_0_vm_reg_write(ring, data0, data1);
+	uvd_v7_0_ring_emit_wreg(ring, data0, data1);
 
 	data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
 	data1 = lower_32_bits(pd_addr);
@@ -1319,7 +1319,7 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 	/* flush TLB */
 	data0 = (hub->vm_inv_eng0_req + eng) << 2;
 	data1 = req;
-	uvd_v7_0_vm_reg_write(ring, data0, data1);
+	uvd_v7_0_ring_emit_wreg(ring, data0, data1);
 
 	/* wait for flush */
 	data0 = (hub->vm_inv_eng0_ack + eng) << 2;
@@ -1380,6 +1380,14 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
 	amdgpu_ring_write(ring, 1 << vmid);
 }
 
+static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
+					uint32_t reg, uint32_t val)
+{
+	amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
+	amdgpu_ring_write(ring,	reg << 2);
+	amdgpu_ring_write(ring, val);
+}
+
 #if 0
 static bool uvd_v7_0_is_idle(void *handle)
 {
@@ -1730,6 +1738,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
 	.pad_ib = amdgpu_ring_generic_pad_ib,
 	.begin_use = amdgpu_uvd_ring_begin_use,
 	.end_use = amdgpu_uvd_ring_end_use,
+	.emit_wreg = uvd_v7_0_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
@@ -1756,6 +1765,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
 	.pad_ib = amdgpu_ring_generic_pad_ib,
 	.begin_use = amdgpu_uvd_ring_begin_use,
 	.end_use = amdgpu_uvd_ring_end_use,
+	.emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
 };
 
 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.14.1

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[PATCH 12/21] drm/amdgpu: wire up emit_wreg for VCE v4

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index a54e88821de3..9a0d6d9824d0 100755
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -1001,6 +1001,14 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
 	amdgpu_ring_write(ring, 1 << vmid);
 }
 
+static void vce_v4_0_emit_wreg(struct amdgpu_ring *ring,
+			       uint32_t reg, uint32_t val)
+{
+	amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
+	amdgpu_ring_write(ring,	reg << 2);
+	amdgpu_ring_write(ring, val);
+}
+
 static int vce_v4_0_set_interrupt_state(struct amdgpu_device *adev,
 					struct amdgpu_irq_src *source,
 					unsigned type,
@@ -1084,6 +1092,7 @@ static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = {
 	.pad_ib = amdgpu_ring_generic_pad_ib,
 	.begin_use = amdgpu_vce_ring_begin_use,
 	.end_use = amdgpu_vce_ring_end_use,
+	.emit_wreg = vce_v4_0_emit_wreg,
 };
 
 static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.14.1

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[PATCH 13/21] drm/amdgpu: wire up emit_wreg for VCN v1

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 85a0ecaba3e3..8efe7f3ec0a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1061,6 +1061,14 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
 	amdgpu_ring_write(ring, 1 << vmid);
 }
 
+static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
+					uint32_t reg, uint32_t val)
+{
+	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
+	amdgpu_ring_write(ring,	reg << 2);
+	amdgpu_ring_write(ring, val);
+}
+
 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
 					struct amdgpu_irq_src *source,
 					unsigned type,
@@ -1152,6 +1160,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
 	.pad_ib = amdgpu_ring_generic_pad_ib,
 	.begin_use = amdgpu_vcn_ring_begin_use,
 	.end_use = amdgpu_vcn_ring_end_use,
+	.emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
-- 
2.14.1

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[PATCH 14/21] drm/amdgpu: add new amdgpu_gmc_emit_flush_gpu_tlb callback

[Christian König]

Add a new GMC function to unify vm flushing.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 93eae393b08d..230826718c98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1779,6 +1779,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_asic_flush_hdp(adev) (adev)->asic_funcs->flush_hdp((adev))
 #define amdgpu_asic_invalidate_hdp(adev) (adev)->asic_funcs->invalidate_hdp((adev))
 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
+#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, pasid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (pasid), (addr))
 #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
 #define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index a4a8374f7f3f..114350a4693f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -52,6 +52,9 @@ struct amdgpu_gmc_funcs {
 	/* flush the vm tlb via mmio */
 	void (*flush_gpu_tlb)(struct amdgpu_device *adev,
 			      uint32_t vmid);
+	/* flush the vm tlb via ring */
+	uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
+				       unsigned pasid, uint64_t pd_addr);
 	/* write pte/pde updates using the cpu */
 	int (*set_pte_pde)(struct amdgpu_device *adev,
 			   void *cpu_pt_addr, /* cpu addr of page table */
-- 
2.14.1

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[PATCH 15/21] drm/amdgpu: implement gmc_v6_0_emit_flush_gpu_tlb

[Christian König]

Unify tlb flushing for gmc v6.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 25 ++++---------------------
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 20 ++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/si.h       |  2 ++
 drivers/gpu/drm/amd/amdgpu/si_dma.c   | 15 +++------------
 4 files changed, 29 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index e72f3e5d24b8..29ce3cc6816e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -38,6 +38,7 @@
 #include "dce/dce_6_0_sh_mask.h"
 #include "gca/gfx_7_2_enum.h"
 #include "si_enums.h"
+#include "si.h"
 
 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -2359,25 +2360,7 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 {
 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
 
-	/* write new base address */
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
-				 WRITE_DATA_DST_SEL(0)));
-	if (vmid < 8) {
-		amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid ));
-	} else {
-		amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8)));
-	}
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, pd_addr >> 12);
-
-	/* bits 0-15 are the VM contexts0-15 */
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
-				 WRITE_DATA_DST_SEL(0)));
-	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, 1 << vmid);
+	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
 	/* wait for the invalidate to complete */
 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
@@ -3528,7 +3511,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
 		5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
 		14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
 		7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
-		17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
+		SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
 		3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
 	.emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
 	.emit_ib = gfx_v6_0_ring_emit_ib,
@@ -3555,7 +3538,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
 		5 + /* gfx_v6_0_ring_emit_hdp_flush */
 		5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
 		7 + /* gfx_v6_0_ring_emit_pipeline_sync */
-		17 + /* gfx_v6_0_ring_emit_vm_flush */
+		SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
 		14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
 	.emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
 	.emit_ib = gfx_v6_0_ring_emit_ib,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 709b167f5a6a..62d05d8c18c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -361,6 +361,25 @@ static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid)
 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 }
 
+static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+					    unsigned vmid, unsigned pasid,
+					    uint64_t pd_addr)
+{
+	uint32_t reg;
+
+	/* write new base address */
+	if (vmid < 8)
+		reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
+	else
+		reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8);
+	amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
+
+	/* bits 0-15 are the VM contexts0-15 */
+	amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
+
+	return pd_addr;
+}
+
 static int gmc_v6_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
 				uint32_t gpu_page_idx, uint64_t addr,
 				uint64_t flags)
@@ -1124,6 +1143,7 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
 
 static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
 	.flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,
+	.emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
 	.set_pte_pde = gmc_v6_0_set_pte_pde,
 	.set_prt = gmc_v6_0_set_prt,
 	.get_vm_pde = gmc_v6_0_get_vm_pde,
diff --git a/drivers/gpu/drm/amd/amdgpu/si.h b/drivers/gpu/drm/amd/amdgpu/si.h
index 589225080c24..06ed7212a0d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.h
+++ b/drivers/gpu/drm/amd/amdgpu/si.h
@@ -24,6 +24,8 @@
 #ifndef __SI_H__
 #define __SI_H__
 
+#define SI_FLUSH_GPU_TLB_NUM_WREG	2
+
 void si_srbm_select(struct amdgpu_device *adev,
 		     u32 me, u32 pipe, u32 queue, u32 vmid);
 int si_set_ip_blocks(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index c70e1d35975c..8f9509f6f15b 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -24,6 +24,7 @@
 #include <drm/drmP.h>
 #include "amdgpu.h"
 #include "amdgpu_trace.h"
+#include "si.h"
 #include "sid.h"
 
 const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
@@ -476,17 +477,7 @@ static void si_dma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 				      unsigned vmid, unsigned pasid,
 				      uint64_t pd_addr)
 {
-	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
-	if (vmid < 8)
-		amdgpu_ring_write(ring, (0xf << 16) | (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
-	else
-		amdgpu_ring_write(ring, (0xf << 16) | (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8)));
-	amdgpu_ring_write(ring, pd_addr >> 12);
-
-	/* bits 0-7 are the VM contexts0-7 */
-	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
-	amdgpu_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST));
-	amdgpu_ring_write(ring, 1 << vmid);
+	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
 	/* wait for invalidate to complete */
 	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0));
@@ -784,7 +775,7 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
 		3 + /* si_dma_ring_emit_hdp_flush */
 		3 + /* si_dma_ring_emit_hdp_invalidate */
 		6 + /* si_dma_ring_emit_pipeline_sync */
-		12 + /* si_dma_ring_emit_vm_flush */
+		SI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* si_dma_ring_emit_vm_flush */
 		9 + 9 + 9, /* si_dma_ring_emit_fence x3 for user fence, vm fence */
 	.emit_ib_size = 7 + 3, /* si_dma_ring_emit_ib */
 	.emit_ib = si_dma_ring_emit_ib,
-- 
2.14.1

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[PATCH 16/21] drm/amdgpu: implement gmc_v7_0_emit_flush_gpu_tlb

[Christian König]

Unify tlb flushing for gmc v7.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/cik.h      |  2 ++
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 15 ++-------------
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 25 +++----------------------
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 19 +++++++++++++++++++
 4 files changed, 26 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h
index c4989f51ecef..201d8786f9cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik.h
@@ -24,6 +24,8 @@
 #ifndef __CIK_H__
 #define __CIK_H__
 
+#define CIK_FLUSH_GPU_TLB_NUM_WREG	2
+
 void cik_srbm_select(struct amdgpu_device *adev,
 		     u32 me, u32 pipe, u32 queue, u32 vmid);
 int cik_set_ip_blocks(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index fbbac8498044..1d32dedb2534 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -886,18 +886,7 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 	u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 			  SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 
-	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-	if (vmid < 8) {
-		amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
-	} else {
-		amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
-	}
-	amdgpu_ring_write(ring, pd_addr >> 12);
-
-	/* flush TLB */
-	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
-	amdgpu_ring_write(ring, 1 << vmid);
+	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
 	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
@@ -1290,7 +1279,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
 		6 + /* cik_sdma_ring_emit_hdp_flush */
 		3 + /* cik_sdma_ring_emit_hdp_invalidate */
 		6 + /* cik_sdma_ring_emit_pipeline_sync */
-		12 + /* cik_sdma_ring_emit_vm_flush */
+		CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
 		9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
 	.emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
 	.emit_ib = cik_sdma_ring_emit_ib,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index a8899ecd9387..91879ccbedd8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3244,26 +3244,7 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 {
 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
 
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
-				 WRITE_DATA_DST_SEL(0)));
-	if (vmid < 8) {
-		amdgpu_ring_write(ring,
-				  (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
-	} else {
-		amdgpu_ring_write(ring,
-				  (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
-	}
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, pd_addr >> 12);
-
-	/* bits 0-15 are the VM contexts0-15 */
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-				 WRITE_DATA_DST_SEL(0)));
-	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, 1 << vmid);
+	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
 	/* wait for the invalidate to complete */
 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
@@ -5132,7 +5113,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
 		5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
 		12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
 		7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
-		17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
+		CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
 		3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
 	.emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
 	.emit_ib = gfx_v7_0_ring_emit_ib_gfx,
@@ -5163,7 +5144,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
 		7 + /* gfx_v7_0_ring_emit_hdp_flush */
 		5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
 		7 + /* gfx_v7_0_ring_emit_pipeline_sync */
-		17 + /* gfx_v7_0_ring_emit_vm_flush */
+		CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */
 		7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
 	.emit_ib_size =	4, /* gfx_v7_0_ring_emit_ib_compute */
 	.emit_ib = gfx_v7_0_ring_emit_ib_compute,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index fba7aaeef4b1..2daf118e69ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -434,6 +434,24 @@ static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid)
 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 }
 
+static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+					    unsigned vmid, unsigned pasid,
+					    uint64_t pd_addr)
+{
+	uint32_t reg;
+
+	if (vmid < 8)
+		reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
+	else
+		reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
+	amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
+
+	/* bits 0-15 are the VM contexts0-15 */
+	amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
+
+	return pd_addr;
+}
+
 /**
  * gmc_v7_0_set_pte_pde - update the page tables using MMIO
  *
@@ -1303,6 +1321,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
 
 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
 	.flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
+	.emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
 	.set_pte_pde = gmc_v7_0_set_pte_pde,
 	.set_prt = gmc_v7_0_set_prt,
 	.get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags,
-- 
2.14.1

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[PATCH 17/21] drm/amdgpu: implement gmc_v8_0_emit_flush_gpu_tlb

[Christian König]

Unify tlb flushing for gmc v8.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 27 +++------------------------
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  | 19 +++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 17 ++---------------
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 15 +--------------
 drivers/gpu/drm/amd/amdgpu/vi.h        |  2 ++
 5 files changed, 27 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index ebec33f87fb1..964bf715405c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6333,28 +6333,7 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 {
 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
 
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
-				 WRITE_DATA_DST_SEL(0)) |
-				 WR_CONFIRM);
-	if (vmid < 8) {
-		amdgpu_ring_write(ring,
-				  (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
-	} else {
-		amdgpu_ring_write(ring,
-				  (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
-	}
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, pd_addr >> 12);
-
-	/* bits 0-15 are the VM contexts0-15 */
-	/* invalidate the cache */
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-				 WRITE_DATA_DST_SEL(0)));
-	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, 1 << vmid);
+	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
 	/* wait for the invalidate to complete */
 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
@@ -6886,7 +6865,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
 	.emit_frame_size = /* maximum 215dw if count 16 IBs in */
 		5 +  /* COND_EXEC */
 		7 +  /* PIPELINE_SYNC */
-		19 + /* VM_FLUSH */
+		VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
 		8 +  /* FENCE for VM_FLUSH */
 		20 + /* GDS switch */
 		4 + /* double SWITCH_BUFFER,
@@ -6933,7 +6912,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
 		7 + /* gfx_v8_0_ring_emit_hdp_flush */
 		5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
 		7 + /* gfx_v8_0_ring_emit_pipeline_sync */
-		17 + /* gfx_v8_0_ring_emit_vm_flush */
+		VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
 		7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
 	.emit_ib_size =	4, /* gfx_v8_0_ring_emit_ib_compute */
 	.emit_ib = gfx_v8_0_ring_emit_ib_compute,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index c6146573c843..da02c61dda38 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -610,6 +610,24 @@ static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev,
 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 }
 
+static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+					    unsigned vmid, unsigned pasid,
+					    uint64_t pd_addr)
+{
+	uint32_t reg;
+
+	if (vmid < 8)
+		reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
+	else
+		reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
+	amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
+
+	/* bits 0-15 are the VM contexts0-15 */
+	amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
+
+	return pd_addr;
+}
+
 /**
  * gmc_v8_0_set_pte_pde - update the page tables using MMIO
  *
@@ -1637,6 +1655,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
 
 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
 	.flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
+	.emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
 	.set_pte_pde = gmc_v8_0_set_pte_pde,
 	.set_prt = gmc_v8_0_set_prt,
 	.get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 0fb4b4409ef1..0aa336371816 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -862,20 +862,7 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
 					 unsigned vmid, unsigned pasid,
 					 uint64_t pd_addr)
 {
-	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-	if (vmid < 8) {
-		amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
-	} else {
-		amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
-	}
-	amdgpu_ring_write(ring, pd_addr >> 12);
-
-	/* flush TLB */
-	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
-	amdgpu_ring_write(ring, 1 << vmid);
+	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
 	/* wait for flush */
 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
@@ -1215,7 +1202,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
 		6 + /* sdma_v2_4_ring_emit_hdp_flush */
 		3 + /* sdma_v2_4_ring_emit_hdp_invalidate */
 		6 + /* sdma_v2_4_ring_emit_pipeline_sync */
-		12 + /* sdma_v2_4_ring_emit_vm_flush */
+		VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */
 		10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
 	.emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */
 	.emit_ib = sdma_v2_4_ring_emit_ib,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 935c3a8b6629..e417546e2048 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1128,20 +1128,7 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 					 unsigned vmid, unsigned pasid,
 					 uint64_t pd_addr)
 {
-	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-	if (vmid < 8) {
-		amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
-	} else {
-		amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
-	}
-	amdgpu_ring_write(ring, pd_addr >> 12);
-
-	/* flush TLB */
-	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
-	amdgpu_ring_write(ring, 1 << vmid);
+	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
 	/* wait for flush */
 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
index 575d7aed5d32..6cc2bee4abf7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.h
+++ b/drivers/gpu/drm/amd/amdgpu/vi.h
@@ -24,6 +24,8 @@
 #ifndef __VI_H__
 #define __VI_H__
 
+#define VI_FLUSH_GPU_TLB_NUM_WREG	2
+
 void vi_srbm_select(struct amdgpu_device *adev,
 		    u32 me, u32 pipe, u32 queue, u32 vmid);
 int vi_set_ip_blocks(struct amdgpu_device *adev);
-- 
2.14.1

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[PATCH 18/21] drm/amdgpu: implement gmc_v9_0_emit_flush_gpu_tlb

[Christian König]

Unify tlb flushing for gmc v9.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  1 -
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 29 ++++------------
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 25 +++++++++++++-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  | 23 ++-----------
 drivers/gpu/drm/amd/amdgpu/soc15.h      |  2 ++
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c   | 43 ++++-------------------
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c   | 22 +++---------
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 61 ++++-----------------------------
 8 files changed, 53 insertions(+), 153 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 114350a4693f..b3d1bd2f51cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -69,7 +69,6 @@ struct amdgpu_gmc_funcs {
 	/* get the pde for a given mc addr */
 	void (*get_vm_pde)(struct amdgpu_device *adev, int level,
 			   u64 *dst, u64 *flags);
-	uint32_t (*get_invalidate_req)(unsigned int vmid);
 };
 
 struct amdgpu_gmc {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index b69bbd2d7df1..afdf57206efa 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3688,31 +3688,16 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 					uint64_t pd_addr)
 {
 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
-	uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid);
-	uint64_t flags = AMDGPU_PTE_VALID;
 	unsigned eng = ring->vm_inv_eng;
 
-	amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
-	pd_addr |= flags;
-
-	gfx_v9_0_write_data_to_reg(ring, usepfp, true,
-				   hub->ctx0_ptb_addr_lo32 + (2 * vmid),
-				   lower_32_bits(pd_addr));
-
-	gfx_v9_0_write_data_to_reg(ring, usepfp, true,
-				   hub->ctx0_ptb_addr_hi32 + (2 * vmid),
-				   upper_32_bits(pd_addr));
-
-	gfx_v9_0_write_data_to_reg(ring, usepfp, true,
-				   hub->vm_inv_eng0_req + eng, req);
+	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
 	/* wait for the invalidate to complete */
-	gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
-			      eng, 0, 1 << vmid, 1 << vmid, 0x20);
+	gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack + eng,
+			      0, 1 << vmid, 1 << vmid, 0x20);
 
 	/* compute doesn't have PFP */
-	if (usepfp) {
+	if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
 		/* sync PFP to ME, otherwise we might get invalid PFP reads */
 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
 		amdgpu_ring_write(ring, 0x0);
@@ -4312,7 +4297,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
 	.emit_frame_size = /* totally 242 maximum if 16 IBs */
 		5 +  /* COND_EXEC */
 		7 +  /* PIPELINE_SYNC */
-		24 + /* VM_FLUSH */
+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
 		8 +  /* FENCE for VM_FLUSH */
 		20 + /* GDS switch */
 		4 + /* double SWITCH_BUFFER,
@@ -4361,7 +4346,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
 		7 + /* gfx_v9_0_ring_emit_hdp_flush */
 		5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
 		7 + /* gfx_v9_0_ring_emit_pipeline_sync */
-		24 + /* gfx_v9_0_ring_emit_vm_flush */
+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* gfx_v9_0_ring_emit_vm_flush */
 		8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
 	.emit_ib_size =	4, /* gfx_v9_0_ring_emit_ib_compute */
 	.emit_ib = gfx_v9_0_ring_emit_ib_compute,
@@ -4393,7 +4378,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
 		7 + /* gfx_v9_0_ring_emit_hdp_flush */
 		5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
 		7 + /* gfx_v9_0_ring_emit_pipeline_sync */
-		24 + /* gfx_v9_0_ring_emit_vm_flush */
+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* gfx_v9_0_ring_emit_vm_flush */
 		8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
 	.emit_ib_size =	4, /* gfx_v9_0_ring_emit_ib_compute */
 	.emit_ib = gfx_v9_0_ring_emit_ib_compute,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index b7e3a4dc952c..f7bcfa53eff0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -365,6 +365,29 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
 	spin_unlock(&adev->gmc.invalidate_lock);
 }
 
+static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+					    unsigned vmid, unsigned pasid,
+					    uint64_t pd_addr)
+{
+	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+	uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
+	uint64_t flags = AMDGPU_PTE_VALID;
+	unsigned eng = ring->vm_inv_eng;
+
+	amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
+	pd_addr |= flags;
+
+	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
+			      lower_32_bits(pd_addr));
+
+	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
+			      upper_32_bits(pd_addr));
+
+	amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
+
+	return pd_addr;
+}
+
 /**
  * gmc_v9_0_set_pte_pde - update the page tables using MMIO
  *
@@ -490,8 +513,8 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
 
 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
 	.flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
+	.emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
 	.set_pte_pde = gmc_v9_0_set_pte_pde,
-	.get_invalidate_req = gmc_v9_0_get_invalidate_req,
 	.get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
 	.get_vm_pde = gmc_v9_0_get_vm_pde
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 282b402d93ee..ee919477d7ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1137,28 +1137,9 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 					 uint64_t pd_addr)
 {
 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-	uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid);
-	uint64_t flags = AMDGPU_PTE_VALID;
 	unsigned eng = ring->vm_inv_eng;
 
-	amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
-	pd_addr |= flags;
-
-	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-	amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2);
-	amdgpu_ring_write(ring, lower_32_bits(pd_addr));
-
-	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-	amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vmid * 2);
-	amdgpu_ring_write(ring, upper_32_bits(pd_addr));
-
-	/* flush TLB */
-	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-	amdgpu_ring_write(ring, hub->vm_inv_eng0_req + eng);
-	amdgpu_ring_write(ring, req);
+	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
 	/* wait for flush */
 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
@@ -1604,7 +1585,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
 		6 + /* sdma_v4_0_ring_emit_hdp_flush */
 		3 + /* sdma_v4_0_ring_emit_hdp_invalidate */
 		6 + /* sdma_v4_0_ring_emit_pipeline_sync */
-		18 + /* sdma_v4_0_ring_emit_vm_flush */
+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v4_0_ring_emit_vm_flush */
 		10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
 	.emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
 	.emit_ib = sdma_v4_0_ring_emit_ib,
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
index 26b3feac5d06..a6b3b00d55e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -27,6 +27,8 @@
 #include "nbio_v6_1.h"
 #include "nbio_v7_0.h"
 
+#define SOC15_FLUSH_GPU_TLB_NUM_WREG	3
+
 extern const struct amd_ip_funcs soc15_common_ip_funcs;
 
 struct soc15_reg_golden {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 42c4296909e9..241e73022cd7 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -25,6 +25,7 @@
 #include <drm/drmP.h>
 #include "amdgpu.h"
 #include "amdgpu_uvd.h"
+#include "soc15.h"
 #include "soc15d.h"
 #include "soc15_common.h"
 #include "mmsch_v1_0.h"
@@ -1295,32 +1296,17 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 					uint64_t pd_addr)
 {
 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-	uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid);
-	uint64_t flags = AMDGPU_PTE_VALID;
 	unsigned eng = ring->vm_inv_eng;
 	uint32_t data0, data1, mask;
 
-	amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
-	pd_addr |= flags;
-
-	data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
-	data1 = upper_32_bits(pd_addr);
-	uvd_v7_0_ring_emit_wreg(ring, data0, data1);
-
-	data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
-	data1 = lower_32_bits(pd_addr);
-	uvd_v7_0_ring_emit_wreg(ring, data0, data1);
+	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
+	/* wait for reg writes */
 	data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
 	data1 = lower_32_bits(pd_addr);
 	mask = 0xffffffff;
 	uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
 
-	/* flush TLB */
-	data0 = (hub->vm_inv_eng0_req + eng) << 2;
-	data1 = req;
-	uvd_v7_0_ring_emit_wreg(ring, data0, data1);
-
 	/* wait for flush */
 	data0 = (hub->vm_inv_eng0_ack + eng) << 2;
 	data1 = 1 << vmid;
@@ -1348,31 +1334,16 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
 					    uint64_t pd_addr)
 {
 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-	uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid);
-	uint64_t flags = AMDGPU_PTE_VALID;
 	unsigned eng = ring->vm_inv_eng;
 
-	amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
-	pd_addr |= flags;
-
-	amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
-	amdgpu_ring_write(ring,	(hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2);
-	amdgpu_ring_write(ring, upper_32_bits(pd_addr));
-
-	amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
-	amdgpu_ring_write(ring,	(hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
-	amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
+	/* wait for reg writes */
 	amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
 	amdgpu_ring_write(ring,	(hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
 	amdgpu_ring_write(ring, 0xffffffff);
 	amdgpu_ring_write(ring, lower_32_bits(pd_addr));
 
-	/* flush TLB */
-	amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
-	amdgpu_ring_write(ring,	(hub->vm_inv_eng0_req + eng) << 2);
-	amdgpu_ring_write(ring, req);
-
 	/* wait for flush */
 	amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
 	amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
@@ -1724,7 +1695,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
 	.emit_frame_size =
 		2 + /* uvd_v7_0_ring_emit_hdp_flush */
 		2 + /* uvd_v7_0_ring_emit_hdp_invalidate */
-		34 + /* uvd_v7_0_ring_emit_vm_flush */
+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 16 + /* uvd_v7_0_ring_emit_vm_flush */
 		14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
 	.emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
 	.emit_ib = uvd_v7_0_ring_emit_ib,
@@ -1751,7 +1722,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
 	.get_wptr = uvd_v7_0_enc_ring_get_wptr,
 	.set_wptr = uvd_v7_0_enc_ring_set_wptr,
 	.emit_frame_size =
-		17 + /* uvd_v7_0_enc_ring_emit_vm_flush */
+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 8 + /* uvd_v7_0_enc_ring_emit_vm_flush */
 		5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
 		1, /* uvd_v7_0_enc_ring_insert_end */
 	.emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 9a0d6d9824d0..e62a24b90aaf 100755
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -28,6 +28,7 @@
 #include <drm/drmP.h>
 #include "amdgpu.h"
 #include "amdgpu_vce.h"
+#include "soc15.h"
 #include "soc15d.h"
 #include "soc15_common.h"
 #include "mmsch_v1_0.h"
@@ -969,31 +970,16 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
 				   uint64_t pd_addr)
 {
 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-	uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid);
-	uint64_t flags = AMDGPU_PTE_VALID;
 	unsigned eng = ring->vm_inv_eng;
 
-	amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
-	pd_addr |= flags;
-
-	amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
-	amdgpu_ring_write(ring,	(hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2);
-	amdgpu_ring_write(ring, upper_32_bits(pd_addr));
-
-	amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
-	amdgpu_ring_write(ring,	(hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
-	amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
+	/* wait for reg writes */
 	amdgpu_ring_write(ring, VCE_CMD_REG_WAIT);
 	amdgpu_ring_write(ring,	(hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
 	amdgpu_ring_write(ring, 0xffffffff);
 	amdgpu_ring_write(ring, lower_32_bits(pd_addr));
 
-	/* flush TLB */
-	amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
-	amdgpu_ring_write(ring,	(hub->vm_inv_eng0_req + eng) << 2);
-	amdgpu_ring_write(ring, req);
-
 	/* wait for flush */
 	amdgpu_ring_write(ring, VCE_CMD_REG_WAIT);
 	amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
@@ -1078,7 +1064,7 @@ static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = {
 	.set_wptr = vce_v4_0_ring_set_wptr,
 	.parse_cs = amdgpu_vce_ring_parse_cs_vm,
 	.emit_frame_size =
-		17 + /* vce_v4_0_emit_vm_flush */
+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 8 + /* vce_v4_0_emit_vm_flush */
 		5 + 5 + /* amdgpu_vce_ring_emit_fence x2 vm fence */
 		1, /* vce_v4_0_ring_insert_end */
 	.emit_ib_size = 5, /* vce_v4_0_ring_emit_ib */
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 8efe7f3ec0a1..76cdef29b9d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -25,6 +25,7 @@
 #include <drm/drmP.h>
 #include "amdgpu.h"
 #include "amdgpu_vcn.h"
+#include "soc15.h"
 #include "soc15d.h"
 #include "soc15_common.h"
 
@@ -852,22 +853,6 @@ static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
 	amdgpu_ring_write(ring, ib->length_dw);
 }
 
-static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring,
-				uint32_t data0, uint32_t data1)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	amdgpu_ring_write(ring,
-		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
-	amdgpu_ring_write(ring, data0);
-	amdgpu_ring_write(ring,
-		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
-	amdgpu_ring_write(ring, data1);
-	amdgpu_ring_write(ring,
-		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
-	amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
-}
-
 static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
 				uint32_t data0, uint32_t data1, uint32_t mask)
 {
@@ -892,32 +877,17 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
 					    uint64_t pd_addr)
 {
 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-	uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid);
-	uint64_t flags = AMDGPU_PTE_VALID;
 	unsigned eng = ring->vm_inv_eng;
 	uint32_t data0, data1, mask;
 
-	amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
-	pd_addr |= flags;
-
-	data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
-	data1 = upper_32_bits(pd_addr);
-	vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
-
-	data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
-	data1 = lower_32_bits(pd_addr);
-	vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
+	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
+	/* wait for register write */
 	data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
 	data1 = lower_32_bits(pd_addr);
 	mask = 0xffffffff;
 	vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
 
-	/* flush TLB */
-	data0 = (hub->vm_inv_eng0_req + eng) << 2;
-	data1 = req;
-	vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
-
 	/* wait for flush */
 	data0 = (hub->vm_inv_eng0_ack + eng) << 2;
 	data1 = 1 << vmid;
@@ -1026,34 +996,17 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
 					    uint64_t pd_addr)
 {
 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-	uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid);
-	uint64_t flags = AMDGPU_PTE_VALID;
 	unsigned eng = ring->vm_inv_eng;
 
-	amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
-	pd_addr |= flags;
-
-	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
-	amdgpu_ring_write(ring,
-			  (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2);
-	amdgpu_ring_write(ring, upper_32_bits(pd_addr));
-
-	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
-	amdgpu_ring_write(ring,
-			  (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
-	amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
 
+	/* wait for reg writes */
 	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
 	amdgpu_ring_write(ring,
 			  (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
 	amdgpu_ring_write(ring, 0xffffffff);
 	amdgpu_ring_write(ring, lower_32_bits(pd_addr));
 
-	/* flush TLB */
-	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
-	amdgpu_ring_write(ring,	(hub->vm_inv_eng0_req + eng) << 2);
-	amdgpu_ring_write(ring, req);
-
 	/* wait for flush */
 	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
 	amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
@@ -1144,7 +1097,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
 	.set_wptr = vcn_v1_0_dec_ring_set_wptr,
 	.emit_frame_size =
 		2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */
-		34 + /* vcn_v1_0_dec_ring_emit_vm_flush */
+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 16 + /* vcn_v1_0_dec_ring_emit_vm_flush */
 		14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
 		6,
 	.emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
@@ -1173,7 +1126,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
 	.get_wptr = vcn_v1_0_enc_ring_get_wptr,
 	.set_wptr = vcn_v1_0_enc_ring_set_wptr,
 	.emit_frame_size =
-		17 + /* vcn_v1_0_enc_ring_emit_vm_flush */
+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 8 + /* vcn_v1_0_enc_ring_emit_vm_flush */
 		5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
 		1, /* vcn_v1_0_enc_ring_insert_end */
 	.emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
-- 
2.14.1

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[PATCH 19/21] drm/amdgpu: add PASID mapping for GMC v7

[Christian König]

This way we can see the PASID in VM faults.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/cik.h      | 2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h
index 201d8786f9cb..e49c6f15a0a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik.h
@@ -24,7 +24,7 @@
 #ifndef __CIK_H__
 #define __CIK_H__
 
-#define CIK_FLUSH_GPU_TLB_NUM_WREG	2
+#define CIK_FLUSH_GPU_TLB_NUM_WREG	3
 
 void cik_srbm_select(struct amdgpu_device *adev,
 		     u32 me, u32 pipe, u32 queue, u32 vmid);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 2daf118e69ac..63fb47ae1f12 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -446,6 +446,8 @@ static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 		reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
 	amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 
+	amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
+
 	/* bits 0-15 are the VM contexts0-15 */
 	amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 
-- 
2.14.1

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[PATCH 20/21] drm/amdgpu: add PASID mapping for GFX v8

[Christian König]

This way we can see the PASID in VM faults.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/vi.h       | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index da02c61dda38..1d0ae23d439f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -622,6 +622,8 @@ static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 		reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
 	amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 
+	amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
+
 	/* bits 0-15 are the VM contexts0-15 */
 	amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
index 6cc2bee4abf7..0429fe332269 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.h
+++ b/drivers/gpu/drm/amd/amdgpu/vi.h
@@ -24,7 +24,7 @@
 #ifndef __VI_H__
 #define __VI_H__
 
-#define VI_FLUSH_GPU_TLB_NUM_WREG	2
+#define VI_FLUSH_GPU_TLB_NUM_WREG	3
 
 void vi_srbm_select(struct amdgpu_device *adev,
 		    u32 me, u32 pipe, u32 queue, u32 vmid);
-- 
2.14.1

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[PATCH 21/21] drm/amdgpu: add PASID mapping for GFX v8

[Christian König]

This way we can see the PASID in VM faults.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index f7bcfa53eff0..2efbecf486c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -33,6 +33,7 @@
 #include "vega10_enum.h"
 #include "mmhub/mmhub_1_0_offset.h"
 #include "athub/athub_1_0_offset.h"
+#include "oss/osssys_4_0_offset.h"
 
 #include "soc15.h"
 #include "soc15_common.h"
@@ -369,10 +370,12 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 					    unsigned vmid, unsigned pasid,
 					    uint64_t pd_addr)
 {
-	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+	struct amdgpu_device *adev = ring->adev;
+	struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
 	uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
 	uint64_t flags = AMDGPU_PTE_VALID;
 	unsigned eng = ring->vm_inv_eng;
+	uint32_t reg;
 
 	amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
 	pd_addr |= flags;
@@ -383,6 +386,13 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
 			      upper_32_bits(pd_addr));
 
+	if (ring->funcs->vmhub == AMDGPU_GFXHUB)
+		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
+	else
+		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
+
+	amdgpu_ring_emit_wreg(ring, reg, pasid);
+
 	amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
 
 	return pd_addr;
-- 
2.14.1

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Re: [PATCH 10/21] drm/amdgpu: wire up emit_wreg for UVD v6

[Alex Deucher]

On Tue, Jan 16, 2018 at 2:40 PM, Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
> Needed for vm_flush unification.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index c6e22eff89e7..b48b843c66ae 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -1059,6 +1059,17 @@ static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
>         amdgpu_ring_write(ring, ib->length_dw);
>  }
>
> +static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
> +                                   uint32_t reg, uint32_t val)
> +{
> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
> +       amdgpu_ring_write(ring, reg << 2);
> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
> +       amdgpu_ring_write(ring, val);
> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
> +       amdgpu_ring_write(ring, 0x8);

Is this valid on UVD6?  I think this may be a UVD7 thing.  Looking at
the other UVD code, I think we just want:
        amdgpu_ring_write(ring, PACKET0(reg, 0));
        amdgpu_ring_write(ring, val);

Alex


> +}
> +
>  static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>                                         unsigned vmid, unsigned pasid,
>                                         uint64_t pd_addr)
> @@ -1595,6 +1606,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
>         .pad_ib = amdgpu_ring_generic_pad_ib,
>         .begin_use = amdgpu_uvd_ring_begin_use,
>         .end_use = amdgpu_uvd_ring_end_use,
> +       .emit_wreg = uvd_v6_0_ring_emit_wreg,
>  };
>
>  static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
> --
> 2.14.1
>
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Re: [PATCH 11/21] drm/amdgpu: wire up emit_wreg for UVD v7

[Alex Deucher]

On Tue, Jan 16, 2018 at 2:40 PM, Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
> Needed for vm_flush unification.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 24 +++++++++++++++++-------
>  1 file changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 44f1a3dde4d6..42c4296909e9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -1255,17 +1255,17 @@ static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
>         amdgpu_ring_write(ring, ib->length_dw);
>  }
>
> -static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring,
> -                               uint32_t data0, uint32_t data1)
> +static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
> +                                   uint32_t reg, uint32_t val)
>  {
>         struct amdgpu_device *adev = ring->adev;
>
>         amdgpu_ring_write(ring,
>                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
> -       amdgpu_ring_write(ring, data0);
> +       amdgpu_ring_write(ring, reg << 2);
>         amdgpu_ring_write(ring,
>                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
> -       amdgpu_ring_write(ring, data1);
> +       amdgpu_ring_write(ring, val);
>         amdgpu_ring_write(ring,
>                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
>         amdgpu_ring_write(ring, 8);


I think this is a special command specifically for writing VM
registers.  I think you just want a regular PACKET0 like I suggested
for UVD 6.  If that's not the case,
uvd_v7_0_ring_emit_hdp_flush() and are
uvd_v7_0_ring_emit_hdp_invalidate() probably wrong then.  Same for UVD
6.

Independent of this patch, it would be nice two switch the magic
numbers written to VCPU_CMD with nicer defines...


Alex


> @@ -1305,11 +1305,11 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>
>         data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
>         data1 = upper_32_bits(pd_addr);
> -       uvd_v7_0_vm_reg_write(ring, data0, data1);
> +       uvd_v7_0_ring_emit_wreg(ring, data0, data1);
>
>         data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
>         data1 = lower_32_bits(pd_addr);
> -       uvd_v7_0_vm_reg_write(ring, data0, data1);
> +       uvd_v7_0_ring_emit_wreg(ring, data0, data1);
>
>         data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
>         data1 = lower_32_bits(pd_addr);
> @@ -1319,7 +1319,7 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>         /* flush TLB */
>         data0 = (hub->vm_inv_eng0_req + eng) << 2;
>         data1 = req;
> -       uvd_v7_0_vm_reg_write(ring, data0, data1);
> +       uvd_v7_0_ring_emit_wreg(ring, data0, data1);
>
>         /* wait for flush */
>         data0 = (hub->vm_inv_eng0_ack + eng) << 2;
> @@ -1380,6 +1380,14 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
>         amdgpu_ring_write(ring, 1 << vmid);
>  }
>
> +static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
> +                                       uint32_t reg, uint32_t val)
> +{
> +       amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
> +       amdgpu_ring_write(ring, reg << 2);
> +       amdgpu_ring_write(ring, val);
> +}
> +
>  #if 0
>  static bool uvd_v7_0_is_idle(void *handle)
>  {
> @@ -1730,6 +1738,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
>         .pad_ib = amdgpu_ring_generic_pad_ib,
>         .begin_use = amdgpu_uvd_ring_begin_use,
>         .end_use = amdgpu_uvd_ring_end_use,
> +       .emit_wreg = uvd_v7_0_ring_emit_wreg,
>  };
>
>  static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
> @@ -1756,6 +1765,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
>         .pad_ib = amdgpu_ring_generic_pad_ib,
>         .begin_use = amdgpu_uvd_ring_begin_use,
>         .end_use = amdgpu_uvd_ring_end_use,
> +       .emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
>  };
>
>  static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
> --
> 2.14.1
>
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Re: [PATCH 01/21] drm/amdgpu: wire up emit_wreg for gfx v6

[Alex Deucher]

On Tue, Jan 16, 2018 at 2:39 PM, Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
> Needed for vm_flush unification.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 39acafbc84d6..e72f3e5d24b8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -2402,6 +2402,18 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>         }
>  }
>
> +static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
> +                                   uint32_t reg, uint32_t val)
> +{
> +       int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
> +
> +       amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
> +       amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
> +                                WRITE_DATA_DST_SEL(0)));
> +       amdgpu_ring_write(ring, reg);
> +       amdgpu_ring_write(ring, 0);
> +       amdgpu_ring_write(ring, val);
> +}
>
>  static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
>  {
> @@ -3529,6 +3541,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
>         .test_ib = gfx_v6_0_ring_test_ib,
>         .insert_nop = amdgpu_ring_insert_nop,
>         .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
> +       .emit_wreg = gfx_v6_0_ring_emit_wreg,

I think you need to update the compute ring_funcs as well for all the gfx IPs.

Alex

>  };
>
>  static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
> --
> 2.14.1
>
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Re: [PATCH 21/21] drm/amdgpu: add PASID mapping for GFX v8

[Chunming Zhou]

patch #19, #20, #21 are Reviewed-by: Chunming Zhou <david1.zhou@amd.com>


On 2018年01月17日 03:40, Christian König wrote:
> This way we can see the PASID in VM faults.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +++++++++++-
>   1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index f7bcfa53eff0..2efbecf486c5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -33,6 +33,7 @@
>   #include "vega10_enum.h"
>   #include "mmhub/mmhub_1_0_offset.h"
>   #include "athub/athub_1_0_offset.h"
> +#include "oss/osssys_4_0_offset.h"
>   
>   #include "soc15.h"
>   #include "soc15_common.h"
> @@ -369,10 +370,12 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>   					    unsigned vmid, unsigned pasid,
>   					    uint64_t pd_addr)
>   {
> -	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
> +	struct amdgpu_device *adev = ring->adev;
> +	struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
>   	uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
>   	uint64_t flags = AMDGPU_PTE_VALID;
>   	unsigned eng = ring->vm_inv_eng;
> +	uint32_t reg;
>   
>   	amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
>   	pd_addr |= flags;
> @@ -383,6 +386,13 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>   	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
>   			      upper_32_bits(pd_addr));
>   
> +	if (ring->funcs->vmhub == AMDGPU_GFXHUB)
> +		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
> +	else
> +		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
> +
> +	amdgpu_ring_emit_wreg(ring, reg, pasid);
> +
>   	amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
>   
>   	return pd_addr;

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Re: [PATCH 21/21] drm/amdgpu: add PASID mapping for GFX v8

[Chunming Zhou]

and please fix patch #21 tile, which should be gfx9 not gfx8.


On 2018年01月17日 14:11, Chunming Zhou wrote:
> patch #19, #20, #21 are Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
>
>
> On 2018年01月17日 03:40, Christian König wrote:
>> This way we can see the PASID in VM faults.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +++++++++++-
>>   1 file changed, 11 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> index f7bcfa53eff0..2efbecf486c5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> @@ -33,6 +33,7 @@
>>   #include "vega10_enum.h"
>>   #include "mmhub/mmhub_1_0_offset.h"
>>   #include "athub/athub_1_0_offset.h"
>> +#include "oss/osssys_4_0_offset.h"
>>     #include "soc15.h"
>>   #include "soc15_common.h"
>> @@ -369,10 +370,12 @@ static uint64_t 
>> gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>>                           unsigned vmid, unsigned pasid,
>>                           uint64_t pd_addr)
>>   {
>> -    struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
>> +    struct amdgpu_device *adev = ring->adev;
>> +    struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
>>       uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
>>       uint64_t flags = AMDGPU_PTE_VALID;
>>       unsigned eng = ring->vm_inv_eng;
>> +    uint32_t reg;
>>         amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
>>       pd_addr |= flags;
>> @@ -383,6 +386,13 @@ static uint64_t 
>> gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>>       amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
>>                     upper_32_bits(pd_addr));
>>   +    if (ring->funcs->vmhub == AMDGPU_GFXHUB)
>> +        reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
>> +    else
>> +        reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
>> +
>> +    amdgpu_ring_emit_wreg(ring, reg, pasid);
>> +
>>       amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
>>         return pd_addr;
>
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Re: [PATCH 21/21] drm/amdgpu: add PASID mapping for GFX v8

[Chunming Zhou]

and please fix patch #21 title, which should be gfx9 not gfx8.


On 2018年01月17日 14:11, Chunming Zhou wrote:
> patch #19, #20, #21 are Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
>
>
> On 2018年01月17日 03:40, Christian König wrote:
>> This way we can see the PASID in VM faults.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +++++++++++-
>>   1 file changed, 11 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> index f7bcfa53eff0..2efbecf486c5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> @@ -33,6 +33,7 @@
>>   #include "vega10_enum.h"
>>   #include "mmhub/mmhub_1_0_offset.h"
>>   #include "athub/athub_1_0_offset.h"
>> +#include "oss/osssys_4_0_offset.h"
>>     #include "soc15.h"
>>   #include "soc15_common.h"
>> @@ -369,10 +370,12 @@ static uint64_t 
>> gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>>                           unsigned vmid, unsigned pasid,
>>                           uint64_t pd_addr)
>>   {
>> -    struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
>> +    struct amdgpu_device *adev = ring->adev;
>> +    struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
>>       uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
>>       uint64_t flags = AMDGPU_PTE_VALID;
>>       unsigned eng = ring->vm_inv_eng;
>> +    uint32_t reg;
>>         amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
>>       pd_addr |= flags;
>> @@ -383,6 +386,13 @@ static uint64_t 
>> gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>>       amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
>>                     upper_32_bits(pd_addr));
>>   +    if (ring->funcs->vmhub == AMDGPU_GFXHUB)
>> +        reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
>> +    else
>> +        reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
>> +
>> +    amdgpu_ring_emit_wreg(ring, reg, pasid);
>> +
>>       amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
>>         return pd_addr;
>
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Re: [PATCH 21/21] drm/amdgpu: add PASID mapping for GFX v8

[Chunming Zhou]

gmc8, gmc9, not gfx...


On 2018年01月17日 14:13, Chunming Zhou wrote:
> and please fix patch #21 title, which should be gfx9 not gfx8.
>
>
> On 2018年01月17日 14:11, Chunming Zhou wrote:
>> patch #19, #20, #21 are Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
>>
>>
>> On 2018年01月17日 03:40, Christian König wrote:
>>> This way we can see the PASID in VM faults.
>>>
>>> Signed-off-by: Christian König <christian.koenig@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +++++++++++-
>>>   1 file changed, 11 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
>>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>> index f7bcfa53eff0..2efbecf486c5 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>> @@ -33,6 +33,7 @@
>>>   #include "vega10_enum.h"
>>>   #include "mmhub/mmhub_1_0_offset.h"
>>>   #include "athub/athub_1_0_offset.h"
>>> +#include "oss/osssys_4_0_offset.h"
>>>     #include "soc15.h"
>>>   #include "soc15_common.h"
>>> @@ -369,10 +370,12 @@ static uint64_t 
>>> gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>>>                           unsigned vmid, unsigned pasid,
>>>                           uint64_t pd_addr)
>>>   {
>>> -    struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
>>> +    struct amdgpu_device *adev = ring->adev;
>>> +    struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
>>>       uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
>>>       uint64_t flags = AMDGPU_PTE_VALID;
>>>       unsigned eng = ring->vm_inv_eng;
>>> +    uint32_t reg;
>>>         amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
>>>       pd_addr |= flags;
>>> @@ -383,6 +386,13 @@ static uint64_t 
>>> gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>>>       amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
>>>                     upper_32_bits(pd_addr));
>>>   +    if (ring->funcs->vmhub == AMDGPU_GFXHUB)
>>> +        reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
>>> +    else
>>> +        reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
>>> +
>>> +    amdgpu_ring_emit_wreg(ring, reg, pasid);
>>> +
>>>       amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
>>>         return pd_addr;
>>
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>
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Re: [PATCH 14/21] drm/amdgpu: add new amdgpu_gmc_emit_flush_gpu_tlb callback

[Chunming Zhou]

I'm not sure if this is a good ongoing, as I know, our per IP topology 
is intended for every generation asic bringup.

I think there are many similar logics which we can abstract, but we 
don't do that.

For emit_wreg above patches, they only can be used by vm flush part, but 
they are common func fallback.

Can we only make emit_wreg as static in their files, and replace every 
where they are used?

Regards,
David Zhou
On 2018年01月17日 03:40, Christian König wrote:
> Add a new GMC function to unify vm flushing.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 1 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 +++
>   2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 93eae393b08d..230826718c98 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1779,6 +1779,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
>   #define amdgpu_asic_flush_hdp(adev) (adev)->asic_funcs->flush_hdp((adev))
>   #define amdgpu_asic_invalidate_hdp(adev) (adev)->asic_funcs->invalidate_hdp((adev))
>   #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
> +#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, pasid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (pasid), (addr))
>   #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
>   #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
>   #define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index a4a8374f7f3f..114350a4693f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -52,6 +52,9 @@ struct amdgpu_gmc_funcs {
>   	/* flush the vm tlb via mmio */
>   	void (*flush_gpu_tlb)(struct amdgpu_device *adev,
>   			      uint32_t vmid);
> +	/* flush the vm tlb via ring */
> +	uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
> +				       unsigned pasid, uint64_t pd_addr);
>   	/* write pte/pde updates using the cpu */
>   	int (*set_pte_pde)(struct amdgpu_device *adev,
>   			   void *cpu_pt_addr, /* cpu addr of page table */

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Re: [PATCH 14/21] drm/amdgpu: add new amdgpu_gmc_emit_flush_gpu_tlb callback

[Christian König]

Am 17.01.2018 um 07:24 schrieb Chunming Zhou:
> I'm not sure if this is a good ongoing, as I know, our per IP topology 
> is intended for every generation asic bringup.

Actually the intention goes beyond that, e.g. we want to reuse IPs for 
newer ASICs as well when they haven't changed.

>
> I think there are many similar logics which we can abstract, but we 
> don't do that.
>
> For emit_wreg above patches, they only can be used by vm flush part, 
> but they are common func fallback.
>
> Can we only make emit_wreg as static in their files, and replace every 
> where they are used?

Not sure what you are suggesting here?

Regards,
Christian.

>
> Regards,
> David Zhou
> On 2018年01月17日 03:40, Christian König wrote:
>> Add a new GMC function to unify vm flushing.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 1 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 +++
>>   2 files changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 93eae393b08d..230826718c98 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -1779,6 +1779,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
>>   #define amdgpu_asic_flush_hdp(adev) 
>> (adev)->asic_funcs->flush_hdp((adev))
>>   #define amdgpu_asic_invalidate_hdp(adev) 
>> (adev)->asic_funcs->invalidate_hdp((adev))
>>   #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) 
>> (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
>> +#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, pasid, addr) 
>> (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (pasid), 
>> (addr))
>>   #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) 
>> (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
>>   #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) 
>> (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
>>   #define amdgpu_gmc_get_pte_flags(adev, flags) 
>> (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>> index a4a8374f7f3f..114350a4693f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>> @@ -52,6 +52,9 @@ struct amdgpu_gmc_funcs {
>>       /* flush the vm tlb via mmio */
>>       void (*flush_gpu_tlb)(struct amdgpu_device *adev,
>>                     uint32_t vmid);
>> +    /* flush the vm tlb via ring */
>> +    uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, 
>> unsigned vmid,
>> +                       unsigned pasid, uint64_t pd_addr);
>>       /* write pte/pde updates using the cpu */
>>       int (*set_pte_pde)(struct amdgpu_device *adev,
>>                  void *cpu_pt_addr, /* cpu addr of page table */
>

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Re: [PATCH 10/21] drm/amdgpu: wire up emit_wreg for UVD v6

[Christian König]

Am 16.01.2018 um 21:01 schrieb Alex Deucher:
> On Tue, Jan 16, 2018 at 2:40 PM, Christian König
> <ckoenig.leichtzumerken@gmail.com> wrote:
>> Needed for vm_flush unification.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> index c6e22eff89e7..b48b843c66ae 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> @@ -1059,6 +1059,17 @@ static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
>>          amdgpu_ring_write(ring, ib->length_dw);
>>   }
>>
>> +static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
>> +                                   uint32_t reg, uint32_t val)
>> +{
>> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
>> +       amdgpu_ring_write(ring, reg << 2);
>> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
>> +       amdgpu_ring_write(ring, val);
>> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
>> +       amdgpu_ring_write(ring, 0x8);
> Is this valid on UVD6?

This is valid on the decode ring of UVD6, only the HEVC UVD6 encode and 
VCE3 rings use different commands.

>    I think this may be a UVD7 thing.  Looking at
> the other UVD code, I think we just want:
>          amdgpu_ring_write(ring, PACKET0(reg, 0));
>          amdgpu_ring_write(ring, val);

IIRC that won't work. The UVD RBC can only write to UVD registers using 
the PACKET0 command.

Regards,
Christian.

>
> Alex
>
>
>> +}
>> +
>>   static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>>                                          unsigned vmid, unsigned pasid,
>>                                          uint64_t pd_addr)
>> @@ -1595,6 +1606,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
>>          .pad_ib = amdgpu_ring_generic_pad_ib,
>>          .begin_use = amdgpu_uvd_ring_begin_use,
>>          .end_use = amdgpu_uvd_ring_end_use,
>> +       .emit_wreg = uvd_v6_0_ring_emit_wreg,
>>   };
>>
>>   static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
>> --
>> 2.14.1
>>
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Re: [PATCH 11/21] drm/amdgpu: wire up emit_wreg for UVD v7

[Christian König]

Am 16.01.2018 um 21:05 schrieb Alex Deucher:
> On Tue, Jan 16, 2018 at 2:40 PM, Christian König
> <ckoenig.leichtzumerken@gmail.com> wrote:
>> Needed for vm_flush unification.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 24 +++++++++++++++++-------
>>   1 file changed, 17 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> index 44f1a3dde4d6..42c4296909e9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> @@ -1255,17 +1255,17 @@ static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
>>          amdgpu_ring_write(ring, ib->length_dw);
>>   }
>>
>> -static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring,
>> -                               uint32_t data0, uint32_t data1)
>> +static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
>> +                                   uint32_t reg, uint32_t val)
>>   {
>>          struct amdgpu_device *adev = ring->adev;
>>
>>          amdgpu_ring_write(ring,
>>                  PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
>> -       amdgpu_ring_write(ring, data0);
>> +       amdgpu_ring_write(ring, reg << 2);
>>          amdgpu_ring_write(ring,
>>                  PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
>> -       amdgpu_ring_write(ring, data1);
>> +       amdgpu_ring_write(ring, val);
>>          amdgpu_ring_write(ring,
>>                  PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
>>          amdgpu_ring_write(ring, 8);
>
> I think this is a special command specifically for writing VM
> registers.  I think you just want a regular PACKET0 like I suggested
> for UVD 6.  If that's not the case,
> uvd_v7_0_ring_emit_hdp_flush() and are
> uvd_v7_0_ring_emit_hdp_invalidate() probably wrong then.  Same for UVD
> 6.

Going to give that a test, but those HDP flush/invalidation 
implementation indeed look like they won't work.

As far as I know the PACKET0 command on the RBC can only write to UVD 
registers.

>
> Independent of this patch, it would be nice two switch the magic
> numbers written to VCPU_CMD with nicer defines...

Agree, completely. But that is a job for Leo/Boyuan I think.

Christian.

>
>
> Alex
>
>
>> @@ -1305,11 +1305,11 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>>
>>          data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
>>          data1 = upper_32_bits(pd_addr);
>> -       uvd_v7_0_vm_reg_write(ring, data0, data1);
>> +       uvd_v7_0_ring_emit_wreg(ring, data0, data1);
>>
>>          data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
>>          data1 = lower_32_bits(pd_addr);
>> -       uvd_v7_0_vm_reg_write(ring, data0, data1);
>> +       uvd_v7_0_ring_emit_wreg(ring, data0, data1);
>>
>>          data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
>>          data1 = lower_32_bits(pd_addr);
>> @@ -1319,7 +1319,7 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>>          /* flush TLB */
>>          data0 = (hub->vm_inv_eng0_req + eng) << 2;
>>          data1 = req;
>> -       uvd_v7_0_vm_reg_write(ring, data0, data1);
>> +       uvd_v7_0_ring_emit_wreg(ring, data0, data1);
>>
>>          /* wait for flush */
>>          data0 = (hub->vm_inv_eng0_ack + eng) << 2;
>> @@ -1380,6 +1380,14 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
>>          amdgpu_ring_write(ring, 1 << vmid);
>>   }
>>
>> +static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
>> +                                       uint32_t reg, uint32_t val)
>> +{
>> +       amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
>> +       amdgpu_ring_write(ring, reg << 2);
>> +       amdgpu_ring_write(ring, val);
>> +}
>> +
>>   #if 0
>>   static bool uvd_v7_0_is_idle(void *handle)
>>   {
>> @@ -1730,6 +1738,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
>>          .pad_ib = amdgpu_ring_generic_pad_ib,
>>          .begin_use = amdgpu_uvd_ring_begin_use,
>>          .end_use = amdgpu_uvd_ring_end_use,
>> +       .emit_wreg = uvd_v7_0_ring_emit_wreg,
>>   };
>>
>>   static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
>> @@ -1756,6 +1765,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
>>          .pad_ib = amdgpu_ring_generic_pad_ib,
>>          .begin_use = amdgpu_uvd_ring_begin_use,
>>          .end_use = amdgpu_uvd_ring_end_use,
>> +       .emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
>>   };
>>
>>   static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
>> --
>> 2.14.1
>>
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Re: [PATCH 01/21] drm/amdgpu: wire up emit_wreg for gfx v6

[Christian König]

Am 16.01.2018 um 21:15 schrieb Alex Deucher:
> On Tue, Jan 16, 2018 at 2:39 PM, Christian König
> <ckoenig.leichtzumerken@gmail.com> wrote:
>> Needed for vm_flush unification.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 13 +++++++++++++
>>   1 file changed, 13 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> index 39acafbc84d6..e72f3e5d24b8 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> @@ -2402,6 +2402,18 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>>          }
>>   }
>>
>> +static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
>> +                                   uint32_t reg, uint32_t val)
>> +{
>> +       int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
>> +
>> +       amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
>> +       amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
>> +                                WRITE_DATA_DST_SEL(0)));
>> +       amdgpu_ring_write(ring, reg);
>> +       amdgpu_ring_write(ring, 0);
>> +       amdgpu_ring_write(ring, val);
>> +}
>>
>>   static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
>>   {
>> @@ -3529,6 +3541,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
>>          .test_ib = gfx_v6_0_ring_test_ib,
>>          .insert_nop = amdgpu_ring_insert_nop,
>>          .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
>> +       .emit_wreg = gfx_v6_0_ring_emit_wreg,
> I think you need to update the compute ring_funcs as well for all the gfx IPs.

Ah, yes good point.

Regards,
Christian.

>
> Alex
>
>>   };
>>
>>   static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
>> --
>> 2.14.1
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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Re: [PATCH 10/21] drm/amdgpu: wire up emit_wreg for UVD v6

[Deucher, Alexander]

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________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Christian König <ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Wednesday, January 17, 2018 7:42 AM
To: Alex Deucher
Cc: amd-gfx list
Subject: Re: [PATCH 10/21] drm/amdgpu: wire up emit_wreg for UVD v6

Am 16.01.2018 um 21:01 schrieb Alex Deucher:
> On Tue, Jan 16, 2018 at 2:40 PM, Christian König
> <ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>> Needed for vm_flush unification.
>>
>> Signed-off-by: Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> index c6e22eff89e7..b48b843c66ae 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> @@ -1059,6 +1059,17 @@ static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
>>          amdgpu_ring_write(ring, ib->length_dw);
>>   }
>>
>> +static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
>> +                                   uint32_t reg, uint32_t val)
>> +{
>> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
>> +       amdgpu_ring_write(ring, reg << 2);
>> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
>> +       amdgpu_ring_write(ring, val);
>> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
>> +       amdgpu_ring_write(ring, 0x8);
> Is this valid on UVD6?

This is valid on the decode ring of UVD6, only the HEVC UVD6 encode and
VCE3 rings use different commands.

>    I think this may be a UVD7 thing.  Looking at
> the other UVD code, I think we just want:
>          amdgpu_ring_write(ring, PACKET0(reg, 0));
>          amdgpu_ring_write(ring, val);

IIRC that won't work. The UVD RBC can only write to UVD registers using
the PACKET0 command.

We probably need to fix a bunch of functions in uvd4,5,6,7 in that case which use packet0 directly to write non-UVD registers.

Alex


Regards,
Christian.

>
> Alex
>
>
>> +}
>> +
>>   static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>>                                          unsigned vmid, unsigned pasid,
>>                                          uint64_t pd_addr)
>> @@ -1595,6 +1606,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
>>          .pad_ib = amdgpu_ring_generic_pad_ib,
>>          .begin_use = amdgpu_uvd_ring_begin_use,
>>          .end_use = amdgpu_uvd_ring_end_use,
>> +       .emit_wreg = uvd_v6_0_ring_emit_wreg,
>>   };
>>
>>   static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
>> --
>> 2.14.1
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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Re: [PATCH 10/21] drm/amdgpu: wire up emit_wreg for UVD v6

[Christian König]

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Am 17.01.2018 um 15:22 schrieb Deucher, Alexander:
>
>
> ------------------------------------------------------------------------
> *From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of 
> Christian König <ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> *Sent:* Wednesday, January 17, 2018 7:42 AM
> *To:* Alex Deucher
> *Cc:* amd-gfx list
> *Subject:* Re: [PATCH 10/21] drm/amdgpu: wire up emit_wreg for UVD v6
> Am 16.01.2018 um 21:01 schrieb Alex Deucher:
> > On Tue, Jan 16, 2018 at 2:40 PM, Christian König
> > <ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> >> Needed for vm_flush unification.
> >>
> >> Signed-off-by: Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org>
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 12 ++++++++++++
> >>   1 file changed, 12 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> >> index c6e22eff89e7..b48b843c66ae 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> >> @@ -1059,6 +1059,17 @@ static void uvd_v6_0_enc_ring_emit_ib(struct 
> amdgpu_ring *ring,
> >>          amdgpu_ring_write(ring, ib->length_dw);
> >>   }
> >>
> >> +static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
> >> +                                   uint32_t reg, uint32_t val)
> >> +{
> >> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
> >> +       amdgpu_ring_write(ring, reg << 2);
> >> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
> >> +       amdgpu_ring_write(ring, val);
> >> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
> >> +       amdgpu_ring_write(ring, 0x8);
> > Is this valid on UVD6?
>
> This is valid on the decode ring of UVD6, only the HEVC UVD6 encode and
> VCE3 rings use different commands.
>
> >    I think this may be a UVD7 thing.  Looking at
> > the other UVD code, I think we just want:
> >          amdgpu_ring_write(ring, PACKET0(reg, 0));
> >          amdgpu_ring_write(ring, val);
>
> IIRC that won't work. The UVD RBC can only write to UVD registers using
> the PACKET0 command.
>
> We probably need to fix a bunch of functions in uvd4,5,6,7 in that 
> case which use packet0 directly to write non-UVD registers.

Yeah, I see. I briefly remember that I questioned if this works or not 
two years ago when we added the code.

Going to wire things up correctly with the new wreg callback.

Christian.

>
> Alex
>
>
> Regards,
> Christian.
>
> >
> > Alex
> >
> >
> >> +}
> >> +
> >>   static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
> >> unsigned vmid, unsigned pasid,
> >> uint64_t pd_addr)
> >> @@ -1595,6 +1606,7 @@ static const struct amdgpu_ring_funcs 
> uvd_v6_0_ring_vm_funcs = {
> >>          .pad_ib = amdgpu_ring_generic_pad_ib,
> >>          .begin_use = amdgpu_uvd_ring_begin_use,
> >>          .end_use = amdgpu_uvd_ring_end_use,
> >> +       .emit_wreg = uvd_v6_0_ring_emit_wreg,
> >>   };
> >>
> >>   static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
> >> --
> >> 2.14.1
> >>
> >> _______________________________________________
> >> amd-gfx mailing list
> >> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx


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Re: [PATCH 14/21] drm/amdgpu: add new amdgpu_gmc_emit_flush_gpu_tlb callback

[Chunming Zhou]

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On 2018年01月17日 20:19, Christian König wrote:
> Am 17.01.2018 um 07:24 schrieb Chunming Zhou:
>> I'm not sure if this is a good ongoing, as I know, our per IP 
>> topology is intended for every generation asic bringup.
>
> Actually the intention goes beyond that, e.g. we want to reuse IPs for 
> newer ASICs as well when they haven't changed.
>
>>
>> I think there are many similar logics which we can abstract, but we 
>> don't do that.
>>
>> For emit_wreg above patches, they only can be used by vm flush part, 
>> but they are common func fallback.
>>
>> Can we only make emit_wreg as static in their files, and replace 
>> every where they are used?
>
> Not sure what you are suggesting here?
my mean is like the attached, only abstract them in file per ip.

Regards,
David Zhou
>
> Regards,
> Christian.
>
>>
>> Regards,
>> David Zhou
>> On 2018年01月17日 03:40, Christian König wrote:
>>> Add a new GMC function to unify vm flushing.
>>>
>>> Signed-off-by: Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 1 +
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 +++
>>>   2 files changed, 4 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index 93eae393b08d..230826718c98 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -1779,6 +1779,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring 
>>> *ring)
>>>   #define amdgpu_asic_flush_hdp(adev) 
>>> (adev)->asic_funcs->flush_hdp((adev))
>>>   #define amdgpu_asic_invalidate_hdp(adev) 
>>> (adev)->asic_funcs->invalidate_hdp((adev))
>>>   #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) 
>>> (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
>>> +#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, pasid, addr) 
>>> (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (pasid), 
>>> (addr))
>>>   #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) 
>>> (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), 
>>> (flags))
>>>   #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) 
>>> (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
>>>   #define amdgpu_gmc_get_pte_flags(adev, flags) 
>>> (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>>> index a4a8374f7f3f..114350a4693f 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>>> @@ -52,6 +52,9 @@ struct amdgpu_gmc_funcs {
>>>       /* flush the vm tlb via mmio */
>>>       void (*flush_gpu_tlb)(struct amdgpu_device *adev,
>>>                     uint32_t vmid);
>>> +    /* flush the vm tlb via ring */
>>> +    uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, 
>>> unsigned vmid,
>>> +                       unsigned pasid, uint64_t pd_addr);
>>>       /* write pte/pde updates using the cpu */
>>>       int (*set_pte_pde)(struct amdgpu_device *adev,
>>>                  void *cpu_pt_addr, /* cpu addr of page table */
>>
>


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>From ce20fa3aba41605e7a5001e08a0e97a5fa1f4cff Mon Sep 17 00:00:00 2001
From: Chunming Zhou <david1.zhou-5C7GfCeVMHo@public.gmane.org>
Date: Thu, 18 Jan 2018 15:05:59 +0800
Subject: [PATCH] drm/amdgpu: abstract write data packet for gfx8

Change-Id: I1512225e94b4875b9c59fcaf1bff818922dbdd7c
Signed-off-by: Chunming Zhou <david1.zhou-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 153 +++++++++++++++++++---------------
 1 file changed, 84 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 3fd7eb2a9a7b..9ba4aae128d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -675,6 +675,24 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
 static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
 static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 
+struct gfx8_write_data {
+	uint32_t n;
+	uint32_t control;
+	uint64_t reg;
+	uint32_t val;
+};
+
+static void gfx_v8_0_ring_write_data(struct amdgpu_ring *ring,
+				     struct gfx8_write_data *wd)
+{
+	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, wd->n));
+	amdgpu_ring_write(ring, wd->control);
+	amdgpu_ring_write(ring, lower_32_bits(wd->reg));
+	amdgpu_ring_write(ring, upper_32_bits(wd->reg));
+	amdgpu_ring_write(ring, wd->val);
+}
+
+
 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 {
 	switch (adev->asic_type) {
@@ -5340,6 +5358,8 @@ static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
 					  uint32_t gws_base, uint32_t gws_size,
 					  uint32_t oa_base, uint32_t oa_size)
 {
+	struct gfx8_write_data wd;
+
 	gds_base = gds_base >> AMDGPU_GDS_SHIFT;
 	gds_size = gds_size >> AMDGPU_GDS_SHIFT;
 
@@ -5350,36 +5370,32 @@ static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
 	oa_size = oa_size >> AMDGPU_OA_SHIFT;
 
 	/* GDS Base */
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-				WRITE_DATA_DST_SEL(0)));
-	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, gds_base);
+	wd.n = 3;
+	wd.control = WRITE_DATA_ENGINE_SEL(0) |	WRITE_DATA_DST_SEL(0);
+	wd.reg = amdgpu_gds_reg_offset[vmid].mem_base;
+	wd.val = gds_base;
+	gfx_v8_0_ring_write_data(ring, &wd);
 
 	/* GDS Size */
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-				WRITE_DATA_DST_SEL(0)));
-	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, gds_size);
+	wd.n = 3;
+	wd.control = WRITE_DATA_ENGINE_SEL(0) |	WRITE_DATA_DST_SEL(0);
+	wd.reg = amdgpu_gds_reg_offset[vmid].mem_size;
+	wd.val = gds_size;
+	gfx_v8_0_ring_write_data(ring, &wd);
 
 	/* GWS */
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-				WRITE_DATA_DST_SEL(0)));
-	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
+	wd.n = 3;
+	wd.control = WRITE_DATA_ENGINE_SEL(0) |	WRITE_DATA_DST_SEL(0);
+	wd.reg = amdgpu_gds_reg_offset[vmid].gws;
+	wd.val = gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base;
+	gfx_v8_0_ring_write_data(ring, &wd);
 
 	/* OA */
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-				WRITE_DATA_DST_SEL(0)));
-	amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
+	wd.n = 3;
+	wd.control = WRITE_DATA_ENGINE_SEL(0) |	WRITE_DATA_DST_SEL(0);
+	wd.reg = amdgpu_gds_reg_offset[vmid].oa;
+	wd.val = (1 << (oa_size + oa_base)) - (1 << oa_base);
+	gfx_v8_0_ring_write_data(ring, &wd);
 }
 
 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
@@ -6233,14 +6249,14 @@ static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
 
 static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 {
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-				 WRITE_DATA_DST_SEL(0) |
-				 WR_CONFIRM));
-	amdgpu_ring_write(ring, mmHDP_DEBUG0);
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, 1);
-
+	struct gfx8_write_data wd = {
+		.n = 3,
+		.control = WRITE_DATA_ENGINE_SEL(0) | WRITE_DATA_DST_SEL(0) |
+			WR_CONFIRM,
+		.reg = mmHDP_DEBUG0,
+		.val = 1
+	};
+	gfx_v8_0_ring_write_data(ring, &wd);
 }
 
 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
@@ -6332,29 +6348,24 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 					uint64_t pd_addr)
 {
 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+	struct gfx8_write_data wd;
 
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
-				 WRITE_DATA_DST_SEL(0)) |
-				 WR_CONFIRM);
-	if (vmid < 8) {
-		amdgpu_ring_write(ring,
-				  (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
-	} else {
-		amdgpu_ring_write(ring,
-				  (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
-	}
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, pd_addr >> 12);
+	wd.n = 3;
+	wd.control = WRITE_DATA_ENGINE_SEL(usepfp) | WRITE_DATA_DST_SEL(0) |
+		WR_CONFIRM;
+	wd.reg = vmid < 8 ? mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid :
+		mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid;
+	wd.val = pd_addr >> 12;
+	gfx_v8_0_ring_write_data(ring, &wd);
 
 	/* bits 0-15 are the VM contexts0-15 */
 	/* invalidate the cache */
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-				 WRITE_DATA_DST_SEL(0)));
-	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, 1 << vmid);
+	wd.n = 3;
+	wd.control = WRITE_DATA_ENGINE_SEL(usepfp) | WRITE_DATA_DST_SEL(0) |
+		WR_CONFIRM;
+	wd.reg = mmVM_INVALIDATE_REQUEST;
+	wd.val = 1 << vmid;
+	gfx_v8_0_ring_write_data(ring, &wd);
 
 	/* wait for the invalidate to complete */
 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
@@ -6501,7 +6512,8 @@ static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
 				 EOP_TC_WB_ACTION_EN |
 				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
 				 EVENT_INDEX(5)));
-	amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
+	amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) |
+			  INT_SEL(int_sel ? 2 : 0));
 	amdgpu_ring_write(ring, addr & 0xfffffffc);
 	amdgpu_ring_write(ring, upper_32_bits(addr));
 	amdgpu_ring_write(ring, lower_32_bits(seq));
@@ -6511,25 +6523,26 @@ static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
 static void gfx_v8_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
 					 u64 seq, unsigned int flags)
 {
+	struct gfx8_write_data wd;
 	/* we only allocate 32bit for each seq wb address */
 	BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 
 	/* write fence seq to the "addr" */
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-				 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
-	amdgpu_ring_write(ring, lower_32_bits(addr));
-	amdgpu_ring_write(ring, upper_32_bits(addr));
-	amdgpu_ring_write(ring, lower_32_bits(seq));
+	wd.n = 3;
+	wd.control = WRITE_DATA_ENGINE_SEL(0) | WRITE_DATA_DST_SEL(5) |
+		WR_CONFIRM;
+	wd.reg = addr;
+	wd.val = lower_32_bits(seq);
+	gfx_v8_0_ring_write_data(ring, &wd);
 
 	if (flags & AMDGPU_FENCE_FLAG_INT) {
 		/* set register to trigger INT */
-		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
-		amdgpu_ring_write(ring, mmCPC_INT_STATUS);
-		amdgpu_ring_write(ring, 0);
-		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
+		wd.n = 3;
+		wd.control = WRITE_DATA_ENGINE_SEL(0) | WRITE_DATA_DST_SEL(0) |
+			WR_CONFIRM;
+		wd.reg = mmCPC_INT_STATUS;
+		wd.val = 0X20000000;
+		gfx_v8_0_ring_write_data(ring, &wd);
 	}
 }
 
@@ -6618,11 +6631,13 @@ static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
 static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
 				  uint32_t val)
 {
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
-	amdgpu_ring_write(ring, reg);
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, val);
+	struct gfx8_write_data wd = {
+	.n = 3,
+	.control = 1 << 16,
+	.reg = reg,
+	.val = val
+	};
+	gfx_v8_0_ring_write_data(ring, &wd);
 }
 
 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
-- 
2.14.1


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Re: [PATCH 14/21] drm/amdgpu: add new amdgpu_gmc_emit_flush_gpu_tlb callback

[Christian König]

Am 18.01.2018 um 08:08 schrieb Chunming Zhou:
>
>
> On 2018年01月17日 20:19, Christian König wrote:
>> Am 17.01.2018 um 07:24 schrieb Chunming Zhou:
>>> I'm not sure if this is a good ongoing, as I know, our per IP 
>>> topology is intended for every generation asic bringup.
>>
>> Actually the intention goes beyond that, e.g. we want to reuse IPs 
>> for newer ASICs as well when they haven't changed.
>>
>>>
>>> I think there are many similar logics which we can abstract, but we 
>>> don't do that.
>>>
>>> For emit_wreg above patches, they only can be used by vm flush part, 
>>> but they are common func fallback.
>>>
>>> Can we only make emit_wreg as static in their files, and replace 
>>> every where they are used?
>>
>> Not sure what you are suggesting here?
> my mean is like the attached, only abstract them in file per ip.

That is not a good idea. The functions should be independent from the 
hardware version.

Additional to that we want to avoid using structures for ring buffer 
content.

Regards,
Christian.

>
>
> Regards,
> David Zhou
>>
>> Regards,
>> Christian.
>>
>>>
>>> Regards,
>>> David Zhou
>>> On 2018年01月17日 03:40, Christian König wrote:
>>>> Add a new GMC function to unify vm flushing.
>>>>
>>>> Signed-off-by: Christian König <christian.koenig@amd.com>
>>>> ---
>>>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 1 +
>>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 +++
>>>>   2 files changed, 4 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>> index 93eae393b08d..230826718c98 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>> @@ -1779,6 +1779,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring 
>>>> *ring)
>>>>   #define amdgpu_asic_flush_hdp(adev) 
>>>> (adev)->asic_funcs->flush_hdp((adev))
>>>>   #define amdgpu_asic_invalidate_hdp(adev) 
>>>> (adev)->asic_funcs->invalidate_hdp((adev))
>>>>   #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) 
>>>> (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
>>>> +#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, pasid, addr) 
>>>> (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (pasid), 
>>>> (addr))
>>>>   #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) 
>>>> (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), 
>>>> (flags))
>>>>   #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) 
>>>> (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
>>>>   #define amdgpu_gmc_get_pte_flags(adev, flags) 
>>>> (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>>>> index a4a8374f7f3f..114350a4693f 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>>>> @@ -52,6 +52,9 @@ struct amdgpu_gmc_funcs {
>>>>       /* flush the vm tlb via mmio */
>>>>       void (*flush_gpu_tlb)(struct amdgpu_device *adev,
>>>>                     uint32_t vmid);
>>>> +    /* flush the vm tlb via ring */
>>>> +    uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, 
>>>> unsigned vmid,
>>>> +                       unsigned pasid, uint64_t pd_addr);
>>>>       /* write pte/pde updates using the cpu */
>>>>       int (*set_pte_pde)(struct amdgpu_device *adev,
>>>>                  void *cpu_pt_addr, /* cpu addr of page table */
>>>
>>
>

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[PATCH 10/21] drm/amdgpu: wire up emit_wreg for UVD v6

[Christian König]

Needed for vm_flush unification.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index c6e22eff89e7..b48b843c66ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1059,6 +1059,17 @@ static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
 	amdgpu_ring_write(ring, ib->length_dw);
 }
 
+static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
+				    uint32_t reg, uint32_t val)
+{
+	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
+	amdgpu_ring_write(ring, reg << 2);
+	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
+	amdgpu_ring_write(ring, val);
+	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
+	amdgpu_ring_write(ring, 0x8);
+}
+
 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 					unsigned vmid, unsigned pasid,
 					uint64_t pd_addr)
@@ -1595,6 +1606,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
 	.pad_ib = amdgpu_ring_generic_pad_ib,
 	.begin_use = amdgpu_uvd_ring_begin_use,
 	.end_use = amdgpu_uvd_ring_end_use,
+	.emit_wreg = uvd_v6_0_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
-- 
2.14.1

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