Re: [PATCH 13/44] drm/amdgpu/vcn1.0: convert internal functions to use vcn_inst

[Boyuan Zhang <Boyuan.Zhang@amd.com>]

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On 2025-01-31 11:57, Alex Deucher wrote:
> Pass the vcn instance structure to these functions rather
> than adev and the instance number.
>
> TODO: clean up the function internals to use the vinst state
> directly rather than accessing it indirectly via adev->vcn.inst[].
>
> Signed-off-by: Alex Deucher<alexander.deucher@amd.com>


Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> 
<mailto:Boyuan.Zhang@amd.com>


> ---
>   drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 85 ++++++++++++++++-----------
>   1 file changed, 51 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index f74767843e85d..613f17be9d829 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -81,7 +81,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_1_0[] = {
>   	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
>   };
>   
> -static int vcn_v1_0_stop(struct amdgpu_device *adev);
> +static int vcn_v1_0_stop(struct amdgpu_vcn_inst *vinst);
>   static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
>   static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
>   static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
> @@ -339,12 +339,13 @@ static int vcn_v1_0_resume(struct amdgpu_ip_block *ip_block)
>   /**
>    * vcn_v1_0_mc_resume_spg_mode - memory controller programming
>    *
> - * @adev: amdgpu_device pointer
> + * @vinst: VCN instance
>    *
>    * Let the VCN memory controller know it's offsets
>    */
> -static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
> +static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_vcn_inst *vinst)
>   {
> +	struct amdgpu_device *adev = vinst->adev;
>   	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
>   	uint32_t offset;
>   
> @@ -410,8 +411,9 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
>   			adev->gfx.config.gb_addr_config);
>   }
>   
> -static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
> +static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst)
>   {
> +	struct amdgpu_device *adev = vinst->adev;
>   	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
>   	uint32_t offset;
>   
> @@ -485,12 +487,13 @@ static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
>   /**
>    * vcn_v1_0_disable_clock_gating - disable VCN clock gating
>    *
> - * @adev: amdgpu_device pointer
> + * @vinst: VCN instance
>    *
>    * Disable clock gating for VCN block
>    */
> -static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
> +static void vcn_v1_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst)
>   {
> +	struct amdgpu_device *adev = vinst->adev;
>   	uint32_t data;
>   
>   	/* JPEG disable CGC */
> @@ -615,8 +618,9 @@ static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
>    *
>    * Enable clock gating for VCN block
>    */
> -static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
> +static void vcn_v1_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst)
>   {
> +	struct amdgpu_device *adev = vinst->adev;
>   	uint32_t data = 0;
>   
>   	/* enable JPEG CGC */
> @@ -680,8 +684,10 @@ static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
>   	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
>   }
>   
> -static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
> +static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,
> +					   uint8_t sram_sel)
>   {
> +	struct amdgpu_device *adev = vinst->adev;
>   	uint32_t reg_data = 0;
>   
>   	/* disable JPEG CGC */
> @@ -734,8 +740,9 @@ static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t s
>   	WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
>   }
>   
> -static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
> +static void vcn_1_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)
>   {
> +	struct amdgpu_device *adev = vinst->adev;
>   	uint32_t data = 0;
>   
>   	if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
> @@ -779,8 +786,9 @@ static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
>   	WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
>   }
>   
> -static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
> +static void vcn_1_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)
>   {
> +	struct amdgpu_device *adev = vinst->adev;
>   	uint32_t data = 0;
>   
>   	if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
> @@ -823,12 +831,13 @@ static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
>   /**
>    * vcn_v1_0_start_spg_mode - start VCN block
>    *
> - * @adev: amdgpu_device pointer
> + * @vinst: VCN instance
>    *
>    * Setup and start the VCN block
>    */
> -static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
> +static int vcn_v1_0_start_spg_mode(struct amdgpu_vcn_inst *vinst)
>   {
> +	struct amdgpu_device *adev = vinst->adev;
>   	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
>   	uint32_t rb_bufsz, tmp;
>   	uint32_t lmi_swap_cntl;
> @@ -837,13 +846,13 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
>   	/* disable byte swapping */
>   	lmi_swap_cntl = 0;
>   
> -	vcn_1_0_disable_static_power_gating(adev);
> +	vcn_1_0_disable_static_power_gating(vinst);
>   
>   	tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
>   	WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
>   
>   	/* disable clock gating */
> -	vcn_v1_0_disable_clock_gating(adev);
> +	vcn_v1_0_disable_clock_gating(vinst);
>   
>   	/* disable interupt */
>   	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
> @@ -885,7 +894,7 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
>   		(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
>   		(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
>   
> -	vcn_v1_0_mc_resume_spg_mode(adev);
> +	vcn_v1_0_mc_resume_spg_mode(vinst);
>   
>   	WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10);
>   	WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0,
> @@ -1001,8 +1010,9 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
>   	return 0;
>   }
>   
> -static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
> +static int vcn_v1_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst)
>   {
> +	struct amdgpu_device *adev = vinst->adev;
>   	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
>   	uint32_t rb_bufsz, tmp;
>   	uint32_t lmi_swap_cntl;
> @@ -1010,7 +1020,7 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
>   	/* disable byte swapping */
>   	lmi_swap_cntl = 0;
>   
> -	vcn_1_0_enable_static_power_gating(adev);
> +	vcn_1_0_enable_static_power_gating(vinst);
>   
>   	/* enable dynamic power gating mode */
>   	tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
> @@ -1019,7 +1029,7 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
>   	WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
>   
>   	/* enable clock gating */
> -	vcn_v1_0_clock_gating_dpg_mode(adev, 0);
> +	vcn_v1_0_clock_gating_dpg_mode(vinst, 0);
>   
>   	/* enable VCPU clock */
>   	tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
> @@ -1068,7 +1078,7 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
>   		 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
>   		 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
>   
> -	vcn_v1_0_mc_resume_dpg_mode(adev);
> +	vcn_v1_0_mc_resume_dpg_mode(vinst);
>   
>   	WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
>   	WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
> @@ -1085,7 +1095,7 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
>   	WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
>   			UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
>   
> -	vcn_v1_0_clock_gating_dpg_mode(adev, 1);
> +	vcn_v1_0_clock_gating_dpg_mode(vinst, 1);
>   	/* setup mmUVD_LMI_CTRL */
>   	WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
>   		(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
> @@ -1145,21 +1155,24 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
>   	return 0;
>   }
>   
> -static int vcn_v1_0_start(struct amdgpu_device *adev)
> +static int vcn_v1_0_start(struct amdgpu_vcn_inst *vinst)
>   {
> +	struct amdgpu_device *adev = vinst->adev;
> +
>   	return (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ?
> -		vcn_v1_0_start_dpg_mode(adev) : vcn_v1_0_start_spg_mode(adev);
> +		vcn_v1_0_start_dpg_mode(vinst) : vcn_v1_0_start_spg_mode(vinst);
>   }
>   
>   /**
>    * vcn_v1_0_stop_spg_mode - stop VCN block
>    *
> - * @adev: amdgpu_device pointer
> + * @vinst: VCN instance
>    *
>    * stop the VCN block
>    */
> -static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
> +static int vcn_v1_0_stop_spg_mode(struct amdgpu_vcn_inst *vinst)
>   {
> +	struct amdgpu_device *adev = vinst->adev;
>   	int tmp;
>   
>   	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
> @@ -1199,13 +1212,14 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
>   
>   	WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
>   
> -	vcn_v1_0_enable_clock_gating(adev);
> -	vcn_1_0_enable_static_power_gating(adev);
> +	vcn_v1_0_enable_clock_gating(vinst);
> +	vcn_1_0_enable_static_power_gating(vinst);
>   	return 0;
>   }
>   
> -static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
> +static int vcn_v1_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
>   {
> +	struct amdgpu_device *adev = vinst->adev;
>   	uint32_t tmp;
>   
>   	/* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
> @@ -1237,14 +1251,15 @@ static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
>   	return 0;
>   }
>   
> -static int vcn_v1_0_stop(struct amdgpu_device *adev)
> +static int vcn_v1_0_stop(struct amdgpu_vcn_inst *vinst)
>   {
> +	struct amdgpu_device *adev = vinst->adev;
>   	int r;
>   
>   	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
> -		r = vcn_v1_0_stop_dpg_mode(adev);
> +		r = vcn_v1_0_stop_dpg_mode(vinst);
>   	else
> -		r = vcn_v1_0_stop_spg_mode(adev);
> +		r = vcn_v1_0_stop_spg_mode(vinst);
>   
>   	return r;
>   }
> @@ -1399,16 +1414,17 @@ static int vcn_v1_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
>   					  enum amd_clockgating_state state)
>   {
>   	struct amdgpu_device *adev = ip_block->adev;
> +	struct amdgpu_vcn_inst *vinst = adev->vcn.inst;
>   	bool enable = (state == AMD_CG_STATE_GATE);
>   
>   	if (enable) {
>   		/* wait for STATUS to clear */
>   		if (!vcn_v1_0_is_idle(adev))
>   			return -EBUSY;
> -		vcn_v1_0_enable_clock_gating(adev);
> +		vcn_v1_0_enable_clock_gating(vinst);
>   	} else {
>   		/* disable HW gating and enable Sw gating */
> -		vcn_v1_0_disable_clock_gating(adev);
> +		vcn_v1_0_disable_clock_gating(vinst);
>   	}
>   	return 0;
>   }
> @@ -1812,14 +1828,15 @@ static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
>   	 */
>   	int ret;
>   	struct amdgpu_device *adev = ip_block->adev;
> +	struct amdgpu_vcn_inst *vinst = adev->vcn.inst;
>   
>   	if (state == adev->vcn.inst[0].cur_state)
>   		return 0;
>   
>   	if (state == AMD_PG_STATE_GATE)
> -		ret = vcn_v1_0_stop(adev);
> +		ret = vcn_v1_0_stop(vinst);
>   	else
> -		ret = vcn_v1_0_start(adev);
> +		ret = vcn_v1_0_start(vinst);
>   
>   	if (!ret)
>   		adev->vcn.inst[0].cur_state = state;

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