From: Boyuan Zhang <Boyuan.Zhang@amd.com>
To: Alex Deucher <alexander.deucher@amd.com>, amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 16/44] drm/amdgpu/vcn4.0: convert internal functions to use vcn_inst
Date: Wed, 5 Feb 2025 10:03:00 -0500 [thread overview]
Message-ID: <844bb7b6-4fc2-4057-995c-7133a599816e@amd.com> (raw)
In-Reply-To: <20250131165741.1798488-17-alexander.deucher@amd.com>
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On 2025-01-31 11:57, Alex Deucher wrote:
> Pass the vcn instance structure to these functions rather
> than adev and the instance number.
>
> TODO: clean up the function internals to use the vinst state
> directly rather than accessing it indirectly via adev->vcn.inst[].
>
> Signed-off-by: Alex Deucher<alexander.deucher@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
<mailto:Boyuan.Zhang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 116 +++++++++++++++-----------
> 1 file changed, 67 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index 1200815b3eee8..3d70e2cc81982 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -449,13 +449,14 @@ static int vcn_v4_0_resume(struct amdgpu_ip_block *ip_block)
> /**
> * vcn_v4_0_mc_resume - memory controller programming
> *
> - * @adev: amdgpu_device pointer
> - * @inst: instance number
> + * @vinst: VCN instance
> *
> * Let the VCN memory controller know it's offsets
> */
> -static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst)
> +static void vcn_v4_0_mc_resume(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst = vinst->inst;
> uint32_t offset, size;
> const struct common_firmware_header *hdr;
>
> @@ -509,14 +510,16 @@ static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst)
> /**
> * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode
> *
> - * @adev: amdgpu_device pointer
> - * @inst_idx: instance number index
> + * @vinst: VCN instance
> * @indirect: indirectly write sram
> *
> * Let the VCN memory controller know it's offsets with dpg mode
> */
> -static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
> +static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,
> + bool indirect)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst_idx = vinst->inst;
> uint32_t offset, size;
> const struct common_firmware_header *hdr;
> hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
> @@ -616,13 +619,14 @@ static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
> /**
> * vcn_v4_0_disable_static_power_gating - disable VCN static power gating
> *
> - * @adev: amdgpu_device pointer
> - * @inst: instance number
> + * @vinst: VCN instance
> *
> * Disable static power gating for VCN block
> */
> -static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
> +static void vcn_v4_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst = vinst->inst;
> uint32_t data = 0;
>
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
> @@ -681,13 +685,14 @@ static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int
> /**
> * vcn_v4_0_enable_static_power_gating - enable VCN static power gating
> *
> - * @adev: amdgpu_device pointer
> - * @inst: instance number
> + * @vinst: VCN instance
> *
> * Enable static power gating for VCN block
> */
> -static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
> +static void vcn_v4_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst = vinst->inst;
> uint32_t data;
>
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
> @@ -736,13 +741,14 @@ static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int
> /**
> * vcn_v4_0_disable_clock_gating - disable VCN clock gating
> *
> - * @adev: amdgpu_device pointer
> - * @inst: instance number
> + * @vinst: VCN instance
> *
> * Disable clock gating for VCN block
> */
> -static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
> +static void vcn_v4_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst = vinst->inst;
> uint32_t data;
>
> if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
> @@ -847,16 +853,18 @@ static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
> /**
> * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
> *
> - * @adev: amdgpu_device pointer
> + * @vinst: VCN instance
> * @sram_sel: sram select
> - * @inst_idx: instance number index
> * @indirect: indirectly write sram
> *
> * Disable clock gating for VCN block with dpg mode
> */
> -static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,
> - int inst_idx, uint8_t indirect)
> +static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,
> + uint8_t sram_sel,
> + uint8_t indirect)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst_idx = vinst->inst;
> uint32_t reg_data = 0;
>
> if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
> @@ -904,13 +912,14 @@ static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, u
> /**
> * vcn_v4_0_enable_clock_gating - enable VCN clock gating
> *
> - * @adev: amdgpu_device pointer
> - * @inst: instance number
> + * @vinst: VCN instance
> *
> * Enable clock gating for VCN block
> */
> -static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
> +static void vcn_v4_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst = vinst->inst;
> uint32_t data;
>
> if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
> @@ -960,9 +969,11 @@ static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
> WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
> }
>
> -static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx,
> +static void vcn_v4_0_enable_ras(struct amdgpu_vcn_inst *vinst,
> bool indirect)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst_idx = vinst->inst;
> uint32_t tmp;
>
> if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
> @@ -985,14 +996,15 @@ static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx,
> /**
> * vcn_v4_0_start_dpg_mode - VCN start with dpg mode
> *
> - * @adev: amdgpu_device pointer
> - * @inst_idx: instance number index
> + * @vinst: VCN instance
> * @indirect: indirectly write sram
> *
> * Start VCN block with dpg mode
> */
> -static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
> +static int vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst_idx = vinst->inst;
> volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
> struct amdgpu_ring *ring;
> uint32_t tmp;
> @@ -1010,7 +1022,7 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
> adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
>
> /* enable clock gating */
> - vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
> + vcn_v4_0_disable_clock_gating_dpg_mode(vinst, 0, indirect);
>
> /* enable VCPU clock */
> tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
> @@ -1058,7 +1070,7 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
>
> - vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect);
> + vcn_v4_0_mc_resume_dpg_mode(vinst, indirect);
>
> tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
> @@ -1070,7 +1082,7 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
> WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
> VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
>
> - vcn_v4_0_enable_ras(adev, inst_idx, indirect);
> + vcn_v4_0_enable_ras(vinst, indirect);
>
> /* enable master interrupt */
> WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
> @@ -1114,13 +1126,14 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
> /**
> * vcn_v4_0_start - VCN start
> *
> - * @adev: amdgpu_device pointer
> - * @i: instance to start
> + * @vinst: VCN instance
> *
> * Start VCN block
> */
> -static int vcn_v4_0_start(struct amdgpu_device *adev, int i)
> +static int vcn_v4_0_start(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int i = vinst->inst;
> volatile struct amdgpu_vcn4_fw_shared *fw_shared;
> struct amdgpu_ring *ring;
> uint32_t tmp;
> @@ -1135,17 +1148,17 @@ static int vcn_v4_0_start(struct amdgpu_device *adev, int i)
> fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
>
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
> - return vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.inst[i].indirect_sram);
> + return vcn_v4_0_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);
>
> /* disable VCN power gating */
> - vcn_v4_0_disable_static_power_gating(adev, i);
> + vcn_v4_0_disable_static_power_gating(vinst);
>
> /* set VCN status busy */
> tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
> WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
>
> /*SW clock gating */
> - vcn_v4_0_disable_clock_gating(adev, i);
> + vcn_v4_0_disable_clock_gating(vinst);
>
> /* enable VCPU clock */
> WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
> @@ -1198,7 +1211,7 @@ static int vcn_v4_0_start(struct amdgpu_device *adev, int i)
> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
>
> - vcn_v4_0_mc_resume(adev, i);
> + vcn_v4_0_mc_resume(vinst);
>
> /* VCN global tiling registers */
> WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
> @@ -1541,13 +1554,14 @@ static int vcn_v4_0_start_sriov(struct amdgpu_device *adev)
> /**
> * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode
> *
> - * @adev: amdgpu_device pointer
> - * @inst_idx: instance number index
> + * @vinst: VCN instance
> *
> * Stop VCN block with dpg mode
> */
> -static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
> +static void vcn_v4_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int inst_idx = vinst->inst;
> struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
> uint32_t tmp;
>
> @@ -1571,13 +1585,14 @@ static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
> /**
> * vcn_v4_0_stop - VCN stop
> *
> - * @adev: amdgpu_device pointer
> - * @i: instance to stop
> + * @vinst: VCN instance
> *
> * Stop VCN block
> */
> -static int vcn_v4_0_stop(struct amdgpu_device *adev, int i)
> +static int vcn_v4_0_stop(struct amdgpu_vcn_inst *vinst)
> {
> + struct amdgpu_device *adev = vinst->adev;
> + int i = vinst->inst;
> volatile struct amdgpu_vcn4_fw_shared *fw_shared;
> uint32_t tmp;
> int r = 0;
> @@ -1589,7 +1604,7 @@ static int vcn_v4_0_stop(struct amdgpu_device *adev, int i)
> fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
>
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
> - vcn_v4_0_stop_dpg_mode(adev, i);
> + vcn_v4_0_stop_dpg_mode(vinst);
> return 0;
> }
>
> @@ -1642,10 +1657,10 @@ static int vcn_v4_0_stop(struct amdgpu_device *adev, int i)
> WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
>
> /* apply HW clock gating */
> - vcn_v4_0_enable_clock_gating(adev, i);
> + vcn_v4_0_enable_clock_gating(vinst);
>
> /* enable VCN power gating */
> - vcn_v4_0_enable_static_power_gating(adev, i);
> + vcn_v4_0_enable_static_power_gating(vinst);
>
> if (adev->pm.dpm_enabled)
> amdgpu_dpm_enable_vcn(adev, false, i);
> @@ -2044,15 +2059,17 @@ static int vcn_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> int i;
>
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
> +
> if (adev->vcn.harvest_config & (1 << i))
> continue;
>
> if (enable) {
> if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
> return -EBUSY;
> - vcn_v4_0_enable_clock_gating(adev, i);
> + vcn_v4_0_enable_clock_gating(vinst);
> } else {
> - vcn_v4_0_disable_clock_gating(adev, i);
> + vcn_v4_0_disable_clock_gating(vinst);
> }
> }
>
> @@ -2064,6 +2081,7 @@ static int vcn_v4_0_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
> int i)
> {
> struct amdgpu_device *adev = ip_block->adev;
> + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
> int ret = 0;
>
> /* for SRIOV, guest should not control VCN Power-gating
> @@ -2079,9 +2097,9 @@ static int vcn_v4_0_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
> return 0;
>
> if (state == AMD_PG_STATE_GATE)
> - ret = vcn_v4_0_stop(adev, i);
> + ret = vcn_v4_0_stop(vinst);
> else
> - ret = vcn_v4_0_start(adev, i);
> + ret = vcn_v4_0_start(vinst);
>
> if (!ret)
> adev->vcn.inst[i].cur_state = state;
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next prev parent reply other threads:[~2025-02-05 15:04 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-31 16:56 [PATCH V3 00/44] VCN instance rework Alex Deucher
2025-01-31 16:56 ` [PATCH 01/44] drm/amdgpu/vcn2.5: split code along instances Alex Deucher
2025-02-04 15:35 ` Boyuan Zhang
2025-01-31 16:56 ` [PATCH 02/44] drm/amdgpu/vcn3.0: " Alex Deucher
2025-02-04 15:40 ` Boyuan Zhang
2025-01-31 16:56 ` [PATCH 03/44] drm/amdgpu/vcn4.0: " Alex Deucher
2025-02-04 15:50 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 04/44] drm/amdgpu/vcn4.0.3: " Alex Deucher
2025-02-04 15:50 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 05/44] drm/amdgpu/vcn4.0.5: " Alex Deucher
2025-02-04 15:51 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 06/44] drm/amdgpu/vcn5.0.0: " Alex Deucher
2025-02-04 15:56 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 07/44] drm/amdgpu/vcn5.0.1: " Alex Deucher
2025-02-04 15:57 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 08/44] drm/amdgpu/vcn: switch work handler to be per instance Alex Deucher
2025-02-04 20:59 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 09/44] drm/amdgpu/vcn: make powergating status " Alex Deucher
2025-02-05 1:50 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 10/44] drm/amdgpu/vcn: move more instanced data to vcn_instance Alex Deucher
2025-02-05 3:06 ` Boyuan Zhang
2025-02-05 20:09 ` Alex Deucher
2025-02-06 13:39 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 11/44] drm/amdgpu/vcn: switch vcn helpers to be instance based Alex Deucher
2025-02-05 13:23 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 12/44] drm/amdgpu/vcn3.0: convert internal functions to use vcn_inst Alex Deucher
2025-02-05 15:00 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 13/44] drm/amdgpu/vcn1.0: " Alex Deucher
2025-02-05 15:01 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 14/44] drm/amdgpu/vcn2.0: " Alex Deucher
2025-02-05 15:01 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 15/44] drm/amdgpu/vcn2.5: " Alex Deucher
2025-02-05 15:02 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 16/44] drm/amdgpu/vcn4.0: " Alex Deucher
2025-02-05 15:03 ` Boyuan Zhang [this message]
2025-01-31 16:57 ` [PATCH 17/44] drm/amdgpu/vcn4.0.3: " Alex Deucher
2025-02-05 15:03 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 18/44] drm/amdgpu/vcn4.0.5: " Alex Deucher
2025-02-05 15:04 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 19/44] drm/amdgpu/vcn5.0.0: " Alex Deucher
2025-02-05 15:05 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 20/44] drm/amdgpu/vcn5.0.1: " Alex Deucher
2025-02-05 15:05 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 21/44] drm/amdgpu/vcn: adjust pause_dpg_mode function signature Alex Deucher
2025-02-06 13:40 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 22/44] drm/amdgpu/vcn: add new per instance callback for powergating Alex Deucher
2025-02-06 13:40 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 23/44] drm/amdgpu/vcn1.0: add set_pg_state callback Alex Deucher
2025-02-06 13:46 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 24/44] drm/amdgpu/vcn2.0: " Alex Deucher
2025-01-31 16:57 ` [PATCH 25/44] drm/amdgpu/vcn2.5: " Alex Deucher
2025-01-31 16:57 ` [PATCH 26/44] drm/amdgpu/vcn3.0: " Alex Deucher
2025-01-31 16:57 ` [PATCH 27/44] drm/amdgpu/vcn4.0: " Alex Deucher
2025-01-31 16:57 ` [PATCH 28/44] drm/amdgpu/vcn4.0.3: " Alex Deucher
2025-01-31 16:57 ` [PATCH 29/44] drm/amdgpu/vcn4.0.5: " Alex Deucher
2025-01-31 16:57 ` [PATCH 30/44] drm/amdgpu/vcn5.0.0: " Alex Deucher
2025-01-31 16:57 ` [PATCH 31/44] drm/amdgpu/vcn5.0.1: " Alex Deucher
2025-01-31 16:57 ` [PATCH 32/44] drm/amdgpu/vcn: use per instance callbacks for idle work handler Alex Deucher
2025-02-06 13:53 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 33/44] drm/amdgpu/vcn: add a generic helper for set_power_gating_state Alex Deucher
2025-02-06 13:54 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 34/44] drm/amdgpu/vcn1.0: use generic set_power_gating_state helper Alex Deucher
2025-01-31 16:57 ` [PATCH 35/44] drm/amdgpu/vcn2.0: " Alex Deucher
2025-01-31 16:57 ` [PATCH 36/44] drm/amdgpu/vcn2.5: " Alex Deucher
2025-01-31 16:57 ` [PATCH 37/44] drm/amdgpu/vcn3.0: " Alex Deucher
2025-01-31 16:57 ` [PATCH 38/44] drm/amdgpu/vcn4.0: " Alex Deucher
2025-01-31 16:57 ` [PATCH 39/44] drm/amdgpu/vcn4.0.3: " Alex Deucher
2025-01-31 16:57 ` [PATCH 40/44] drm/amdgpu/vcn4.0.5: " Alex Deucher
2025-01-31 16:57 ` [PATCH 41/44] drm/amdgpu/vcn5.0.0: " Alex Deucher
2025-01-31 16:57 ` [PATCH 42/44] drm/amdgpu/vcn5.0.1: " Alex Deucher
2025-01-31 16:57 ` [PATCH 43/44] drm/amdgpu/vcn: optimize firmware storage Alex Deucher
2025-02-06 14:48 ` Boyuan Zhang
2025-01-31 16:57 ` [PATCH 44/44] drm/amdgpu/vcn: use dev_info() for firmware information Alex Deucher
2025-02-06 14:49 ` Boyuan Zhang
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