[PATCH 1/3] drm/amd/amdgpu: Move UVD TRAP after amdgpu_uvd_sw_init

[PATCH 1/3] drm/amd/amdgpu: Move UVD TRAP after amdgpu_uvd_sw_init

[James Zhu]

Signed-off-by: James Zhu <James.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index c6e22ef..612455d 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -393,6 +393,10 @@ static int uvd_v6_0_sw_init(void *handle)
 	int i, r;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+	r = amdgpu_uvd_sw_init(adev);
+	if (r)
+		return r;
+
 	/* UVD TRAP */
 	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
 	if (r)
@@ -407,10 +411,6 @@ static int uvd_v6_0_sw_init(void *handle)
 		}
 	}
 
-	r = amdgpu_uvd_sw_init(adev);
-	if (r)
-		return r;
-
 	if (uvd_v6_0_enc_support(adev)) {
 		struct drm_sched_rq *rq;
 		ring = &adev->uvd.ring_enc[0];
-- 
2.7.4

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[PATCH 2/3] drm/amd/amdgpu: Replace uvd_v6_0_enc_support with uvd.num_enc_rings after uvd_v6_0_early_init

[James Zhu]

Signed-off-by: James Zhu <James.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 55 +++++++++++++++--------------------
 1 file changed, 23 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 612455d..319d4b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -402,17 +402,16 @@ static int uvd_v6_0_sw_init(void *handle)
 	if (r)
 		return r;
 
-	/* UVD ENC TRAP */
-	if (uvd_v6_0_enc_support(adev)) {
+	if (adev->uvd.num_enc_rings) {
+		struct drm_sched_rq *rq;
+
+		/* UVD ENC TRAP */
 		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 			r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 119, &adev->uvd.irq);
 			if (r)
 				return r;
 		}
-	}
 
-	if (uvd_v6_0_enc_support(adev)) {
-		struct drm_sched_rq *rq;
 		ring = &adev->uvd.ring_enc[0];
 		rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 		r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
@@ -433,14 +432,12 @@ static int uvd_v6_0_sw_init(void *handle)
 	if (r)
 		return r;
 
-	if (uvd_v6_0_enc_support(adev)) {
-		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-			ring = &adev->uvd.ring_enc[i];
-			sprintf(ring->name, "uvd_enc%d", i);
-			r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
-			if (r)
-				return r;
-		}
+	for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+		ring = &adev->uvd.ring_enc[i];
+		sprintf(ring->name, "uvd_enc%d", i);
+		r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
+		if (r)
+			return r;
 	}
 
 	return r;
@@ -455,7 +452,7 @@ static int uvd_v6_0_sw_fini(void *handle)
 	if (r)
 		return r;
 
-	if (uvd_v6_0_enc_support(adev)) {
+	if (adev->uvd.num_enc_rings) {
 		drm_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
 
 		for (i = 0; i < adev->uvd.num_enc_rings; ++i)
@@ -517,21 +514,19 @@ static int uvd_v6_0_hw_init(void *handle)
 
 	amdgpu_ring_commit(ring);
 
-	if (uvd_v6_0_enc_support(adev)) {
-		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-			ring = &adev->uvd.ring_enc[i];
-			ring->ready = true;
-			r = amdgpu_ring_test_ring(ring);
-			if (r) {
-				ring->ready = false;
-				goto done;
-			}
+	for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+		ring = &adev->uvd.ring_enc[i];
+		ring->ready = true;
+		r = amdgpu_ring_test_ring(ring);
+		if (r) {
+			ring->ready = false;
+			goto done;
 		}
 	}
 
 done:
 	if (!r) {
-		if (uvd_v6_0_enc_support(adev))
+		if (adev->uvd.num_enc_rings)
 			DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 		else
 			DRM_INFO("UVD initialized successfully.\n");
@@ -852,7 +847,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
 
 	WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
 
-	if (uvd_v6_0_enc_support(adev)) {
+	if (adev->uvd.num_enc_rings) {
 		ring = &adev->uvd.ring_enc[0];
 		WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 		WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
@@ -1254,13 +1249,13 @@ static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
 		amdgpu_fence_process(&adev->uvd.ring);
 		break;
 	case 119:
-		if (likely(uvd_v6_0_enc_support(adev)))
+		if (likely(adev->uvd.num_enc_rings))
 			amdgpu_fence_process(&adev->uvd.ring_enc[0]);
 		else
 			int_handled = false;
 		break;
 	case 120:
-		if (likely(uvd_v6_0_enc_support(adev)))
+		if (likely(adev->uvd.num_enc_rings))
 			amdgpu_fence_process(&adev->uvd.ring_enc[1]);
 		else
 			int_handled = false;
@@ -1652,11 +1647,7 @@ static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
 
 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
 {
-	if (uvd_v6_0_enc_support(adev))
-		adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
-	else
-		adev->uvd.irq.num_types = 1;
-
+	adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
 	adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
 }
 
-- 
2.7.4

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[PATCH 3/3] drm/amd/amdgpu: Add Polaris version check

[James Zhu]

Add Polaris version check if firmware support UVD encode

Signed-off-by: James Zhu <James.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 319d4b3..e720c4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -37,8 +37,12 @@
 #include "gmc/gmc_8_1_d.h"
 #include "vi.h"
 
+/* Polaris10/11/12 firmware version */
+#define FW_1_130_16 ((1 << 24) | (130 << 16) | (16 << 8))
+
 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
+static void uvd_v6_0_unset_enc_ring_funcs(struct amdgpu_device *adev);
 
 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
 static int uvd_v6_0_start(struct amdgpu_device *adev);
@@ -402,6 +406,11 @@ static int uvd_v6_0_sw_init(void *handle)
 	if (r)
 		return r;
 
+	if (adev->uvd.fw_version < FW_1_130_16) {
+		uvd_v6_0_unset_enc_ring_funcs(adev);
+		adev->uvd.num_enc_rings = 0;
+	}
+
 	if (adev->uvd.num_enc_rings) {
 		struct drm_sched_rq *rq;
 
@@ -1640,6 +1649,18 @@ static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev)
 	DRM_INFO("UVD ENC is enabled in VM mode\n");
 }
 
+static void uvd_v6_0_unset_enc_ring_funcs(struct amdgpu_device *adev)
+{
+	int i;
+
+	for (i = 0; i < adev->uvd.num_enc_rings; ++i)
+		adev->uvd.ring_enc[i].funcs = NULL;
+
+	adev->uvd.irq.num_types = 1;
+
+	DRM_INFO("UVD ENC is disabled\n");
+}
+
 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
 	.set = uvd_v6_0_set_interrupt_state,
 	.process = uvd_v6_0_process_interrupt,
-- 
2.7.4

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Re: [PATCH 3/3] drm/amd/amdgpu: Add Polaris version check

[Leo Liu]

On 01/18/2018 10:49 AM, James Zhu wrote:
> Add Polaris version check if firmware support UVD encode
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 21 +++++++++++++++++++++
>   1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index 319d4b3..e720c4f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -37,8 +37,12 @@
>   #include "gmc/gmc_8_1_d.h"
>   #include "vi.h"
>   
> +/* Polaris10/11/12 firmware version */
> +#define FW_1_130_16 ((1 << 24) | (130 << 16) | (16 << 8))
> +
>   static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
>   static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
> +static void uvd_v6_0_unset_enc_ring_funcs(struct amdgpu_device *adev);
>   
>   static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
>   static int uvd_v6_0_start(struct amdgpu_device *adev);
> @@ -402,6 +406,11 @@ static int uvd_v6_0_sw_init(void *handle)
>   	if (r)
>   		return r;
>   
> +	if (adev->uvd.fw_version < FW_1_130_16) {
> +		uvd_v6_0_unset_enc_ring_funcs(adev);
This looks a little weird to me. Is possible just move initial set ring 
funcs to after firmware loading?

Leo


> +		adev->uvd.num_enc_rings = 0;
> +	}
> +
>   	if (adev->uvd.num_enc_rings) {
>   		struct drm_sched_rq *rq;
>   
> @@ -1640,6 +1649,18 @@ static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev)
>   	DRM_INFO("UVD ENC is enabled in VM mode\n");
>   }
>   
> +static void uvd_v6_0_unset_enc_ring_funcs(struct amdgpu_device *adev)
> +{
> +	int i;
> +
> +	for (i = 0; i < adev->uvd.num_enc_rings; ++i)
> +		adev->uvd.ring_enc[i].funcs = NULL;
> +
> +	adev->uvd.irq.num_types = 1;
> +
> +	DRM_INFO("UVD ENC is disabled\n");
> +}
> +
>   static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
>   	.set = uvd_v6_0_set_interrupt_state,
>   	.process = uvd_v6_0_process_interrupt,

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