* [PATCH] drm/amdgpu: Add GDS clearing workaround in later init for gfx9
@ 2019-06-07 16:38 Zhu, James
[not found] ` <1559925472-20077-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 8+ messages in thread
From: Zhu, James @ 2019-06-07 16:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Shamis, Leonid, Gabra, Maroun, Zhu, James, Liu, Shaoyun
Since Hardware bug, GDS exist ECC error after cold boot up,
adding GDS clearing workaround in later init for gfx9.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 48 +++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 76722fc..81f6ba8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3634,6 +3634,50 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
};
+
+static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
+{
+ struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
+ int r;
+
+ r = amdgpu_ring_alloc(ring, 17);
+ if (r) {
+ DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",
+ ring->name, r);
+ return r;
+ }
+
+ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
+ WRITE_DATA_DST_SEL(0));
+ amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, 0x10000);
+
+ amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
+ amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
+ PACKET3_DMA_DATA_DST_SEL(1) |
+ PACKET3_DMA_DATA_SRC_SEL(2) |
+ PACKET3_DMA_DATA_ENGINE(0)));
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 0x10000);
+
+ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
+ WRITE_DATA_DST_SEL(0));
+ amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, 0x0);
+
+ amdgpu_ring_commit(ring);
+
+ return 0;
+}
+
+
static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
@@ -3810,6 +3854,10 @@ static int gfx_v9_0_ecc_late_init(void *handle)
return 0;
}
+ r = gfx_v9_0_do_edc_gds_workarounds(adev);
+ if (r)
+ return r;
+
/* requires IBs so do in late init after IB pool is initialized */
r = gfx_v9_0_do_edc_gpr_workarounds(adev);
if (r)
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/amdgpu: Add GDS clearing workaround in later init for gfx9
[not found] ` <1559925472-20077-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2019-06-07 18:16 ` Alex Deucher
[not found] ` <CADnq5_NBWcUtXsBbQP5uBvaOFgWXw3Lhj=ZOisVyTctqZph=xQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 8+ messages in thread
From: Alex Deucher @ 2019-06-07 18:16 UTC (permalink / raw)
To: Zhu, James
Cc: Shamis, Leonid, Gabra, Maroun,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Liu, Shaoyun
On Fri, Jun 7, 2019 at 12:38 PM Zhu, James <James.Zhu@amd.com> wrote:
>
> Since Hardware bug, GDS exist ECC error after cold boot up,
> adding GDS clearing workaround in later init for gfx9.
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 48 +++++++++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 76722fc..81f6ba8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3634,6 +3634,50 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
> { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
> };
>
> +
> +static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
> +{
> + struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
> + int r;
> +
> + r = amdgpu_ring_alloc(ring, 17);
> + if (r) {
> + DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",
> + ring->name, r);
> + return r;
> + }
> +
> + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
> + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
> + WRITE_DATA_DST_SEL(0));
> + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
> + amdgpu_ring_write(ring, 0);
> + amdgpu_ring_write(ring, 0x10000);
hardcoded size, please use the size from the driver.
> +
> + amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
> + amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
> + PACKET3_DMA_DATA_DST_SEL(1) |
> + PACKET3_DMA_DATA_SRC_SEL(2) |
> + PACKET3_DMA_DATA_ENGINE(0)));
> + amdgpu_ring_write(ring, 0);
> + amdgpu_ring_write(ring, 0);
> + amdgpu_ring_write(ring, 0);
> + amdgpu_ring_write(ring, 0);
> + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 0x10000);
Instead of hardcoding the size, can you use the gds size from the
driver (adev->gds.gds_size).
With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> +
> + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
> + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
> + WRITE_DATA_DST_SEL(0));
> + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
> + amdgpu_ring_write(ring, 0);
> + amdgpu_ring_write(ring, 0x0);
> +
> + amdgpu_ring_commit(ring);
> +
> + return 0;
> +}
> +
> +
> static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
> {
> struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
> @@ -3810,6 +3854,10 @@ static int gfx_v9_0_ecc_late_init(void *handle)
> return 0;
> }
>
> + r = gfx_v9_0_do_edc_gds_workarounds(adev);
> + if (r)
> + return r;
> +
> /* requires IBs so do in late init after IB pool is initialized */
> r = gfx_v9_0_do_edc_gpr_workarounds(adev);
> if (r)
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/amdgpu: Add GDS clearing workaround in later init for gfx9
[not found] ` <CADnq5_NBWcUtXsBbQP5uBvaOFgWXw3Lhj=ZOisVyTctqZph=xQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2019-06-07 19:12 ` James Zhu
[not found] ` <19203faa-970e-732b-a0e0-d2d1fe69ce30-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 8+ messages in thread
From: James Zhu @ 2019-06-07 19:12 UTC (permalink / raw)
To: Alex Deucher, Zhu, James
Cc: Shamis, Leonid, Gabra, Maroun,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Liu, Shaoyun
On 2019-06-07 2:16 p.m., Alex Deucher wrote:
> On Fri, Jun 7, 2019 at 12:38 PM Zhu, James <James.Zhu@amd.com> wrote:
>> Since Hardware bug, GDS exist ECC error after cold boot up,
>> adding GDS clearing workaround in later init for gfx9.
>>
>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 48 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 48 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 76722fc..81f6ba8 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -3634,6 +3634,50 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
>> { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
>> };
>>
>> +
>> +static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
>> +{
>> + struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
>> + int r;
>> +
>> + r = amdgpu_ring_alloc(ring, 17);
>> + if (r) {
>> + DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",
>> + ring->name, r);
>> + return r;
>> + }
>> +
>> + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
>> + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
>> + WRITE_DATA_DST_SEL(0));
>> + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
>> + amdgpu_ring_write(ring, 0);
>> + amdgpu_ring_write(ring, 0x10000);
> hardcoded size, please use the size from the driver.
>
>> +
>> + amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
>> + amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
>> + PACKET3_DMA_DATA_DST_SEL(1) |
>> + PACKET3_DMA_DATA_SRC_SEL(2) |
>> + PACKET3_DMA_DATA_ENGINE(0)));
>> + amdgpu_ring_write(ring, 0);
>> + amdgpu_ring_write(ring, 0);
>> + amdgpu_ring_write(ring, 0);
>> + amdgpu_ring_write(ring, 0);
>> + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 0x10000);
> Instead of hardcoding the size, can you use the gds size from the
> driver (adev->gds.gds_size).
Hi Alex,
Do you mean adev->gds.mem.total_size?
But I see below operation in gfx_v9_0_ngg_init.
adev->gds.mem.total_size -= ....
Or you want me to add gds_size in struct amdgpu_gds?
James
>
> With that fixed:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
>> +
>> + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
>> + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
>> + WRITE_DATA_DST_SEL(0));
>> + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
>> + amdgpu_ring_write(ring, 0);
>> + amdgpu_ring_write(ring, 0x0);
>> +
>> + amdgpu_ring_commit(ring);
>> +
>> + return 0;
>> +}
>> +
>> +
>> static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
>> {
>> struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
>> @@ -3810,6 +3854,10 @@ static int gfx_v9_0_ecc_late_init(void *handle)
>> return 0;
>> }
>>
>> + r = gfx_v9_0_do_edc_gds_workarounds(adev);
>> + if (r)
>> + return r;
>> +
>> /* requires IBs so do in late init after IB pool is initialized */
>> r = gfx_v9_0_do_edc_gpr_workarounds(adev);
>> if (r)
>> --
>> 2.7.4
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/amdgpu: Add GDS clearing workaround in later init for gfx9
[not found] ` <19203faa-970e-732b-a0e0-d2d1fe69ce30-5C7GfCeVMHo@public.gmane.org>
@ 2019-06-07 19:42 ` James Zhu
[not found] ` <65266293-ac7a-c3ef-752b-1691299b1f28-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 8+ messages in thread
From: James Zhu @ 2019-06-07 19:42 UTC (permalink / raw)
To: Zhu, James, Alex Deucher
Cc: Shamis, Leonid, Gabra, Maroun,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Liu, Shaoyun
On 2019-06-07 3:12 p.m., Zhu, James wrote:
> On 2019-06-07 2:16 p.m., Alex Deucher wrote:
>> On Fri, Jun 7, 2019 at 12:38 PM Zhu, James <James.Zhu@amd.com> wrote:
>>> Since Hardware bug, GDS exist ECC error after cold boot up,
>>> adding GDS clearing workaround in later init for gfx9.
>>>
>>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 48 +++++++++++++++++++++++++++++++++++
>>> 1 file changed, 48 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> index 76722fc..81f6ba8 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> @@ -3634,6 +3634,50 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
>>> { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
>>> };
>>>
>>> +
>>> +static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
>>> +{
>>> + struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
>>> + int r;
>>> +
>>> + r = amdgpu_ring_alloc(ring, 17);
>>> + if (r) {
>>> + DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",
>>> + ring->name, r);
>>> + return r;
>>> + }
>>> +
>>> + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
>>> + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
>>> + WRITE_DATA_DST_SEL(0));
>>> + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
>>> + amdgpu_ring_write(ring, 0);
>>> + amdgpu_ring_write(ring, 0x10000);
>> hardcoded size, please use the size from the driver.
>>
>>> +
>>> + amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
>>> + amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
>>> + PACKET3_DMA_DATA_DST_SEL(1) |
>>> + PACKET3_DMA_DATA_SRC_SEL(2) |
>>> + PACKET3_DMA_DATA_ENGINE(0)));
>>> + amdgpu_ring_write(ring, 0);
>>> + amdgpu_ring_write(ring, 0);
>>> + amdgpu_ring_write(ring, 0);
>>> + amdgpu_ring_write(ring, 0);
>>> + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 0x10000);
>> Instead of hardcoding the size, can you use the gds size from the
>> driver (adev->gds.gds_size).
> Hi Alex,
>
> Do you mean adev->gds.mem.total_size?
>
> But I see below operation in gfx_v9_0_ngg_init.
>
> adev->gds.mem.total_size -= ....
>
> Or you want me to add gds_size in struct amdgpu_gds?
>
> James
Yeah, The amd-staging-drm-next branch has adev->gds.gds_size.
James
>
>> With that fixed:
>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>>
>>> +
>>> + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
>>> + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
>>> + WRITE_DATA_DST_SEL(0));
>>> + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
>>> + amdgpu_ring_write(ring, 0);
>>> + amdgpu_ring_write(ring, 0x0);
>>> +
>>> + amdgpu_ring_commit(ring);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +
>>> static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
>>> {
>>> struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
>>> @@ -3810,6 +3854,10 @@ static int gfx_v9_0_ecc_late_init(void *handle)
>>> return 0;
>>> }
>>>
>>> + r = gfx_v9_0_do_edc_gds_workarounds(adev);
>>> + if (r)
>>> + return r;
>>> +
>>> /* requires IBs so do in late init after IB pool is initialized */
>>> r = gfx_v9_0_do_edc_gpr_workarounds(adev);
>>> if (r)
>>> --
>>> 2.7.4
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/amdgpu: Add GDS clearing workaround in later init for gfx9
[not found] ` <65266293-ac7a-c3ef-752b-1691299b1f28-5C7GfCeVMHo@public.gmane.org>
@ 2019-06-07 20:16 ` Shamis, Leonid
[not found] ` <3598A781-7AF5-4DDE-83AE-8835E85573D3-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 8+ messages in thread
From: Shamis, Leonid @ 2019-06-07 20:16 UTC (permalink / raw)
To: Zhu, James, Alex Deucher
Cc: Gabra, Maroun,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Liu, Shaoyun
James,
Do you set GDS_VMID0_BASE to 0?.. I don't see it in your patch.
Regards,
Leonid
On 2019-06-07, 15:42, "Zhu, James" <James.Zhu@amd.com> wrote:
On 2019-06-07 3:12 p.m., Zhu, James wrote:
> On 2019-06-07 2:16 p.m., Alex Deucher wrote:
>> On Fri, Jun 7, 2019 at 12:38 PM Zhu, James <James.Zhu@amd.com> wrote:
>>> Since Hardware bug, GDS exist ECC error after cold boot up,
>>> adding GDS clearing workaround in later init for gfx9.
>>>
>>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 48 +++++++++++++++++++++++++++++++++++
>>> 1 file changed, 48 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> index 76722fc..81f6ba8 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> @@ -3634,6 +3634,50 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
>>> { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
>>> };
>>>
>>> +
>>> +static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
>>> +{
>>> + struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
>>> + int r;
>>> +
>>> + r = amdgpu_ring_alloc(ring, 17);
>>> + if (r) {
>>> + DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",
>>> + ring->name, r);
>>> + return r;
>>> + }
>>> +
>>> + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
>>> + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
>>> + WRITE_DATA_DST_SEL(0));
>>> + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
>>> + amdgpu_ring_write(ring, 0);
>>> + amdgpu_ring_write(ring, 0x10000);
>> hardcoded size, please use the size from the driver.
>>
>>> +
>>> + amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
>>> + amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
>>> + PACKET3_DMA_DATA_DST_SEL(1) |
>>> + PACKET3_DMA_DATA_SRC_SEL(2) |
>>> + PACKET3_DMA_DATA_ENGINE(0)));
>>> + amdgpu_ring_write(ring, 0);
>>> + amdgpu_ring_write(ring, 0);
>>> + amdgpu_ring_write(ring, 0);
>>> + amdgpu_ring_write(ring, 0);
>>> + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 0x10000);
>> Instead of hardcoding the size, can you use the gds size from the
>> driver (adev->gds.gds_size).
> Hi Alex,
>
> Do you mean adev->gds.mem.total_size?
>
> But I see below operation in gfx_v9_0_ngg_init.
>
> adev->gds.mem.total_size -= ....
>
> Or you want me to add gds_size in struct amdgpu_gds?
>
> James
Yeah, The amd-staging-drm-next branch has adev->gds.gds_size.
James
>
>> With that fixed:
>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>>
>>> +
>>> + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
>>> + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
>>> + WRITE_DATA_DST_SEL(0));
>>> + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
>>> + amdgpu_ring_write(ring, 0);
>>> + amdgpu_ring_write(ring, 0x0);
>>> +
>>> + amdgpu_ring_commit(ring);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +
>>> static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
>>> {
>>> struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
>>> @@ -3810,6 +3854,10 @@ static int gfx_v9_0_ecc_late_init(void *handle)
>>> return 0;
>>> }
>>>
>>> + r = gfx_v9_0_do_edc_gds_workarounds(adev);
>>> + if (r)
>>> + return r;
>>> +
>>> /* requires IBs so do in late init after IB pool is initialized */
>>> r = gfx_v9_0_do_edc_gpr_workarounds(adev);
>>> if (r)
>>> --
>>> 2.7.4
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/amdgpu: Add GDS clearing workaround in later init for gfx9
[not found] ` <3598A781-7AF5-4DDE-83AE-8835E85573D3-5C7GfCeVMHo@public.gmane.org>
@ 2019-06-08 12:50 ` Christian König
[not found] ` <3ab2a128-3433-0e45-b555-2aff0892f8e6-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-06-10 14:16 ` James Zhu
1 sibling, 1 reply; 8+ messages in thread
From: Christian König @ 2019-06-08 12:50 UTC (permalink / raw)
To: Shamis, Leonid, Zhu, James, Alex Deucher
Cc: Gabra, Maroun,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Liu, Shaoyun
Yeah, that would be a good idea as well.
Additional to that I suggest to update GDS_VMID0_BASE/_SIZE with direct
register writes instead of PM4 packets.
Christian.
Am 07.06.19 um 22:16 schrieb Shamis, Leonid:
> James,
>
> Do you set GDS_VMID0_BASE to 0?.. I don't see it in your patch.
>
> Regards,
> Leonid
>
> On 2019-06-07, 15:42, "Zhu, James" <James.Zhu@amd.com> wrote:
>
>
> On 2019-06-07 3:12 p.m., Zhu, James wrote:
> > On 2019-06-07 2:16 p.m., Alex Deucher wrote:
> >> On Fri, Jun 7, 2019 at 12:38 PM Zhu, James <James.Zhu@amd.com> wrote:
> >>> Since Hardware bug, GDS exist ECC error after cold boot up,
> >>> adding GDS clearing workaround in later init for gfx9.
> >>>
> >>> Signed-off-by: James Zhu <James.Zhu@amd.com>
> >>> ---
> >>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 48 +++++++++++++++++++++++++++++++++++
> >>> 1 file changed, 48 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >>> index 76722fc..81f6ba8 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >>> @@ -3634,6 +3634,50 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
> >>> { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
> >>> };
> >>>
> >>> +
> >>> +static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
> >>> +{
> >>> + struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
> >>> + int r;
> >>> +
> >>> + r = amdgpu_ring_alloc(ring, 17);
> >>> + if (r) {
> >>> + DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",
> >>> + ring->name, r);
> >>> + return r;
> >>> + }
> >>> +
> >>> + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
> >>> + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
> >>> + WRITE_DATA_DST_SEL(0));
> >>> + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
> >>> + amdgpu_ring_write(ring, 0);
> >>> + amdgpu_ring_write(ring, 0x10000);
> >> hardcoded size, please use the size from the driver.
> >>
> >>> +
> >>> + amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
> >>> + amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
> >>> + PACKET3_DMA_DATA_DST_SEL(1) |
> >>> + PACKET3_DMA_DATA_SRC_SEL(2) |
> >>> + PACKET3_DMA_DATA_ENGINE(0)));
> >>> + amdgpu_ring_write(ring, 0);
> >>> + amdgpu_ring_write(ring, 0);
> >>> + amdgpu_ring_write(ring, 0);
> >>> + amdgpu_ring_write(ring, 0);
> >>> + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 0x10000);
> >> Instead of hardcoding the size, can you use the gds size from the
> >> driver (adev->gds.gds_size).
> > Hi Alex,
> >
> > Do you mean adev->gds.mem.total_size?
> >
> > But I see below operation in gfx_v9_0_ngg_init.
> >
> > adev->gds.mem.total_size -= ....
> >
> > Or you want me to add gds_size in struct amdgpu_gds?
> >
> > James
>
> Yeah, The amd-staging-drm-next branch has adev->gds.gds_size.
>
> James
>
> >
> >> With that fixed:
> >> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> >>
> >>> +
> >>> + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
> >>> + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
> >>> + WRITE_DATA_DST_SEL(0));
> >>> + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
> >>> + amdgpu_ring_write(ring, 0);
> >>> + amdgpu_ring_write(ring, 0x0);
> >>> +
> >>> + amdgpu_ring_commit(ring);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +
> >>> static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
> >>> {
> >>> struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
> >>> @@ -3810,6 +3854,10 @@ static int gfx_v9_0_ecc_late_init(void *handle)
> >>> return 0;
> >>> }
> >>>
> >>> + r = gfx_v9_0_do_edc_gds_workarounds(adev);
> >>> + if (r)
> >>> + return r;
> >>> +
> >>> /* requires IBs so do in late init after IB pool is initialized */
> >>> r = gfx_v9_0_do_edc_gpr_workarounds(adev);
> >>> if (r)
> >>> --
> >>> 2.7.4
> >>>
> >>> _______________________________________________
> >>> amd-gfx mailing list
> >>> amd-gfx@lists.freedesktop.org
> >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/amdgpu: Add GDS clearing workaround in later init for gfx9
[not found] ` <3598A781-7AF5-4DDE-83AE-8835E85573D3-5C7GfCeVMHo@public.gmane.org>
2019-06-08 12:50 ` Christian König
@ 2019-06-10 14:16 ` James Zhu
1 sibling, 0 replies; 8+ messages in thread
From: James Zhu @ 2019-06-10 14:16 UTC (permalink / raw)
To: Shamis, Leonid, Zhu, James, Alex Deucher
Cc: Gabra, Maroun,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Liu, Shaoyun
On 2019-06-07 4:16 p.m., Shamis, Leonid wrote:
> James,
>
> Do you set GDS_VMID0_BASE to 0?.. I don't see it in your patch.
sure I will add it.
JAmes
>
> Regards,
> Leonid
>
> On 2019-06-07, 15:42, "Zhu, James" <James.Zhu@amd.com> wrote:
>
>
> On 2019-06-07 3:12 p.m., Zhu, James wrote:
> > On 2019-06-07 2:16 p.m., Alex Deucher wrote:
> >> On Fri, Jun 7, 2019 at 12:38 PM Zhu, James <James.Zhu@amd.com> wrote:
> >>> Since Hardware bug, GDS exist ECC error after cold boot up,
> >>> adding GDS clearing workaround in later init for gfx9.
> >>>
> >>> Signed-off-by: James Zhu <James.Zhu@amd.com>
> >>> ---
> >>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 48 +++++++++++++++++++++++++++++++++++
> >>> 1 file changed, 48 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >>> index 76722fc..81f6ba8 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >>> @@ -3634,6 +3634,50 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
> >>> { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
> >>> };
> >>>
> >>> +
> >>> +static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
> >>> +{
> >>> + struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
> >>> + int r;
> >>> +
> >>> + r = amdgpu_ring_alloc(ring, 17);
> >>> + if (r) {
> >>> + DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",
> >>> + ring->name, r);
> >>> + return r;
> >>> + }
> >>> +
> >>> + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
> >>> + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
> >>> + WRITE_DATA_DST_SEL(0));
> >>> + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
> >>> + amdgpu_ring_write(ring, 0);
> >>> + amdgpu_ring_write(ring, 0x10000);
> >> hardcoded size, please use the size from the driver.
> >>
> >>> +
> >>> + amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
> >>> + amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
> >>> + PACKET3_DMA_DATA_DST_SEL(1) |
> >>> + PACKET3_DMA_DATA_SRC_SEL(2) |
> >>> + PACKET3_DMA_DATA_ENGINE(0)));
> >>> + amdgpu_ring_write(ring, 0);
> >>> + amdgpu_ring_write(ring, 0);
> >>> + amdgpu_ring_write(ring, 0);
> >>> + amdgpu_ring_write(ring, 0);
> >>> + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 0x10000);
> >> Instead of hardcoding the size, can you use the gds size from the
> >> driver (adev->gds.gds_size).
> > Hi Alex,
> >
> > Do you mean adev->gds.mem.total_size?
> >
> > But I see below operation in gfx_v9_0_ngg_init.
> >
> > adev->gds.mem.total_size -= ....
> >
> > Or you want me to add gds_size in struct amdgpu_gds?
> >
> > James
>
> Yeah, The amd-staging-drm-next branch has adev->gds.gds_size.
>
> James
>
> >
> >> With that fixed:
> >> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> >>
> >>> +
> >>> + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
> >>> + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
> >>> + WRITE_DATA_DST_SEL(0));
> >>> + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE));
> >>> + amdgpu_ring_write(ring, 0);
> >>> + amdgpu_ring_write(ring, 0x0);
> >>> +
> >>> + amdgpu_ring_commit(ring);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +
> >>> static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
> >>> {
> >>> struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
> >>> @@ -3810,6 +3854,10 @@ static int gfx_v9_0_ecc_late_init(void *handle)
> >>> return 0;
> >>> }
> >>>
> >>> + r = gfx_v9_0_do_edc_gds_workarounds(adev);
> >>> + if (r)
> >>> + return r;
> >>> +
> >>> /* requires IBs so do in late init after IB pool is initialized */
> >>> r = gfx_v9_0_do_edc_gpr_workarounds(adev);
> >>> if (r)
> >>> --
> >>> 2.7.4
> >>>
> >>> _______________________________________________
> >>> amd-gfx mailing list
> >>> amd-gfx@lists.freedesktop.org
> >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/amdgpu: Add GDS clearing workaround in later init for gfx9
[not found] ` <3ab2a128-3433-0e45-b555-2aff0892f8e6-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2019-06-10 14:21 ` James Zhu
0 siblings, 0 replies; 8+ messages in thread
From: James Zhu @ 2019-06-10 14:21 UTC (permalink / raw)
To: Koenig, Christian, Shamis, Leonid, Zhu, James, Alex Deucher
Cc: Gabra, Maroun,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Liu, Shaoyun
On 2019-06-08 8:50 a.m., Christian König wrote:
> Yeah, that would be a good idea as well.
>
> Additional to that I suggest to update GDS_VMID0_BASE/_SIZE with
> direct register writes instead of PM4 packets.
I can do so.
James
>
> Christian.
>
> Am 07.06.19 um 22:16 schrieb Shamis, Leonid:
>> James,
>>
>> Do you set GDS_VMID0_BASE to 0?.. I don't see it in your patch.
>>
>> Regards,
>> Leonid
>>
>> On 2019-06-07, 15:42, "Zhu, James" <James.Zhu@amd.com> wrote:
>>
>> On 2019-06-07 3:12 p.m., Zhu, James wrote:
>> > On 2019-06-07 2:16 p.m., Alex Deucher wrote:
>> >> On Fri, Jun 7, 2019 at 12:38 PM Zhu, James
>> <James.Zhu@amd.com> wrote:
>> >>> Since Hardware bug, GDS exist ECC error after cold boot up,
>> >>> adding GDS clearing workaround in later init for gfx9.
>> >>>
>> >>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>> >>> ---
>> >>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 48
>> +++++++++++++++++++++++++++++++++++
>> >>> 1 file changed, 48 insertions(+)
>> >>>
>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> >>> index 76722fc..81f6ba8 100644
>> >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> >>> @@ -3634,6 +3634,50 @@ static const struct soc15_reg_entry
>> sec_ded_counter_registers[] = {
>> >>> { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
>> >>> };
>> >>>
>> >>> +
>> >>> +static int gfx_v9_0_do_edc_gds_workarounds(struct
>> amdgpu_device *adev)
>> >>> +{
>> >>> + struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
>> >>> + int r;
>> >>> +
>> >>> + r = amdgpu_ring_alloc(ring, 17);
>> >>> + if (r) {
>> >>> + DRM_ERROR("amdgpu: GDS workarounds failed to
>> lock ring %s (%d).\n",
>> >>> + ring->name, r);
>> >>> + return r;
>> >>> + }
>> >>> +
>> >>> + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA,
>> 3));
>> >>> + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
>> >>> + WRITE_DATA_DST_SEL(0));
>> >>> + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0,
>> mmGDS_VMID0_SIZE));
>> >>> + amdgpu_ring_write(ring, 0);
>> >>> + amdgpu_ring_write(ring, 0x10000);
>> >> hardcoded size, please use the size from the driver.
>> >>
>> >>> +
>> >>> + amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
>> >>> + amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
>> >>> + PACKET3_DMA_DATA_DST_SEL(1) |
>> >>> + PACKET3_DMA_DATA_SRC_SEL(2) |
>> >>> + PACKET3_DMA_DATA_ENGINE(0)));
>> >>> + amdgpu_ring_write(ring, 0);
>> >>> + amdgpu_ring_write(ring, 0);
>> >>> + amdgpu_ring_write(ring, 0);
>> >>> + amdgpu_ring_write(ring, 0);
>> >>> + amdgpu_ring_write(ring,
>> PACKET3_DMA_DATA_CMD_RAW_WAIT | 0x10000);
>> >> Instead of hardcoding the size, can you use the gds size from
>> the
>> >> driver (adev->gds.gds_size).
>> > Hi Alex,
>> >
>> > Do you mean adev->gds.mem.total_size?
>> >
>> > But I see below operation in gfx_v9_0_ngg_init.
>> >
>> > adev->gds.mem.total_size -= ....
>> >
>> > Or you want me to add gds_size in struct amdgpu_gds?
>> >
>> > James
>> Yeah, The amd-staging-drm-next branch has adev->gds.gds_size.
>> James
>> >
>> >> With that fixed:
>> >> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>> >>
>> >>> +
>> >>> + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA,
>> 3));
>> >>> + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(0) |
>> >>> + WRITE_DATA_DST_SEL(0));
>> >>> + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0,
>> mmGDS_VMID0_SIZE));
>> >>> + amdgpu_ring_write(ring, 0);
>> >>> + amdgpu_ring_write(ring, 0x0);
>> >>> +
>> >>> + amdgpu_ring_commit(ring);
>> >>> +
>> >>> + return 0;
>> >>> +}
>> >>> +
>> >>> +
>> >>> static int gfx_v9_0_do_edc_gpr_workarounds(struct
>> amdgpu_device *adev)
>> >>> {
>> >>> struct amdgpu_ring *ring =
>> &adev->gfx.compute_ring[0];
>> >>> @@ -3810,6 +3854,10 @@ static int
>> gfx_v9_0_ecc_late_init(void *handle)
>> >>> return 0;
>> >>> }
>> >>>
>> >>> + r = gfx_v9_0_do_edc_gds_workarounds(adev);
>> >>> + if (r)
>> >>> + return r;
>> >>> +
>> >>> /* requires IBs so do in late init after IB pool
>> is initialized */
>> >>> r = gfx_v9_0_do_edc_gpr_workarounds(adev);
>> >>> if (r)
>> >>> --
>> >>> 2.7.4
>> >>>
>> >>> _______________________________________________
>> >>> amd-gfx mailing list
>> >>> amd-gfx@lists.freedesktop.org
>> >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-06-10 14:21 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-06-07 16:38 [PATCH] drm/amdgpu: Add GDS clearing workaround in later init for gfx9 Zhu, James
[not found] ` <1559925472-20077-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2019-06-07 18:16 ` Alex Deucher
[not found] ` <CADnq5_NBWcUtXsBbQP5uBvaOFgWXw3Lhj=ZOisVyTctqZph=xQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-06-07 19:12 ` James Zhu
[not found] ` <19203faa-970e-732b-a0e0-d2d1fe69ce30-5C7GfCeVMHo@public.gmane.org>
2019-06-07 19:42 ` James Zhu
[not found] ` <65266293-ac7a-c3ef-752b-1691299b1f28-5C7GfCeVMHo@public.gmane.org>
2019-06-07 20:16 ` Shamis, Leonid
[not found] ` <3598A781-7AF5-4DDE-83AE-8835E85573D3-5C7GfCeVMHo@public.gmane.org>
2019-06-08 12:50 ` Christian König
[not found] ` <3ab2a128-3433-0e45-b555-2aff0892f8e6-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-06-10 14:21 ` James Zhu
2019-06-10 14:16 ` James Zhu
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox