[PATCH 1/3] drm/amd/display: Disable ips before dc interrupt setting

[PATCH 1/3] drm/amd/display: Disable ips before dc interrupt setting

[Roman.Li]

From: Roman Li <Roman.Li@amd.com>

[Why]
While in IPS2 an access to dcn registers is not allowed.
If interrupt results in dc call, we should disable IPS.

[How]
Safeguard register access in IPS2 by disabling idle optimization
before calling dc interrupt setting api.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Tested-by: Mark Broadworth <mark.broadworth@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 58b880acb087..3390f0d8420a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -711,7 +711,7 @@ static inline int dm_irq_state(struct amdgpu_device *adev,
 {
 	bool st;
 	enum dc_irq_source irq_source;
-
+	struct dc *dc = adev->dm.dc;
 	struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];
 
 	if (!acrtc) {
@@ -729,6 +729,9 @@ static inline int dm_irq_state(struct amdgpu_device *adev,
 
 	st = (state == AMDGPU_IRQ_STATE_ENABLE);
 
+	if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)
+		dc_allow_idle_optimizations(dc, false);
+
 	dc_interrupt_set(adev->dm.dc, irq_source, st);
 	return 0;
 }
-- 
2.34.1

[PATCH 2/3] drm/amd: Add a DC debug mask for IPS

[Roman.Li]

From: Roman Li <Roman.Li@amd.com>

For debugging IPS-related issues, expose a new debug mask
that allows to disable IPS.
Usage:
amdgpu.dcdebugmask=0x800

Signed-off-by: Roman Li <Roman.Li@amd.com>
Tested-by: Mark Broadworth <mark.broadworth@amd.com>
---
 drivers/gpu/drm/amd/include/amd_shared.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index da9b670fec86..a89d93154ddb 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -259,6 +259,7 @@ enum DC_DEBUG_MASK {
 	DC_ENABLE_DML2 = 0x100,
 	DC_DISABLE_PSR_SU = 0x200,
 	DC_DISABLE_REPLAY = 0x400,
+	DC_DISABLE_IPS = 0x800,
 };
 
 enum amd_dpm_forced_level;
-- 
2.34.1

Re: [PATCH 2/3] drm/amd: Add a DC debug mask for IPS

[Mario Limonciello]

On 1/24/2024 11:09, Roman.Li@amd.com wrote:
> From: Roman Li <Roman.Li@amd.com>
> 
> For debugging IPS-related issues, expose a new debug mask
> that allows to disable IPS.
> Usage:
> amdgpu.dcdebugmask=0x800
> 
> Signed-off-by: Roman Li <Roman.Li@amd.com>
> Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
>   drivers/gpu/drm/amd/include/amd_shared.h | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
> index da9b670fec86..a89d93154ddb 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -259,6 +259,7 @@ enum DC_DEBUG_MASK {
>   	DC_ENABLE_DML2 = 0x100,
>   	DC_DISABLE_PSR_SU = 0x200,
>   	DC_DISABLE_REPLAY = 0x400,
> +	DC_DISABLE_IPS = 0x800,
>   };
>   
>   enum amd_dpm_forced_level;

[PATCH 3/3] drm/amd/display: "Enable IPS by default"

[Roman.Li]

From: Roman Li <Roman.Li@amd.com>

[Why]
IPS was temporary disabled due to instability.
It was fixed in dmub firmware and with:
- "drm/amd/display: Add IPS checks before dcn register access"
- "drm/amd/display: Disable ips before dc interrupt setting"

[How]
Enable IPS by default.
Disable IPS if 0x800 bit set in amdgpu.dcdebugmask module params

Signed-off-by: Roman Li <Roman.Li@amd.com>
Tested-by: Mark Broadworth <mark.broadworth@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 41994a60e2cd..9d909c09a14f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1719,7 +1719,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 	init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
 	init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
 
-	init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;
+        if (amdgpu_dc_debug_mask & DC_DISABLE_IPS)
+		init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;
 
 	init_data.flags.disable_ips_in_vpb = 1;
 
-- 
2.34.1

Re: [PATCH 3/3] drm/amd/display: "Enable IPS by default"

[Mario Limonciello]

On 1/24/2024 11:09, Roman.Li@amd.com wrote:
> From: Roman Li <Roman.Li@amd.com>
> 
> [Why]
> IPS was temporary disabled due to instability.
> It was fixed in dmub firmware and with:
> - "drm/amd/display: Add IPS checks before dcn register access"
> - "drm/amd/display: Disable ips before dc interrupt setting"
> 
> [How]
> Enable IPS by default.
> Disable IPS if 0x800 bit set in amdgpu.dcdebugmask module params
> 
> Signed-off-by: Roman Li <Roman.Li@amd.com>
> Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 41994a60e2cd..9d909c09a14f 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1719,7 +1719,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
>   	init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
>   	init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
>   
> -	init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;
> +        if (amdgpu_dc_debug_mask & DC_DISABLE_IPS)
> +		init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;
>   
>   	init_data.flags.disable_ips_in_vpb = 1;
>   

Re: [PATCH 1/3] drm/amd/display: Disable ips before dc interrupt setting

[Mario Limonciello]

On 1/24/2024 11:09, Roman.Li@amd.com wrote:
> From: Roman Li <Roman.Li@amd.com>
> 
> [Why]
> While in IPS2 an access to dcn registers is not allowed.
> If interrupt results in dc call, we should disable IPS.
> 
> [How]
> Safeguard register access in IPS2 by disabling idle optimization
> before calling dc interrupt setting api.
> 
> Signed-off-by: Roman Li <Roman.Li@amd.com>
> Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
> index 58b880acb087..3390f0d8420a 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
> @@ -711,7 +711,7 @@ static inline int dm_irq_state(struct amdgpu_device *adev,
>   {
>   	bool st;
>   	enum dc_irq_source irq_source;
> -
> +	struct dc *dc = adev->dm.dc;
>   	struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];
>   
>   	if (!acrtc) {
> @@ -729,6 +729,9 @@ static inline int dm_irq_state(struct amdgpu_device *adev,
>   
>   	st = (state == AMDGPU_IRQ_STATE_ENABLE);
>   
> +	if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)
> +		dc_allow_idle_optimizations(dc, false);
> +
>   	dc_interrupt_set(adev->dm.dc, irq_source, st);
>   	return 0;
>   }