Re: [PATCH v3] drm/amd/display: Disable VUpdate interrupt for DCN hardware

["Li, Sun peng (Leo)" <Sunpeng.Li-5C7GfCeVMHo@public.gmane.org>]

On 2019-11-05 2:01 p.m., sunpeng.li@amd.com wrote:
> From: Leo Li <sunpeng.li@amd.com>
> 
> [Why]
> 
> On DCN hardware, the crtc_high_irq handler makes vupdate_high_irq
> handler redundant.
> 
> All the vupdate handler does is handle vblank events, and update vrr
> for DCE hw (excluding VEGA, more on that later). As far as usermode is
> concerned. vstartup happens close enough to vupdate on DCN that it can
> be considered the "same". Handling vblank and updating vrr at vstartup
> effectively replaces vupdate on DCN.
> 
> Vega is a bit special. Like DCN, the VRR registers on Vega are
> double-buffered, and swapped at vupdate. But Unlike DCN, it lacks a
> vstartup interrupt. This means we can't quite remove the vupdate handler
> for it, since delayed user events due to vrr are sent off there.
> 
> [How]
> 
> Remove registration of vupdate interrupt handler for DCN. Disable
> vupdate interrupt if asic family DCN, enable otherwise.
> 
> Signed-off-by: Leo Li <sunpeng.li@amd.com>
> ---
> 
> v2: Don't exclude vega when enabling vupdate interrupts
> 
> v3: Move FAMILY_AI check inside dm_set_vupdate_irq()
> 
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 +++----------------
>  1 file changed, 4 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 256a23a0ec28..d40185dfd0c0 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -2241,34 +2241,6 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
>  				dm_dcn_crtc_high_irq, c_irq_params);
>  	}
>  
> -	/* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
> -	 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
> -	 * to trigger at end of each vblank, regardless of state of the lock,
> -	 * matching DCE behaviour.
> -	 */
> -	for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
> -	     i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
> -	     i++) {
> -		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
> -
> -		if (r) {
> -			DRM_ERROR("Failed to add vupdate irq id!\n");
> -			return r;
> -		}
> -
> -		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
> -		int_params.irq_source =
> -			dc_interrupt_to_irq_source(dc, i, 0);
> -
> -		c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
> -
> -		c_irq_params->adev = adev;
> -		c_irq_params->irq_src = int_params.irq_source;
> -
> -		amdgpu_dm_irq_register_interrupt(adev, &int_params,
> -				dm_vupdate_high_irq, c_irq_params);
> -	}
> -
>  	/* Use GRPH_PFLIP interrupt */
>  	for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
>  			i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
> @@ -4249,6 +4221,10 @@ static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
>  	struct amdgpu_device *adev = crtc->dev->dev_private;
>  	int rc;
>  
> +	/* Do not set vupdate for DCN hardware */
> +	if (adev->family <= AMDGPU_FAMILY_AI)

Err, no. s/<=/>/...

Leo

> +		return 0;
> +
>  	irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
>  
>  	rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
> 
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