* [PATCH v2 0/7] Refactor smu feature bit implementation
@ 2026-01-20 6:12 Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 1/7] drm/amd/pm: Add smu feature bits data struct Lijo Lazar
` (7 more replies)
0 siblings, 8 replies; 10+ messages in thread
From: Lijo Lazar @ 2026-01-20 6:12 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking.Zhang, Alexander.Deucher, Asad.Kamal, kevinyang.wang
Presently a 64-bit bitmask is used to represent the PM features enabled/supported by SOC. The
number of features has grown to nearly 64 and could extend beyond that. Instead of using a 64-bit
mask, implement a data structure around bitmap and move the implementation to use the datastructure
instead of directly operating on 64-bit bitmask.
v2:
Use to_arr32 instead of direct assignment
Lijo Lazar (7):
drm/amd/pm: Add smu feature bits data struct
drm/amd/pm: Add smu feature interface functions
drm/amd/pm: Remove unused logic in SMUv14.0.2
drm/amd/pm: Initialize allowed feature list
drm/amd/pm: Use feature bits data structure
drm/amd/pm: Change get_enabled_mask signature
drm/amd/pm: Add default feature number definition
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 48 ++---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 204 +++++++++++++++++-
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 33 ++-
.../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 24 ++-
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 119 +++++-----
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 116 +++++-----
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 5 +-
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 29 +--
.../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 4 +-
.../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 37 ++--
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 6 +-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 58 +++--
.../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 20 +-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 34 +--
.../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 29 +--
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 39 ++--
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 103 +++++----
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 29 +--
.../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 6 +-
.../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 33 +--
.../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 69 ++----
.../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 6 +-
.../drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 33 +--
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 82 +++----
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 2 +-
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 2 +-
26 files changed, 662 insertions(+), 508 deletions(-)
--
2.49.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 1/7] drm/amd/pm: Add smu feature bits data struct
2026-01-20 6:12 [PATCH v2 0/7] Refactor smu feature bit implementation Lijo Lazar
@ 2026-01-20 6:12 ` Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 2/7] drm/amd/pm: Add smu feature interface functions Lijo Lazar
` (6 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Lijo Lazar @ 2026-01-20 6:12 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking.Zhang, Alexander.Deucher, Asad.Kamal, kevinyang.wang
Add a bitmap struct to represent smu feature bits and functions to set/clear features.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 81 +++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 1def04826f10..017df903a7bd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -472,6 +472,11 @@ struct smu_power_context {
};
#define SMU_FEATURE_MAX (64)
+
+struct smu_feature_bits {
+ DECLARE_BITMAP(bits, SMU_FEATURE_MAX);
+};
+
struct smu_feature {
uint32_t feature_num;
DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
@@ -1974,4 +1979,80 @@ int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type ms
void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id);
bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id);
+
+static inline bool smu_feature_bits_is_set(const struct smu_feature_bits *bits,
+ unsigned int bit)
+{
+ if (bit >= SMU_FEATURE_MAX)
+ return false;
+
+ return test_bit(bit, bits->bits);
+}
+
+static inline void smu_feature_bits_set_bit(struct smu_feature_bits *bits,
+ unsigned int bit)
+{
+ if (bit < SMU_FEATURE_MAX)
+ __set_bit(bit, bits->bits);
+}
+
+static inline void smu_feature_bits_clear_bit(struct smu_feature_bits *bits,
+ unsigned int bit)
+{
+ if (bit < SMU_FEATURE_MAX)
+ __clear_bit(bit, bits->bits);
+}
+
+static inline void smu_feature_bits_clearall(struct smu_feature_bits *bits)
+{
+ bitmap_zero(bits->bits, SMU_FEATURE_MAX);
+}
+
+static inline void smu_feature_bits_fill(struct smu_feature_bits *bits)
+{
+ bitmap_fill(bits->bits, SMU_FEATURE_MAX);
+}
+
+static inline bool
+smu_feature_bits_test_mask(const struct smu_feature_bits *bits,
+ const unsigned long *mask)
+{
+ return bitmap_intersects(bits->bits, mask, SMU_FEATURE_MAX);
+}
+
+static inline void smu_feature_bits_from_arr32(struct smu_feature_bits *bits,
+ const uint32_t *arr,
+ unsigned int nbits)
+{
+ bitmap_from_arr32(bits->bits, arr, nbits);
+}
+
+static inline void
+smu_feature_bits_to_arr32(const struct smu_feature_bits *bits, uint32_t *arr,
+ unsigned int nbits)
+{
+ bitmap_to_arr32(arr, bits->bits, nbits);
+}
+
+static inline bool smu_feature_bits_empty(const struct smu_feature_bits *bits,
+ unsigned int nbits)
+{
+ return bitmap_empty(bits->bits, nbits);
+}
+
+static inline void smu_feature_bits_copy(struct smu_feature_bits *dst,
+ const unsigned long *src,
+ unsigned int nbits)
+{
+ bitmap_copy(dst->bits, src, nbits);
+}
+
+static inline void smu_feature_bits_or(struct smu_feature_bits *dst,
+ const struct smu_feature_bits *src1,
+ const unsigned long *src2,
+ unsigned int nbits)
+{
+ bitmap_or(dst->bits, src1->bits, src2, nbits);
+}
+
#endif
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 2/7] drm/amd/pm: Add smu feature interface functions
2026-01-20 6:12 [PATCH v2 0/7] Refactor smu feature bit implementation Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 1/7] drm/amd/pm: Add smu feature bits data struct Lijo Lazar
@ 2026-01-20 6:12 ` Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 3/7] drm/amd/pm: Remove unused logic in SMUv14.0.2 Lijo Lazar
` (5 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Lijo Lazar @ 2026-01-20 6:12 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking.Zhang, Alexander.Deucher, Asad.Kamal, kevinyang.wang
Instead of using bitmap operations, add wrapper interface functions to
operate on smu features.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 20 ++--
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 104 +++++++++++++++++-
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 5 +-
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 4 +-
.../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 4 +-
.../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 4 +-
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 6 +-
7 files changed, 120 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 6b6b05e8f736..ccb771dacde1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -690,7 +690,6 @@ static int smu_sys_set_pp_table(void *handle,
static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
{
- struct smu_feature *feature = &smu->smu_feature;
uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
int ret = 0;
@@ -702,20 +701,19 @@ static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
* such scenario.
*/
if (smu->adev->scpm_enabled) {
- bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
+ smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
return 0;
}
- bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
+ smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
SMU_FEATURE_MAX/32);
if (ret)
return ret;
- bitmap_or(feature->allowed, feature->allowed,
- (unsigned long *)allowed_feature_mask,
- feature->feature_num);
+ smu_feature_list_add_bits(smu, SMU_FEATURE_LIST_ALLOWED,
+ (unsigned long *)allowed_feature_mask);
return ret;
}
@@ -1365,9 +1363,7 @@ static int smu_sw_init(struct amdgpu_ip_block *ip_block)
int i, ret;
smu->pool_size = adev->pm.smu_prv_buffer_size;
- smu->smu_feature.feature_num = SMU_FEATURE_MAX;
- bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
- bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
+ smu_feature_init(smu, SMU_FEATURE_MAX);
INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
@@ -1656,7 +1652,6 @@ static void smu_wbrf_fini(struct smu_context *smu)
static int smu_smc_hw_setup(struct smu_context *smu)
{
- struct smu_feature *feature = &smu->smu_feature;
struct amdgpu_device *adev = smu->adev;
uint8_t pcie_gen = 0, pcie_width = 0;
uint64_t features_supported;
@@ -1819,9 +1814,8 @@ static int smu_smc_hw_setup(struct smu_context *smu)
dev_err(adev->dev, "Failed to retrieve supported dpm features!\n");
return ret;
}
- bitmap_copy(feature->supported,
- (unsigned long *)&features_supported,
- feature->feature_num);
+ smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED,
+ (unsigned long *)&features_supported);
if (!smu_is_dpm_running(smu))
dev_info(adev->dev, "dpm has been disabled\n");
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 017df903a7bd..2290298579e1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -477,10 +477,15 @@ struct smu_feature_bits {
DECLARE_BITMAP(bits, SMU_FEATURE_MAX);
};
+enum smu_feature_list {
+ SMU_FEATURE_LIST_SUPPORTED,
+ SMU_FEATURE_LIST_ALLOWED,
+ SMU_FEATURE_LIST_MAX,
+};
+
struct smu_feature {
uint32_t feature_num;
- DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
- DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
+ struct smu_feature_bits bits[SMU_FEATURE_LIST_MAX];
};
struct smu_clocks {
@@ -2055,4 +2060,99 @@ static inline void smu_feature_bits_or(struct smu_feature_bits *dst,
bitmap_or(dst->bits, src1->bits, src2, nbits);
}
+static inline struct smu_feature_bits *
+__smu_feature_get_list(struct smu_context *smu, enum smu_feature_list list)
+{
+ if (unlikely(list >= SMU_FEATURE_LIST_MAX)) {
+ dev_warn(smu->adev->dev, "Invalid feature list: %d\n", list);
+ return &smu->smu_feature.bits[SMU_FEATURE_LIST_SUPPORTED];
+ }
+
+ return &smu->smu_feature.bits[list];
+}
+
+static inline bool smu_feature_list_is_set(struct smu_context *smu,
+ enum smu_feature_list list,
+ unsigned int bit)
+{
+ if (bit >= smu->smu_feature.feature_num)
+ return false;
+
+ return smu_feature_bits_is_set(__smu_feature_get_list(smu, list), bit);
+}
+
+static inline void smu_feature_list_set_bit(struct smu_context *smu,
+ enum smu_feature_list list,
+ unsigned int bit)
+{
+ if (bit >= smu->smu_feature.feature_num)
+ return;
+
+ smu_feature_bits_set_bit(__smu_feature_get_list(smu, list), bit);
+}
+
+static inline void smu_feature_list_clear_bit(struct smu_context *smu,
+ enum smu_feature_list list,
+ unsigned int bit)
+{
+ if (bit >= smu->smu_feature.feature_num)
+ return;
+
+ smu_feature_bits_clear_bit(__smu_feature_get_list(smu, list), bit);
+}
+
+static inline void smu_feature_list_set_all(struct smu_context *smu,
+ enum smu_feature_list list)
+{
+ smu_feature_bits_fill(__smu_feature_get_list(smu, list));
+}
+
+static inline void smu_feature_list_clear_all(struct smu_context *smu,
+ enum smu_feature_list list)
+{
+ smu_feature_bits_clearall(__smu_feature_get_list(smu, list));
+}
+
+static inline bool smu_feature_list_is_empty(struct smu_context *smu,
+ enum smu_feature_list list)
+{
+ return smu_feature_bits_empty(__smu_feature_get_list(smu, list),
+ smu->smu_feature.feature_num);
+}
+
+static inline void smu_feature_list_set_bits(struct smu_context *smu,
+ enum smu_feature_list dst_list,
+ const unsigned long *src)
+{
+ smu_feature_bits_copy(__smu_feature_get_list(smu, dst_list), src,
+ smu->smu_feature.feature_num);
+}
+
+static inline void smu_feature_list_add_bits(struct smu_context *smu,
+ enum smu_feature_list list,
+ const unsigned long *src)
+{
+ struct smu_feature_bits *bits = __smu_feature_get_list(smu, list);
+
+ smu_feature_bits_or(bits, bits, src, smu->smu_feature.feature_num);
+}
+
+static inline void smu_feature_list_to_arr32(struct smu_context *smu,
+ enum smu_feature_list list,
+ uint32_t *arr)
+{
+ smu_feature_bits_to_arr32(__smu_feature_get_list(smu, list), arr,
+ smu->smu_feature.feature_num);
+}
+
+static inline void smu_feature_init(struct smu_context *smu, int feature_num)
+{
+ if (!feature_num || smu->smu_feature.feature_num != 0)
+ return;
+
+ smu->smu_feature.feature_num = feature_num;
+ smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_SUPPORTED);
+ smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
+}
+
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index eb1b9faf8e5c..1d0f9f8ddf9b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -750,12 +750,13 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu)
int ret = 0;
uint32_t feature_mask[2];
- if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) {
+ if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
+ feature->feature_num < 64) {
ret = -EINVAL;
goto failed;
}
- bitmap_to_arr32(feature_mask, feature->allowed, 64);
+ smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
feature_mask[1], NULL);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 51f96fdcec24..d9b1725c3afc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -761,11 +761,11 @@ int smu_v13_0_set_allowed_mask(struct smu_context *smu)
int ret = 0;
uint32_t feature_mask[2];
- if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
+ if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
feature->feature_num < 64)
return -EINVAL;
- bitmap_to_arr32(feature_mask, feature->allowed, 64);
+ smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
feature_mask[1], NULL);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index f85ba23f9d99..5c991e2e15ff 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
@@ -746,11 +746,11 @@ int smu_v14_0_set_allowed_mask(struct smu_context *smu)
int ret = 0;
uint32_t feature_mask[2];
- if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
+ if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
feature->feature_num < 64)
return -EINVAL;
- bitmap_to_arr32(feature_mask, feature->allowed, 64);
+ smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
feature_mask[1], NULL);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
index 6557085a7c72..d77eaac556d9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
@@ -715,11 +715,11 @@ int smu_v15_0_set_allowed_mask(struct smu_context *smu)
int ret = 0;
uint32_t feature_mask[2];
- if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
+ if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
feature->feature_num < 64)
return -EINVAL;
- bitmap_to_arr32(feature_mask, feature->allowed, 64);
+ smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
feature_mask[1], NULL);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 24835600c1cd..9bb7e3760c0f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -677,7 +677,6 @@ int smu_cmn_to_asic_specific_index(struct smu_context *smu,
int smu_cmn_feature_is_supported(struct smu_context *smu,
enum smu_feature_mask mask)
{
- struct smu_feature *feature = &smu->smu_feature;
int feature_id;
feature_id = smu_cmn_to_asic_specific_index(smu,
@@ -686,9 +685,8 @@ int smu_cmn_feature_is_supported(struct smu_context *smu,
if (feature_id < 0)
return 0;
- WARN_ON(feature_id > feature->feature_num);
-
- return test_bit(feature_id, feature->supported);
+ return smu_feature_list_is_set(smu, SMU_FEATURE_LIST_SUPPORTED,
+ feature_id);
}
static int __smu_get_enabled_features(struct smu_context *smu,
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 3/7] drm/amd/pm: Remove unused logic in SMUv14.0.2
2026-01-20 6:12 [PATCH v2 0/7] Refactor smu feature bit implementation Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 1/7] drm/amd/pm: Add smu feature bits data struct Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 2/7] drm/amd/pm: Add smu feature interface functions Lijo Lazar
@ 2026-01-20 6:12 ` Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 4/7] drm/amd/pm: Initialize allowed feature list Lijo Lazar
` (4 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Lijo Lazar @ 2026-01-20 6:12 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking.Zhang, Alexander.Deucher, Asad.Kamal, kevinyang.wang
Remove commented and redundant logic in get_allowed_feature_mask
implementation.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
---
.../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 39 -------------------
1 file changed, 39 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
index faae1da81bd4..d2aa5fabfca4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
@@ -268,50 +268,11 @@ static int
smu_v14_0_2_get_allowed_feature_mask(struct smu_context *smu,
uint32_t *feature_mask, uint32_t num)
{
- struct amdgpu_device *adev = smu->adev;
- /*u32 smu_version;*/
-
if (num > 2)
return -EINVAL;
memset(feature_mask, 0xff, sizeof(uint32_t) * num);
- if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
- }
-#if 0
- if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) ||
- !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
-
- if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK))
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
-
- /* PMFW 78.58 contains a critical fix for gfxoff feature */
- smu_cmn_get_smc_version(smu, NULL, &smu_version);
- if ((smu_version < 0x004e3a00) ||
- !(adev->pm.pp_feature & PP_GFXOFF_MASK))
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT);
-
- if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
- }
-
- if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK))
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
-
- if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT);
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT);
- }
-
- if (!(adev->pm.pp_feature & PP_ULV_MASK))
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT);
-#endif
-
return 0;
}
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 4/7] drm/amd/pm: Initialize allowed feature list
2026-01-20 6:12 [PATCH v2 0/7] Refactor smu feature bit implementation Lijo Lazar
` (2 preceding siblings ...)
2026-01-20 6:12 ` [PATCH v2 3/7] drm/amd/pm: Remove unused logic in SMUv14.0.2 Lijo Lazar
@ 2026-01-20 6:12 ` Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 5/7] drm/amd/pm: Use feature bits data structure Lijo Lazar
` (3 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Lijo Lazar @ 2026-01-20 6:12 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking.Zhang, Alexander.Deucher, Asad.Kamal, kevinyang.wang
Instead of returning feature bit mask of allowed features, initialize
the allowed features in the callback implementation itself.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 17 +---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 24 +----
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 11 +--
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 92 +++++++++----------
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 89 +++++++++---------
.../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 11 +--
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 35 +++----
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 12 +--
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 80 ++++++++--------
.../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 11 +--
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 2 +-
11 files changed, 158 insertions(+), 226 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index ccb771dacde1..e75dd0152ea7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -688,11 +688,8 @@ static int smu_sys_set_pp_table(void *handle,
return ret;
}
-static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
+static int smu_init_driver_allowed_feature_mask(struct smu_context *smu)
{
- uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
- int ret = 0;
-
/*
* With SCPM enabled, the allowed featuremasks setting(via
* PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted.
@@ -707,15 +704,7 @@ static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
- ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
- SMU_FEATURE_MAX/32);
- if (ret)
- return ret;
-
- smu_feature_list_add_bits(smu, SMU_FEATURE_LIST_ALLOWED,
- (unsigned long *)allowed_feature_mask);
-
- return ret;
+ return smu_init_allowed_features(smu);
}
static int smu_set_funcs(struct amdgpu_device *adev)
@@ -1946,7 +1935,7 @@ static int smu_hw_init(struct amdgpu_ip_block *ip_block)
if (!smu->pm_enabled)
return 0;
- ret = smu_get_driver_allowed_feature_mask(smu);
+ ret = smu_init_driver_allowed_feature_mask(smu);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 2290298579e1..7c63c631f6d4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -812,11 +812,10 @@ struct pptable_funcs {
int (*run_btc)(struct smu_context *smu);
/**
- * @get_allowed_feature_mask: Get allowed feature mask.
- * &feature_mask: Array to store feature mask.
- * &num: Elements in &feature_mask.
+ * @init_allowed_features: Initialize allowed features bitmap.
+ * Directly sets allowed features using smu_feature wrapper functions.
*/
- int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
+ int (*init_allowed_features)(struct smu_context *smu);
/**
* @get_current_power_state: Get the current power state.
@@ -2052,14 +2051,6 @@ static inline void smu_feature_bits_copy(struct smu_feature_bits *dst,
bitmap_copy(dst->bits, src, nbits);
}
-static inline void smu_feature_bits_or(struct smu_feature_bits *dst,
- const struct smu_feature_bits *src1,
- const unsigned long *src2,
- unsigned int nbits)
-{
- bitmap_or(dst->bits, src1->bits, src2, nbits);
-}
-
static inline struct smu_feature_bits *
__smu_feature_get_list(struct smu_context *smu, enum smu_feature_list list)
{
@@ -2128,15 +2119,6 @@ static inline void smu_feature_list_set_bits(struct smu_context *smu,
smu->smu_feature.feature_num);
}
-static inline void smu_feature_list_add_bits(struct smu_context *smu,
- enum smu_feature_list list,
- const unsigned long *src)
-{
- struct smu_feature_bits *bits = __smu_feature_get_list(smu, list);
-
- smu_feature_bits_or(bits, bits, src, smu->smu_feature.feature_num);
-}
-
static inline void smu_feature_list_to_arr32(struct smu_context *smu,
enum smu_feature_list list,
uint32_t *arr)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 7c5ce6a6e2ca..b22a0e91826d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -345,14 +345,9 @@ static int arcturus_init_smc_tables(struct smu_context *smu)
}
static int
-arcturus_get_allowed_feature_mask(struct smu_context *smu,
- uint32_t *feature_mask, uint32_t num)
+arcturus_init_allowed_features(struct smu_context *smu)
{
- if (num > 2)
- return -EINVAL;
-
- /* pptable will handle the features to enable */
- memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
+ smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
return 0;
}
@@ -1877,7 +1872,7 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
static const struct pptable_funcs arcturus_ppt_funcs = {
/* init dpm */
- .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
+ .init_allowed_features = arcturus_init_allowed_features,
/* btc */
.run_btc = arcturus_run_btc,
/* dpm/clk tables */
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 1f84654bbc85..f14eed052526 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -275,89 +275,83 @@ static bool is_asic_secure(struct smu_context *smu)
}
static int
-navi10_get_allowed_feature_mask(struct smu_context *smu,
- uint32_t *feature_mask, uint32_t num)
+navi10_init_allowed_features(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
- if (num > 2)
- return -EINVAL;
-
- memset(feature_mask, 0, sizeof(uint32_t) * num);
-
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
- | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
- | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
- | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
- | FEATURE_MASK(FEATURE_PPT_BIT)
- | FEATURE_MASK(FEATURE_TDC_BIT)
- | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
- | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
- | FEATURE_MASK(FEATURE_VR0HOT_BIT)
- | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
- | FEATURE_MASK(FEATURE_THERMAL_BIT)
- | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
- | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
- | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
- | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
- | FEATURE_MASK(FEATURE_BACO_BIT)
- | FEATURE_MASK(FEATURE_GFX_SS_BIT)
- | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
- | FEATURE_MASK(FEATURE_FW_CTF_BIT)
- | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT)
- | FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT);
+ smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
+
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_EDC_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_PLUS_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_LED_DISPLAY_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TEMP_DEPENDENT_VMIN_BIT);
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT);
if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT);
if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT);
if (adev->pm.pp_feature & PP_ULV_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT);
if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT);
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT);
if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT);
if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT);
if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VCN_PG_BIT);
if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_JPEG_PG_BIT);
if (smu->dc_controlled_by_gpio)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT);
if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT);
- /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
if (!(is_asic_secure(smu) &&
(amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
(adev->rev_id == 0)) &&
- (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
- | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
- | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
+ (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT);
+ }
- /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
if (is_asic_secure(smu) &&
(amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
(adev->rev_id == 0))
- *(uint64_t *)feature_mask &=
- ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);
return 0;
}
@@ -3277,7 +3271,7 @@ static int navi10_set_config_table(struct smu_context *smu,
}
static const struct pptable_funcs navi10_ppt_funcs = {
- .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
+ .init_allowed_features = navi10_init_allowed_features,
.set_default_dpm_table = navi10_set_default_dpm_table,
.dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
.dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index f930ba2733e9..98a02fc08214 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -276,85 +276,82 @@ static const uint8_t sienna_cichlid_throttler_map[] = {
};
static int
-sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
- uint32_t *feature_mask, uint32_t num)
+sienna_cichlid_init_allowed_features(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
- if (num > 2)
- return -EINVAL;
-
- memset(feature_mask, 0, sizeof(uint32_t) * num);
-
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
- | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
- | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
- | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
- | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
- | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
- | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
- | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
- | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
- | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
- | FEATURE_MASK(FEATURE_GFX_SS_BIT)
- | FEATURE_MASK(FEATURE_VR0HOT_BIT)
- | FEATURE_MASK(FEATURE_PPT_BIT)
- | FEATURE_MASK(FEATURE_TDC_BIT)
- | FEATURE_MASK(FEATURE_BACO_BIT)
- | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
- | FEATURE_MASK(FEATURE_FW_CTF_BIT)
- | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
- | FEATURE_MASK(FEATURE_THERMAL_BIT)
- | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
+ smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
+
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_UCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT);
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_GPO_BIT);
}
if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
(amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) &&
!(adev->flags & AMD_IS_APU))
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_DCS_BIT);
- if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
- | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
- | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
+ if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT);
+ }
if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT);
if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT);
if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT);
if (adev->pm.pp_feature & PP_ULV_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT);
if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT);
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT);
if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT);
if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT);
if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_PG_BIT);
if (smu->dc_controlled_by_gpio)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT);
if (amdgpu_device_should_use_aspm(adev))
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT);
return 0;
}
@@ -3085,7 +3082,7 @@ static int sienna_cichlid_mode2_reset(struct smu_context *smu)
}
static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
- .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
+ .init_allowed_features = sienna_cichlid_init_allowed_features,
.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
.dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
.dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 9de0b676bb7b..3b6a34644a92 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -329,14 +329,9 @@ static int aldebaran_init_smc_tables(struct smu_context *smu)
return smu_v13_0_init_smc_tables(smu);
}
-static int aldebaran_get_allowed_feature_mask(struct smu_context *smu,
- uint32_t *feature_mask, uint32_t num)
+static int aldebaran_init_allowed_features(struct smu_context *smu)
{
- if (num > 2)
- return -EINVAL;
-
- /* pptable will handle the features to enable */
- memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
+ smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
return 0;
}
@@ -1967,7 +1962,7 @@ static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu,
static const struct pptable_funcs aldebaran_ppt_funcs = {
/* init dpm */
- .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
+ .init_allowed_features = aldebaran_init_allowed_features,
/* dpm/clk tables */
.set_default_dpm_table = aldebaran_set_default_dpm_table,
.populate_umd_state_clk = aldebaran_populate_umd_state_clk,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index ce52b616b935..9c4298736b28 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -287,49 +287,44 @@ static const uint8_t smu_v13_0_0_throttler_map[] = {
};
static int
-smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
- uint32_t *feature_mask, uint32_t num)
+smu_v13_0_0_init_allowed_features(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
- if (num > 2)
- return -EINVAL;
-
- memset(feature_mask, 0xff, sizeof(uint32_t) * num);
+ smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) {
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT);
+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT);
+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_IMU_BIT);
}
if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) ||
!(adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_MMHUB_PG_BIT);
if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK))
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT);
- /* PMFW 78.58 contains a critical fix for gfxoff feature */
if ((smu->smc_fw_version < 0x004e3a00) ||
!(adev->pm.pp_feature & PP_GFXOFF_MASK))
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT);
+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT);
if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);
+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VMEMP_SCALING_BIT);
+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VDDIO_MEM_SCALING_BIT);
}
if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK))
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT);
if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT);
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT);
+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT);
+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT);
}
if (!(adev->pm.pp_feature & PP_ULV_MASK))
- *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT);
+ smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT);
return 0;
}
@@ -3130,7 +3125,7 @@ static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu,
}
static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
- .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
+ .init_allowed_features = smu_v13_0_0_init_allowed_features,
.set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
.i2c_init = smu_v13_0_0_i2c_control_init,
.i2c_fini = smu_v13_0_0_i2c_control_fini,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 1e82c43c851a..bd893e95515f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -742,15 +742,9 @@ static int smu_v13_0_6_fini_smc_tables(struct smu_context *smu)
return smu_v13_0_fini_smc_tables(smu);
}
-static int smu_v13_0_6_get_allowed_feature_mask(struct smu_context *smu,
- uint32_t *feature_mask,
- uint32_t num)
+static int smu_v13_0_6_init_allowed_features(struct smu_context *smu)
{
- if (num > 2)
- return -EINVAL;
-
- /* pptable will handle the features to enable */
- memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
+ smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
return 0;
}
@@ -3836,7 +3830,7 @@ static int smu_v13_0_6_get_ras_smu_drv(struct smu_context *smu, const struct ras
static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
/* init dpm */
- .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask,
+ .init_allowed_features = smu_v13_0_6_init_allowed_features,
/* dpm/clk tables */
.set_default_dpm_table = smu_v13_0_6_set_default_dpm_table,
.populate_umd_state_clk = smu_v13_0_6_populate_umd_state_clk,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 0375e8484b2a..415766dbfe6c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -265,71 +265,67 @@ static const uint8_t smu_v13_0_7_throttler_map[] = {
};
static int
-smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu,
- uint32_t *feature_mask, uint32_t num)
+smu_v13_0_7_init_allowed_features(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
- if (num > 2)
- return -EINVAL;
-
- memset(feature_mask, 0, sizeof(uint32_t) * num);
+ smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DATA_READ_BIT);
if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_IMU_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
}
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT);
if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VMEMP_SCALING_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VDDIO_MEM_SCALING_BIT);
}
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT);
if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT);
if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT);
if (adev->pm.pp_feature & PP_ULV_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
-
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT);
+
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_VCN_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THROTTLERS_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_TEMP_READ_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_MPCLK_DS_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_MPCLK_DS_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_PCC_DFLL_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_CG_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT);
if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCN_BIT);
if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) &&
(adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
+ smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_MMHUB_PG_BIT);
return 0;
}
@@ -2736,7 +2732,7 @@ static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu,
}
static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
- .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
+ .init_allowed_features = smu_v13_0_7_init_allowed_features,
.set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
.is_dpm_running = smu_v13_0_7_is_dpm_running,
.init_microcode = smu_v13_0_init_microcode,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
index d2aa5fabfca4..3c351ee41e68 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
@@ -264,14 +264,9 @@ static const uint8_t smu_v14_0_2_throttler_map[] = {
[THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
};
-static int
-smu_v14_0_2_get_allowed_feature_mask(struct smu_context *smu,
- uint32_t *feature_mask, uint32_t num)
+static int smu_v14_0_2_init_allowed_features(struct smu_context *smu)
{
- if (num > 2)
- return -EINVAL;
-
- memset(feature_mask, 0xff, sizeof(uint32_t) * num);
+ smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
return 0;
}
@@ -2757,7 +2752,7 @@ static int smu_v14_0_2_set_power_limit(struct smu_context *smu,
}
static const struct pptable_funcs smu_v14_0_2_ppt_funcs = {
- .get_allowed_feature_mask = smu_v14_0_2_get_allowed_feature_mask,
+ .init_allowed_features = smu_v14_0_2_init_allowed_features,
.set_default_dpm_table = smu_v14_0_2_set_default_dpm_table,
.i2c_init = smu_v14_0_2_i2c_control_init,
.i2c_fini = smu_v14_0_2_i2c_control_fini,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
index 0f7778410a3a..24848da90234 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
@@ -70,7 +70,7 @@
#define smu_apply_clocks_adjust_rules(smu) smu_ppt_funcs(apply_clocks_adjust_rules, 0, smu)
#define smu_notify_smc_display_config(smu) smu_ppt_funcs(notify_smc_display_config, 0, smu)
#define smu_run_btc(smu) smu_ppt_funcs(run_btc, 0, smu)
-#define smu_get_allowed_feature_mask(smu, feature_mask, num) smu_ppt_funcs(get_allowed_feature_mask, 0, smu, feature_mask, num)
+#define smu_init_allowed_features(smu) smu_ppt_funcs(init_allowed_features, 0, smu)
#define smu_set_watermarks_table(smu, clock_ranges) smu_ppt_funcs(set_watermarks_table, 0, smu, clock_ranges)
#define smu_thermal_temperature_range_update(smu, range, rw) smu_ppt_funcs(thermal_temperature_range_update, 0, smu, range, rw)
#define smu_register_irq_handler(smu) smu_ppt_funcs(register_irq_handler, 0, smu)
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 5/7] drm/amd/pm: Use feature bits data structure
2026-01-20 6:12 [PATCH v2 0/7] Refactor smu feature bit implementation Lijo Lazar
` (3 preceding siblings ...)
2026-01-20 6:12 ` [PATCH v2 4/7] drm/amd/pm: Initialize allowed feature list Lijo Lazar
@ 2026-01-20 6:12 ` Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 6/7] drm/amd/pm: Change get_enabled_mask signature Lijo Lazar
` (2 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Lijo Lazar @ 2026-01-20 6:12 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking.Zhang, Alexander.Deucher, Asad.Kamal, kevinyang.wang
Feature bits are not necessarily restricted to 64-bits. Use
smu_feature_bits data structure to represent feature mask for checking
DPM status.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 17 ++++++++++
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 21 +++++++-----
.../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 16 +++++----
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 26 ++++++++-------
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 26 ++++++++-------
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 28 +++++++++-------
.../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 25 ++++++++------
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 22 ++++++++-----
.../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 33 ++++++++++---------
.../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 28 +++++++++-------
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 22 +++++++++----
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 22 ++++++++-----
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 28 +++++++++-------
.../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 32 ++++++++++--------
.../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 18 +++++-----
.../drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 32 ++++++++++--------
16 files changed, 237 insertions(+), 159 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 7c63c631f6d4..c58290686f0d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -477,6 +477,23 @@ struct smu_feature_bits {
DECLARE_BITMAP(bits, SMU_FEATURE_MAX);
};
+/*
+ * Helpers for initializing smu_feature_bits statically.
+ * Use SMU_FEATURE_BIT_INIT() which automatically handles array indexing:
+ * static const struct smu_feature_bits example = {
+ * .bits = {
+ * SMU_FEATURE_BIT_INIT(5),
+ * SMU_FEATURE_BIT_INIT(10),
+ * SMU_FEATURE_BIT_INIT(65),
+ * SMU_FEATURE_BIT_INIT(100)
+ * }
+ * };
+ */
+#define SMU_FEATURE_BITS_ELEM(bit) ((bit) / BITS_PER_LONG)
+#define SMU_FEATURE_BITS_POS(bit) ((bit) % BITS_PER_LONG)
+#define SMU_FEATURE_BIT_INIT(bit) \
+ [SMU_FEATURE_BITS_ELEM(bit)] = (1UL << SMU_FEATURE_BITS_POS(bit))
+
enum smu_feature_list {
SMU_FEATURE_LIST_SUPPORTED,
SMU_FEATURE_LIST_ALLOWED,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index b22a0e91826d..814f24b7ccc4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -65,14 +65,15 @@
#define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000
#define SMU_FEATURES_HIGH_SHIFT 32
-#define SMC_DPM_FEATURE ( \
- FEATURE_DPM_PREFETCHER_MASK | \
- FEATURE_DPM_GFXCLK_MASK | \
- FEATURE_DPM_UCLK_MASK | \
- FEATURE_DPM_SOCCLK_MASK | \
- FEATURE_DPM_MP0CLK_MASK | \
- FEATURE_DPM_FCLK_MASK | \
- FEATURE_DPM_XGMI_MASK)
+static const struct smu_feature_bits arcturus_dpm_features = {
+ .bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_XGMI_BIT) }
+};
#define smnPCIE_ESM_CTRL 0x111003D0
@@ -1527,12 +1528,14 @@ static bool arcturus_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint64_t feature_enabled;
+ uint32_t feature_mask[2];
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ smu_feature_bits_to_arr32(&arcturus_dpm_features, feature_mask, 64);
+ return !!(feature_enabled & *(uint64_t *)feature_mask);
}
static int arcturus_dpm_set_vcn_enable(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index 4a5dcc893665..406acfbbbc63 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -60,11 +60,13 @@ static struct gfx_user_settings {
static uint32_t cyan_skillfish_sclk_default;
-#define FEATURE_MASK(feature) (1ULL << feature)
-#define SMC_DPM_FEATURE ( \
- FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_SOC_DPM_BIT) | \
- FEATURE_MASK(FEATURE_GFX_DPM_BIT))
+static const struct smu_feature_bits cyan_skillfish_dpm_features = {
+ .bits = {
+ SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_SOC_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT)
+ }
+};
static struct cmn2asic_msg_mapping cyan_skillfish_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
@@ -362,6 +364,7 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu)
struct amdgpu_device *adev = smu->adev;
int ret = 0;
uint64_t feature_enabled;
+ uint32_t feature_mask[2];
/* we need to re-init after suspend so return false */
if (adev->in_suspend)
@@ -378,7 +381,8 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu)
cyan_skillfish_get_smu_metrics_data(smu, METRICS_CURR_GFXCLK,
&cyan_skillfish_sclk_default);
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ smu_feature_bits_to_arr32(&cyan_skillfish_dpm_features, feature_mask, 64);
+ return !!(feature_enabled & *(uint64_t *)feature_mask);
}
static ssize_t cyan_skillfish_get_gpu_metrics(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index f14eed052526..f5be64395108 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -58,16 +58,18 @@
#undef pr_info
#undef pr_debug
-#define FEATURE_MASK(feature) (1ULL << feature)
-#define SMC_DPM_FEATURE ( \
- FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
- FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \
- FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
+static const struct smu_feature_bits navi10_dpm_features = {
+ .bits = {
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFX_PACE_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_DCEFCLK_BIT)
+ }
+};
#define SMU_11_0_GFX_BUSY_THRESHOLD 15
@@ -1620,12 +1622,14 @@ static bool navi10_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint64_t feature_enabled;
+ uint32_t feature_mask[2];
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ smu_feature_bits_to_arr32(&navi10_dpm_features, feature_mask, 64);
+ return !!(feature_enabled & *(uint64_t *)feature_mask);
}
static int navi10_get_fan_speed_rpm(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 98a02fc08214..7d23b6c8c538 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -60,16 +60,18 @@
#undef pr_info
#undef pr_debug
-#define FEATURE_MASK(feature) (1ULL << feature)
-#define SMC_DPM_FEATURE ( \
- FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
- FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
+static const struct smu_feature_bits sienna_cichlid_dpm_features = {
+ .bits = {
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_DCEFCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT)
+ }
+};
#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
@@ -1535,12 +1537,14 @@ static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint64_t feature_enabled;
+ uint32_t feature_mask[2];
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ smu_feature_bits_to_arr32(&sienna_cichlid_dpm_features, feature_mask, 64);
+ return !!(feature_enabled & *(uint64_t *)feature_mask);
}
static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 4de1778ea6b3..f8b76577d008 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -58,17 +58,19 @@
#define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L
#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
-#define FEATURE_MASK(feature) (1ULL << feature)
-#define SMC_DPM_FEATURE ( \
- FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
- FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
- FEATURE_MASK(FEATURE_GFX_DPM_BIT))
+static const struct smu_feature_bits vangogh_dpm_features = {
+ .bits = {
+ SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT)
+ }
+};
static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
@@ -505,6 +507,7 @@ static bool vangogh_is_dpm_running(struct smu_context *smu)
struct amdgpu_device *adev = smu->adev;
int ret = 0;
uint64_t feature_enabled;
+ uint32_t feature_mask[2];
/* we need to re-init after suspend so return false */
if (adev->in_suspend)
@@ -515,7 +518,8 @@ static bool vangogh_is_dpm_running(struct smu_context *smu)
if (ret)
return false;
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ smu_feature_bits_to_arr32(&vangogh_dpm_features, feature_mask, 64);
+ return !!(feature_enabled & *(uint64_t *)feature_mask);
}
static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 3b6a34644a92..4185c7282a11 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -61,15 +61,18 @@
[smu_feature] = {1, (aldebaran_feature)}
#define FEATURE_MASK(feature) (1ULL << feature)
-#define SMC_DPM_FEATURE ( \
- FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \
- FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \
- FEATURE_MASK(FEATURE_DPM_VCN_BIT))
+static const struct smu_feature_bits aldebaran_dpm_features = {
+ .bits = {
+ SMU_FEATURE_BIT_INIT(FEATURE_DATA_CALCULATIONS),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_LCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_XGMI_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_VCN_BIT)
+ }
+};
#define smnPCIE_ESM_CTRL 0x111003D0
@@ -1396,11 +1399,13 @@ static bool aldebaran_is_dpm_running(struct smu_context *smu)
{
int ret;
uint64_t feature_enabled;
+ uint32_t feature_mask[2];
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ smu_feature_bits_to_arr32(&aldebaran_dpm_features, feature_mask, 64);
+ return !!(feature_enabled & *(uint64_t *)feature_mask);
}
static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 9c4298736b28..0856c1c34d7a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -59,14 +59,16 @@
#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
-#define FEATURE_MASK(feature) (1ULL << feature)
-#define SMC_DPM_FEATURE ( \
- FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
+static const struct smu_feature_bits smu_v13_0_0_dpm_features = {
+ .bits = {
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT)
+ }
+};
#define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
@@ -690,12 +692,14 @@ static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint64_t feature_enabled;
+ uint32_t feature_mask[2];
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ smu_feature_bits_to_arr32(&smu_v13_0_0_dpm_features, feature_mask, 64);
+ return !!(feature_enabled & *(uint64_t *)feature_mask);
}
static int smu_v13_0_0_system_features_control(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 41c61362f7fc..741762f4bd2c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -52,24 +52,25 @@
#define mmMP1_SMN_C2PMSG_90 0x029a
#define mmMP1_SMN_C2PMSG_90_BASE_IDX 1
-#define FEATURE_MASK(feature) (1ULL << feature)
-
#define SMU_13_0_4_UMD_PSTATE_GFXCLK 938
#define SMU_13_0_4_UMD_PSTATE_SOCCLK 938
#define SMU_13_0_4_UMD_PSTATE_FCLK 1875
-#define SMC_DPM_FEATURE ( \
- FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
- FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_ISP_DPM_BIT) | \
- FEATURE_MASK(FEATURE_IPU_DPM_BIT) | \
- FEATURE_MASK(FEATURE_GFX_DPM_BIT))
+static const struct smu_feature_bits smu_v13_0_4_dpm_features = {
+ .bits = {
+ SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_ISP_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_IPU_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT)
+ }
+};
static struct cmn2asic_msg_mapping smu_v13_0_4_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
@@ -213,13 +214,15 @@ static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint64_t feature_enabled;
+ uint32_t feature_mask[2];
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ smu_feature_bits_to_arr32(&smu_v13_0_4_dpm_features, feature_mask, 64);
+ return !!(feature_enabled & *(uint64_t *)feature_mask);
}
static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
index e4be727789c0..7311162e50f0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
@@ -51,17 +51,19 @@
#define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4)
#define mmMP1_C2PMSG_33_BASE_IDX 0
-#define FEATURE_MASK(feature) (1ULL << feature)
-#define SMC_DPM_FEATURE ( \
- FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \
- FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
- FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)| \
- FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)| \
- FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT))
+static const struct smu_feature_bits smu_v13_0_5_dpm_features = {
+ .bits = {
+ SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT)
+ }
+};
static struct cmn2asic_msg_mapping smu_v13_0_5_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
@@ -231,13 +233,15 @@ static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint64_t feature_enabled;
+ uint32_t feature_mask[2];
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ smu_feature_bits_to_arr32(&smu_v13_0_5_dpm_features, feature_mask, 64);
+ return !!(feature_enabled & *(uint64_t *)feature_mask);
}
static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index bd893e95515f..97866e570192 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -76,12 +76,18 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin");
[smu_feature] = { 1, (smu_13_0_6_feature) }
#define FEATURE_MASK(feature) (1ULL << feature)
-#define SMC_DPM_FEATURE \
- (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \
- FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_UCLK) | \
- FEATURE_MASK(FEATURE_DPM_SOCCLK) | FEATURE_MASK(FEATURE_DPM_FCLK) | \
- FEATURE_MASK(FEATURE_DPM_LCLK) | FEATURE_MASK(FEATURE_DPM_XGMI) | \
- FEATURE_MASK(FEATURE_DPM_VCN))
+static const struct smu_feature_bits smu_v13_0_6_dpm_features = {
+ .bits = {
+ SMU_FEATURE_BIT_INIT(FEATURE_DATA_CALCULATION),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_LCLK),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_XGMI),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_VCN)
+ }
+};
#define smnPCIE_ESM_CTRL 0x93D0
#define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288
@@ -2284,6 +2290,7 @@ static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
{
int ret;
uint64_t feature_enabled;
+ uint32_t feature_mask[2];
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12))
return smu_v13_0_12_is_dpm_running(smu);
@@ -2293,7 +2300,8 @@ static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
if (ret)
return false;
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ smu_feature_bits_to_arr32(&smu_v13_0_6_dpm_features, feature_mask, 64);
+ return !!(feature_enabled & *(uint64_t *)feature_mask);
}
static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 415766dbfe6c..eeff6c874635 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -59,14 +59,16 @@
#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
-#define FEATURE_MASK(feature) (1ULL << feature)
-#define SMC_DPM_FEATURE ( \
- FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
+static const struct smu_feature_bits smu_v13_0_7_dpm_features = {
+ .bits = {
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT)
+ }
+};
#define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 0x3b10028
@@ -698,12 +700,14 @@ static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint64_t feature_enabled;
+ uint32_t feature_mask[2];
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ smu_feature_bits_to_arr32(&smu_v13_0_7_dpm_features, feature_mask, 64);
+ return !!(feature_enabled & *(uint64_t *)feature_mask);
}
static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index 7f70f79c3b2f..2331dbb9181a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -55,17 +55,19 @@
#define SMU_13_0_1_UMD_PSTATE_SOCCLK 678
#define SMU_13_0_1_UMD_PSTATE_FCLK 1800
-#define FEATURE_MASK(feature) (1ULL << feature)
-#define SMC_DPM_FEATURE ( \
- FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
- FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
- FEATURE_MASK(FEATURE_GFX_DPM_BIT))
+static const struct smu_feature_bits yellow_carp_dpm_features = {
+ .bits = {
+ SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT)
+ }
+};
static struct cmn2asic_msg_mapping yellow_carp_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
@@ -258,13 +260,15 @@ static bool yellow_carp_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint64_t feature_enabled;
+ uint32_t feature_mask[2];
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ smu_feature_bits_to_arr32(&yellow_carp_dpm_features, feature_mask, 64);
+ return !!(feature_enabled & *(uint64_t *)feature_mask);
}
static int yellow_carp_post_smu_init(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
index a4e376e8328c..019e43fdecd6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
@@ -72,19 +72,21 @@
#define SMU_14_0_4_UMD_PSTATE_GFXCLK 938
#define SMU_14_0_4_UMD_PSTATE_SOCCLK 938
-#define FEATURE_MASK(feature) (1ULL << feature)
-#define SMC_DPM_FEATURE ( \
- FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
- FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
- FEATURE_MASK(FEATURE_ISP_DPM_BIT)| \
- FEATURE_MASK(FEATURE_IPU_DPM_BIT) | \
- FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \
- FEATURE_MASK(FEATURE_VPE_DPM_BIT))
+static const struct smu_feature_bits smu_v14_0_0_dpm_features = {
+ .bits = {
+ SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_ISP_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_IPU_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_VPE_DPM_BIT)
+ }
+};
enum smu_mall_pg_config {
SMU_MALL_PG_CONFIG_PMFW_CONTROL = 0,
@@ -471,13 +473,15 @@ static bool smu_v14_0_0_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint64_t feature_enabled;
+ uint32_t feature_mask[2];
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ smu_feature_bits_to_arr32(&smu_v14_0_0_dpm_features, feature_mask, 64);
+ return !!(feature_enabled & *(uint64_t *)feature_mask);
}
static int smu_v14_0_0_set_watermarks_table(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
index 3c351ee41e68..eb8bad2de1cc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
@@ -56,13 +56,13 @@
#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
-#define FEATURE_MASK(feature) (1ULL << feature)
-#define SMC_DPM_FEATURE ( \
- FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
- FEATURE_MASK(FEATURE_DPM_FCLK_BIT))
+static const struct smu_feature_bits smu_v14_0_2_dpm_features = {
+ .bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT) }
+};
#define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
#define DEBUGSMC_MSG_Mode1Reset 2
@@ -590,12 +590,14 @@ static bool smu_v14_0_2_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint64_t feature_enabled;
+ uint32_t feature_mask[2];
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ smu_feature_bits_to_arr32(&smu_v14_0_2_dpm_features, feature_mask, 64);
+ return !!(feature_enabled & *(uint64_t *)feature_mask);
}
static uint32_t smu_v14_0_2_get_throttler_status(SmuMetrics_t *metrics)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c
index b48444706c1e..d66e9a1a0ef8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c
@@ -70,19 +70,21 @@
#define SMU_15_0_UMD_PSTATE_FCLK 1800
-#define FEATURE_MASK(feature) (1ULL << feature)
-#define SMC_DPM_FEATURE ( \
- FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
- FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
- FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
- FEATURE_MASK(FEATURE_ISP_DPM_BIT)| \
- FEATURE_MASK(FEATURE_NPU_DPM_BIT) | \
- FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \
- FEATURE_MASK(FEATURE_VPE_DPM_BIT))
+static const struct smu_feature_bits smu_v15_0_0_dpm_features = {
+ .bits = {
+ SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_ISP_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_NPU_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT),
+ SMU_FEATURE_BIT_INIT(FEATURE_VPE_DPM_BIT)
+ }
+};
enum smu_mall_pg_config {
SMU_MALL_PG_CONFIG_PMFW_CONTROL = 0,
@@ -445,13 +447,15 @@ static bool smu_v15_0_0_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
uint64_t feature_enabled;
+ uint32_t feature_mask[2];
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ smu_feature_bits_to_arr32(&smu_v15_0_0_dpm_features, feature_mask, 64);
+ return !!(feature_enabled & *(uint64_t *)feature_mask);
}
static int smu_v15_0_0_set_watermarks_table(struct smu_context *smu,
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 6/7] drm/amd/pm: Change get_enabled_mask signature
2026-01-20 6:12 [PATCH v2 0/7] Refactor smu feature bit implementation Lijo Lazar
` (4 preceding siblings ...)
2026-01-20 6:12 ` [PATCH v2 5/7] drm/amd/pm: Use feature bits data structure Lijo Lazar
@ 2026-01-20 6:12 ` Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 7/7] drm/amd/pm: Add default feature number definition Lijo Lazar
2026-01-22 10:44 ` [PATCH v2 0/7] Refactor smu feature bit implementation Lazar, Lijo
7 siblings, 0 replies; 10+ messages in thread
From: Lijo Lazar @ 2026-01-20 6:12 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking.Zhang, Alexander.Deucher, Asad.Kamal, kevinyang.wang
Use smu_feature_bits instead of uint64_t pointer and operate on
feature bits.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
---
v2:
Use to_arr32 instead of direct assignment
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 17 +++--
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 9 ++-
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 7 +-
.../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 14 ++--
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 7 +-
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 7 +-
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 7 +-
.../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 4 +-
.../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 7 +-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 7 +-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 20 +++---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 7 +-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 7 +-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 11 ++-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 7 +-
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 7 +-
.../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 7 +-
.../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 7 +-
.../drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 7 +-
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 72 +++++++++----------
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 2 +-
21 files changed, 123 insertions(+), 117 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index e75dd0152ea7..62d34f69149c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1643,7 +1643,7 @@ static int smu_smc_hw_setup(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
uint8_t pcie_gen = 0, pcie_width = 0;
- uint64_t features_supported;
+ struct smu_feature_bits features_supported;
int ret = 0;
switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
@@ -1804,7 +1804,7 @@ static int smu_smc_hw_setup(struct smu_context *smu)
return ret;
}
smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED,
- (unsigned long *)&features_supported);
+ features_supported.bits);
if (!smu_is_dpm_running(smu))
dev_info(adev->dev, "dpm has been disabled\n");
@@ -3149,10 +3149,19 @@ static int smu_read_sensor(void *handle,
*((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100;
*size = 4;
break;
- case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
- ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);
+ case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: {
+ struct smu_feature_bits feature_mask;
+ uint32_t features[2];
+
+ /* TBD: need to handle for > 64 bits */
+ ret = smu_feature_get_enabled_mask(smu, &feature_mask);
+ if (!ret) {
+ smu_feature_bits_to_arr32(&feature_mask, features, 64);
+ *(uint64_t *)data = *(uint64_t *)features;
+ }
*size = 8;
break;
+ }
case AMDGPU_PP_SENSOR_UVD_POWER:
*(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
*size = 4;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index c58290686f0d..4019ef859504 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -1229,7 +1229,8 @@ struct pptable_funcs {
* on the SMU.
* &feature_mask: Enabled feature mask.
*/
- int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask);
+ int (*get_enabled_mask)(struct smu_context *smu,
+ struct smu_feature_bits *feature_mask);
/**
* @feature_is_enabled: Test if a feature is enabled.
@@ -2061,6 +2062,12 @@ static inline bool smu_feature_bits_empty(const struct smu_feature_bits *bits,
return bitmap_empty(bits->bits, nbits);
}
+static inline bool smu_feature_bits_full(const struct smu_feature_bits *bits,
+ unsigned int nbits)
+{
+ return bitmap_full(bits->bits, nbits);
+}
+
static inline void smu_feature_bits_copy(struct smu_feature_bits *dst,
const unsigned long *src,
unsigned int nbits)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 814f24b7ccc4..0c4afd1e1aab 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -1527,15 +1527,14 @@ static int arcturus_set_performance_level(struct smu_context *smu,
static bool arcturus_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
- uint64_t feature_enabled;
- uint32_t feature_mask[2];
+ struct smu_feature_bits feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- smu_feature_bits_to_arr32(&arcturus_dpm_features, feature_mask, 64);
- return !!(feature_enabled & *(uint64_t *)feature_mask);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ arcturus_dpm_features.bits);
}
static int arcturus_dpm_set_vcn_enable(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index 406acfbbbc63..87953a4d0a43 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -363,8 +363,7 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
int ret = 0;
- uint64_t feature_enabled;
- uint32_t feature_mask[2];
+ struct smu_feature_bits feature_enabled;
/* we need to re-init after suspend so return false */
if (adev->in_suspend)
@@ -381,8 +380,8 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu)
cyan_skillfish_get_smu_metrics_data(smu, METRICS_CURR_GFXCLK,
&cyan_skillfish_sclk_default);
- smu_feature_bits_to_arr32(&cyan_skillfish_dpm_features, feature_mask, 64);
- return !!(feature_enabled & *(uint64_t *)feature_mask);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ cyan_skillfish_dpm_features.bits);
}
static ssize_t cyan_skillfish_get_gpu_metrics(struct smu_context *smu,
@@ -569,12 +568,13 @@ static int cyan_skillfish_get_dpm_ultimate_freq(struct smu_context *smu,
return 0;
}
-static int cyan_skillfish_get_enabled_mask(struct smu_context *smu,
- uint64_t *feature_mask)
+static int
+cyan_skillfish_get_enabled_mask(struct smu_context *smu,
+ struct smu_feature_bits *feature_mask)
{
if (!feature_mask)
return -EINVAL;
- memset(feature_mask, 0xff, sizeof(*feature_mask));
+ smu_feature_bits_fill(feature_mask);
return 0;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index f5be64395108..737bfdfb814c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1621,15 +1621,14 @@ static int navi10_display_config_changed(struct smu_context *smu)
static bool navi10_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
- uint64_t feature_enabled;
- uint32_t feature_mask[2];
+ struct smu_feature_bits feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- smu_feature_bits_to_arr32(&navi10_dpm_features, feature_mask, 64);
- return !!(feature_enabled & *(uint64_t *)feature_mask);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ navi10_dpm_features.bits);
}
static int navi10_get_fan_speed_rpm(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 7d23b6c8c538..6268bc5ed3e6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1536,15 +1536,14 @@ static int sienna_cichlid_display_config_changed(struct smu_context *smu)
static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
- uint64_t feature_enabled;
- uint32_t feature_mask[2];
+ struct smu_feature_bits feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- smu_feature_bits_to_arr32(&sienna_cichlid_dpm_features, feature_mask, 64);
- return !!(feature_enabled & *(uint64_t *)feature_mask);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ sienna_cichlid_dpm_features.bits);
}
static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index f8b76577d008..08179840697e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -506,8 +506,7 @@ static bool vangogh_is_dpm_running(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
int ret = 0;
- uint64_t feature_enabled;
- uint32_t feature_mask[2];
+ struct smu_feature_bits feature_enabled;
/* we need to re-init after suspend so return false */
if (adev->in_suspend)
@@ -518,8 +517,8 @@ static bool vangogh_is_dpm_running(struct smu_context *smu)
if (ret)
return false;
- smu_feature_bits_to_arr32(&vangogh_dpm_features, feature_mask, 64);
- return !!(feature_enabled & *(uint64_t *)feature_mask);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ vangogh_dpm_features.bits);
}
static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index 5346b60b09b9..31e21ff8859a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -1434,11 +1434,11 @@ static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)
}
static int renoir_get_enabled_mask(struct smu_context *smu,
- uint64_t *feature_mask)
+ struct smu_feature_bits *feature_mask)
{
if (!feature_mask)
return -EINVAL;
- memset(feature_mask, 0xff, sizeof(*feature_mask));
+ smu_feature_bits_fill(feature_mask);
return 0;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 4185c7282a11..ad23682217ee 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -1398,14 +1398,13 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_
static bool aldebaran_is_dpm_running(struct smu_context *smu)
{
int ret;
- uint64_t feature_enabled;
- uint32_t feature_mask[2];
+ struct smu_feature_bits feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- smu_feature_bits_to_arr32(&aldebaran_dpm_features, feature_mask, 64);
- return !!(feature_enabled & *(uint64_t *)feature_mask);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ aldebaran_dpm_features.bits);
}
static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 0856c1c34d7a..de770c10da3d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -691,15 +691,14 @@ static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu)
static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
- uint64_t feature_enabled;
- uint32_t feature_mask[2];
+ struct smu_feature_bits feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- smu_feature_bits_to_arr32(&smu_v13_0_0_dpm_features, feature_mask, 64);
- return !!(feature_enabled & *(uint64_t *)feature_mask);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ smu_v13_0_0_dpm_features.bits);
}
static int smu_v13_0_0_system_features_control(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
index 9a34e5460b35..3d60d3c1e585 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
@@ -52,10 +52,13 @@
#define SMU_13_0_12_FEA_MAP(smu_feature, smu_13_0_12_feature) \
[smu_feature] = { 1, (smu_13_0_12_feature) }
-#define FEATURE_MASK(feature) (1ULL << feature)
-#define SMC_DPM_FEATURE \
- (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \
- FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_FCLK))
+static const struct smu_feature_bits smu_v13_0_12_dpm_features = {
+ .bits = {
+ SMU_FEATURE_BIT_INIT(FEATURE_DATA_CALCULATION),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK),
+ SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK)
+ }
+};
#define NUM_JPEG_RINGS_FW 10
#define NUM_JPEG_RINGS_GPU_METRICS(gpu_metrics) \
@@ -199,14 +202,14 @@ void smu_v13_0_12_tables_fini(struct smu_context *smu)
}
static int smu_v13_0_12_get_enabled_mask(struct smu_context *smu,
- uint64_t *feature_mask)
+ struct smu_feature_bits *feature_mask)
{
int ret;
ret = smu_cmn_get_enabled_mask(smu, feature_mask);
if (ret == -EIO) {
- *feature_mask = 0;
+ smu_feature_bits_clearall(feature_mask);
ret = 0;
}
@@ -372,14 +375,15 @@ int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu)
bool smu_v13_0_12_is_dpm_running(struct smu_context *smu)
{
int ret;
- uint64_t feature_enabled;
+ struct smu_feature_bits feature_enabled;
ret = smu_v13_0_12_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- return !!(feature_enabled & SMC_DPM_FEATURE);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ smu_v13_0_12_dpm_features.bits);
}
int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 741762f4bd2c..75b90ac0c29c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -213,16 +213,15 @@ static int smu_v13_0_4_fini_smc_tables(struct smu_context *smu)
static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
- uint64_t feature_enabled;
- uint32_t feature_mask[2];
+ struct smu_feature_bits feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- smu_feature_bits_to_arr32(&smu_v13_0_4_dpm_features, feature_mask, 64);
- return !!(feature_enabled & *(uint64_t *)feature_mask);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ smu_v13_0_4_dpm_features.bits);
}
static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
index 7311162e50f0..8ee5002e3d6b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
@@ -232,16 +232,15 @@ static int smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
- uint64_t feature_enabled;
- uint32_t feature_mask[2];
+ struct smu_feature_bits feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- smu_feature_bits_to_arr32(&smu_v13_0_5_dpm_features, feature_mask, 64);
- return !!(feature_enabled & *(uint64_t *)feature_mask);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ smu_v13_0_5_dpm_features.bits);
}
static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 97866e570192..be7d77eee2b0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -2272,14 +2272,14 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu,
}
static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu,
- uint64_t *feature_mask)
+ struct smu_feature_bits *feature_mask)
{
int ret;
ret = smu_cmn_get_enabled_mask(smu, feature_mask);
if (ret == -EIO && !smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
- *feature_mask = 0;
+ smu_feature_bits_clearall(feature_mask);
ret = 0;
}
@@ -2289,8 +2289,7 @@ static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu,
static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
{
int ret;
- uint64_t feature_enabled;
- uint32_t feature_mask[2];
+ struct smu_feature_bits feature_enabled;
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12))
return smu_v13_0_12_is_dpm_running(smu);
@@ -2300,8 +2299,8 @@ static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
if (ret)
return false;
- smu_feature_bits_to_arr32(&smu_v13_0_6_dpm_features, feature_mask, 64);
- return !!(feature_enabled & *(uint64_t *)feature_mask);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ smu_v13_0_6_dpm_features.bits);
}
static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index eeff6c874635..fe3d6bfe6812 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -699,15 +699,14 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu)
static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
- uint64_t feature_enabled;
- uint32_t feature_mask[2];
+ struct smu_feature_bits feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- smu_feature_bits_to_arr32(&smu_v13_0_7_dpm_features, feature_mask, 64);
- return !!(feature_enabled & *(uint64_t *)feature_mask);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ smu_v13_0_7_dpm_features.bits);
}
static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index 2331dbb9181a..f9789b1fcbf8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -259,16 +259,15 @@ static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
static bool yellow_carp_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
- uint64_t feature_enabled;
- uint32_t feature_mask[2];
+ struct smu_feature_bits feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- smu_feature_bits_to_arr32(&yellow_carp_dpm_features, feature_mask, 64);
- return !!(feature_enabled & *(uint64_t *)feature_mask);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ yellow_carp_dpm_features.bits);
}
static int yellow_carp_post_smu_init(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
index 019e43fdecd6..dbdf7653cc53 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
@@ -472,16 +472,15 @@ static int smu_v14_0_0_read_sensor(struct smu_context *smu,
static bool smu_v14_0_0_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
- uint64_t feature_enabled;
- uint32_t feature_mask[2];
+ struct smu_feature_bits feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- smu_feature_bits_to_arr32(&smu_v14_0_0_dpm_features, feature_mask, 64);
- return !!(feature_enabled & *(uint64_t *)feature_mask);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ smu_v14_0_0_dpm_features.bits);
}
static int smu_v14_0_0_set_watermarks_table(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
index eb8bad2de1cc..becfd356b4e7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
@@ -589,15 +589,14 @@ static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu)
static bool smu_v14_0_2_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
- uint64_t feature_enabled;
- uint32_t feature_mask[2];
+ struct smu_feature_bits feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- smu_feature_bits_to_arr32(&smu_v14_0_2_dpm_features, feature_mask, 64);
- return !!(feature_enabled & *(uint64_t *)feature_mask);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ smu_v14_0_2_dpm_features.bits);
}
static uint32_t smu_v14_0_2_get_throttler_status(SmuMetrics_t *metrics)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c
index d66e9a1a0ef8..c3f22844ba2f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c
@@ -446,16 +446,15 @@ static int smu_v15_0_0_read_sensor(struct smu_context *smu,
static bool smu_v15_0_0_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
- uint64_t feature_enabled;
- uint32_t feature_mask[2];
+ struct smu_feature_bits feature_enabled;
ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
- smu_feature_bits_to_arr32(&smu_v15_0_0_dpm_features, feature_mask, 64);
- return !!(feature_enabled & *(uint64_t *)feature_mask);
+ return smu_feature_bits_test_mask(&feature_enabled,
+ smu_v15_0_0_dpm_features.bits);
}
static int smu_v15_0_0_set_watermarks_table(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 9bb7e3760c0f..a9e0b52bc739 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -690,7 +690,7 @@ int smu_cmn_feature_is_supported(struct smu_context *smu,
}
static int __smu_get_enabled_features(struct smu_context *smu,
- uint64_t *enabled_features)
+ struct smu_feature_bits *enabled_features)
{
return smu_cmn_call_asic_func(get_enabled_mask, smu, enabled_features);
}
@@ -699,7 +699,7 @@ int smu_cmn_feature_is_enabled(struct smu_context *smu,
enum smu_feature_mask mask)
{
struct amdgpu_device *adev = smu->adev;
- uint64_t enabled_features;
+ struct smu_feature_bits enabled_features;
int feature_id;
if (__smu_get_enabled_features(smu, &enabled_features)) {
@@ -712,7 +712,8 @@ int smu_cmn_feature_is_enabled(struct smu_context *smu,
* enabled. Also considering they have no feature_map available, the
* check here can avoid unwanted feature_map check below.
*/
- if (enabled_features == ULLONG_MAX)
+ if (smu_feature_bits_full(&enabled_features,
+ smu->smu_feature.feature_num))
return 1;
feature_id = smu_cmn_to_asic_specific_index(smu,
@@ -721,7 +722,7 @@ int smu_cmn_feature_is_enabled(struct smu_context *smu,
if (feature_id < 0)
return 0;
- return test_bit(feature_id, (unsigned long *)&enabled_features);
+ return smu_feature_bits_is_set(&enabled_features, feature_id);
}
bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
@@ -763,45 +764,38 @@ bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
}
int smu_cmn_get_enabled_mask(struct smu_context *smu,
- uint64_t *feature_mask)
+ struct smu_feature_bits *feature_mask)
{
- uint32_t *feature_mask_high;
- uint32_t *feature_mask_low;
+ uint32_t features[2];
int ret = 0, index = 0;
if (!feature_mask)
return -EINVAL;
- feature_mask_low = &((uint32_t *)feature_mask)[0];
- feature_mask_high = &((uint32_t *)feature_mask)[1];
-
index = smu_cmn_to_asic_specific_index(smu,
CMN2ASIC_MAPPING_MSG,
SMU_MSG_GetEnabledSmuFeatures);
if (index > 0) {
- ret = smu_cmn_send_smc_msg_with_param(smu,
- SMU_MSG_GetEnabledSmuFeatures,
- 0,
- feature_mask_low);
+ ret = smu_cmn_send_smc_msg_with_param(
+ smu, SMU_MSG_GetEnabledSmuFeatures, 0, &features[0]);
if (ret)
return ret;
- ret = smu_cmn_send_smc_msg_with_param(smu,
- SMU_MSG_GetEnabledSmuFeatures,
- 1,
- feature_mask_high);
+ ret = smu_cmn_send_smc_msg_with_param(
+ smu, SMU_MSG_GetEnabledSmuFeatures, 1, &features[1]);
} else {
- ret = smu_cmn_send_smc_msg(smu,
- SMU_MSG_GetEnabledSmuFeaturesHigh,
- feature_mask_high);
+ ret = smu_cmn_send_smc_msg(
+ smu, SMU_MSG_GetEnabledSmuFeaturesHigh, &features[1]);
if (ret)
return ret;
- ret = smu_cmn_send_smc_msg(smu,
- SMU_MSG_GetEnabledSmuFeaturesLow,
- feature_mask_low);
+ ret = smu_cmn_send_smc_msg(
+ smu, SMU_MSG_GetEnabledSmuFeaturesLow, &features[0]);
}
+ if (!ret)
+ smu_feature_bits_from_arr32(feature_mask, features, 64);
+
return ret;
}
@@ -886,7 +880,8 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
char *buf)
{
int8_t sort_feature[MAX(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)];
- uint64_t feature_mask;
+ struct smu_feature_bits feature_mask;
+ uint32_t features[2];
int i, feature_index;
uint32_t count = 0;
size_t size = 0;
@@ -894,8 +889,10 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
if (__smu_get_enabled_features(smu, &feature_mask))
return 0;
- size = sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n",
- upper_32_bits(feature_mask), lower_32_bits(feature_mask));
+ /* TBD: Need to handle for > 64 bits */
+ smu_feature_bits_to_arr32(&feature_mask, features, 64);
+ size = sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n",
+ features[1], features[0]);
memset(sort_feature, -1, sizeof(sort_feature));
@@ -916,12 +913,13 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
if (sort_feature[feature_index] < 0)
continue;
- size += sysfs_emit_at(buf, size, "%02d. %-20s (%2d) : %s\n",
- count++,
- smu_get_feature_name(smu, sort_feature[feature_index]),
- feature_index,
- !!test_bit(feature_index, (unsigned long *)&feature_mask) ?
- "enabled" : "disabled");
+ size += sysfs_emit_at(
+ buf, size, "%02d. %-20s (%2d) : %s\n", count++,
+ smu_get_feature_name(smu, sort_feature[feature_index]),
+ feature_index,
+ smu_feature_bits_is_set(&feature_mask, feature_index) ?
+ "enabled" :
+ "disabled");
}
return size;
@@ -931,7 +929,8 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
uint64_t new_mask)
{
int ret = 0;
- uint64_t feature_mask;
+ struct smu_feature_bits feature_mask;
+ uint64_t feature_mask_u64;
uint64_t feature_2_enabled = 0;
uint64_t feature_2_disabled = 0;
@@ -939,8 +938,9 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
if (ret)
return ret;
- feature_2_enabled = ~feature_mask & new_mask;
- feature_2_disabled = feature_mask & ~new_mask;
+ feature_mask_u64 = *(uint64_t *)feature_mask.bits;
+ feature_2_enabled = ~feature_mask_u64 & new_mask;
+ feature_2_disabled = feature_mask_u64 & ~new_mask;
if (feature_2_enabled) {
ret = smu_cmn_feature_update_enable_state(smu,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
index 92ad2ece7a36..b7bfddc65fb2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
@@ -141,7 +141,7 @@ bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
enum smu_clk_type clk_type);
int smu_cmn_get_enabled_mask(struct smu_context *smu,
- uint64_t *feature_mask);
+ struct smu_feature_bits *feature_mask);
uint64_t smu_cmn_get_indep_throttler_status(
const unsigned long dep_status,
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 7/7] drm/amd/pm: Add default feature number definition
2026-01-20 6:12 [PATCH v2 0/7] Refactor smu feature bit implementation Lijo Lazar
` (5 preceding siblings ...)
2026-01-20 6:12 ` [PATCH v2 6/7] drm/amd/pm: Change get_enabled_mask signature Lijo Lazar
@ 2026-01-20 6:12 ` Lijo Lazar
2026-01-22 10:44 ` [PATCH v2 0/7] Refactor smu feature bit implementation Lazar, Lijo
7 siblings, 0 replies; 10+ messages in thread
From: Lijo Lazar @ 2026-01-20 6:12 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking.Zhang, Alexander.Deucher, Asad.Kamal, kevinyang.wang
The number of default features could be different from the actual width
of the bitmap. Use a different definition for it. Also increase the max
width of bitmap to 128.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 3 ++-
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 6 ++++--
7 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 62d34f69149c..5ea4c6dab2de 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1352,7 +1352,7 @@ static int smu_sw_init(struct amdgpu_ip_block *ip_block)
int i, ret;
smu->pool_size = adev->pm.smu_prv_buffer_size;
- smu_feature_init(smu, SMU_FEATURE_MAX);
+ smu_feature_init(smu, SMU_FEATURE_NUM_DEFAULT);
INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 4019ef859504..512493a8452b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -471,7 +471,8 @@ struct smu_power_context {
struct smu_power_gate power_gate;
};
-#define SMU_FEATURE_MAX (64)
+#define SMU_FEATURE_NUM_DEFAULT (64)
+#define SMU_FEATURE_MAX (128)
struct smu_feature_bits {
DECLARE_BITMAP(bits, SMU_FEATURE_MAX);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 1d0f9f8ddf9b..56efcfa327df 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -751,7 +751,7 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu)
uint32_t feature_mask[2];
if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
- feature->feature_num < 64) {
+ feature->feature_num < SMU_FEATURE_NUM_DEFAULT) {
ret = -EINVAL;
goto failed;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index d9b1725c3afc..c4a994445b80 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -762,7 +762,7 @@ int smu_v13_0_set_allowed_mask(struct smu_context *smu)
uint32_t feature_mask[2];
if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
- feature->feature_num < 64)
+ feature->feature_num < SMU_FEATURE_NUM_DEFAULT)
return -EINVAL;
smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index 5c991e2e15ff..79ce32c4bb4d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
@@ -747,7 +747,7 @@ int smu_v14_0_set_allowed_mask(struct smu_context *smu)
uint32_t feature_mask[2];
if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
- feature->feature_num < 64)
+ feature->feature_num < SMU_FEATURE_NUM_DEFAULT)
return -EINVAL;
smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
index d77eaac556d9..a2854d528bab 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
@@ -716,7 +716,7 @@ int smu_v15_0_set_allowed_mask(struct smu_context *smu)
uint32_t feature_mask[2];
if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
- feature->feature_num < 64)
+ feature->feature_num < SMU_FEATURE_NUM_DEFAULT)
return -EINVAL;
smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index a9e0b52bc739..6fd50c2fd20e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -794,7 +794,8 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu,
}
if (!ret)
- smu_feature_bits_from_arr32(feature_mask, features, 64);
+ smu_feature_bits_from_arr32(feature_mask, features,
+ SMU_FEATURE_NUM_DEFAULT);
return ret;
}
@@ -909,7 +910,8 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
size += sysfs_emit_at(buf, size, "%-2s. %-20s %-3s : %-s\n",
"No", "Feature", "Bit", "State");
- for (feature_index = 0; feature_index < SMU_FEATURE_MAX; feature_index++) {
+ for (feature_index = 0; feature_index < smu->smu_feature.feature_num;
+ feature_index++) {
if (sort_feature[feature_index] < 0)
continue;
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 0/7] Refactor smu feature bit implementation
2026-01-20 6:12 [PATCH v2 0/7] Refactor smu feature bit implementation Lijo Lazar
` (6 preceding siblings ...)
2026-01-20 6:12 ` [PATCH v2 7/7] drm/amd/pm: Add default feature number definition Lijo Lazar
@ 2026-01-22 10:44 ` Lazar, Lijo
2026-01-23 6:06 ` Kamal, Asad
7 siblings, 1 reply; 10+ messages in thread
From: Lazar, Lijo @ 2026-01-22 10:44 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking.Zhang, Alexander.Deucher, Asad.Kamal, kevinyang.wang
<ping>
On 20-Jan-26 11:42 AM, Lijo Lazar wrote:
> Presently a 64-bit bitmask is used to represent the PM features enabled/supported by SOC. The
> number of features has grown to nearly 64 and could extend beyond that. Instead of using a 64-bit
> mask, implement a data structure around bitmap and move the implementation to use the datastructure
> instead of directly operating on 64-bit bitmask.
>
> v2:
> Use to_arr32 instead of direct assignment
>
> Lijo Lazar (7):
> drm/amd/pm: Add smu feature bits data struct
> drm/amd/pm: Add smu feature interface functions
> drm/amd/pm: Remove unused logic in SMUv14.0.2
> drm/amd/pm: Initialize allowed feature list
> drm/amd/pm: Use feature bits data structure
> drm/amd/pm: Change get_enabled_mask signature
> drm/amd/pm: Add default feature number definition
>
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 48 ++---
> drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 204 +++++++++++++++++-
> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 33 ++-
> .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 24 ++-
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 119 +++++-----
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 116 +++++-----
> .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 5 +-
> .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 29 +--
> .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 4 +-
> .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 37 ++--
> .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 6 +-
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 58 +++--
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 20 +-
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 34 +--
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 29 +--
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 39 ++--
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 103 +++++----
> .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 29 +--
> .../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 6 +-
> .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 33 +--
> .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 69 ++----
> .../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 6 +-
> .../drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 33 +--
> drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 82 +++----
> drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 2 +-
> drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 2 +-
> 26 files changed, 662 insertions(+), 508 deletions(-)
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH v2 0/7] Refactor smu feature bit implementation
2026-01-22 10:44 ` [PATCH v2 0/7] Refactor smu feature bit implementation Lazar, Lijo
@ 2026-01-23 6:06 ` Kamal, Asad
0 siblings, 0 replies; 10+ messages in thread
From: Kamal, Asad @ 2026-01-23 6:06 UTC (permalink / raw)
To: Lazar, Lijo, amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking, Deucher, Alexander, Wang, Yang(Kevin)
[AMD Official Use Only - AMD Internal Distribution Only]
Series is
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Thanks & Regards
Asad
-----Original Message-----
From: Lazar, Lijo <Lijo.Lazar@amd.com>
Sent: Thursday, January 22, 2026 4:14 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Kamal, Asad <Asad.Kamal@amd.com>; Wang, Yang(Kevin) <KevinYang.Wang@amd.com>
Subject: Re: [PATCH v2 0/7] Refactor smu feature bit implementation
<ping>
On 20-Jan-26 11:42 AM, Lijo Lazar wrote:
> Presently a 64-bit bitmask is used to represent the PM features
> enabled/supported by SOC. The number of features has grown to nearly
> 64 and could extend beyond that. Instead of using a 64-bit mask,
> implement a data structure around bitmap and move the implementation to use the datastructure instead of directly operating on 64-bit bitmask.
>
> v2:
> Use to_arr32 instead of direct assignment
>
> Lijo Lazar (7):
> drm/amd/pm: Add smu feature bits data struct
> drm/amd/pm: Add smu feature interface functions
> drm/amd/pm: Remove unused logic in SMUv14.0.2
> drm/amd/pm: Initialize allowed feature list
> drm/amd/pm: Use feature bits data structure
> drm/amd/pm: Change get_enabled_mask signature
> drm/amd/pm: Add default feature number definition
>
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 48 ++---
> drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 204 +++++++++++++++++-
> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 33 ++-
> .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 24 ++-
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 119 +++++-----
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 116 +++++-----
> .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 5 +-
> .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 29 +--
> .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 4 +-
> .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 37 ++--
> .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 6 +-
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 58 +++--
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 20 +-
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 34 +--
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 29 +--
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 39 ++--
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 103 +++++----
> .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 29 +--
> .../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 6 +-
> .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 33 +--
> .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 69 ++----
> .../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 6 +-
> .../drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 33 +--
> drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 82 +++----
> drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 2 +-
> drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 2 +-
> 26 files changed, 662 insertions(+), 508 deletions(-)
>
^ permalink raw reply [flat|nested] 10+ messages in thread
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Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
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2026-01-20 6:12 [PATCH v2 0/7] Refactor smu feature bit implementation Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 1/7] drm/amd/pm: Add smu feature bits data struct Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 2/7] drm/amd/pm: Add smu feature interface functions Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 3/7] drm/amd/pm: Remove unused logic in SMUv14.0.2 Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 4/7] drm/amd/pm: Initialize allowed feature list Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 5/7] drm/amd/pm: Use feature bits data structure Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 6/7] drm/amd/pm: Change get_enabled_mask signature Lijo Lazar
2026-01-20 6:12 ` [PATCH v2 7/7] drm/amd/pm: Add default feature number definition Lijo Lazar
2026-01-22 10:44 ` [PATCH v2 0/7] Refactor smu feature bit implementation Lazar, Lijo
2026-01-23 6:06 ` Kamal, Asad
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