* [PATCH 1/3] drm/amdgpu: set GTT_USWC on reserved VRAM allocations
@ 2018-10-05 21:01 Marek Olšák
[not found] ` <20181005210144.13999-1-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 8+ messages in thread
From: Marek Olšák @ 2018-10-05 21:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 904014dc5915..8e0f47343e0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -241,21 +241,23 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
if (!size) {
amdgpu_bo_unref(bo_ptr);
return 0;
}
memset(&bp, 0, sizeof(bp));
bp.size = size;
bp.byte_align = align;
bp.domain = domain;
bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
- AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+ AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+ (domain & AMDGPU_GEM_DOMAIN_VRAM ?
+ AMDGPU_GEM_CREATE_CPU_GTT_USWC : 0);
bp.type = ttm_bo_type_kernel;
bp.resv = NULL;
if (!*bo_ptr) {
r = amdgpu_bo_create(adev, &bp, bo_ptr);
if (r) {
dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
r);
return r;
}
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread[parent not found: <20181005210144.13999-1-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* [PATCH 2/3] drm/amdgpu: increase the size of HQD EOP buffers [not found] ` <20181005210144.13999-1-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2018-10-05 21:01 ` Marek Olšák [not found] ` <20181005210144.13999-2-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2018-10-05 21:01 ` [PATCH 3/3] drm/amdgpu: put HQD EOP buffers into VRAM Marek Olšák 2018-10-06 11:44 ` [PATCH 1/3] drm/amdgpu: set GTT_USWC on reserved VRAM allocations Christian König 2 siblings, 1 reply; 8+ messages in thread From: Marek Olšák @ 2018-10-05 21:01 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW From: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 77e05c19022a..191feafc3b60 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -47,21 +47,21 @@ #include "gca/gfx_8_0_enum.h" #include "dce/dce_10_0_d.h" #include "dce/dce_10_0_sh_mask.h" #include "smu/smu_7_1_3_d.h" #include "ivsrcid/ivsrcid_vislands30.h" #define GFX8_NUM_GFX_RINGS 1 -#define GFX8_MEC_HPD_SIZE 2048 +#define GFX8_MEC_HPD_SIZE 4096 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) #define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 4b020cc4bea9..a9d3d6a3fb41 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -34,21 +34,21 @@ #include "vega10_enum.h" #include "hdp/hdp_4_0_offset.h" #include "soc15_common.h" #include "clearstate_gfx9.h" #include "v9_structs.h" #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" #define GFX9_NUM_GFX_RINGS 1 -#define GFX9_MEC_HPD_SIZE 2048 +#define GFX9_MEC_HPD_SIZE 4096 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L #define mmPWR_MISC_CNTL_STATUS 0x0183 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
[parent not found: <20181005210144.13999-2-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 2/3] drm/amdgpu: increase the size of HQD EOP buffers [not found] ` <20181005210144.13999-2-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2018-10-09 16:17 ` Alex Deucher [not found] ` <CADnq5_M-uz+ABbZpm1-SFS26f1Q8T-w00FwXiMxj9HeAx8PhQw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 8+ messages in thread From: Alex Deucher @ 2018-10-09 16:17 UTC (permalink / raw) To: Marek Olsak; +Cc: amd-gfx list On Fri, Oct 5, 2018 at 5:01 PM Marek Olšák <maraeo@gmail.com> wrote: > > From: Marek Olšák <marek.olsak@amd.com> > > Signed-off-by: Marek Olšák <marek.olsak@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- Any reason not to bump the size for gfx7 as well? Alex > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index 77e05c19022a..191feafc3b60 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -47,21 +47,21 @@ > #include "gca/gfx_8_0_enum.h" > > #include "dce/dce_10_0_d.h" > #include "dce/dce_10_0_sh_mask.h" > > #include "smu/smu_7_1_3_d.h" > > #include "ivsrcid/ivsrcid_vislands30.h" > > #define GFX8_NUM_GFX_RINGS 1 > -#define GFX8_MEC_HPD_SIZE 2048 > +#define GFX8_MEC_HPD_SIZE 4096 > > #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 > #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 > #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002 > #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003 > > #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) > #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) > #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) > #define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT) > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index 4b020cc4bea9..a9d3d6a3fb41 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -34,21 +34,21 @@ > #include "vega10_enum.h" > #include "hdp/hdp_4_0_offset.h" > > #include "soc15_common.h" > #include "clearstate_gfx9.h" > #include "v9_structs.h" > > #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" > > #define GFX9_NUM_GFX_RINGS 1 > -#define GFX9_MEC_HPD_SIZE 2048 > +#define GFX9_MEC_HPD_SIZE 4096 > #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L > #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L > > #define mmPWR_MISC_CNTL_STATUS 0x0183 > #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0 > #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0 > #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1 > #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L > #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L > > -- > 2.17.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
[parent not found: <CADnq5_M-uz+ABbZpm1-SFS26f1Q8T-w00FwXiMxj9HeAx8PhQw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH 2/3] drm/amdgpu: increase the size of HQD EOP buffers [not found] ` <CADnq5_M-uz+ABbZpm1-SFS26f1Q8T-w00FwXiMxj9HeAx8PhQw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2018-10-18 19:46 ` Marek Olšák 2018-10-18 19:57 ` Alex Deucher 0 siblings, 1 reply; 8+ messages in thread From: Marek Olšák @ 2018-10-18 19:46 UTC (permalink / raw) To: Alex Deucher; +Cc: amd-gfx mailing list [-- Attachment #1.1: Type: text/plain, Size: 604 bytes --] On Tue, Oct 9, 2018 at 12:17 PM Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > On Fri, Oct 5, 2018 at 5:01 PM Marek Olšák <maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > > > > From: Marek Olšák <marek.olsak-5C7GfCeVMHo@public.gmane.org> > > > > Signed-off-by: Marek Olšák <marek.olsak-5C7GfCeVMHo@public.gmane.org> > > --- > > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- > > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- > > Any reason not to bump the size for gfx7 as well? > No, I just don't know if gfx7 supports the same size. Marek [-- Attachment #1.2: Type: text/html, Size: 1201 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] drm/amdgpu: increase the size of HQD EOP buffers 2018-10-18 19:46 ` Marek Olšák @ 2018-10-18 19:57 ` Alex Deucher 0 siblings, 0 replies; 8+ messages in thread From: Alex Deucher @ 2018-10-18 19:57 UTC (permalink / raw) To: Marek Olsak; +Cc: amd-gfx list On Thu, Oct 18, 2018 at 3:47 PM Marek Olšák <maraeo@gmail.com> wrote: > > On Tue, Oct 9, 2018 at 12:17 PM Alex Deucher <alexdeucher@gmail.com> wrote: >> >> On Fri, Oct 5, 2018 at 5:01 PM Marek Olšák <maraeo@gmail.com> wrote: >> > >> > From: Marek Olšák <marek.olsak@amd.com> >> > >> > Signed-off-by: Marek Olšák <marek.olsak@amd.com> >> > --- >> > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- >> > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- >> >> Any reason not to bump the size for gfx7 as well? > > > No, I just don't know if gfx7 supports the same size. Looks like it does not. gfx7 is 2^11, gfx8 is 2^12. Series is: Reviewed-by: Alex Deucher <alexander.deucher@amd.com> _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/3] drm/amdgpu: put HQD EOP buffers into VRAM [not found] ` <20181005210144.13999-1-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2018-10-05 21:01 ` [PATCH 2/3] drm/amdgpu: increase the size of HQD EOP buffers Marek Olšák @ 2018-10-05 21:01 ` Marek Olšák [not found] ` <20181005210144.13999-3-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2018-10-06 11:44 ` [PATCH 1/3] drm/amdgpu: set GTT_USWC on reserved VRAM allocations Christian König 2 siblings, 1 reply; 8+ messages in thread From: Marek Olšák @ 2018-10-05 21:01 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW From: Marek Olšák <marek.olsak@amd.com> This increases performance of compute queues. EOP events (PKT3_RELEASE_MEM) are stored into these buffers. Signed-off-by: Marek Olšák <marek.olsak@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 0e72bc09939a..000180d79f30 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2774,21 +2774,21 @@ static int gfx_v7_0_mec_init(struct amdgpu_device *adev) bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); /* take ownership of the relevant compute queues */ amdgpu_gfx_compute_queue_acquire(adev); /* allocate space for ALL pipes (even the ones we don't own) */ mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * GFX7_MEC_HPD_SIZE * 2; r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_DOMAIN_VRAM, &adev->gfx.mec.hpd_eop_obj, &adev->gfx.mec.hpd_eop_gpu_addr, (void **)&hpd); if (r) { dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r); gfx_v7_0_mec_fini(adev); return r; } /* clear memory. Not sure if this is required or not */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 191feafc3b60..8b6dae7a10bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -1436,21 +1436,21 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev) size_t mec_hpd_size; bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); /* take ownership of the relevant compute queues */ amdgpu_gfx_compute_queue_acquire(adev); mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_DOMAIN_VRAM, &adev->gfx.mec.hpd_eop_obj, &adev->gfx.mec.hpd_eop_gpu_addr, (void **)&hpd); if (r) { dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); return r; } memset(hpd, 0, mec_hpd_size); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index a9d3d6a3fb41..3aaacf61d85e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1247,21 +1247,21 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev) const struct gfx_firmware_header_v1_0 *mec_hdr; bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); /* take ownership of the relevant compute queues */ amdgpu_gfx_compute_queue_acquire(adev); mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_DOMAIN_VRAM, &adev->gfx.mec.hpd_eop_obj, &adev->gfx.mec.hpd_eop_gpu_addr, (void **)&hpd); if (r) { dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); gfx_v9_0_mec_fini(adev); return r; } memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
[parent not found: <20181005210144.13999-3-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 3/3] drm/amdgpu: put HQD EOP buffers into VRAM [not found] ` <20181005210144.13999-3-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2018-10-09 16:18 ` Alex Deucher 0 siblings, 0 replies; 8+ messages in thread From: Alex Deucher @ 2018-10-09 16:18 UTC (permalink / raw) To: Marek Olsak; +Cc: amd-gfx list On Fri, Oct 5, 2018 at 5:01 PM Marek Olšák <maraeo@gmail.com> wrote: > > From: Marek Olšák <marek.olsak@amd.com> > > This increases performance of compute queues. > EOP events (PKT3_RELEASE_MEM) are stored into these buffers. > > Signed-off-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > index 0e72bc09939a..000180d79f30 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > @@ -2774,21 +2774,21 @@ static int gfx_v7_0_mec_init(struct amdgpu_device *adev) > bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); > > /* take ownership of the relevant compute queues */ > amdgpu_gfx_compute_queue_acquire(adev); > > /* allocate space for ALL pipes (even the ones we don't own) */ > mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec > * GFX7_MEC_HPD_SIZE * 2; > > r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, > - AMDGPU_GEM_DOMAIN_GTT, > + AMDGPU_GEM_DOMAIN_VRAM, > &adev->gfx.mec.hpd_eop_obj, > &adev->gfx.mec.hpd_eop_gpu_addr, > (void **)&hpd); > if (r) { > dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r); > gfx_v7_0_mec_fini(adev); > return r; > } > > /* clear memory. Not sure if this is required or not */ > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index 191feafc3b60..8b6dae7a10bf 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -1436,21 +1436,21 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev) > size_t mec_hpd_size; > > bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); > > /* take ownership of the relevant compute queues */ > amdgpu_gfx_compute_queue_acquire(adev); > > mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; > > r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, > - AMDGPU_GEM_DOMAIN_GTT, > + AMDGPU_GEM_DOMAIN_VRAM, > &adev->gfx.mec.hpd_eop_obj, > &adev->gfx.mec.hpd_eop_gpu_addr, > (void **)&hpd); > if (r) { > dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); > return r; > } > > memset(hpd, 0, mec_hpd_size); > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index a9d3d6a3fb41..3aaacf61d85e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -1247,21 +1247,21 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev) > > const struct gfx_firmware_header_v1_0 *mec_hdr; > > bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); > > /* take ownership of the relevant compute queues */ > amdgpu_gfx_compute_queue_acquire(adev); > mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; > > r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, > - AMDGPU_GEM_DOMAIN_GTT, > + AMDGPU_GEM_DOMAIN_VRAM, > &adev->gfx.mec.hpd_eop_obj, > &adev->gfx.mec.hpd_eop_gpu_addr, > (void **)&hpd); > if (r) { > dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); > gfx_v9_0_mec_fini(adev); > return r; > } > > memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); > -- > 2.17.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] drm/amdgpu: set GTT_USWC on reserved VRAM allocations [not found] ` <20181005210144.13999-1-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2018-10-05 21:01 ` [PATCH 2/3] drm/amdgpu: increase the size of HQD EOP buffers Marek Olšák 2018-10-05 21:01 ` [PATCH 3/3] drm/amdgpu: put HQD EOP buffers into VRAM Marek Olšák @ 2018-10-06 11:44 ` Christian König 2 siblings, 0 replies; 8+ messages in thread From: Christian König @ 2018-10-06 11:44 UTC (permalink / raw) To: Marek Olšák, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Am 05.10.2018 um 23:01 schrieb Marek Olšák: > From: Marek Olšák <marek.olsak@amd.com> > > Signed-off-by: Marek Olšák <marek.olsak@amd.com> VRAM is always accessed USWC, so that doesn't looks like it would have any effect to me. The rest of the series looks good to me, Christian. > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c > index 904014dc5915..8e0f47343e0e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c > @@ -241,21 +241,23 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev, > if (!size) { > amdgpu_bo_unref(bo_ptr); > return 0; > } > > memset(&bp, 0, sizeof(bp)); > bp.size = size; > bp.byte_align = align; > bp.domain = domain; > bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | > - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; > + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | > + (domain & AMDGPU_GEM_DOMAIN_VRAM ? > + AMDGPU_GEM_CREATE_CPU_GTT_USWC : 0); > bp.type = ttm_bo_type_kernel; > bp.resv = NULL; > > if (!*bo_ptr) { > r = amdgpu_bo_create(adev, &bp, bo_ptr); > if (r) { > dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", > r); > return r; > } _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2018-10-18 19:57 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-10-05 21:01 [PATCH 1/3] drm/amdgpu: set GTT_USWC on reserved VRAM allocations Marek Olšák
[not found] ` <20181005210144.13999-1-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-10-05 21:01 ` [PATCH 2/3] drm/amdgpu: increase the size of HQD EOP buffers Marek Olšák
[not found] ` <20181005210144.13999-2-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-10-09 16:17 ` Alex Deucher
[not found] ` <CADnq5_M-uz+ABbZpm1-SFS26f1Q8T-w00FwXiMxj9HeAx8PhQw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-10-18 19:46 ` Marek Olšák
2018-10-18 19:57 ` Alex Deucher
2018-10-05 21:01 ` [PATCH 3/3] drm/amdgpu: put HQD EOP buffers into VRAM Marek Olšák
[not found] ` <20181005210144.13999-3-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-10-09 16:18 ` Alex Deucher
2018-10-06 11:44 ` [PATCH 1/3] drm/amdgpu: set GTT_USWC on reserved VRAM allocations Christian König
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox