* [PATCH 1/8] drm/amdgpu: Fix hardcoded base offset of vram pages
@ 2018-03-15 6:11 Feifei Xu
[not found] ` <1521094324-23252-1-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Feifei Xu @ 2018-03-15 6:11 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Feifei.Xu-5C7GfCeVMHo, Hawking Zhang
In gmc_v9_0_vram_gtt_location(),the vram_base_offset is hardcoded
to 0 in dGPU. Fix it by reading mmMC_VM_FB_OFFSET or return
zfb_phys_addr if ZFB is enabled.
Change-Id: I585b7d4d96ebab2a5d7178fe8d1d6a746ef0c72a
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index a70cbc4..0f61e05 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -697,10 +697,7 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
amdgpu_device_vram_location(adev, &adev->gmc, base);
amdgpu_device_gart_location(adev, mc);
/* base offset of vram pages */
- if (adev->flags & AMD_IS_APU)
- adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
- else
- adev->vm_manager.vram_base_offset = 0;
+ adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
}
/**
--
2.7.4
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^ permalink raw reply related [flat|nested] 16+ messages in thread[parent not found: <1521094324-23252-1-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org>]
* [PATCH 2/8] drm/amdgpu: add new member in amdgpu_mc for zfb support [not found] ` <1521094324-23252-1-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> @ 2018-03-15 6:11 ` Feifei Xu [not found] ` <1521094324-23252-2-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> 2018-03-15 6:11 ` [PATCH 3/8] drm/amdgpu: add amdgpu module parameter for zfb Feifei Xu ` (6 subsequent siblings) 7 siblings, 1 reply; 16+ messages in thread From: Feifei Xu @ 2018-03-15 6:11 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Feifei.Xu-5C7GfCeVMHo, Hawking Zhang Change-Id: I8253c8ff80e0cbd1f12e5ee801600e7619e6718f Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: John Bridgman <john.bridgman@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index 893c249..8f35f7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -107,6 +107,9 @@ struct amdgpu_gmc { bool translate_further; const struct amdgpu_gmc_funcs *gmc_funcs; + /* zero frame buffer */ + u64 zfb_phys_addr; + u64 zfb_size; }; #endif -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
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* Re: [PATCH 2/8] drm/amdgpu: add new member in amdgpu_mc for zfb support [not found] ` <1521094324-23252-2-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> @ 2018-03-15 8:10 ` Christian König 0 siblings, 0 replies; 16+ messages in thread From: Christian König @ 2018-03-15 8:10 UTC (permalink / raw) To: Feifei Xu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hawking Zhang Am 15.03.2018 um 07:11 schrieb Feifei Xu: > Change-Id: I8253c8ff80e0cbd1f12e5ee801600e7619e6718f > Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> > Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> > Acked-by: John Bridgman <john.bridgman@amd.com> > Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h > index 893c249..8f35f7e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h > @@ -107,6 +107,9 @@ struct amdgpu_gmc { > bool translate_further; > > const struct amdgpu_gmc_funcs *gmc_funcs; > + /* zero frame buffer */ > + u64 zfb_phys_addr; > + u64 zfb_size; Please use tabs instead of spaces for indentation. Christian. > }; > > #endif _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/8] drm/amdgpu: add amdgpu module parameter for zfb [not found] ` <1521094324-23252-1-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> 2018-03-15 6:11 ` [PATCH 2/8] drm/amdgpu: add new member in amdgpu_mc for zfb support Feifei Xu @ 2018-03-15 6:11 ` Feifei Xu [not found] ` <1521094324-23252-3-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> 2018-03-15 6:12 ` [PATCH 4/8] drm/amdgpu: init zfb start address and size Feifei Xu ` (5 subsequent siblings) 7 siblings, 1 reply; 16+ messages in thread From: Feifei Xu @ 2018-03-15 6:11 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Feifei.Xu-5C7GfCeVMHo Users can pass in an array to decide enable/disable Zero Frame Buffer. zfb[0] = zfb_size(MB), zfb[1] = zfb_phys_addr(MB). If zbf_size > 0, zfb is enabled. Otherwise disabled. Usage for example: modprobe amdgpu zfb=256,8192 Change-Id: I711062eb86b6cdff74572cabb3df250c6708e473 Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: John Bridgman <john.bridgman@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 2e6d986..949b451 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -129,6 +129,7 @@ extern int amdgpu_lbpw; extern int amdgpu_compute_multipipe; extern int amdgpu_gpu_recovery; extern int amdgpu_emu_mode; +extern ulong amdgpu_zfb[]; #ifdef CONFIG_DRM_AMDGPU_SI extern int amdgpu_si_support; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index e670936..53ba4ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -132,6 +132,7 @@ int amdgpu_lbpw = -1; int amdgpu_compute_multipipe = -1; int amdgpu_gpu_recovery = -1; /* auto */ int amdgpu_emu_mode = 0; +ulong amdgpu_zfb[2] = {0,4096UL}; /* {0,0x100000000} */ MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); @@ -290,6 +291,10 @@ module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); +MODULE_PARM_DESC(zfb, + "Enable Zero Frame Buffer feature (zfb will be set like xxxx,xxxx(zfb_size MB,zfb_phys_addr MB),default disabled)"); +module_param_array_named(zfb, amdgpu_zfb, ulong, NULL, 0444); + #ifdef CONFIG_DRM_AMDGPU_SI #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
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* Re: [PATCH 3/8] drm/amdgpu: add amdgpu module parameter for zfb [not found] ` <1521094324-23252-3-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> @ 2018-03-15 8:11 ` Christian König 0 siblings, 0 replies; 16+ messages in thread From: Christian König @ 2018-03-15 8:11 UTC (permalink / raw) To: Feifei Xu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Am 15.03.2018 um 07:11 schrieb Feifei Xu: > Users can pass in an array to decide enable/disable Zero Frame Buffer. > zfb[0] = zfb_size(MB), zfb[1] = zfb_phys_addr(MB). > If zbf_size > 0, zfb is enabled. Otherwise disabled. > Usage for example: > modprobe amdgpu zfb=256,8192 > > Change-Id: I711062eb86b6cdff74572cabb3df250c6708e473 > Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> > Acked-by: John Bridgman <john.bridgman@amd.com> > Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index 2e6d986..949b451 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -129,6 +129,7 @@ extern int amdgpu_lbpw; > extern int amdgpu_compute_multipipe; > extern int amdgpu_gpu_recovery; > extern int amdgpu_emu_mode; > +extern ulong amdgpu_zfb[]; > > #ifdef CONFIG_DRM_AMDGPU_SI > extern int amdgpu_si_support; > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > index e670936..53ba4ad 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > @@ -132,6 +132,7 @@ int amdgpu_lbpw = -1; > int amdgpu_compute_multipipe = -1; > int amdgpu_gpu_recovery = -1; /* auto */ > int amdgpu_emu_mode = 0; > +ulong amdgpu_zfb[2] = {0,4096UL}; /* {0,0x100000000} */ > > MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); > module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); > @@ -290,6 +291,10 @@ module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); > MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); > module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); > > +MODULE_PARM_DESC(zfb, > + "Enable Zero Frame Buffer feature (zfb will be set like xxxx,xxxx(zfb_size MB,zfb_phys_addr MB),default disabled)"); > +module_param_array_named(zfb, amdgpu_zfb, ulong, NULL, 0444); > + As discussed please drop the array and just specify the size. Christian. > #ifdef CONFIG_DRM_AMDGPU_SI > > #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/8] drm/amdgpu: init zfb start address and size [not found] ` <1521094324-23252-1-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> 2018-03-15 6:11 ` [PATCH 2/8] drm/amdgpu: add new member in amdgpu_mc for zfb support Feifei Xu 2018-03-15 6:11 ` [PATCH 3/8] drm/amdgpu: add amdgpu module parameter for zfb Feifei Xu @ 2018-03-15 6:12 ` Feifei Xu [not found] ` <1521094324-23252-4-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> 2018-03-15 6:12 ` [PATCH 5/8] drm/amdgpu: user reserved zfb to init vram base offset " Feifei Xu ` (4 subsequent siblings) 7 siblings, 1 reply; 16+ messages in thread From: Feifei Xu @ 2018-03-15 6:12 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Feifei.Xu-5C7GfCeVMHo, Hawking Zhang Use module parameter passed from user to initialize zfb start address and size. Change-Id: I3d786e863114a217f89ff7c3d4ffdabf000f31a4 Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: John Bridgman <john.bridgman@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2188763..b88cb4b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -859,6 +859,16 @@ static void amdgpu_device_check_arguments(struct amdgpu_device *adev) amdgpu_lockup_timeout = 10000; } + if (amdgpu_zfb[0] > 0) { + dev_warn(adev->dev, + "Zero Frame Buffer is enabled.\n"); + adev->gmc.zfb_phys_addr = amdgpu_zfb[1] << 20; + adev->gmc.zfb_size = amdgpu_zfb[0] << 20; + } else { + adev->gmc.zfb_phys_addr = 0; + adev->gmc.zfb_size = 0; + } + adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); } -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
[parent not found: <1521094324-23252-4-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 4/8] drm/amdgpu: init zfb start address and size [not found] ` <1521094324-23252-4-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> @ 2018-03-15 8:13 ` Christian König 0 siblings, 0 replies; 16+ messages in thread From: Christian König @ 2018-03-15 8:13 UTC (permalink / raw) To: Feifei Xu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hawking Zhang Am 15.03.2018 um 07:12 schrieb Feifei Xu: > Use module parameter passed from user to initialize zfb start address > and size. > > Change-Id: I3d786e863114a217f89ff7c3d4ffdabf000f31a4 > Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> > Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> > Acked-by: John Bridgman <john.bridgman@amd.com> > Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index 2188763..b88cb4b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -859,6 +859,16 @@ static void amdgpu_device_check_arguments(struct amdgpu_device *adev) > amdgpu_lockup_timeout = 10000; > } > > + if (amdgpu_zfb[0] > 0) { > + dev_warn(adev->dev, > + "Zero Frame Buffer is enabled.\n"); > + adev->gmc.zfb_phys_addr = amdgpu_zfb[1] << 20; > + adev->gmc.zfb_size = amdgpu_zfb[0] << 20; As discussed please use dma_alloc_coherent() to allocate from CMA here instead of specifying the DMA address manually. Christian. > + } else { > + adev->gmc.zfb_phys_addr = 0; > + adev->gmc.zfb_size = 0; > + } > + > adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); > } > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 5/8] drm/amdgpu: user reserved zfb to init vram base offset and size [not found] ` <1521094324-23252-1-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> ` (2 preceding siblings ...) 2018-03-15 6:12 ` [PATCH 4/8] drm/amdgpu: init zfb start address and size Feifei Xu @ 2018-03-15 6:12 ` Feifei Xu [not found] ` <1521094324-23252-5-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> 2018-03-15 6:12 ` [PATCH 6/8] drm/amdgpu: enable physical transaction for ptd/pde when ZFB is enabled Feifei Xu ` (3 subsequent siblings) 7 siblings, 1 reply; 16+ messages in thread From: Feifei Xu @ 2018-03-15 6:12 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Feifei.Xu-5C7GfCeVMHo, Hawking Zhang Change-Id: I866dd16548304a42298b0cb28741f27cba3a76ca Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: John Bridgman <john.bridgman@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 0f61e05..94e13c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -697,7 +697,10 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, amdgpu_device_vram_location(adev, &adev->gmc, base); amdgpu_device_gart_location(adev, mc); /* base offset of vram pages */ - adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); + if (adev->gmc.zfb_size > 0) + adev->vm_manager.vram_base_offset = adev->gmc.zfb_phys_addr; + else + adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); } /** @@ -761,8 +764,11 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) } /* size in MB on si */ - adev->gmc.mc_vram_size = - adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; + if (adev->gmc.zfb_size > 0) + adev->gmc.mc_vram_size = adev->gmc.zfb_size; + else + adev->gmc.mc_vram_size = + adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; adev->gmc.real_vram_size = adev->gmc.mc_vram_size; if (!(adev->flags & AMD_IS_APU)) { @@ -770,12 +776,20 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) if (r) return r; } - adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); - adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); + if (adev->gmc.zfb_size > 0) { + adev->gmc.aper_base = adev->gmc.zfb_phys_addr; + adev->gmc.aper_size = adev->gmc.zfb_size; + } else { + adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); + adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); + } #ifdef CONFIG_X86_64 if (adev->flags & AMD_IS_APU) { - adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); + if (adev->gmc.zfb_size > 0) + adev->gmc.aper_base = adev->gmc.zfb_phys_addr; + else + adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); adev->gmc.aper_size = adev->gmc.real_vram_size; } #endif -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
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* Re: [PATCH 5/8] drm/amdgpu: user reserved zfb to init vram base offset and size [not found] ` <1521094324-23252-5-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> @ 2018-03-15 8:15 ` Christian König 0 siblings, 0 replies; 16+ messages in thread From: Christian König @ 2018-03-15 8:15 UTC (permalink / raw) To: Feifei Xu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hawking Zhang Am 15.03.2018 um 07:12 schrieb Feifei Xu: > Change-Id: I866dd16548304a42298b0cb28741f27cba3a76ca > Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> > Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> > Acked-by: John Bridgman <john.bridgman@amd.com> > Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 26 ++++++++++++++++++++------ > 1 file changed, 20 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index 0f61e05..94e13c8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -697,7 +697,10 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, > amdgpu_device_vram_location(adev, &adev->gmc, base); > amdgpu_device_gart_location(adev, mc); > /* base offset of vram pages */ > - adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); > + if (adev->gmc.zfb_size > 0) > + adev->vm_manager.vram_base_offset = adev->gmc.zfb_phys_addr; > + else > + adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); > } > > /** > @@ -761,8 +764,11 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) > } > > /* size in MB on si */ > - adev->gmc.mc_vram_size = > - adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; > + if (adev->gmc.zfb_size > 0) > + adev->gmc.mc_vram_size = adev->gmc.zfb_size; > + else > + adev->gmc.mc_vram_size = > + adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; > adev->gmc.real_vram_size = adev->gmc.mc_vram_size; > > if (!(adev->flags & AMD_IS_APU)) { > @@ -770,12 +776,20 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) > if (r) > return r; > } > - adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); > - adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); > + if (adev->gmc.zfb_size > 0) { > + adev->gmc.aper_base = adev->gmc.zfb_phys_addr; > + adev->gmc.aper_size = adev->gmc.zfb_size; > + } else { > + adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); > + adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); > + } > > #ifdef CONFIG_X86_64 > if (adev->flags & AMD_IS_APU) { > - adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); > + if (adev->gmc.zfb_size > 0) > + adev->gmc.aper_base = adev->gmc.zfb_phys_addr; > + else > + adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); > adev->gmc.aper_size = adev->gmc.real_vram_size; > } > #endif Completely drop those changes and instead override adev->gmc.aper_base and adev->gmc.aper_size after determining them when ZFB is active. Christian. _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 6/8] drm/amdgpu: enable physical transaction for ptd/pde when ZFB is enabled [not found] ` <1521094324-23252-1-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> ` (3 preceding siblings ...) 2018-03-15 6:12 ` [PATCH 5/8] drm/amdgpu: user reserved zfb to init vram base offset " Feifei Xu @ 2018-03-15 6:12 ` Feifei Xu [not found] ` <1521094324-23252-6-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> 2018-03-15 6:12 ` [PATCH 7/8] drm/amdgpu: program AGP aperture as frame buffer " Feifei Xu ` (2 subsequent siblings) 7 siblings, 1 reply; 16+ messages in thread From: Feifei Xu @ 2018-03-15 6:12 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Feifei.Xu-5C7GfCeVMHo, Hawking Zhang Change-Id: I2b45d765f1f60252fa1c02aced94f8100d575ddc Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: John Bridgman <john.bridgman@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 9 +++++++-- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 9 +++++++-- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index acfbd2d..0d72f52 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -155,8 +155,13 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp); tmp = mmVM_L2_CNTL4_DEFAULT; - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); + if (adev->gmc.zfb_size > 0) { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1); + } else { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); + } WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp); } diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index 3dd5816..bd3777a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -166,8 +166,13 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) } tmp = mmVM_L2_CNTL4_DEFAULT; - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); + if (adev->gmc.zfb_size > 0) { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1); + } else { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); + } WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp); } -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
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* Re: [PATCH 6/8] drm/amdgpu: enable physical transaction for ptd/pde when ZFB is enabled [not found] ` <1521094324-23252-6-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> @ 2018-03-15 8:17 ` Christian König 0 siblings, 0 replies; 16+ messages in thread From: Christian König @ 2018-03-15 8:17 UTC (permalink / raw) To: Feifei Xu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hawking Zhang Am 15.03.2018 um 07:12 schrieb Feifei Xu: > Change-Id: I2b45d765f1f60252fa1c02aced94f8100d575ddc > Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> > Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> > Acked-by: John Bridgman <john.bridgman@amd.com> > Reviewed-by: Alex Deucher <alexander.deucher@amd.com> There is a typo in the subject, apart from that the patch is Reviewed-by: Christian König <christian.koenig@amd.com>. Christian. > --- > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 9 +++++++-- > drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 9 +++++++-- > 2 files changed, 14 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > index acfbd2d..0d72f52 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > @@ -155,8 +155,13 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) > WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp); > > tmp = mmVM_L2_CNTL4_DEFAULT; > - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); > - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); > + if (adev->gmc.zfb_size > 0) { > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1); > + } else { > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); > + } > WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp); > } > > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > index 3dd5816..bd3777a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > @@ -166,8 +166,13 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) > } > > tmp = mmVM_L2_CNTL4_DEFAULT; > - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); > - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); > + if (adev->gmc.zfb_size > 0) { > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1); > + } else { > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); > + } > WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp); > } > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 7/8] drm/amdgpu: program AGP aperture as frame buffer when ZFB is enabled [not found] ` <1521094324-23252-1-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> ` (4 preceding siblings ...) 2018-03-15 6:12 ` [PATCH 6/8] drm/amdgpu: enable physical transaction for ptd/pde when ZFB is enabled Feifei Xu @ 2018-03-15 6:12 ` Feifei Xu [not found] ` <1521094324-23252-7-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> 2018-03-15 6:12 ` [PATCH 8/8] drm/amdgpu: program system bit for pte/pde " Feifei Xu 2018-03-15 8:09 ` [PATCH 1/8] drm/amdgpu: Fix hardcoded base offset of vram pages Christian König 7 siblings, 1 reply; 16+ messages in thread From: Feifei Xu @ 2018-03-15 6:12 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Feifei.Xu-5C7GfCeVMHo, Hawking Zhang From: Hawking Zhang <Hawking.Zhang@amd.com> Change-Id: I09f9ddea0ad23af00fadd9af7aaccf7160e4e569 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: John Bridgman <john.bridgman@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 19 +++++++++++++++---- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 19 +++++++++++++++---- 2 files changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index 0d72f52..3689f1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -71,10 +71,21 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) { uint64_t value; - /* Disable AGP. */ - WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0); - WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); - WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF); + if (adev->gmc.zfb_size > 0) { + /* Disable LFB */ + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0); + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF); + + /* Enable AGP */ + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, adev->gmc.zfb_phys_addr >> 24); + WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.vram_end >> 24); + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.vram_start >> 24); + } else { + /* Disable AGP. */ + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0); + WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF); + } /* Program the system aperture low logical page number. */ WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index bd3777a..ef79d49 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -82,10 +82,21 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) uint64_t value; uint32_t tmp; - /* Disable AGP. */ - WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); - WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0); - WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF); + if (adev->gmc.zfb_size > 0) { + /* Disable LFB */ + WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP, 0); + WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF); + + /* Enable AGP */ + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, adev->gmc.zfb_phys_addr >> 24); + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.vram_end >> 24); + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.vram_start >> 24); + } else { + /* Disable AGP. */ + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0); + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF); + } /* Program the system aperture low logical page number. */ WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
[parent not found: <1521094324-23252-7-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 7/8] drm/amdgpu: program AGP aperture as frame buffer when ZFB is enabled [not found] ` <1521094324-23252-7-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> @ 2018-03-15 8:18 ` Christian König 0 siblings, 0 replies; 16+ messages in thread From: Christian König @ 2018-03-15 8:18 UTC (permalink / raw) To: Feifei Xu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hawking Zhang Am 15.03.2018 um 07:12 schrieb Feifei Xu: > From: Hawking Zhang <Hawking.Zhang@amd.com> > > Change-Id: I09f9ddea0ad23af00fadd9af7aaccf7160e4e569 > Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> > Acked-by: John Bridgman <john.bridgman@amd.com> > Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 19 +++++++++++++++---- > drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 19 +++++++++++++++---- > 2 files changed, 30 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > index 0d72f52..3689f1d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > @@ -71,10 +71,21 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) > { > uint64_t value; > > - /* Disable AGP. */ > - WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0); > - WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); > - WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF); > + if (adev->gmc.zfb_size > 0) { > + /* Disable LFB */ > + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0); > + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF); > + > + /* Enable AGP */ > + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, adev->gmc.zfb_phys_addr >> 24); > + WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.vram_end >> 24); > + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.vram_start >> 24); > + } else { > + /* Disable AGP. */ > + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0); > + WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); > + WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF); > + } > > /* Program the system aperture low logical page number. */ > WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > index bd3777a..ef79d49 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > @@ -82,10 +82,21 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) > uint64_t value; > uint32_t tmp; > > - /* Disable AGP. */ > - WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); > - WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0); > - WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF); > + if (adev->gmc.zfb_size > 0) { > + /* Disable LFB */ > + WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP, 0); > + WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF); > + > + /* Enable AGP */ > + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, adev->gmc.zfb_phys_addr >> 24); > + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.vram_end >> 24); > + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.vram_start >> 24); > + } else { > + /* Disable AGP. */ > + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); > + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0); > + WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF); > + } > > /* Program the system aperture low logical page number. */ > WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 8/8] drm/amdgpu: program system bit for pte/pde when ZFB is enabled [not found] ` <1521094324-23252-1-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> ` (5 preceding siblings ...) 2018-03-15 6:12 ` [PATCH 7/8] drm/amdgpu: program AGP aperture as frame buffer " Feifei Xu @ 2018-03-15 6:12 ` Feifei Xu [not found] ` <1521094324-23252-8-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> 2018-03-15 8:09 ` [PATCH 1/8] drm/amdgpu: Fix hardcoded base offset of vram pages Christian König 7 siblings, 1 reply; 16+ messages in thread From: Feifei Xu @ 2018-03-15 6:12 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Cc: Feifei.Xu-5C7GfCeVMHo, Hawking Zhang Change-Id: I9e4babf1e91855fb66e65cf2f82db64a1cd6fc97 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: John Bridgman <john.bridgman@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 ++ 3 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index 3689f1d..6b172ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -44,6 +44,8 @@ static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) + adev->vm_manager.vram_base_offset; value &= 0x0000FFFFFFFFF000ULL; value |= 0x1; /*valid bit*/ + if (adev->gmc.zfb_size > 0) + value |= 0x2; /*system bit*/ WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, lower_32_bits(value)); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 94e13c8..f3b6a5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -480,6 +480,9 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, if (flags & AMDGPU_VM_PAGE_WRITEABLE) pte_flag |= AMDGPU_PTE_WRITEABLE; + if (adev->gmc.zfb_size > 0) + pte_flag |= AMDGPU_PTE_SYSTEM; + switch (flags & AMDGPU_VM_MTYPE_MASK) { case AMDGPU_VM_MTYPE_DEFAULT: pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); @@ -515,6 +518,9 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, adev->gmc.vram_start; BUG_ON(*addr & 0xFFFF00000000003FULL); + if (adev->gmc.zfb_size > 0) + *flags |= AMDGPU_PTE_SYSTEM; + if (!adev->gmc.translate_further) return; diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index ef79d49..471a59b 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -54,6 +54,8 @@ static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) adev->vm_manager.vram_base_offset; value &= 0x0000FFFFFFFFF000ULL; value |= 0x1; /* valid bit */ + if (adev->gmc.zfb_size > 0) + value |= 0x2; /* system bit*/ WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, lower_32_bits(value)); -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
[parent not found: <1521094324-23252-8-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 8/8] drm/amdgpu: program system bit for pte/pde when ZFB is enabled [not found] ` <1521094324-23252-8-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> @ 2018-03-15 8:19 ` Christian König 0 siblings, 0 replies; 16+ messages in thread From: Christian König @ 2018-03-15 8:19 UTC (permalink / raw) To: Feifei Xu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hawking Zhang Am 15.03.2018 um 07:12 schrieb Feifei Xu: > Change-Id: I9e4babf1e91855fb66e65cf2f82db64a1cd6fc97 > Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> > Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> > Acked-by: John Bridgman <john.bridgman@amd.com> > Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 ++++++ > drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 ++ > 3 files changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > index 3689f1d..6b172ca 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > @@ -44,6 +44,8 @@ static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) > + adev->vm_manager.vram_base_offset; > value &= 0x0000FFFFFFFFF000ULL; > value |= 0x1; /*valid bit*/ > + if (adev->gmc.zfb_size > 0) > + value |= 0x2; /*system bit*/ Please use the AMDGPU_PTE_SYSTEM constant here. Would be nice to have that for the valid bit as well. Christian. > > WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, > lower_32_bits(value)); > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index 94e13c8..f3b6a5f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -480,6 +480,9 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, > if (flags & AMDGPU_VM_PAGE_WRITEABLE) > pte_flag |= AMDGPU_PTE_WRITEABLE; > > + if (adev->gmc.zfb_size > 0) > + pte_flag |= AMDGPU_PTE_SYSTEM; > + > switch (flags & AMDGPU_VM_MTYPE_MASK) { > case AMDGPU_VM_MTYPE_DEFAULT: > pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); > @@ -515,6 +518,9 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, > adev->gmc.vram_start; > BUG_ON(*addr & 0xFFFF00000000003FULL); > > + if (adev->gmc.zfb_size > 0) > + *flags |= AMDGPU_PTE_SYSTEM; > + > if (!adev->gmc.translate_further) > return; > > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > index ef79d49..471a59b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > @@ -54,6 +54,8 @@ static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) > adev->vm_manager.vram_base_offset; > value &= 0x0000FFFFFFFFF000ULL; > value |= 0x1; /* valid bit */ > + if (adev->gmc.zfb_size > 0) > + value |= 0x2; /* system bit*/ > > WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, > lower_32_bits(value)); _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/8] drm/amdgpu: Fix hardcoded base offset of vram pages [not found] ` <1521094324-23252-1-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org> ` (6 preceding siblings ...) 2018-03-15 6:12 ` [PATCH 8/8] drm/amdgpu: program system bit for pte/pde " Feifei Xu @ 2018-03-15 8:09 ` Christian König 7 siblings, 0 replies; 16+ messages in thread From: Christian König @ 2018-03-15 8:09 UTC (permalink / raw) To: Feifei Xu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hawking Zhang Am 15.03.2018 um 07:11 schrieb Feifei Xu: > In gmc_v9_0_vram_gtt_location(),the vram_base_offset is hardcoded > to 0 in dGPU. Fix it by reading mmMC_VM_FB_OFFSET or return > zfb_phys_addr if ZFB is enabled. > > Change-Id: I585b7d4d96ebab2a5d7178fe8d1d6a746ef0c72a > Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> > Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +---- > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index a70cbc4..0f61e05 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -697,10 +697,7 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, > amdgpu_device_vram_location(adev, &adev->gmc, base); > amdgpu_device_gart_location(adev, mc); > /* base offset of vram pages */ > - if (adev->flags & AMD_IS_APU) > - adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); > - else > - adev->vm_manager.vram_base_offset = 0; > + adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); > } > > /** _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2018-03-15 8:19 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
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2018-03-15 6:11 [PATCH 1/8] drm/amdgpu: Fix hardcoded base offset of vram pages Feifei Xu
[not found] ` <1521094324-23252-1-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org>
2018-03-15 6:11 ` [PATCH 2/8] drm/amdgpu: add new member in amdgpu_mc for zfb support Feifei Xu
[not found] ` <1521094324-23252-2-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org>
2018-03-15 8:10 ` Christian König
2018-03-15 6:11 ` [PATCH 3/8] drm/amdgpu: add amdgpu module parameter for zfb Feifei Xu
[not found] ` <1521094324-23252-3-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org>
2018-03-15 8:11 ` Christian König
2018-03-15 6:12 ` [PATCH 4/8] drm/amdgpu: init zfb start address and size Feifei Xu
[not found] ` <1521094324-23252-4-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org>
2018-03-15 8:13 ` Christian König
2018-03-15 6:12 ` [PATCH 5/8] drm/amdgpu: user reserved zfb to init vram base offset " Feifei Xu
[not found] ` <1521094324-23252-5-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org>
2018-03-15 8:15 ` Christian König
2018-03-15 6:12 ` [PATCH 6/8] drm/amdgpu: enable physical transaction for ptd/pde when ZFB is enabled Feifei Xu
[not found] ` <1521094324-23252-6-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org>
2018-03-15 8:17 ` Christian König
2018-03-15 6:12 ` [PATCH 7/8] drm/amdgpu: program AGP aperture as frame buffer " Feifei Xu
[not found] ` <1521094324-23252-7-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org>
2018-03-15 8:18 ` Christian König
2018-03-15 6:12 ` [PATCH 8/8] drm/amdgpu: program system bit for pte/pde " Feifei Xu
[not found] ` <1521094324-23252-8-git-send-email-Feifei.Xu-5C7GfCeVMHo@public.gmane.org>
2018-03-15 8:19 ` Christian König
2018-03-15 8:09 ` [PATCH 1/8] drm/amdgpu: Fix hardcoded base offset of vram pages Christian König
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