From: "Xin Li (Intel)" <xin@zytor.com>
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Subject: [RFC PATCH v1 07/15] x86/msr: Remove pmu_msr_{read,write}()
Date: Mon, 31 Mar 2025 01:22:43 -0700 [thread overview]
Message-ID: <20250331082251.3171276-8-xin@zytor.com> (raw)
In-Reply-To: <20250331082251.3171276-1-xin@zytor.com>
Now pmu_msr_{read,write}() just do pmu_msr_chk_emulated(), so remove
them and call pmu_msr_chk_emulated() directly.
Suggested-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: Xin Li (Intel) <xin@zytor.com>
---
arch/x86/xen/enlighten_pv.c | 17 ++++++++++-------
arch/x86/xen/pmu.c | 24 ++++--------------------
arch/x86/xen/xen-ops.h | 3 +--
3 files changed, 15 insertions(+), 29 deletions(-)
diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
index 7401cce19939..a047dadf4511 100644
--- a/arch/x86/xen/enlighten_pv.c
+++ b/arch/x86/xen/enlighten_pv.c
@@ -1090,8 +1090,9 @@ static void xen_write_cr4(unsigned long cr4)
static u64 xen_do_read_msr(unsigned int msr, int *err)
{
u64 val = 0; /* Avoid uninitialized value for safe variant. */
+ bool emulated;
- if (pmu_msr_read(msr, &val, err))
+ if (pmu_msr_chk_emulated(msr, &val, true, &emulated) && emulated)
return val;
if (err)
@@ -1134,6 +1135,7 @@ static void xen_do_write_msr(unsigned int msr, unsigned int low,
unsigned int high, int *err)
{
u64 val;
+ bool emulated;
switch (msr) {
case MSR_FS_BASE:
@@ -1163,12 +1165,13 @@ static void xen_do_write_msr(unsigned int msr, unsigned int low,
default:
val = (u64)high << 32 | low;
- if (!pmu_msr_write(msr, val)) {
- if (err)
- *err = native_write_msr_safe(msr, val);
- else
- native_write_msr(msr, val);
- }
+ if (pmu_msr_chk_emulated(msr, &val, false, &emulated) && emulated)
+ return;
+
+ if (err)
+ *err = native_write_msr_safe(msr, val);
+ else
+ native_write_msr(msr, val);
}
}
diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c
index 1364cd3fb3ef..4d20503430dd 100644
--- a/arch/x86/xen/pmu.c
+++ b/arch/x86/xen/pmu.c
@@ -128,7 +128,7 @@ static inline uint32_t get_fam15h_addr(u32 addr)
return addr;
}
-static inline bool is_amd_pmu_msr(unsigned int msr)
+static bool is_amd_pmu_msr(u32 msr)
{
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
@@ -194,8 +194,7 @@ static bool is_intel_pmu_msr(u32 msr_index, int *type, int *index)
}
}
-static bool xen_intel_pmu_emulate(unsigned int msr, u64 *val, int type,
- int index, bool is_read)
+static bool xen_intel_pmu_emulate(u32 msr, u64 *val, int type, int index, bool is_read)
{
uint64_t *reg = NULL;
struct xen_pmu_intel_ctxt *ctxt;
@@ -257,7 +256,7 @@ static bool xen_intel_pmu_emulate(unsigned int msr, u64 *val, int type,
return false;
}
-static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read)
+static bool xen_amd_pmu_emulate(u32 msr, u64 *val, bool is_read)
{
uint64_t *reg = NULL;
int i, off = 0;
@@ -298,8 +297,7 @@ static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read)
return false;
}
-static bool pmu_msr_chk_emulated(unsigned int msr, uint64_t *val, bool is_read,
- bool *emul)
+bool pmu_msr_chk_emulated(u32 msr, u64 *val, bool is_read, bool *emul)
{
int type, index = 0;
@@ -313,20 +311,6 @@ static bool pmu_msr_chk_emulated(unsigned int msr, uint64_t *val, bool is_read,
return true;
}
-bool pmu_msr_read(u32 msr, u64 *val, int *err)
-{
- bool emulated;
-
- return pmu_msr_chk_emulated(msr, val, true, &emulated) && emulated;
-}
-
-bool pmu_msr_write(u32 msr, u64 val)
-{
- bool emulated;
-
- return pmu_msr_chk_emulated(msr, &val, false, &emulated) && emulated;
-}
-
static unsigned long long xen_amd_read_pmc(int counter)
{
struct xen_pmu_amd_ctxt *ctxt;
diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
index 4a0a1d73d8b8..6545661010ce 100644
--- a/arch/x86/xen/xen-ops.h
+++ b/arch/x86/xen/xen-ops.h
@@ -274,8 +274,7 @@ void xen_pmu_finish(int cpu);
static inline void xen_pmu_init(int cpu) {}
static inline void xen_pmu_finish(int cpu) {}
#endif
-bool pmu_msr_read(u32 msr, u64 *val, int *err);
-bool pmu_msr_write(u32 msr, u64 val);
+bool pmu_msr_chk_emulated(u32 msr, u64 *val, bool is_read, bool *emul);
int pmu_apic_update(uint32_t reg);
unsigned long long xen_read_pmc(int counter);
--
2.49.0
next prev parent reply other threads:[~2025-03-31 8:24 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-31 8:22 [RFC PATCH v1 00/15] MSR refactor with new MSR instructions support Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 01/15] x86/msr: Replace __wrmsr() with native_wrmsrl() Xin Li (Intel)
2025-03-31 10:17 ` Ingo Molnar
2025-03-31 20:32 ` H. Peter Anvin
2025-04-01 5:53 ` Xin Li
2025-04-02 15:41 ` Dave Hansen
2025-04-02 15:56 ` H. Peter Anvin
2025-04-09 19:53 ` Ingo Molnar
2025-04-09 19:56 ` Dave Hansen
2025-04-09 20:11 ` Ingo Molnar
2025-04-01 7:52 ` Ingo Molnar
2025-04-02 3:45 ` Xin Li
2025-04-02 4:10 ` Ingo Molnar
2025-04-02 4:57 ` Xin Li
2025-04-08 17:34 ` Xin Li
2025-04-03 5:09 ` Xin Li
2025-04-03 6:01 ` H. Peter Anvin
2025-04-09 19:17 ` [PATCH] x86/msr: Standardize on 'u32' MSR indices in <asm/msr.h> Ingo Molnar
2025-03-31 21:45 ` [RFC PATCH v1 01/15] x86/msr: Replace __wrmsr() with native_wrmsrl() Andrew Cooper
2025-04-01 5:13 ` H. Peter Anvin
2025-04-01 5:29 ` Xin Li
2025-04-03 7:13 ` Xin Li
2025-03-31 8:22 ` [RFC PATCH v1 02/15] x86/msr: Replace __rdmsr() with native_rdmsrl() Xin Li (Intel)
2025-03-31 10:26 ` Ingo Molnar
2025-03-31 8:22 ` [RFC PATCH v1 03/15] x86/msr: Simplify pmu_msr_{read,write}() Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 04/15] x86/msr: Let pv_cpu_ops.write_msr{_safe}() take an u64 instead of two u32 Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 05/15] x86/msr: Replace wrmsr(msr, low, 0) with wrmsrl(msr, value) Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 06/15] x86/msr: Remove MSR write APIs that take the MSR value in two u32 arguments Xin Li (Intel)
2025-03-31 8:22 ` Xin Li (Intel) [this message]
2025-03-31 8:22 ` [RFC PATCH v1 08/15] x86/cpufeatures: Add a CPU feature bit for MSR immediate form instructions Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 09/15] x86/opcode: Add immediate form MSR instructions to x86-opcode-map Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 10/15] KVM: VMX: Use WRMSRNS or its immediate form when available Xin Li (Intel)
2025-03-31 20:27 ` Konrad Rzeszutek Wilk
2025-03-31 20:38 ` Borislav Petkov
2025-03-31 20:41 ` Andrew Cooper
2025-03-31 20:55 ` H. Peter Anvin
2025-03-31 20:45 ` H. Peter Anvin
2025-04-10 23:24 ` Sean Christopherson
2025-04-11 16:18 ` Xin Li
2025-04-11 20:50 ` H. Peter Anvin
2025-04-12 4:28 ` Xin Li
2025-04-11 21:12 ` Jim Mattson
2025-04-12 4:32 ` Xin Li
2025-04-12 23:10 ` H. Peter Anvin
2025-04-14 17:48 ` Xin Li
2025-04-15 6:56 ` H. Peter Anvin
2025-04-15 17:06 ` Xin Li
2025-04-15 17:07 ` H. Peter Anvin
2025-03-31 8:22 ` [RFC PATCH v1 11/15] x86/extable: Implement EX_TYPE_FUNC_REWIND Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 12/15] x86/msr: Use the alternatives mechanism to write MSR Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 13/15] x86/msr: Use the alternatives mechanism to read MSR Xin Li (Intel)
2025-04-14 17:13 ` Francesco Lavra
2025-04-17 11:10 ` Xin Li
2025-03-31 8:22 ` [RFC PATCH v1 14/15] x86/extable: Add support for the immediate form MSR instructions Xin Li (Intel)
2025-03-31 8:22 ` [RFC PATCH v1 15/15] x86/msr: Move the ARGS macros after the MSR read/write APIs Xin Li (Intel)
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