[PATCH v7 0/2] dmaengine: arm-dma350: handle shared channel IRQ wiring on sky1

[PATCH v7 0/2] dmaengine: arm-dma350: handle shared channel IRQ wiring on sky1

[Jun Guo]

This series updates DMA-350 support for the SKY1 integration where all
DMA
channel interrupt outputs are wired to the same GIC SPI.

Patch 1 enables DMANSECCTRL.INTREN_ANYCHINTR in the driver so
per-channel
interrupt status is propagated even when channels share one parent IRQ
line.

Patch 2 adds the SKY1 DMA-350 DT node and describes the channel
interrupt
sources using 8 channel entries, while all entries map to the same SPI.

Tested on CIX SKY1 with dmatest:
  % echo 2000 > /sys/module/dmatest/parameters/timeout
  % echo 1 > /sys/module/dmatest/parameters/iterations
  % echo "" > /sys/module/dmatest/parameters/channel
  % echo 1 > /sys/module/dmatest/parameters/run

Changes in v7:
- Modify the commit log format for the driver patch.

Changes in v6:
- Drop the dt-binding update and keep the existing 8-channel interrupt
 schema.
- Simplify driver change to a minimal fix:
 enable DMANSECCTRL.INTREN_ANYCHINTR.
- Update SKY1 DT node to describe 8 channel interrupt entries mapped
 to one SPI.

Changes in v5:
- Fix the formatting issue in the AI tag.
- Remove the unnecessary "cix,sky1-dma-350".

Changes in v4:
- Reword binding text to align with kernel style.
- Revise the AI attribution to the standard format.
- Remove redundant links from the commit log.

Changes in v3:
- Rework binding compatible description to match generic-first model.
- Keep interrupts schema support for both 1-IRQ and 8-IRQ topologies.
- Drop SoC match-data dependency for IRQ mode selection.
- Detect IRQ topology via platform_irq_count() in probe path.
- Refactor IRQ handling into a shared channel handler.
- Enable DMANSECCTRL.INTREN_ANYCHINTR only in combined IRQ mode.

Changes in v2:
- Update to kernel standards, enhance patch description, and refactor
 driver to use match data for hardware differentiation instead of
 compatible strings.

Jun Guo (2):
  dmaengine: arm-dma350: enable ANYCH interrupt for shared IRQ wiring
  arm64: dts: cix: add sky1 DMA-350 node with channel IRQ entries

 arch/arm64/boot/dts/cix/sky1.dtsi | 14 ++++++++++++++
 drivers/dma/arm-dma350.c          |  9 +++++++++
 2 files changed, 23 insertions(+)

-- 
2.34.1

[PATCH v7 1/2] dmaengine: arm-dma350: enable ANYCH interrupt for shared IRQ wiring

[Jun Guo]

Enable DMANSECCTRL.INTREN_ANYCHINTR during probe so channel
interrupts are propagated when integrators wire DMA-350 channels
onto a shared IRQ line.

Signed-off-by: Jun Guo <jun.guo@cixtech.com>
---
 drivers/dma/arm-dma350.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c
index 84220fa83029..09403aca8bb0 100644
--- a/drivers/dma/arm-dma350.c
+++ b/drivers/dma/arm-dma350.c
@@ -13,6 +13,11 @@
 #include "dmaengine.h"
 #include "virt-dma.h"
 
+#define DMANSECCTRL		0x200
+
+#define NSEC_CTRL		0x0c
+#define INTREN_ANYCHINTR_EN	BIT(0)
+
 #define DMAINFO			0x0f00
 
 #define DMA_BUILDCFG0		0xb0
@@ -582,6 +587,10 @@ static int d350_probe(struct platform_device *pdev)
 	dmac->dma.device_issue_pending = d350_issue_pending;
 	INIT_LIST_HEAD(&dmac->dma.channels);
 
+	reg = readl_relaxed(base + DMANSECCTRL + NSEC_CTRL);
+	writel_relaxed(reg | INTREN_ANYCHINTR_EN,
+		       base + DMANSECCTRL + NSEC_CTRL);
+
 	/* Would be nice to have per-channel caps for this... */
 	memset = true;
 	for (int i = 0; i < nchan; i++) {
-- 
2.34.1

[PATCH v7 2/2] arm64: dts: cix: add sky1 DMA-350 node with channel IRQ entries

[Jun Guo]

Describe the DMA-350 channel interrupt sources in DT using 8
interrupt entries, while all entries map to the same GIC SPI
as wired on this platform.

Signed-off-by: Jun Guo <jun.guo@cixtech.com>
---
 arch/arm64/boot/dts/cix/sky1.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index bb5cfb1f2113..823adeef51f1 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -444,6 +444,20 @@ iomuxc: pinctrl@4170000 {
 			reg = <0x0 0x04170000 0x0 0x1000>;
 		};
 
+		fch_dmac: dma-controller@4190000 {
+			compatible = "arm,dma-350";
+			reg = <0x0 0x4190000 0x0 0x10000>;
+			interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
+			#dma-cells = <1>;
+		};
+
 		mbox_ap2se: mailbox@5060000 {
 			compatible = "cix,sky1-mbox";
 			reg = <0x0 0x05060000 0x0 0x10000>;
-- 
2.34.1

Re: [PATCH v7 1/2] dmaengine: arm-dma350: enable ANYCH interrupt for shared IRQ wiring

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Enabling the global ANYCH interrupt before clearing channel states and handling error paths can cause spurious interrupt storms and break shared IRQ lines.
--

commit 0bf9d17ebbd8be17166134ed8865c553f2b5eec7
Author: Jun Guo <jun.guo@cixtech.com>

dmaengine: arm-dma350: enable ANYCH interrupt for shared IRQ wiring

This commit enables DMANSECCTRL.INTREN_ANYCHINTR during probe so that channel
interrupts are propagated when integrators wire DMA-350 channels onto a shared
IRQ line.

> diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c
> index 84220fa83029d..09403aca8bb06 100644
> --- a/drivers/dma/arm-dma350.c
> +++ b/drivers/dma/arm-dma350.c

[ ... ]

> @@ -582,6 +587,10 @@ static int d350_probe(struct platform_device *pdev)
>  	dmac->dma.device_issue_pending = d350_issue_pending;
>  	INIT_LIST_HEAD(&dmac->dma.channels);
>  
> +	reg = readl_relaxed(base + DMANSECCTRL + NSEC_CTRL);
> +	writel_relaxed(reg | INTREN_ANYCHINTR_EN,
> +		       base + DMANSECCTRL + NSEC_CTRL);
> +

[Severity: High]
Will enabling INTREN_ANYCHINTR_EN here, before clearing the individual channel
states, potentially cause an interrupt storm on shared IRQ lines?

If a bootloader left a channel with a pending interrupt, this will immediately
assert the shared interrupt line before the DMA driver has registered its IRQ
handler or cleared the channel state in the loop below.

Additionally, if the probe fails midway (for instance, if platform_get_irq
returns an error for a channel):

drivers/dma/arm-dma350.c:d350_probe() {
        ...
        dch->irq = platform_get_irq(pdev, i);
        if (dch->irq < 0)
            return dev_err_probe(dev, dch->irq, ...);
}

Does this error path leave the global ANYCH interrupt enabled without sending
CH_CMD_CLEAR to the remaining channels? Any uncleared pending interrupt on
those remaining channels could permanently assert the shared IRQ line,
eventually causing the kernel to disable the shared IRQ entirely.

>  	/* Would be nice to have per-channel caps for this... */
>  	memset = true;
>  	for (int i = 0; i < nchan; i++) {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260521072924.3000282-1-jun.guo@cixtech.com?part=1