DMA Engine development
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Claudiu Beznea" <claudiu.beznea@kernel.org>
Cc: dmaengine@vger.kernel.org, wsa+renesas@sang-engineering.com,
	Frank.Li@kernel.org, vkoul@kernel.org
Subject: Re: [PATCH v6 10/18] dmaengine: sh: rz-dmac: Refactor pause/resume code
Date: Tue, 26 May 2026 09:28:30 +0000	[thread overview]
Message-ID: <20260526092830.E5F321F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260526084710.3491480-11-claudiu.beznea@kernel.org>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Software status tracking becomes inconsistent if hardware pause/resume operations time out.
- [High] Unconditional hardware resume ignores other active pause requests.
--

commit 9f2ce07d8501ca3cb4ac77194345402583e5ba4b
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

dmaengine: sh: rz-dmac: Refactor pause/resume code

This refactors the pause/resume support in the rz-dmac driver.
It introduces a bitmask-based status field to allow reusing the pause
and resume code for system suspend/resume and cyclic DMA operations.

> diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
> index 1f884ec101f80..557364443a5fd 100644
> --- a/drivers/dma/sh/rz-dmac.c
> +++ b/drivers/dma/sh/rz-dmac.c
[ ... ]
> @@ -795,35 +811,70 @@ static enum dma_status rz_dmac_tx_status(struct dma_chan *chan,
[ ... ]
> +static int rz_dmac_device_resume_set(struct rz_dmac_chan *channel,
> +				     unsigned long clear_bitmask)
> +{
> +	int ret = 0;
> +	u32 val;
> +
> +	lockdep_assert_held(&channel->vc.lock);
> +
> +	/* Do not check CHSTAT_SUS but rely on HW capabilities. */
> +
> +	rz_dmac_ch_writel(channel, CHCTRL_CLRSUS, CHCTRL, 1);

[Severity: High]
Does this unconditional hardware resume ignore other active pause requests?

The bitmask-based status tracking appears to be designed to handle multiple
independent pause conditions. However, writing CHCTRL_CLRSUS happens
regardless of the remaining state.

If a channel is paused for multiple reasons, clearing one condition will
immediately unpause the hardware while other constraints are still active.
Could this regression lead to unexpected DMA execution and data corruption?

> +	ret = read_poll_timeout_atomic(rz_dmac_ch_readl, val,
> +				       !(val & CHSTAT_SUS), 1, 1024, false,
> +				       channel, CHSTAT, 1);
> +
> +	channel->status &= ~clear_bitmask;

[Severity: High]
Should channel->status be cleared if the hardware resume operation times out?

If read_poll_timeout_atomic returns an error like -ETIMEDOUT, the status
bitmask is still unconditionally cleared.

If a caller later attempts to retry the resume operation, it will exit early
because the status bit is already gone, leaving the hardware permanently
suspended while the software stack thinks it is active. Does this create a
regression where the channel can no longer be resumed?

> +
> +	return ret;
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260526084710.3491480-1-claudiu.beznea@kernel.org?part=10

  reply	other threads:[~2026-05-26  9:28 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-26  8:46 [PATCH v6 00/18] Renesas: dmaengine and ASoC fixes Claudiu Beznea
2026-05-26  8:46 ` [PATCH v6 01/18] dmaengine: sh: rz-dmac: Move interrupt request after everything is set up Claudiu Beznea
2026-05-26  8:54   ` Biju Das
2026-05-26  9:45     ` Claudiu Beznea
2026-05-26  9:51       ` Biju Das
2026-05-26 10:25         ` Claudiu Beznea
2026-05-26 10:39           ` Biju Das
2026-05-26  9:20   ` sashiko-bot
2026-05-28 13:44   ` Tommaso Merciai
2026-05-26  8:46 ` [PATCH v6 02/18] dmaengine: sh: rz-dmac: Fix incorrect NULL check for list_first_entry() Claudiu Beznea
2026-05-26  9:03   ` sashiko-bot
2026-05-28 13:45   ` Tommaso Merciai
2026-05-26  8:46 ` [PATCH v6 03/18] dmaengine: sh: rz-dmac: Use list_first_entry_or_null() Claudiu Beznea
2026-05-28 13:45   ` Tommaso Merciai
2026-05-26  8:46 ` [PATCH v6 04/18] dmaengine: sh: rz-dmac: Use rz_dmac_disable_hw() Claudiu Beznea
2026-05-26  9:15   ` sashiko-bot
2026-05-28 13:46   ` Tommaso Merciai
2026-05-26  8:46 ` [PATCH v6 05/18] dmaengine: sh: rz-dmac: Add helper to compute the lmdesc address Claudiu Beznea
2026-05-28 13:47   ` Tommaso Merciai
2026-05-26  8:46 ` [PATCH v6 06/18] dmaengine: sh: rz-dmac: Save the start LM descriptor Claudiu Beznea
2026-05-26  9:41   ` sashiko-bot
2026-05-28 13:47   ` Tommaso Merciai
2026-05-26  8:46 ` [PATCH v6 07/18] dmaengine: sh: rz-dmac: Add helper to check if the channel is enabled Claudiu Beznea
2026-05-28 13:48   ` Tommaso Merciai
2026-05-26  8:47 ` [PATCH v6 08/18] dmaengine: sh: rz-dmac: Add helper to check if the channel is paused Claudiu Beznea
2026-05-28 13:48   ` Tommaso Merciai
2026-05-26  8:47 ` [PATCH v6 09/18] dmaengine: sh: rz-dmac: Use virt-dma APIs for channel descriptor processing Claudiu Beznea
2026-05-26  9:28   ` sashiko-bot
2026-05-28 13:49   ` Tommaso Merciai
2026-05-26  8:47 ` [PATCH v6 10/18] dmaengine: sh: rz-dmac: Refactor pause/resume code Claudiu Beznea
2026-05-26  9:28   ` sashiko-bot [this message]
2026-05-28 13:50   ` Tommaso Merciai
2026-05-26  8:47 ` [PATCH v6 11/18] dmaengine: sh: rz-dmac: Drop the update of channel->chctrl with CHCTRL_SETEN Claudiu Beznea
2026-05-26  9:11   ` sashiko-bot
2026-05-28 13:50   ` Tommaso Merciai
2026-05-26  8:47 ` [PATCH v6 12/18] dmaengine: sh: rz-dmac: Add cyclic DMA support Claudiu Beznea
2026-05-26  9:31   ` sashiko-bot
2026-05-28 13:51   ` Tommaso Merciai
2026-05-26  8:47 ` [PATCH v6 13/18] dmaengine: sh: rz-dmac: Adjust rz_dmac_chan_get_residue() to return error codes Claudiu Beznea
2026-05-28 13:51   ` Tommaso Merciai
2026-05-26  8:47 ` [PATCH v6 14/18] dmaengine: sh: rz-dmac: Add runtime PM support Claudiu Beznea
2026-05-26  9:57   ` sashiko-bot
2026-05-28 13:52   ` Tommaso Merciai
2026-05-26  8:47 ` [PATCH v6 15/18] dmaengine: sh: rz-dmac: Add suspend to RAM support Claudiu Beznea
2026-05-26  9:43   ` sashiko-bot
2026-05-28 14:38   ` Tommaso Merciai
2026-05-26  8:47 ` [PATCH v6 16/18] ASoC: renesas: rz-ssi: Add pause support Claudiu Beznea
2026-05-26  9:46   ` sashiko-bot
2026-05-26  8:47 ` [PATCH v6 17/18] ASoC: renesas: rz-ssi: Use generic PCM dmaengine APIs Claudiu Beznea
2026-05-26 10:00   ` sashiko-bot
2026-05-26  8:47 ` [PATCH v6 18/18] dmaengine: sh: rz-dmac: Set the Link End (LE) bit on the last descriptor Claudiu Beznea
2026-05-26  9:43   ` sashiko-bot
2026-05-28 14:39   ` Tommaso Merciai

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260526092830.E5F321F000E9@smtp.kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=Frank.Li@kernel.org \
    --cc=claudiu.beznea@kernel.org \
    --cc=dmaengine@vger.kernel.org \
    --cc=sashiko-reviews@lists.linux.dev \
    --cc=vkoul@kernel.org \
    --cc=wsa+renesas@sang-engineering.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox