From: Baolu Lu <baolu.lu@linux.intel.com>
To: "Tian, Kevin" <kevin.tian@intel.com>,
"iommu@lists.linux.dev" <iommu@lists.linux.dev>,
"dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>
Cc: baolu.lu@linux.intel.com, Joerg Roedel <joro@8bytes.org>,
Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
"Yu, Fenghua" <fenghua.yu@intel.com>,
"Jiang, Dave" <dave.jiang@intel.com>,
Vinod Koul <vkoul@kernel.org>,
Jacob Pan <jacob.jun.pan@linux.intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 5/5] iommu/vt-d: Move PRI handling to IOPF feature path
Date: Thu, 16 Mar 2023 16:17:00 +0800 [thread overview]
Message-ID: <4a9dd732-344d-64f3-0c9c-b21c196bf940@linux.intel.com> (raw)
In-Reply-To: <BN9PR11MB52766D4948FA00CB02D3F2188CBC9@BN9PR11MB5276.namprd11.prod.outlook.com>
On 2023/3/16 15:17, Tian, Kevin wrote:
>> From: Lu Baolu <baolu.lu@linux.intel.com>
>> Sent: Thursday, March 9, 2023 10:57 AM
>>
>> @@ -4689,17 +4704,21 @@ static int intel_iommu_disable_iopf(struct device
>> *dev)
>> {
>> struct device_domain_info *info = dev_iommu_priv_get(dev);
>> struct intel_iommu *iommu = info->iommu;
>> - int ret;
>>
>> - ret = iommu_unregister_device_fault_handler(dev);
>> - if (ret)
>> - return ret;
>> + if (!info->pri_enabled)
>> + return -EINVAL;
>>
>> - ret = iopf_queue_remove_device(iommu->iopf_queue, dev);
>> - if (ret)
>> - iommu_register_device_fault_handler(dev,
>> iommu_queue_iopf, dev);
>> + pci_disable_pri(to_pci_dev(dev));
>> + info->pri_enabled = 0;
>>
>> - return ret;
>> + /*
>> + * With pri_enabled checked, unregistering fault handler and
>> + * removing device from iopf queue should never fail.
>> + */
>> + iommu_unregister_device_fault_handler(dev);
>> + iopf_queue_remove_device(iommu->iopf_queue, dev);
>> +
>> + return 0;
>> }
>
> PCIe spec says that clearing the enable bit doesn't mean in-fly
> page requests are completed:
> --
> Enable (E) - This field, when set, indicates that the Page Request
> Interface is allowed to make page requests. If this field is Clear,
> the Page Request Interface is not allowed to issue page requests.
> If both this field and the Stopped field are Clear, then the Page
> Request Interface will not issue new page requests, but has
> outstanding page requests that have been transmitted or are
> queued for transmission
Yes. So the iommu driver should drain the in-fly PRQs.
The Intel VT-d implementation drains the PRQs when any PASID is unbound
from the iommu domain (see intel_svm_drain_prq()) before reuse. Before
disabling iopf, the device driver should unbind pasid and disable sva,
so when it comes here, the PRQ should have been drained.
Perhaps I can add below comments to make this clear:
/*
* PCIe spec states that by clearing PRI enable bit, the Page
* Request Interface will not issue new page requests, but has
* outstanding page requests that have been transmitted or are
* queued for transmission. This is supposed to be called after
* the device driver has stopped DMA, all PASIDs have been
* unbound and the outstanding PRQs have been drained.
*/
Best regards,
baolu
next prev parent reply other threads:[~2023-03-16 8:18 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-09 2:56 [PATCH v2 0/5] Refactor code for non-PRI IOPF Lu Baolu
2023-03-09 2:56 ` [PATCH v2 1/5] dmaengine: idxd: Add enable/disable device IOPF feature Lu Baolu
2023-03-09 3:51 ` Fenghua Yu
2023-03-16 7:08 ` Tian, Kevin
2023-03-09 2:56 ` [PATCH v2 2/5] iommu/vt-d: Allow SVA with device-specific IOPF Lu Baolu
2023-03-16 7:09 ` Tian, Kevin
2023-03-16 7:31 ` Baolu Lu
2023-03-20 16:00 ` Jacob Pan
2023-03-21 5:43 ` Baolu Lu
2023-03-09 2:56 ` [PATCH v2 3/5] iommu/vt-d: Move iopf code from SVA to IOPF enabling path Lu Baolu
2023-03-16 7:10 ` Tian, Kevin
2023-03-09 2:56 ` [PATCH v2 4/5] iommu/vt-d: Move pfsid and ats_qdep calculation to device probe path Lu Baolu
2023-03-16 7:10 ` Tian, Kevin
2023-03-20 16:11 ` Jacob Pan
2023-03-09 2:56 ` [PATCH v2 5/5] iommu/vt-d: Move PRI handling to IOPF feature path Lu Baolu
2023-03-16 7:17 ` Tian, Kevin
2023-03-16 8:17 ` Baolu Lu [this message]
2023-03-17 0:06 ` Tian, Kevin
2023-03-17 0:47 ` Baolu Lu
2023-03-20 16:28 ` Jacob Pan
2023-03-09 3:01 ` [PATCH v2 0/5] Refactor code for non-PRI IOPF Baolu Lu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=4a9dd732-344d-64f3-0c9c-b21c196bf940@linux.intel.com \
--to=baolu.lu@linux.intel.com \
--cc=dave.jiang@intel.com \
--cc=dmaengine@vger.kernel.org \
--cc=fenghua.yu@intel.com \
--cc=iommu@lists.linux.dev \
--cc=jacob.jun.pan@linux.intel.com \
--cc=joro@8bytes.org \
--cc=kevin.tian@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=robin.murphy@arm.com \
--cc=vkoul@kernel.org \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox