[PATCH 0/2] dmaengine: idxd: Fix max batch size issues for Intel IAA

[PATCH 0/2] dmaengine: idxd: Fix max batch size issues for Intel IAA

[Xiaochen Shen]

Fix max batch size related issues for Intel IAA:
1. Fix max batch size default values.
2. Make max batch size attributes in sysfs invisible.

Xiaochen Shen (2):
  dmaengine: idxd: Fix max batch size for Intel IAA
  dmaengine: idxd: Make max batch size attributes in sysfs invisible for
    Intel IAA

 .../ABI/stable/sysfs-driver-dma-idxd          |  2 ++
 drivers/dma/idxd/device.c                     |  6 ++--
 drivers/dma/idxd/idxd.h                       | 32 +++++++++++++++++++
 drivers/dma/idxd/init.c                       |  4 +--
 drivers/dma/idxd/sysfs.c                      | 32 ++++++++++++++++++-
 5 files changed, 70 insertions(+), 6 deletions(-)

-- 
2.18.4

[PATCH 1/2] dmaengine: idxd: Fix max batch size for Intel IAA

[Xiaochen Shen]

From Intel IAA spec [1], Intel IAA does not support batch processing.

Two batch related default values for IAA are incorrect in current code:
(1) The max batch size of device is set during device initialization,
    that indicates batch is supported. It should be always 0 on IAA.
(2) The max batch size of work queue is set to WQ_DEFAULT_MAX_BATCH (32)
    as the default value regardless of Intel DSA or IAA device during
    work queue setup and cleanup. It should be always 0 on IAA.

Fix the issues by setting the max batch size of device and max batch
size of work queue to 0 on IAA device, that means batch is not
supported.

[1]: https://cdrdv2.intel.com/v1/dl/getContent/721858

Fixes: 23084545dbb0 ("dmaengine: idxd: set max_xfer and max_batch for RO device")
Fixes: 92452a72ebdf ("dmaengine: idxd: set defaults for wq configs")
Fixes: bfe1d56091c1 ("dmaengine: idxd: Init and probe for Intel data accelerators")
Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Fenghua Yu <fenghua.yu@intel.com>
---
 drivers/dma/idxd/device.c |  6 +++---
 drivers/dma/idxd/idxd.h   | 32 ++++++++++++++++++++++++++++++++
 drivers/dma/idxd/init.c   |  4 ++--
 drivers/dma/idxd/sysfs.c  |  2 +-
 4 files changed, 38 insertions(+), 6 deletions(-)

diff --git a/drivers/dma/idxd/device.c b/drivers/dma/idxd/device.c
index 5a8cc52c1abf..cc7aabe4dc84 100644
--- a/drivers/dma/idxd/device.c
+++ b/drivers/dma/idxd/device.c
@@ -388,7 +388,7 @@ static void idxd_wq_disable_cleanup(struct idxd_wq *wq)
 	clear_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags);
 	memset(wq->name, 0, WQ_NAME_SIZE);
 	wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;
-	wq->max_batch_size = WQ_DEFAULT_MAX_BATCH;
+	idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH);
 }
 
 static void idxd_wq_device_reset_cleanup(struct idxd_wq *wq)
@@ -863,7 +863,7 @@ static int idxd_wq_config_write(struct idxd_wq *wq)
 
 	/* bytes 12-15 */
 	wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes);
-	wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size);
+	idxd_wqcfg_set_max_batch_shift(idxd->data->type, wq->wqcfg, ilog2(wq->max_batch_size));
 
 	dev_dbg(dev, "WQ %d CFGs\n", wq->id);
 	for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
@@ -1031,7 +1031,7 @@ static int idxd_wq_load_config(struct idxd_wq *wq)
 	wq->priority = wq->wqcfg->priority;
 
 	wq->max_xfer_bytes = 1ULL << wq->wqcfg->max_xfer_shift;
-	wq->max_batch_size = 1ULL << wq->wqcfg->max_batch_shift;
+	idxd_wq_set_max_batch_size(idxd->data->type, wq, 1U << wq->wqcfg->max_batch_shift);
 
 	for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
 		wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i);
diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h
index fed0dfc1eaa8..c1617416d379 100644
--- a/drivers/dma/idxd/idxd.h
+++ b/drivers/dma/idxd/idxd.h
@@ -540,6 +540,38 @@ static inline int idxd_wq_refcount(struct idxd_wq *wq)
 	return wq->client_count;
 };
 
+/*
+ * Intel IAA does not support batch processing.
+ * The max batch size of device, max batch size of wq and
+ * max batch shift of wqcfg should be always 0 on IAA.
+ */
+static inline void idxd_set_max_batch_size(int idxd_type, struct idxd_device *idxd,
+					   u32 max_batch_size)
+{
+	if (idxd_type == IDXD_TYPE_IAX)
+		idxd->max_batch_size = 0;
+	else
+		idxd->max_batch_size = max_batch_size;
+}
+
+static inline void idxd_wq_set_max_batch_size(int idxd_type, struct idxd_wq *wq,
+					      u32 max_batch_size)
+{
+	if (idxd_type == IDXD_TYPE_IAX)
+		wq->max_batch_size = 0;
+	else
+		wq->max_batch_size = max_batch_size;
+}
+
+static inline void idxd_wqcfg_set_max_batch_shift(int idxd_type, union wqcfg *wqcfg,
+						  u32 max_batch_shift)
+{
+	if (idxd_type == IDXD_TYPE_IAX)
+		wqcfg->max_batch_shift = 0;
+	else
+		wqcfg->max_batch_shift = max_batch_shift;
+}
+
 int __must_check __idxd_driver_register(struct idxd_device_driver *idxd_drv,
 					struct module *module, const char *mod_name);
 #define idxd_driver_register(driver) \
diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c
index aa3478257ddb..6d03849c698b 100644
--- a/drivers/dma/idxd/init.c
+++ b/drivers/dma/idxd/init.c
@@ -177,7 +177,7 @@ static int idxd_setup_wqs(struct idxd_device *idxd)
 		init_completion(&wq->wq_dead);
 		init_completion(&wq->wq_resurrect);
 		wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;
-		wq->max_batch_size = WQ_DEFAULT_MAX_BATCH;
+		idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH);
 		wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES;
 		wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev));
 		if (!wq->wqcfg) {
@@ -389,7 +389,7 @@ static void idxd_read_caps(struct idxd_device *idxd)
 
 	idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift;
 	dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes);
-	idxd->max_batch_size = 1U << idxd->hw.gen_cap.max_batch_shift;
+	idxd_set_max_batch_size(idxd->data->type, idxd, 1U << idxd->hw.gen_cap.max_batch_shift);
 	dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size);
 	if (idxd->hw.gen_cap.config_en)
 		set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags);
diff --git a/drivers/dma/idxd/sysfs.c b/drivers/dma/idxd/sysfs.c
index 3f262a57441b..fa729fac4b97 100644
--- a/drivers/dma/idxd/sysfs.c
+++ b/drivers/dma/idxd/sysfs.c
@@ -961,7 +961,7 @@ static ssize_t wq_max_batch_size_store(struct device *dev, struct device_attribu
 	if (batch_size > idxd->max_batch_size)
 		return -EINVAL;
 
-	wq->max_batch_size = (u32)batch_size;
+	idxd_wq_set_max_batch_size(idxd->data->type, wq, (u32)batch_size);
 
 	return count;
 }
-- 
2.18.4

[PATCH 2/2] dmaengine: idxd: Make max batch size attributes in sysfs invisible for Intel IAA

[Xiaochen Shen]

In current code, dev.max_batch_size and wq.max_batch_size attributes in
sysfs are exposed to user to show or update the values.

From Intel IAA spec [1], Intel IAA does not support batch processing. So
these sysfs attributes should not be supported on IAA device.

Fix this issue by making the attributes of max_batch_size invisible in
sysfs through is_visible() filter when the device is IAA.

Add description in the ABI documentation to mention that the attributes
are not visible when the device does not support batch.

[1]: https://cdrdv2.intel.com/v1/dl/getContent/721858

Fixes: e7184b159dd3 ("dmaengine: idxd: add support for configurable max wq batch size")
Fixes: c52ca478233c ("dmaengine: idxd: add configuration component of driver")
Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Fenghua Yu <fenghua.yu@intel.com>
---
 .../ABI/stable/sysfs-driver-dma-idxd          |  2 ++
 drivers/dma/idxd/sysfs.c                      | 30 +++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/Documentation/ABI/stable/sysfs-driver-dma-idxd b/Documentation/ABI/stable/sysfs-driver-dma-idxd
index 0c2b613f2373..da3f6d01e0bd 100644
--- a/Documentation/ABI/stable/sysfs-driver-dma-idxd
+++ b/Documentation/ABI/stable/sysfs-driver-dma-idxd
@@ -22,6 +22,7 @@ Date:           Oct 25, 2019
 KernelVersion:  5.6.0
 Contact:        dmaengine@vger.kernel.org
 Description:    The largest number of work descriptors in a batch.
+		It's not visible when the device does not support batch.
 
 What:           /sys/bus/dsa/devices/dsa<m>/max_work_queues_size
 Date:           Oct 25, 2019
@@ -205,6 +206,7 @@ KernelVersion:	5.10.0
 Contact:	dmaengine@vger.kernel.org
 Description:	The max batch size for this workqueue. Cannot exceed device
 		max batch size. Configurable parameter.
+		It's not visible when the device does not support batch.
 
 What:		/sys/bus/dsa/devices/wq<m>.<n>/ats_disable
 Date:		Nov 13, 2020
diff --git a/drivers/dma/idxd/sysfs.c b/drivers/dma/idxd/sysfs.c
index fa729fac4b97..b13a8cc4d24f 100644
--- a/drivers/dma/idxd/sysfs.c
+++ b/drivers/dma/idxd/sysfs.c
@@ -1055,6 +1055,20 @@ static ssize_t wq_enqcmds_retries_store(struct device *dev, struct device_attrib
 static struct device_attribute dev_attr_wq_enqcmds_retries =
 		__ATTR(enqcmds_retries, 0644, wq_enqcmds_retries_show, wq_enqcmds_retries_store);
 
+static umode_t idxd_wq_visible(struct kobject *kobj,
+			       struct attribute *attr, int n)
+{
+	struct device *dev = container_of(kobj, struct device, kobj);
+	struct idxd_wq *wq = confdev_to_wq(dev);
+
+	/* Intel IAA does not support batch processing, make it invisible */
+	if (attr == &dev_attr_wq_max_batch_size.attr &&
+			wq->idxd->data->type == IDXD_TYPE_IAX)
+		return 0;
+
+	return attr->mode;
+}
+
 static struct attribute *idxd_wq_attributes[] = {
 	&dev_attr_wq_clients.attr,
 	&dev_attr_wq_state.attr,
@@ -1077,6 +1091,7 @@ static struct attribute *idxd_wq_attributes[] = {
 
 static const struct attribute_group idxd_wq_attribute_group = {
 	.attrs = idxd_wq_attributes,
+	.is_visible = idxd_wq_visible,
 };
 
 static const struct attribute_group *idxd_wq_attribute_groups[] = {
@@ -1366,6 +1381,20 @@ static ssize_t cmd_status_store(struct device *dev, struct device_attribute *att
 }
 static DEVICE_ATTR_RW(cmd_status);
 
+static umode_t idxd_device_visible(struct kobject *kobj,
+				   struct attribute *attr, int n)
+{
+	struct device *dev = container_of(kobj, struct device, kobj);
+	struct idxd_device *idxd = confdev_to_idxd(dev);
+
+	/* Intel IAA does not support batch processing, make it invisible */
+	if (attr == &dev_attr_max_batch_size.attr &&
+			idxd->data->type == IDXD_TYPE_IAX)
+		return 0;
+
+	return attr->mode;
+}
+
 static struct attribute *idxd_device_attributes[] = {
 	&dev_attr_version.attr,
 	&dev_attr_max_groups.attr,
@@ -1393,6 +1422,7 @@ static struct attribute *idxd_device_attributes[] = {
 
 static const struct attribute_group idxd_device_attribute_group = {
 	.attrs = idxd_device_attributes,
+	.is_visible = idxd_device_visible,
 };
 
 static const struct attribute_group *idxd_attribute_groups[] = {
-- 
2.18.4

RE: [PATCH 0/2] dmaengine: idxd: Fix max batch size issues for Intel IAA

[Yu, Fenghua]

Hi, Vinod,

> Fix max batch size related issues for Intel IAA:
> 1. Fix max batch size default values.
> 2. Make max batch size attributes in sysfs invisible.

Any comment on this patch set? Would you apply it?

Thanks.

-Fenghua

Re: [PATCH 0/2] dmaengine: idxd: Fix max batch size issues for Intel IAA

[Vinod Koul]

On 15-09-22, 16:21, Yu, Fenghua wrote:
> Hi, Vinod,
> 
> > Fix max batch size related issues for Intel IAA:
> > 1. Fix max batch size default values.
> > 2. Make max batch size attributes in sysfs invisible.
> 
> Any comment on this patch set? Would you apply it?

This does not apply for me (i guess due to other idxd patches I have
applied today), pls rebase on next and resend

-- 
~Vinod

RE: [PATCH 0/2] dmaengine: idxd: Fix max batch size issues for Intel IAA

[Yu, Fenghua]

Hi, Vinod,

On 29-09-22, 9:47, Vinod Koul wrote:
> On 15-09-22, 16:21, Yu, Fenghua wrote:
> > Hi, Vinod,
> >
> > > Fix max batch size related issues for Intel IAA:
> > > 1. Fix max batch size default values.
> > > 2. Make max batch size attributes in sysfs invisible.
> >
> > Any comment on this patch set? Would you apply it?
> 
> This does not apply for me (i guess due to other idxd patches I have applied
> today), pls rebase on next and resend

Is this the repo we need to rebase the patch set to? Which branch should be used?
https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git

Thanks.

-Fenghua

Re: [PATCH 0/2] dmaengine: idxd: Fix max batch size issues for Intel IAA

[Xiaochen Shen]

Hi Vinod,

Thank you very much for code review!

On 9/30/2022 0:46, Vinod Koul wrote:
> On 15-09-22, 16:21, Yu, Fenghua wrote:
>> Hi, Vinod,
>>
>>> Fix max batch size related issues for Intel IAA:
>>> 1. Fix max batch size default values.
>>> 2. Make max batch size attributes in sysfs invisible.
>>
>> Any comment on this patch set? Would you apply it?
> 
> This does not apply for me (i guess due to other idxd patches I have
> applied today), pls rebase on next and resend
> 

Could you help check if these idxd patches are merged into 'next' branch of
https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git ?

I will rebase on top of 'next' branch and resend the patch soon.
Thank you very much!


Best regards,
Xiaochen

Re: [PATCH 0/2] dmaengine: idxd: Fix max batch size issues for Intel IAA

[Vinod Koul]

On 30-09-22, 11:18, Xiaochen Shen wrote:
> Hi Vinod,
> 
> Thank you very much for code review!
> 
> On 9/30/2022 0:46, Vinod Koul wrote:
> > On 15-09-22, 16:21, Yu, Fenghua wrote:
> > > Hi, Vinod,
> > > 
> > > > Fix max batch size related issues for Intel IAA:
> > > > 1. Fix max batch size default values.
> > > > 2. Make max batch size attributes in sysfs invisible.
> > > 
> > > Any comment on this patch set? Would you apply it?
> > 
> > This does not apply for me (i guess due to other idxd patches I have
> > applied today), pls rebase on next and resend
> > 
> 
> Could you help check if these idxd patches are merged into 'next' branch of
> https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git ?
> 
> I will rebase on top of 'next' branch and resend the patch soon.
> Thank you very much!

yes pls rebase on -next branch, thanks

-- 
~Vinod

Re: [PATCH 0/2] dmaengine: idxd: Fix max batch size issues for Intel IAA

[Xiaochen Shen]

Hi Vinod,

On 10/1/2022 0:18, Vinod Koul wrote:
> yes pls rebase on -next branch, thanks

Please find v2 patchset which is rebased on -next branch:
https://lore.kernel.org/all/20220930201528.18621-1-xiaochen.shen@intel.com/

Thank you very much!


Best regards,
Xiaochen