* [v2] dmaengine: fsl-edma: remove dma_slave_config direction usage
From: Vinod Koul @ 2018-10-07 14:14 UTC (permalink / raw)
To: dmaengine; +Cc: Vinod Koul, Angelo Dureghello, Krzysztof Kozlowski
dma_slave_config direction was marked as deprecated quite some
time back, remove the usage from this driver so that the field
can be removed
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
CC: Angelo Dureghello <angelo@sysam.it>
CC: Krzysztof Kozlowski <krzk@kernel.org>
Angelo, Krzysztof,
I have rebased this against the latest fsl-edma changes, can you
please verify this and let me know, thnx
drivers/dma/fsl-edma-common.c | 74 +++++++++++++++++++++++++------------------
drivers/dma/fsl-edma-common.h | 12 ++-----
include/linux/dmaengine.h | 1 -
3 files changed, 46 insertions(+), 41 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 8ba80f4b6f55..8876c4c1bb2c 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -178,19 +178,7 @@ int fsl_edma_slave_config(struct dma_chan *chan,
{
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
- fsl_chan->fsc.dir = cfg->direction;
- if (cfg->direction == DMA_DEV_TO_MEM) {
- fsl_chan->fsc.dev_addr = cfg->src_addr;
- fsl_chan->fsc.addr_width = cfg->src_addr_width;
- fsl_chan->fsc.burst = cfg->src_maxburst;
- fsl_chan->fsc.attr = fsl_edma_get_tcd_attr(cfg->src_addr_width);
- } else if (cfg->direction == DMA_MEM_TO_DEV) {
- fsl_chan->fsc.dev_addr = cfg->dst_addr;
- fsl_chan->fsc.addr_width = cfg->dst_addr_width;
- fsl_chan->fsc.burst = cfg->dst_maxburst;
- fsl_chan->fsc.attr = fsl_edma_get_tcd_attr(cfg->dst_addr_width);
- } else
- return -EINVAL;
+ memcpy(&fsl_chan->cfg, cfg, sizeof(*cfg));
return 0;
}
@@ -202,7 +190,7 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
struct fsl_edma_desc *edesc = fsl_chan->edesc;
struct edma_regs *regs = &fsl_chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- enum dma_transfer_direction dir = fsl_chan->fsc.dir;
+ enum dma_transfer_direction dir = edesc->dirn;
dma_addr_t cur_addr, dma_addr;
size_t len, size;
int i;
@@ -387,7 +375,7 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
u32 src_addr, dst_addr, last_sg, nbytes;
u16 soff, doff, iter;
- if (!is_slave_direction(fsl_chan->fsc.dir))
+ if (!is_slave_direction(direction))
return NULL;
sg_len = buf_len / period_len;
@@ -395,9 +383,21 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
if (!fsl_desc)
return NULL;
fsl_desc->iscyclic = true;
+ fsl_desc->dirn = direction;
dma_buf_next = dma_addr;
- nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst;
+ if (direction == DMA_MEM_TO_DEV) {
+ fsl_chan->attr =
+ fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width);
+ nbytes = fsl_chan->cfg.dst_addr_width *
+ fsl_chan->cfg.dst_maxburst;
+ } else {
+ fsl_chan->attr =
+ fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width);
+ nbytes = fsl_chan->cfg.src_addr_width *
+ fsl_chan->cfg.src_maxburst;
+ }
+
iter = period_len / nbytes;
for (i = 0; i < sg_len; i++) {
@@ -407,20 +407,20 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
/* get next sg's physical address */
last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
- if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) {
+ if (direction == DMA_MEM_TO_DEV) {
src_addr = dma_buf_next;
- dst_addr = fsl_chan->fsc.dev_addr;
- soff = fsl_chan->fsc.addr_width;
+ dst_addr = fsl_chan->cfg.dst_addr;
+ soff = fsl_chan->cfg.dst_addr_width;
doff = 0;
} else {
- src_addr = fsl_chan->fsc.dev_addr;
+ src_addr = fsl_chan->cfg.src_addr;
dst_addr = dma_buf_next;
soff = 0;
- doff = fsl_chan->fsc.addr_width;
+ doff = fsl_chan->cfg.src_addr_width;
}
fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr,
- fsl_chan->fsc.attr, soff, nbytes, 0, iter,
+ fsl_chan->attr, soff, nbytes, 0, iter,
iter, doff, last_sg, true, false, true);
dma_buf_next += period_len;
}
@@ -441,42 +441,54 @@ struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
u16 soff, doff, iter;
int i;
- if (!is_slave_direction(fsl_chan->fsc.dir))
+ if (!is_slave_direction(direction))
return NULL;
fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
if (!fsl_desc)
return NULL;
fsl_desc->iscyclic = false;
+ fsl_desc->dirn = direction;
+
+ if (direction == DMA_MEM_TO_DEV) {
+ fsl_chan->attr =
+ fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width);
+ nbytes = fsl_chan->cfg.dst_addr_width *
+ fsl_chan->cfg.dst_maxburst;
+ } else {
+ fsl_chan->attr =
+ fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width);
+ nbytes = fsl_chan->cfg.src_addr_width *
+ fsl_chan->cfg.src_maxburst;
+ }
- nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst;
for_each_sg(sgl, sg, sg_len, i) {
/* get next sg's physical address */
last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
- if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) {
+ if (direction == DMA_MEM_TO_DEV) {
src_addr = sg_dma_address(sg);
- dst_addr = fsl_chan->fsc.dev_addr;
- soff = fsl_chan->fsc.addr_width;
+ dst_addr = fsl_chan->cfg.dst_addr;
+ soff = fsl_chan->cfg.dst_addr_width;
doff = 0;
} else {
- src_addr = fsl_chan->fsc.dev_addr;
+ src_addr = fsl_chan->cfg.src_addr;
dst_addr = sg_dma_address(sg);
soff = 0;
- doff = fsl_chan->fsc.addr_width;
+ doff = fsl_chan->cfg.src_addr_width;
}
iter = sg_dma_len(sg) / nbytes;
if (i < sg_len - 1) {
last_sg = fsl_desc->tcd[(i + 1)].ptcd;
fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
- dst_addr, fsl_chan->fsc.attr, soff,
+ dst_addr, fsl_chan->attr, soff,
nbytes, 0, iter, iter, doff, last_sg,
false, false, true);
} else {
last_sg = 0;
fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
- dst_addr, fsl_chan->fsc.attr, soff,
+ dst_addr, fsl_chan->attr, soff,
nbytes, 0, iter, iter, doff, last_sg,
true, true, false);
}
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index a6f5b99ee95f..8917e8865959 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -109,14 +109,6 @@ struct fsl_edma_sw_tcd {
struct fsl_edma_hw_tcd *vtcd;
};
-struct fsl_edma_slave_config {
- enum dma_transfer_direction dir;
- enum dma_slave_buswidth addr_width;
- u32 dev_addr;
- u32 burst;
- u32 attr;
-};
-
struct fsl_edma_chan {
struct virt_dma_chan vchan;
enum dma_status status;
@@ -125,7 +117,8 @@ struct fsl_edma_chan {
u32 slave_id;
struct fsl_edma_engine *edma;
struct fsl_edma_desc *edesc;
- struct fsl_edma_slave_config fsc;
+ struct dma_slave_config cfg;
+ u32 attr;
struct dma_pool *tcd_pool;
};
@@ -133,6 +126,7 @@ struct fsl_edma_desc {
struct virt_dma_desc vdesc;
struct fsl_edma_chan *echan;
bool iscyclic;
+ enum dma_transfer_direction dirn;
unsigned int n_tcds;
struct fsl_edma_sw_tcd tcd[];
};
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index d49ec5c31944..f158eaae0ef6 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -365,7 +365,6 @@ enum dma_slave_buswidth {
* data, then prefer to do that.
*/
struct dma_slave_config {
- enum dma_transfer_direction direction;
phys_addr_t src_addr;
phys_addr_t dst_addr;
enum dma_slave_buswidth src_addr_width;
^ permalink raw reply related
* dmaengine: rcar-dmac: set scatter/gather max segment size
From: Vinod Koul @ 2018-10-07 14:34 UTC (permalink / raw)
To: Wolfram Sang; +Cc: dmaengine, linux-renesas-soc, Geert Uytterhoeven
On 14-09-18, 17:43, Wolfram Sang wrote:
> Fix warning when running with CONFIG_DMA_API_DEBUG_SG=y by allocating a
> device_dma_parameters structure and filling in the max segment size.
Applied, thanks
^ permalink raw reply
* [v3,1/7] dt-bindings: stm32-dma: Add DMA/MDMA chaining support bindings
From: Vinod Koul @ 2018-10-07 14:57 UTC (permalink / raw)
To: Pierre-Yves MORDRET
Cc: Rob Herring, Mark Rutland, Alexandre Torgue, Maxime Coquelin,
Dan Williams, devicetree, dmaengine, linux-arm-kernel,
linux-kernel
On 28-09-18, 15:01, Pierre-Yves MORDRET wrote:
> From: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
>
> This patch adds dma bindings to support DMA/MDMA chaining transfer.
> 1 bit is to manage both DMA FIFO Threshold
> 1 bit is to manage DMA/MDMA Chaining features.
> 2 bits are used to specify SDRAM size to use for DMA/MDMA chaining.
Please do mention which specific bits?
> The size in bytes of a certain order is given by the formula:
> (2 ^ order) * PAGE_SIZE.
> The order is given by those 2 bits.
> For cyclic, whether chaining is chosen, any value above 1 can be set :
> SRAM buffer size will rely on period size and not on this DT value.
>
> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
> ---
> Version history:
> v3:
> v2:
> * rework content
> v1:
> * Initial
> ---
> ---
> .../devicetree/bindings/dma/stm32-dma.txt | 27 +++++++++++++++++++++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/stm32-dma.txt b/Documentation/devicetree/bindings/dma/stm32-dma.txt
> index c5f5190..2bac8c7 100644
> --- a/Documentation/devicetree/bindings/dma/stm32-dma.txt
> +++ b/Documentation/devicetree/bindings/dma/stm32-dma.txt
> @@ -17,6 +17,12 @@ Optional properties:
> - resets: Reference to a reset controller asserting the DMA controller
> - st,mem2mem: boolean; if defined, it indicates that the controller supports
> memory-to-memory transfer
> +- dmas: A list of eight dma specifiers, one for each entry in dma-names.
> + Refer to stm32-mdma.txt for more details.
> +- dma-names: should contain "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6" and
> + "ch7" and represents each STM32 DMA channel connected to a STM32 MDMA one.
> +- memory-region : phandle to a node describing memory to be used for
> + M2M intermediate transfer between DMA and MDMA.
>
> Example:
>
> @@ -36,6 +42,16 @@ Example:
> st,mem2mem;
> resets = <&rcc 150>;
> dma-requests = <8>;
> + dmas = <&mdma1 8 0x10 0x1200000a 0x40026408 0x00000020 1>,
> + <&mdma1 9 0x10 0x1200000a 0x40026408 0x00000800 1>,
> + <&mdma1 10 0x10 0x1200000a 0x40026408 0x00200000 1>,
> + <&mdma1 11 0x10 0x1200000a 0x40026408 0x08000000 1>,
> + <&mdma1 12 0x10 0x1200000a 0x4002640C 0x00000020 1>,
> + <&mdma1 13 0x10 0x1200000a 0x4002640C 0x00000800 1>,
> + <&mdma1 14 0x10 0x1200000a 0x4002640C 0x00200000 1>,
> + <&mdma1 15 0x10 0x1200000a 0x4002640C 0x08000000 1>;
> + dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
> + memory-region = <&sram_dmapool>;
> };
>
> * DMA client
> @@ -68,7 +84,16 @@ channel: a phandle to the DMA controller plus the following four integer cells:
> 0x1: 1/2 full FIFO
> 0x2: 3/4 full FIFO
> 0x3: full FIFO
> -
> + -bit 2: Intermediate M2M transfer from/to DDR to/from SRAM throughout MDMA
> + 0: MDMA not used to generate an intermediate M2M transfer
> + 1: MDMA used to generate an intermediate M2M transfer.
> + -bit 3-4: indicated SRAM Buffer size in (2^order)*PAGE_SIZE.
> + PAGE_SIZE is given by Linux at 4KiB: include/asm-generic/page.h.
> + Order is given by those 2 bits starting at 0.
> + Valid only whether Intermediate M2M transfer is set.
why do we need this as a property?
> + For cyclic, whether Intermediate M2M transfer is chosen, any value can
> + be set: SRAM buffer size will rely on period size and not on this DT
> + value.
>
> Example:
>
> --
> 2.7.4
^ permalink raw reply
* [v3,2/7] dt-bindings: stm32-dmamux: Add one cell to support DMA/MDMA chain
From: Vinod Koul @ 2018-10-07 14:58 UTC (permalink / raw)
To: Pierre-Yves MORDRET
Cc: Rob Herring, Mark Rutland, Alexandre Torgue, Maxime Coquelin,
Dan Williams, devicetree, dmaengine, linux-arm-kernel,
linux-kernel
On 28-09-18, 15:01, Pierre-Yves MORDRET wrote:
> From: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
>
> Add one cell to support DMA/MDMA chaining.
>
> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
> ---
> Version history:
> v3:
> v2:
> * rework content
> v1:
> * Initial
> ---
> ---
> Documentation/devicetree/bindings/dma/stm32-dmamux.txt | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt
> index 1b893b2..5e92b59 100644
> --- a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt
> +++ b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt
> @@ -4,9 +4,9 @@ Required properties:
> - compatible: "st,stm32h7-dmamux"
> - reg: Memory map for accessing module
> - #dma-cells: Should be set to <3>.
> - First parameter is request line number.
> - Second is DMA channel configuration
> - Third is Fifo threshold
> +- First parameter is request line number.
> +- Second is DMA channel configuration
> +- Third is a 32bit bitfield
please separate out formatting changes and actual change proposed..
> For more details about the three cells, please see
> stm32-dma.txt documentation binding file
> - dma-masters: Phandle pointing to the DMA controllers.
> --
> 2.7.4
^ permalink raw reply
* [v3,3/7] dt-bindings: stm32-mdma: Add DMA/MDMA chaining support bindings
From: Vinod Koul @ 2018-10-07 14:59 UTC (permalink / raw)
To: Pierre-Yves MORDRET
Cc: Rob Herring, Mark Rutland, Alexandre Torgue, Maxime Coquelin,
Dan Williams, devicetree, dmaengine, linux-arm-kernel,
linux-kernel
On 28-09-18, 15:01, Pierre-Yves MORDRET wrote:
> From: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
>
> This patch adds the description of the 2 properties needed to support M2M
> transfer triggered by STM32 DMA when his transfer is complete.
>
> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
> ---
> Version history:
> v3:
> v2:
> * rework content
> v1:
> * Initial
> ---
> ---
> Documentation/devicetree/bindings/dma/stm32-mdma.txt | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/stm32-mdma.txt b/Documentation/devicetree/bindings/dma/stm32-mdma.txt
> index d18772d..27c2812 100644
> --- a/Documentation/devicetree/bindings/dma/stm32-mdma.txt
> +++ b/Documentation/devicetree/bindings/dma/stm32-mdma.txt
> @@ -10,7 +10,7 @@ Required properties:
> - interrupts: Should contain the MDMA interrupt.
> - clocks: Should contain the input clock of the DMA instance.
> - resets: Reference to a reset controller asserting the DMA controller.
> -- #dma-cells : Must be <5>. See DMA client paragraph for more details.
> +- #dma-cells : Must be <6>. See DMA client paragraph for more details.
can you update the example for 6 cells?
Also what happens to dts using 5 cells..
>
> Optional properties:
> - dma-channels: Number of DMA channels supported by the controller.
> @@ -26,7 +26,7 @@ Example:
> interrupts = <122>;
> clocks = <&timer_clk>;
> resets = <&rcc 992>;
> - #dma-cells = <5>;
> + #dma-cells = <6>;
> dma-channels = <16>;
> dma-requests = <32>;
> st,ahb-addr-masks = <0x20000000>, <0x00000000>;
> @@ -35,8 +35,8 @@ Example:
> * DMA client
>
> DMA clients connected to the STM32 MDMA controller must use the format
> -described in the dma.txt file, using a five-cell specifier for each channel:
> -a phandle to the MDMA controller plus the following five integer cells:
> +described in the dma.txt file, using a six-cell specifier for each channel:
> +a phandle to the MDMA controller plus the following six integer cells:
>
> 1. The request line number
> 2. The priority level
> @@ -76,6 +76,10 @@ a phandle to the MDMA controller plus the following five integer cells:
> if no HW ack signal is used by the MDMA client
> 5. A 32bit mask specifying the value to be written to acknowledge the request
> if no HW ack signal is used by the MDMA client
> +6. A bitfield value specifying if the MDMA client wants to generate M2M
> + transfer with HW trigger (1) or not (0). This bitfield should be only
> + enabled for M2M transfer triggered by STM32 DMA client. The memory devices
> + involved in this kind of transfer are SRAM and DDR.
>
> Example:
>
> --
> 2.7.4
^ permalink raw reply
* [v3,4/7] dmaengine: stm32-dma: Add DMA/MDMA chaining support
From: Vinod Koul @ 2018-10-07 16:00 UTC (permalink / raw)
To: Pierre-Yves MORDRET
Cc: Rob Herring, Mark Rutland, Alexandre Torgue, Maxime Coquelin,
Dan Williams, devicetree, dmaengine, linux-arm-kernel,
linux-kernel
On 28-09-18, 15:01, Pierre-Yves MORDRET wrote:
> This patch adds support of DMA/MDMA chaining support.
> It introduces an intermediate transfer between peripherals and STM32 DMA.
> This intermediate transfer is triggered by SW for single M2D transfer and
> by STM32 DMA IP for all other modes (sg, cyclic) and direction (D2M).
>
> A generic SRAM allocator is used for this intermediate buffer
> Each DMA channel will be able to define its SRAM needs to achieve chaining
> feature : (2 ^ order) * PAGE_SIZE.
> For cyclic, SRAM buffer is derived from period length (rounded on
> PAGE_SIZE).
So IIUC, you chain two dma txns together and transfer data via an SRAM?
>
> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
> ---
> Version history:
> v3:
> * Solve KBuild warning
> v2:
> v1:
> * Initial
> ---
> ---
> drivers/dma/stm32-dma.c | 879 ++++++++++++++++++++++++++++++++++++++++++------
that is a lot of change for a driver, consider splitting it up
logically in smaller changes...
> 1 file changed, 772 insertions(+), 107 deletions(-)
>
> diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
> index 379e8d5..85e81c4 100644
> --- a/drivers/dma/stm32-dma.c
> +++ b/drivers/dma/stm32-dma.c
> @@ -15,11 +15,14 @@
> #include <linux/dmaengine.h>
> #include <linux/dma-mapping.h>
> #include <linux/err.h>
> +#include <linux/genalloc.h>
> #include <linux/init.h>
> +#include <linux/iopoll.h>
> #include <linux/jiffies.h>
> #include <linux/list.h>
> #include <linux/module.h>
> #include <linux/of.h>
> +#include <linux/of_address.h>
> #include <linux/of_device.h>
> #include <linux/of_dma.h>
> #include <linux/platform_device.h>
> @@ -118,6 +121,7 @@
> #define STM32_DMA_FIFO_THRESHOLD_FULL 0x03
>
> #define STM32_DMA_MAX_DATA_ITEMS 0xffff
> +#define STM32_DMA_SRAM_GRANULARITY PAGE_SIZE
> /*
> * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter
> * gather at boundary. Thus it's safer to round down this value on FIFO
> @@ -135,6 +139,12 @@
> /* DMA Features */
> #define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0)
> #define STM32_DMA_THRESHOLD_FTR_GET(n) ((n) & STM32_DMA_THRESHOLD_FTR_MASK)
> +#define STM32_DMA_MDMA_CHAIN_FTR_MASK BIT(2)
> +#define STM32_DMA_MDMA_CHAIN_FTR_GET(n) (((n) & STM32_DMA_MDMA_CHAIN_FTR_MASK) \
> + >> 2)
> +#define STM32_DMA_MDMA_SRAM_SIZE_MASK GENMASK(4, 3)
> +#define STM32_DMA_MDMA_SRAM_SIZE_GET(n) (((n) & STM32_DMA_MDMA_SRAM_SIZE_MASK) \
> + >> 3)
>
> enum stm32_dma_width {
> STM32_DMA_BYTE,
> @@ -176,15 +186,31 @@ struct stm32_dma_chan_reg {
> u32 dma_sfcr;
> };
>
> +struct stm32_dma_mdma_desc {
> + struct sg_table sgt;
> + struct dma_async_tx_descriptor *desc;
> +};
> +
> +struct stm32_dma_mdma {
> + struct dma_chan *chan;
> + enum dma_transfer_direction dir;
> + dma_addr_t sram_buf;
> + u32 sram_period;
> + u32 num_sgs;
> +};
> +
> struct stm32_dma_sg_req {
> - u32 len;
> + struct scatterlist stm32_sgl_req;
> struct stm32_dma_chan_reg chan_reg;
> + struct stm32_dma_mdma_desc m_desc;
> };
>
> struct stm32_dma_desc {
> struct virt_dma_desc vdesc;
> bool cyclic;
> u32 num_sgs;
> + dma_addr_t dma_buf;
> + void *dma_buf_cpu;
> struct stm32_dma_sg_req sg_req[];
> };
>
> @@ -201,6 +227,10 @@ struct stm32_dma_chan {
> u32 threshold;
> u32 mem_burst;
> u32 mem_width;
> + struct stm32_dma_mdma mchan;
> + u32 use_mdma;
> + u32 sram_size;
> + u32 residue_after_drain;
> };
>
> struct stm32_dma_device {
> @@ -210,6 +240,7 @@ struct stm32_dma_device {
> struct reset_control *rst;
> bool mem2mem;
> struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS];
> + struct gen_pool *sram_pool;
> };
>
> static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan)
> @@ -497,11 +528,15 @@ static void stm32_dma_stop(struct stm32_dma_chan *chan)
> static int stm32_dma_terminate_all(struct dma_chan *c)
> {
> struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
> + struct stm32_dma_mdma *mchan = &chan->mchan;
> unsigned long flags;
> LIST_HEAD(head);
>
> spin_lock_irqsave(&chan->vchan.lock, flags);
>
> + if (chan->use_mdma)
> + dmaengine_terminate_async(mchan->chan);
> +
> if (chan->busy) {
> stm32_dma_stop(chan);
> chan->desc = NULL;
> @@ -514,9 +549,96 @@ static int stm32_dma_terminate_all(struct dma_chan *c)
> return 0;
> }
>
> +static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan)
> +{
> + u32 dma_scr, width, ndtr;
> + struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
> +
> + dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
> + width = STM32_DMA_SCR_PSIZE_GET(dma_scr);
> + ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
> +
> + return ndtr << width;
> +}
> +
> +static int stm32_dma_mdma_drain(struct stm32_dma_chan *chan)
> +{
> + struct stm32_dma_mdma *mchan = &chan->mchan;
> + struct stm32_dma_sg_req *sg_req;
> + struct dma_device *ddev = mchan->chan->device;
> + struct dma_async_tx_descriptor *desc = NULL;
> + enum dma_status status;
> + dma_addr_t src_buf, dst_buf;
> + u32 mdma_residue, mdma_wrote, dma_to_write, len;
> + struct dma_tx_state state;
> + int ret;
> +
> + /* DMA/MDMA chain: drain remaining data in SRAM */
> +
> + /* Get the residue on MDMA side */
> + status = dmaengine_tx_status(mchan->chan, mchan->chan->cookie, &state);
> + if (status == DMA_COMPLETE)
> + return status;
> +
> + mdma_residue = state.residue;
> + sg_req = &chan->desc->sg_req[chan->next_sg - 1];
> + len = sg_dma_len(&sg_req->stm32_sgl_req);
> +
> + /*
> + * Total = mdma blocks * sram_period + rest (< sram_period)
> + * so mdma blocks * sram_period = len - mdma residue - rest
> + */
> + mdma_wrote = len - mdma_residue - (len % mchan->sram_period);
> +
> + /* Remaining data stuck in SRAM */
> + dma_to_write = mchan->sram_period - stm32_dma_get_remaining_bytes(chan);
> + if (dma_to_write > 0) {
> + /* Stop DMA current operation */
> + stm32_dma_disable_chan(chan);
> +
> + /* Terminate current MDMA to initiate a new one */
> + dmaengine_terminate_all(mchan->chan);
> +
> + /* Double buffer management */
> + src_buf = mchan->sram_buf +
> + ((mdma_wrote / mchan->sram_period) & 0x1) *
> + mchan->sram_period;
> + dst_buf = sg_dma_address(&sg_req->stm32_sgl_req) + mdma_wrote;
> +
> + desc = ddev->device_prep_dma_memcpy(mchan->chan,
> + dst_buf, src_buf,
> + dma_to_write,
> + DMA_PREP_INTERRUPT);
why would you do that?
If at all you need to create anothe txn, I think it would be good to
prepare a new descriptor and chain it, not call the dmaengine APIs..
^ permalink raw reply
* [v5,4/7] dmaengine: xilinx_dma: program hardware supported buffer length
From: Andrea Merello @ 2018-10-08 6:46 UTC (permalink / raw)
To: Vinod
Cc: dan.j.williams, michal.simek, appana.durga.rao, dmaengine,
linux-arm-kernel, linux-kernel, Rob Herring, Mark Rutland,
devicetree, Radhey Shyam Pandey
On Tue, Oct 2, 2018 at 4:56 PM Vinod <vkoul@kernel.org> wrote:
>
> On 28-09-18, 08:53, Andrea Merello wrote:
> > On Tue, Sep 18, 2018 at 6:25 PM Vinod <vkoul@kernel.org> wrote:
>
> > > > @@ -964,7 +968,7 @@ static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan,
> > > > int size, int done)
> > > > {
> > > > size_t copy = min_t(size_t, size - done,
> > > > - XILINX_DMA_MAX_TRANS_LEN);
> > > > + chan->xdev->max_buffer_len);
> > >
> > > hmm why not add max_buffer_len in patch 1 again, and then use default
> > > len as XILINX_DMA_MAX_TRANS_LEN and add multiple lengths here :)
> >
> > Sorry, I'm not getting your point. Could you please elaborate the "add
> > multiple lengths here" thing ?
>
> IIRC (sorry been travelling and vacation), add
> chan->xdev->max_buffer_len in patch 1 and initialize it to
> XILINX_DMA_MAX_TRANS_LEN. Then in subsequent patches update the length.
Ah ok. IMO introducing max_buffer_len seems more related to what 4/7
does (actually getting the max transfer len from DT, thus it is not
constant anymore) rather than to what 1/7 does (commonizing the
calculation of transfer len as it is).. This is why I've introduced it
in 4/7..
.. But if you prefer this way, I'll change this :) .. Maybe we can
change 1/7 commit message so that this change looks less off-topic..
But I have not found a very good title yet.. Something like "Prepare
for DMA copy size calculation rework" ?
> --
> ~Vinod
^ permalink raw reply
* dmaengine: owl: Fix warnings generated during build
From: Manivannan Sadhasivam @ 2018-10-08 17:16 UTC (permalink / raw)
To: vkoul
Cc: afaerber, dmaengine, liuwei, 96boards, linux-arm-kernel,
linux-kernel, hzhang, bdong, manivannanece23, thomas.liau, pn,
edgar.righi, Manivannan Sadhasivam
Following warnings are generated when compiled with W=1,
drivers/dma/owl-dma.c:170: warning: Function parameter or member 'cyclic'
not described in 'owl_dma_txd'
drivers/dma/owl-dma.c:198: warning: Function parameter or member 'cfg' not
described in 'owl_dma_vchan'
drivers/dma/owl-dma.c:198: warning: Function parameter or member 'drq' not
described in 'owl_dma_vchan'
drivers/dma/owl-dma.c:225: warning: Function parameter or member 'irq' not
described in 'owl_dma'
Fix this by adding comments for relevant struct members to appear in
kernel-doc.
Fixes: d64e1b3f5cce ("dmaengine: owl: Add Slave and Cyclic mode support for
Actions Semi Owl S900 SoC")
Reported-by: Vinod Koul <vinod.koul@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/dma/owl-dma.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/dma/owl-dma.c b/drivers/dma/owl-dma.c
index 1d26db4c9229..90bbcef99ef8 100644
--- a/drivers/dma/owl-dma.c
+++ b/drivers/dma/owl-dma.c
@@ -162,6 +162,7 @@ struct owl_dma_lli {
* struct owl_dma_txd - Wrapper for struct dma_async_tx_descriptor
* @vd: virtual DMA descriptor
* @lli_list: link list of lli nodes
+ * @cyclic: flag to indicate cyclic transfers
*/
struct owl_dma_txd {
struct virt_dma_desc vd;
@@ -188,6 +189,8 @@ struct owl_dma_pchan {
* @vc: wrappped virtual channel
* @pchan: the physical channel utilized by this channel
* @txd: active transaction on this channel
+ * @cfg: slave configuration for this channel
+ * @drq: physical DMA request ID for this channel
*/
struct owl_dma_vchan {
struct virt_dma_chan vc;
@@ -204,6 +207,7 @@ struct owl_dma_vchan {
* @clk: clock for the DMA controller
* @lock: a lock to use when change DMA controller global register
* @lli_pool: a pool for the LLI descriptors
+ * @irq: interrupt ID for the DMA controller
* @nr_pchans: the number of physical channels
* @pchans: array of data for the physical channels
* @nr_vchans: the number of physical channels
^ permalink raw reply related
* dmaengine: owl: Fix warnings generated during build
From: Andreas Färber @ 2018-10-08 18:26 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: vkoul, dmaengine, liuwei, 96boards, linux-arm-kernel,
linux-kernel, hzhang, bdong, manivannanece23, thomas.liau, pn,
edgar.righi
Am 08.10.18 um 19:16 schrieb Manivannan Sadhasivam:
> Following warnings are generated when compiled with W=1,
>
> drivers/dma/owl-dma.c:170: warning: Function parameter or member 'cyclic'
> not described in 'owl_dma_txd'
> drivers/dma/owl-dma.c:198: warning: Function parameter or member 'cfg' not
> described in 'owl_dma_vchan'
> drivers/dma/owl-dma.c:198: warning: Function parameter or member 'drq' not
> described in 'owl_dma_vchan'
> drivers/dma/owl-dma.c:225: warning: Function parameter or member 'irq' not
> described in 'owl_dma'
>
> Fix this by adding comments for relevant struct members to appear in
> kernel-doc.
>
> Fixes: d64e1b3f5cce ("dmaengine: owl: Add Slave and Cyclic mode support for
> Actions Semi Owl S900 SoC")
If possible, one line please, and it could go between Reported-by and
Signed-off-by below without extra white lines.
Otherwise looks okay,
Reviewed-by: Andreas Färber <afaerber@suse.de>
Thanks,
Andreas
>
> Reported-by: Vinod Koul <vinod.koul@linaro.org>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> drivers/dma/owl-dma.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/dma/owl-dma.c b/drivers/dma/owl-dma.c
> index 1d26db4c9229..90bbcef99ef8 100644
> --- a/drivers/dma/owl-dma.c
> +++ b/drivers/dma/owl-dma.c
> @@ -162,6 +162,7 @@ struct owl_dma_lli {
> * struct owl_dma_txd - Wrapper for struct dma_async_tx_descriptor
> * @vd: virtual DMA descriptor
> * @lli_list: link list of lli nodes
> + * @cyclic: flag to indicate cyclic transfers
> */
> struct owl_dma_txd {
> struct virt_dma_desc vd;
> @@ -188,6 +189,8 @@ struct owl_dma_pchan {
> * @vc: wrappped virtual channel
> * @pchan: the physical channel utilized by this channel
> * @txd: active transaction on this channel
> + * @cfg: slave configuration for this channel
> + * @drq: physical DMA request ID for this channel
> */
> struct owl_dma_vchan {
> struct virt_dma_chan vc;
> @@ -204,6 +207,7 @@ struct owl_dma_vchan {
> * @clk: clock for the DMA controller
> * @lock: a lock to use when change DMA controller global register
> * @lli_pool: a pool for the LLI descriptors
> + * @irq: interrupt ID for the DMA controller
> * @nr_pchans: the number of physical channels
> * @pchans: array of data for the physical channels
> * @nr_vchans: the number of physical channels
>
^ permalink raw reply
* [1/7] dmaengine: stm32-dma: threshold manages with bitfield feature
From: Joel Fernandes @ 2018-10-09 5:47 UTC (permalink / raw)
To: stable
Cc: Pierre Yves MORDRET, Vinod Koul, gregkh, Alexandre Torgue,
Dan Williams, dmaengine, Joel Fernandes (Google),
moderated list:ARM/STM32 ARCHITECTURE, linux-kernel,
Maxime Coquelin
From: Pierre Yves MORDRET <pierre-yves.mordret@st.com>
>From now on, DMA bitfield is to manage DMA FIFO Threshold.
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
drivers/dma/stm32-dma.c | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index 786fc8fcc38e..4099948b6914 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -116,6 +116,10 @@
#define STM32_DMA_MAX_DATA_PARAM 0x03
#define STM32_DMA_MAX_BURST 16
+/* DMA Features */
+#define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0)
+#define STM32_DMA_THRESHOLD_FTR_GET(n) ((n) & STM32_DMA_THRESHOLD_FTR_MASK)
+
enum stm32_dma_width {
STM32_DMA_BYTE,
STM32_DMA_HALF_WORD,
@@ -129,11 +133,18 @@ enum stm32_dma_burst_size {
STM32_DMA_BURST_INCR16,
};
+/**
+ * struct stm32_dma_cfg - STM32 DMA custom configuration
+ * @channel_id: channel ID
+ * @request_line: DMA request
+ * @stream_config: 32bit mask specifying the DMA channel configuration
+ * @features: 32bit mask specifying the DMA Feature list
+ */
struct stm32_dma_cfg {
u32 channel_id;
u32 request_line;
u32 stream_config;
- u32 threshold;
+ u32 features;
};
struct stm32_dma_chan_reg {
@@ -171,6 +182,7 @@ struct stm32_dma_chan {
u32 next_sg;
struct dma_slave_config dma_sconfig;
struct stm32_dma_chan_reg chan_reg;
+ u32 threshold;
};
struct stm32_dma_device {
@@ -976,7 +988,8 @@ static void stm32_dma_set_config(struct stm32_dma_chan *chan,
/* Enable Interrupts */
chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;
- chan->chan_reg.dma_sfcr = cfg->threshold & STM32_DMA_SFCR_FTH_MASK;
+ chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features);
+ chan->chan_reg.dma_sfcr = STM32_DMA_SFCR_FTH(chan->threshold);
}
static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
@@ -996,7 +1009,7 @@ static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
cfg.channel_id = dma_spec->args[0];
cfg.request_line = dma_spec->args[1];
cfg.stream_config = dma_spec->args[2];
- cfg.threshold = dma_spec->args[3];
+ cfg.features = dma_spec->args[3];
if ((cfg.channel_id >= STM32_DMA_MAX_CHANNELS) ||
(cfg.request_line >= STM32_DMA_MAX_REQUEST_ID)) {
^ permalink raw reply related
* [2/7] dmaengine: stm32-dma: fix incomplete configuration in cyclic mode
From: Joel Fernandes @ 2018-10-09 5:47 UTC (permalink / raw)
To: stable
Cc: Pierre Yves MORDRET, Hugues Fruchet, Vinod Koul, gregkh,
Alexandre Torgue, Dan Williams, dmaengine,
Joel Fernandes (Google), moderated list:ARM/STM32 ARCHITECTURE,
linux-kernel, Maxime Coquelin
From: Pierre Yves MORDRET <pierre-yves.mordret@st.com>
When in cyclic mode, the configuration is updated after having started the
DMA hardware (STM32_DMA_SCR_EN) leading to incomplete configuration of
SMxAR registers.
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Hugues Fruchet <hugues.fruchet@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
drivers/dma/stm32-dma.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index 4099948b6914..fae7de54f00a 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -441,6 +441,8 @@ static void stm32_dma_dump_reg(struct stm32_dma_chan *chan)
dev_dbg(chan2dev(chan), "SFCR: 0x%08x\n", sfcr);
}
+static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan);
+
static void stm32_dma_start_transfer(struct stm32_dma_chan *chan)
{
struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
@@ -483,6 +485,9 @@ static void stm32_dma_start_transfer(struct stm32_dma_chan *chan)
if (status)
stm32_dma_irq_clear(chan, status);
+ if (chan->desc->cyclic)
+ stm32_dma_configure_next_sg(chan);
+
stm32_dma_dump_reg(chan);
/* Start DMA */
@@ -576,8 +581,7 @@ static void stm32_dma_issue_pending(struct dma_chan *c)
if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) {
dev_dbg(chan2dev(chan), "vchan %p: issued\n", &chan->vchan);
stm32_dma_start_transfer(chan);
- if (chan->desc->cyclic)
- stm32_dma_configure_next_sg(chan);
+
}
spin_unlock_irqrestore(&chan->vchan.lock, flags);
}
^ permalink raw reply related
* [3/7] dmaengine: stm32-dma: fix typo and reported checkpatch warnings
From: Joel Fernandes @ 2018-10-09 5:47 UTC (permalink / raw)
To: stable
Cc: Pierre Yves MORDRET, Vinod Koul, gregkh, Alexandre Torgue,
Dan Williams, dmaengine, Joel Fernandes (Google),
moderated list:ARM/STM32 ARCHITECTURE, linux-kernel,
Maxime Coquelin
From: Pierre Yves MORDRET <pierre-yves.mordret@st.com>
Fix typo in a comment and solved reported checkpatch warnings.
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
drivers/dma/stm32-dma.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index fae7de54f00a..b64e14a83dec 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -60,7 +60,8 @@
#define STM32_DMA_SCR_PINC BIT(9) /* Peripheral increment mode */
#define STM32_DMA_SCR_CIRC BIT(8) /* Circular mode */
#define STM32_DMA_SCR_PFCTRL BIT(5) /* Peripheral Flow Controller */
-#define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Cplete Int Enable*/
+#define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable
+ */
#define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */
#define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */
#define STM32_DMA_SCR_EN BIT(0) /* Stream Enable */
@@ -918,7 +919,7 @@ static enum dma_status stm32_dma_tx_status(struct dma_chan *c,
u32 residue = 0;
status = dma_cookie_status(c, cookie, state);
- if ((status == DMA_COMPLETE) || (!state))
+ if (status == DMA_COMPLETE || !state)
return status;
spin_lock_irqsave(&chan->vchan.lock, flags);
@@ -982,7 +983,7 @@ static void stm32_dma_desc_free(struct virt_dma_desc *vdesc)
}
static void stm32_dma_set_config(struct stm32_dma_chan *chan,
- struct stm32_dma_cfg *cfg)
+ struct stm32_dma_cfg *cfg)
{
stm32_dma_clear_reg(&chan->chan_reg);
@@ -1015,8 +1016,8 @@ static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
cfg.stream_config = dma_spec->args[2];
cfg.features = dma_spec->args[3];
- if ((cfg.channel_id >= STM32_DMA_MAX_CHANNELS) ||
- (cfg.request_line >= STM32_DMA_MAX_REQUEST_ID)) {
+ if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS ||
+ cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) {
dev_err(dev, "Bad channel and/or request id\n");
return NULL;
}
^ permalink raw reply related
* [4/7] dmaengine: stm32-dma: Improve memory burst management
From: Joel Fernandes @ 2018-10-09 5:47 UTC (permalink / raw)
To: stable
Cc: Pierre Yves MORDRET, M'boumba Cedric Madianga, Vinod Koul,
gregkh, Alexandre Torgue, Dan Williams, dmaengine,
Joel Fernandes (Google), moderated list:ARM/STM32 ARCHITECTURE,
linux-kernel, Maxime Coquelin
From: Pierre Yves MORDRET <pierre-yves.mordret@st.com>
This patch improves memory burst capability using best burst size
according to transferred buffer size from/to memory.
>From now on, memory burst is not necessarily same as with peripheral
burst one and fifo threshold is directly managed by this driver in order
to fit with computed memory burst.
Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
drivers/dma/stm32-dma.c | 204 ++++++++++++++++++++++++++++++++++------
1 file changed, 175 insertions(+), 29 deletions(-)
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index b64e14a83dec..21ad359a5a59 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -5,6 +5,7 @@
*
* Copyright (C) M'boumba Cedric Madianga 2015
* Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
+ * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
*
* License terms: GNU General Public License (GPL), version 2
*/
@@ -115,6 +116,8 @@
#define STM32_DMA_MAX_CHANNELS 0x08
#define STM32_DMA_MAX_REQUEST_ID 0x08
#define STM32_DMA_MAX_DATA_PARAM 0x03
+#define STM32_DMA_FIFO_SIZE 16 /* FIFO is 16 bytes */
+#define STM32_DMA_MIN_BURST 4
#define STM32_DMA_MAX_BURST 16
/* DMA Features */
@@ -184,6 +187,8 @@ struct stm32_dma_chan {
struct dma_slave_config dma_sconfig;
struct stm32_dma_chan_reg chan_reg;
u32 threshold;
+ u32 mem_burst;
+ u32 mem_width;
};
struct stm32_dma_device {
@@ -248,6 +253,85 @@ static int stm32_dma_get_width(struct stm32_dma_chan *chan,
}
}
+static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len,
+ u32 threshold)
+{
+ enum dma_slave_buswidth max_width;
+
+ if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL)
+ max_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ else
+ max_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+
+ while ((buf_len < max_width || buf_len % max_width) &&
+ max_width > DMA_SLAVE_BUSWIDTH_1_BYTE)
+ max_width = max_width >> 1;
+
+ return max_width;
+}
+
+static bool stm32_dma_fifo_threshold_is_allowed(u32 burst, u32 threshold,
+ enum dma_slave_buswidth width)
+{
+ u32 remaining;
+
+ if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) {
+ if (burst != 0) {
+ /*
+ * If number of beats fit in several whole bursts
+ * this configuration is allowed.
+ */
+ remaining = ((STM32_DMA_FIFO_SIZE / width) *
+ (threshold + 1) / 4) % burst;
+
+ if (remaining == 0)
+ return true;
+ } else {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold)
+{
+ switch (threshold) {
+ case STM32_DMA_FIFO_THRESHOLD_FULL:
+ if (buf_len >= STM32_DMA_MAX_BURST)
+ return true;
+ else
+ return false;
+ case STM32_DMA_FIFO_THRESHOLD_HALFFULL:
+ if (buf_len >= STM32_DMA_MAX_BURST / 2)
+ return true;
+ else
+ return false;
+ default:
+ return false;
+ }
+}
+
+static u32 stm32_dma_get_best_burst(u32 buf_len, u32 max_burst, u32 threshold,
+ enum dma_slave_buswidth width)
+{
+ u32 best_burst = max_burst;
+
+ if (best_burst == 1 || !stm32_dma_is_burst_possible(buf_len, threshold))
+ return 0;
+
+ while ((buf_len < best_burst * width && best_burst > 1) ||
+ !stm32_dma_fifo_threshold_is_allowed(best_burst, threshold,
+ width)) {
+ if (best_burst > STM32_DMA_MIN_BURST)
+ best_burst = best_burst >> 1;
+ else
+ best_burst = 0;
+ }
+
+ return best_burst;
+}
+
static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst)
{
switch (maxburst) {
@@ -267,12 +351,12 @@ static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst)
}
static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan,
- u32 src_maxburst, u32 dst_maxburst)
+ u32 src_burst, u32 dst_burst)
{
chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK;
chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;
- if ((!src_maxburst) && (!dst_maxburst)) {
+ if (!src_burst && !dst_burst) {
/* Using direct mode */
chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;
} else {
@@ -589,37 +673,52 @@ static void stm32_dma_issue_pending(struct dma_chan *c)
static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,
enum dma_transfer_direction direction,
- enum dma_slave_buswidth *buswidth)
+ enum dma_slave_buswidth *buswidth,
+ u32 buf_len)
{
enum dma_slave_buswidth src_addr_width, dst_addr_width;
int src_bus_width, dst_bus_width;
int src_burst_size, dst_burst_size;
- u32 src_maxburst, dst_maxburst;
- u32 dma_scr = 0;
+ u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst;
+ u32 dma_scr, threshold;
src_addr_width = chan->dma_sconfig.src_addr_width;
dst_addr_width = chan->dma_sconfig.dst_addr_width;
src_maxburst = chan->dma_sconfig.src_maxburst;
dst_maxburst = chan->dma_sconfig.dst_maxburst;
+ threshold = chan->threshold;
switch (direction) {
case DMA_MEM_TO_DEV:
+ /* Set device data size */
dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
if (dst_bus_width < 0)
return dst_bus_width;
- dst_burst_size = stm32_dma_get_burst(chan, dst_maxburst);
+ /* Set device burst size */
+ dst_best_burst = stm32_dma_get_best_burst(buf_len,
+ dst_maxburst,
+ threshold,
+ dst_addr_width);
+
+ dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
if (dst_burst_size < 0)
return dst_burst_size;
- if (!src_addr_width)
- src_addr_width = dst_addr_width;
-
+ /* Set memory data size */
+ src_addr_width = stm32_dma_get_max_width(buf_len, threshold);
+ chan->mem_width = src_addr_width;
src_bus_width = stm32_dma_get_width(chan, src_addr_width);
if (src_bus_width < 0)
return src_bus_width;
- src_burst_size = stm32_dma_get_burst(chan, src_maxburst);
+ /* Set memory burst size */
+ src_maxburst = STM32_DMA_MAX_BURST;
+ src_best_burst = stm32_dma_get_best_burst(buf_len,
+ src_maxburst,
+ threshold,
+ src_addr_width);
+ src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
if (src_burst_size < 0)
return src_burst_size;
@@ -629,27 +728,46 @@ static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,
STM32_DMA_SCR_PBURST(dst_burst_size) |
STM32_DMA_SCR_MBURST(src_burst_size);
+ /* Set FIFO threshold */
+ chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
+ chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);
+
+ /* Set peripheral address */
chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;
*buswidth = dst_addr_width;
break;
case DMA_DEV_TO_MEM:
+ /* Set device data size */
src_bus_width = stm32_dma_get_width(chan, src_addr_width);
if (src_bus_width < 0)
return src_bus_width;
- src_burst_size = stm32_dma_get_burst(chan, src_maxburst);
+ /* Set device burst size */
+ src_best_burst = stm32_dma_get_best_burst(buf_len,
+ src_maxburst,
+ threshold,
+ src_addr_width);
+ chan->mem_burst = src_best_burst;
+ src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
if (src_burst_size < 0)
return src_burst_size;
- if (!dst_addr_width)
- dst_addr_width = src_addr_width;
-
+ /* Set memory data size */
+ dst_addr_width = stm32_dma_get_max_width(buf_len, threshold);
+ chan->mem_width = dst_addr_width;
dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
if (dst_bus_width < 0)
return dst_bus_width;
- dst_burst_size = stm32_dma_get_burst(chan, dst_maxburst);
+ /* Set memory burst size */
+ dst_maxburst = STM32_DMA_MAX_BURST;
+ dst_best_burst = stm32_dma_get_best_burst(buf_len,
+ dst_maxburst,
+ threshold,
+ dst_addr_width);
+ chan->mem_burst = dst_best_burst;
+ dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
if (dst_burst_size < 0)
return dst_burst_size;
@@ -659,6 +777,11 @@ static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,
STM32_DMA_SCR_PBURST(src_burst_size) |
STM32_DMA_SCR_MBURST(dst_burst_size);
+ /* Set FIFO threshold */
+ chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
+ chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);
+
+ /* Set peripheral address */
chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr;
*buswidth = chan->dma_sconfig.src_addr_width;
break;
@@ -668,8 +791,9 @@ static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,
return -EINVAL;
}
- stm32_dma_set_fifo_config(chan, src_maxburst, dst_maxburst);
+ stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst);
+ /* Set DMA control register */
chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |
STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK |
STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK);
@@ -709,10 +833,6 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg(
if (!desc)
return NULL;
- ret = stm32_dma_set_xfer_param(chan, direction, &buswidth);
- if (ret < 0)
- goto err;
-
/* Set peripheral flow controller */
if (chan->dma_sconfig.device_fc)
chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;
@@ -720,6 +840,11 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg(
chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
for_each_sg(sgl, sg, sg_len, i) {
+ ret = stm32_dma_set_xfer_param(chan, direction, &buswidth,
+ sg_dma_len(sg));
+ if (ret < 0)
+ goto err;
+
desc->sg_req[i].len = sg_dma_len(sg);
nb_data_items = desc->sg_req[i].len / buswidth;
@@ -784,7 +909,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic(
return NULL;
}
- ret = stm32_dma_set_xfer_param(chan, direction, &buswidth);
+ ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len);
if (ret < 0)
return NULL;
@@ -833,9 +958,10 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(
dma_addr_t src, size_t len, unsigned long flags)
{
struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
- u32 num_sgs;
+ enum dma_slave_buswidth max_width;
struct stm32_dma_desc *desc;
size_t xfer_count, offset;
+ u32 num_sgs, best_burst, dma_burst, threshold;
int i;
num_sgs = DIV_ROUND_UP(len, STM32_DMA_MAX_DATA_ITEMS);
@@ -843,25 +969,34 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(
if (!desc)
return NULL;
+ threshold = chan->threshold;
+
for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) {
xfer_count = min_t(size_t, len - offset,
STM32_DMA_MAX_DATA_ITEMS);
- desc->sg_req[i].len = xfer_count;
+ /* Compute best burst size */
+ max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+ best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST,
+ threshold, max_width);
+ dma_burst = stm32_dma_get_burst(chan, best_burst);
stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
desc->sg_req[i].chan_reg.dma_scr =
STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM) |
+ STM32_DMA_SCR_PBURST(dma_burst) |
+ STM32_DMA_SCR_MBURST(dma_burst) |
STM32_DMA_SCR_MINC |
STM32_DMA_SCR_PINC |
STM32_DMA_SCR_TCIE |
STM32_DMA_SCR_TEIE;
- desc->sg_req[i].chan_reg.dma_sfcr = STM32_DMA_SFCR_DMDIS |
- STM32_DMA_SFCR_FTH(STM32_DMA_FIFO_THRESHOLD_FULL) |
- STM32_DMA_SFCR_FEIE;
+ desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
+ desc->sg_req[i].chan_reg.dma_sfcr |=
+ STM32_DMA_SFCR_FTH(threshold);
desc->sg_req[i].chan_reg.dma_spar = src + offset;
desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset;
desc->sg_req[i].chan_reg.dma_sndtr = xfer_count;
+ desc->sg_req[i].len = xfer_count;
}
desc->num_sgs = num_sgs;
@@ -886,6 +1021,7 @@ static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,
struct stm32_dma_desc *desc,
u32 next_sg)
{
+ u32 modulo, burst_size;
u32 residue = 0;
int i;
@@ -893,8 +1029,10 @@ static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,
* In cyclic mode, for the last period, residue = remaining bytes from
* NDTR
*/
- if (chan->desc->cyclic && next_sg == 0)
- return stm32_dma_get_remaining_bytes(chan);
+ if (chan->desc->cyclic && next_sg == 0) {
+ residue = stm32_dma_get_remaining_bytes(chan);
+ goto end;
+ }
/*
* For all other periods in cyclic mode, and in sg mode,
@@ -905,6 +1043,15 @@ static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,
residue += desc->sg_req[i].len;
residue += stm32_dma_get_remaining_bytes(chan);
+end:
+ if (!chan->mem_burst)
+ return residue;
+
+ burst_size = chan->mem_burst * chan->mem_width;
+ modulo = residue % burst_size;
+ if (modulo)
+ residue = residue - modulo + burst_size;
+
return residue;
}
@@ -994,7 +1141,6 @@ static void stm32_dma_set_config(struct stm32_dma_chan *chan,
chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;
chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features);
- chan->chan_reg.dma_sfcr = STM32_DMA_SFCR_FTH(chan->threshold);
}
static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
^ permalink raw reply related
* [5/7] dmaengine: stm32-dma: fix DMA IRQ status handling
From: Joel Fernandes @ 2018-10-09 5:47 UTC (permalink / raw)
To: stable
Cc: Pierre Yves MORDRET, Vinod Koul, gregkh, Alexandre Torgue,
Dan Williams, dmaengine, Joel Fernandes (Google),
moderated list:ARM/STM32 ARCHITECTURE, linux-kernel,
Maxime Coquelin
From: Pierre Yves MORDRET <pierre-yves.mordret@st.com>
Update the way Transfer Complete and Half Transfer Complete status are
acknowledge. Even if HTI is not enabled its status is shown when reading
registers, driver has to clear it gently and not raise an error.
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
drivers/dma/stm32-dma.c | 29 +++++++++++++++++++++++++----
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index 21ad359a5a59..b40486454a2c 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -34,9 +34,14 @@
#define STM32_DMA_LIFCR 0x0008 /* DMA Low Int Flag Clear Reg */
#define STM32_DMA_HIFCR 0x000c /* DMA High Int Flag Clear Reg */
#define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */
+#define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */
#define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */
#define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */
#define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */
+#define STM32_DMA_MASKI (STM32_DMA_TCI \
+ | STM32_DMA_TEI \
+ | STM32_DMA_DMEI \
+ | STM32_DMA_FEI)
/* DMA Stream x Configuration Register */
#define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */
@@ -643,13 +648,29 @@ static irqreturn_t stm32_dma_chan_irq(int irq, void *devid)
status = stm32_dma_irq_status(chan);
scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
- if ((status & STM32_DMA_TCI) && (scr & STM32_DMA_SCR_TCIE)) {
+ if (status & STM32_DMA_TCI) {
stm32_dma_irq_clear(chan, STM32_DMA_TCI);
- stm32_dma_handle_chan_done(chan);
-
- } else {
+ if (scr & STM32_DMA_SCR_TCIE)
+ stm32_dma_handle_chan_done(chan);
+ status &= ~STM32_DMA_TCI;
+ }
+ if (status & STM32_DMA_HTI) {
+ stm32_dma_irq_clear(chan, STM32_DMA_HTI);
+ status &= ~STM32_DMA_HTI;
+ }
+ if (status & STM32_DMA_FEI) {
+ stm32_dma_irq_clear(chan, STM32_DMA_FEI);
+ status &= ~STM32_DMA_FEI;
+ if (!(scr & STM32_DMA_SCR_EN))
+ dev_err(chan2dev(chan), "FIFO Error\n");
+ else
+ dev_dbg(chan2dev(chan), "FIFO over/underrun\n");
+ }
+ if (status) {
stm32_dma_irq_clear(chan, status);
dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
+ if (!(scr & STM32_DMA_SCR_EN))
+ dev_err(chan2dev(chan), "chan disabled by HW\n");
}
spin_unlock(&chan->vchan.lock);
^ permalink raw reply related
* [6/7] dmaengine: stm32-dma: fix max items per transfer
From: Joel Fernandes @ 2018-10-09 5:47 UTC (permalink / raw)
To: stable
Cc: Pierre Yves MORDRET, Vinod Koul, gregkh, Alexandre Torgue,
Dan Williams, dmaengine, Joel Fernandes (Google),
moderated list:ARM/STM32 ARCHITECTURE, linux-kernel,
Maxime Coquelin
From: Pierre Yves MORDRET <pierre-yves.mordret@st.com>
Having 0 in item counter register is valid and stands for a "No or Ended
transfer". Therefore valid transfer starts from @+0 to @+0xFFFE leading to
unaligned scatter gather at boundary. Thus it's safer to round down this
value on its FIFO size (16 Bytes).
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
drivers/dma/stm32-dma.c | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index b40486454a2c..05a2974cd2c0 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -38,10 +38,6 @@
#define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */
#define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */
#define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */
-#define STM32_DMA_MASKI (STM32_DMA_TCI \
- | STM32_DMA_TEI \
- | STM32_DMA_DMEI \
- | STM32_DMA_FEI)
/* DMA Stream x Configuration Register */
#define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */
@@ -118,6 +114,13 @@
#define STM32_DMA_FIFO_THRESHOLD_FULL 0x03
#define STM32_DMA_MAX_DATA_ITEMS 0xffff
+/*
+ * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter
+ * gather at boundary. Thus it's safer to round down this value on FIFO
+ * size (16 Bytes)
+ */
+#define STM32_DMA_ALIGNED_MAX_DATA_ITEMS \
+ ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16)
#define STM32_DMA_MAX_CHANNELS 0x08
#define STM32_DMA_MAX_REQUEST_ID 0x08
#define STM32_DMA_MAX_DATA_PARAM 0x03
@@ -869,7 +872,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg(
desc->sg_req[i].len = sg_dma_len(sg);
nb_data_items = desc->sg_req[i].len / buswidth;
- if (nb_data_items > STM32_DMA_MAX_DATA_ITEMS) {
+ if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
dev_err(chan2dev(chan), "nb items not supported\n");
goto err;
}
@@ -935,7 +938,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic(
return NULL;
nb_data_items = period_len / buswidth;
- if (nb_data_items > STM32_DMA_MAX_DATA_ITEMS) {
+ if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
dev_err(chan2dev(chan), "number of items not supported\n");
return NULL;
}
@@ -985,7 +988,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(
u32 num_sgs, best_burst, dma_burst, threshold;
int i;
- num_sgs = DIV_ROUND_UP(len, STM32_DMA_MAX_DATA_ITEMS);
+ num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
desc = stm32_dma_alloc_desc(num_sgs);
if (!desc)
return NULL;
@@ -994,7 +997,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(
for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) {
xfer_count = min_t(size_t, len - offset,
- STM32_DMA_MAX_DATA_ITEMS);
+ STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
/* Compute best burst size */
max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^ permalink raw reply related
* [7/7] dmaengine: stm32-dma: properly mask irq bits
From: Joel Fernandes @ 2018-10-09 5:47 UTC (permalink / raw)
To: stable
Cc: Pierre Yves MORDRET, Antonio Borneo, Vinod Koul, gregkh,
Alexandre Torgue, Dan Williams, dmaengine,
Joel Fernandes (Google), moderated list:ARM/STM32 ARCHITECTURE,
linux-kernel, Maxime Coquelin
From: Pierre Yves MORDRET <pierre-yves.mordret@st.com>
A single register of the controller holds the information for four dma
channels.
The functions stm32_dma_irq_status() don't mask the relevant bits after
the shift, thus adjacent channel's status is also reported in the returned
value.
Fixed by masking the value before returning it.
Similarly, the function stm32_dma_irq_clear() don't mask the input value
before shifting it, thus an incorrect input value could disable the
interrupts of adjacent channels.
Fixed by masking the input value before using it.
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
drivers/dma/stm32-dma.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index 05a2974cd2c0..8c5807362a25 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -38,6 +38,10 @@
#define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */
#define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */
#define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */
+#define STM32_DMA_MASKI (STM32_DMA_TCI \
+ | STM32_DMA_TEI \
+ | STM32_DMA_DMEI \
+ | STM32_DMA_FEI)
/* DMA Stream x Configuration Register */
#define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */
@@ -405,7 +409,7 @@ static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan)
flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
- return flags;
+ return flags & STM32_DMA_MASKI;
}
static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)
@@ -420,6 +424,7 @@ static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)
* If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
* If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
*/
+ flags &= STM32_DMA_MASKI;
dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
if (chan->id & 4)
^ permalink raw reply related
* [v3,1/7] dt-bindings: stm32-dma: Add DMA/MDMA chaining support bindings
From: Pierre Yves MORDRET @ 2018-10-09 7:18 UTC (permalink / raw)
To: Vinod
Cc: Rob Herring, Mark Rutland, Alexandre Torgue, Maxime Coquelin,
Dan Williams, devicetree, dmaengine, linux-arm-kernel,
linux-kernel
Hi Vinod
On 10/07/2018 04:57 PM, Vinod wrote:
> On 28-09-18, 15:01, Pierre-Yves MORDRET wrote:
>> From: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
>>
>> This patch adds dma bindings to support DMA/MDMA chaining transfer.
>> 1 bit is to manage both DMA FIFO Threshold
>> 1 bit is to manage DMA/MDMA Chaining features.
>> 2 bits are used to specify SDRAM size to use for DMA/MDMA chaining.
>
> Please do mention which specific bits?
This is written below into DMA Client section. But I can put some words here.
>
>> The size in bytes of a certain order is given by the formula:
>> (2 ^ order) * PAGE_SIZE.
>> The order is given by those 2 bits.
>> For cyclic, whether chaining is chosen, any value above 1 can be set :
>> SRAM buffer size will rely on period size and not on this DT value.
>>
>> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
>> ---
>> Version history:
>> v3:
>> v2:
>> * rework content
>> v1:
>> * Initial
>> ---
>> ---
>> .../devicetree/bindings/dma/stm32-dma.txt | 27 +++++++++++++++++++++-
>> 1 file changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/dma/stm32-dma.txt b/Documentation/devicetree/bindings/dma/stm32-dma.txt
>> index c5f5190..2bac8c7 100644
>> --- a/Documentation/devicetree/bindings/dma/stm32-dma.txt
>> +++ b/Documentation/devicetree/bindings/dma/stm32-dma.txt
>> @@ -17,6 +17,12 @@ Optional properties:
>> - resets: Reference to a reset controller asserting the DMA controller
>> - st,mem2mem: boolean; if defined, it indicates that the controller supports
>> memory-to-memory transfer
>> +- dmas: A list of eight dma specifiers, one for each entry in dma-names.
>> + Refer to stm32-mdma.txt for more details.
>> +- dma-names: should contain "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6" and
>> + "ch7" and represents each STM32 DMA channel connected to a STM32 MDMA one.
>> +- memory-region : phandle to a node describing memory to be used for
>> + M2M intermediate transfer between DMA and MDMA.
>>
>> Example:
>>
>> @@ -36,6 +42,16 @@ Example:
>> st,mem2mem;
>> resets = <&rcc 150>;
>> dma-requests = <8>;
>> + dmas = <&mdma1 8 0x10 0x1200000a 0x40026408 0x00000020 1>,
>> + <&mdma1 9 0x10 0x1200000a 0x40026408 0x00000800 1>,
>> + <&mdma1 10 0x10 0x1200000a 0x40026408 0x00200000 1>,
>> + <&mdma1 11 0x10 0x1200000a 0x40026408 0x08000000 1>,
>> + <&mdma1 12 0x10 0x1200000a 0x4002640C 0x00000020 1>,
>> + <&mdma1 13 0x10 0x1200000a 0x4002640C 0x00000800 1>,
>> + <&mdma1 14 0x10 0x1200000a 0x4002640C 0x00200000 1>,
>> + <&mdma1 15 0x10 0x1200000a 0x4002640C 0x08000000 1>;
>> + dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
>> + memory-region = <&sram_dmapool>;
>> };
>>
>> * DMA client
>> @@ -68,7 +84,16 @@ channel: a phandle to the DMA controller plus the following four integer cells:
>> 0x1: 1/2 full FIFO
>> 0x2: 3/4 full FIFO
>> 0x3: full FIFO
>> -
>> + -bit 2: Intermediate M2M transfer from/to DDR to/from SRAM throughout MDMA
>> + 0: MDMA not used to generate an intermediate M2M transfer
>> + 1: MDMA used to generate an intermediate M2M transfer.
>> + -bit 3-4: indicated SRAM Buffer size in (2^order)*PAGE_SIZE.
>> + PAGE_SIZE is given by Linux at 4KiB: include/asm-generic/page.h.
>> + Order is given by those 2 bits starting at 0.
>> + Valid only whether Intermediate M2M transfer is set.
>
> why do we need this as a property?
In some UC, we need more than 4KiB in case of chaining for better performances.
Chaining has to be enabled by client if performance is at sacks.
>
>> + For cyclic, whether Intermediate M2M transfer is chosen, any value can
>> + be set: SRAM buffer size will rely on period size and not on this DT
>> + value.
>>
>> Example:
>>
>> --
>> 2.7.4
>
^ permalink raw reply
* [v2] dmaengine: fsl-edma: remove dma_slave_config direction usage
From: Krzysztof Kozlowski @ 2018-10-09 7:22 UTC (permalink / raw)
To: vkoul; +Cc: dmaengine, angelo
On Sun, 7 Oct 2018 at 16:15, Vinod Koul <vkoul@kernel.org> wrote:
>
> dma_slave_config direction was marked as deprecated quite some
> time back, remove the usage from this driver so that the field
> can be removed
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> CC: Angelo Dureghello <angelo@sysam.it>
> CC: Krzysztof Kozlowski <krzk@kernel.org>
>
> Angelo, Krzysztof,
>
> I have rebased this against the latest fsl-edma changes, can you
> please verify this and let me know, thnx
I applied it on top of linux next (20181008) and compilation fails:
../drivers/i2c/busses/i2c-imx.c: In function ‘i2c_imx_dma_request’:
../drivers/i2c/busses/i2c-imx.c:298:13: error: ‘struct
dma_slave_config’ has no member named ‘direction’
dma_sconfig.direction = DMA_MEM_TO_DEV;
^
../drivers/i2c/busses/i2c-imx.c:315:13: error: ‘struct
dma_slave_config’ has no member named ‘direction’
dma_sconfig.direction = DMA_DEV_TO_MEM;
^
../drivers/mmc/host/mmci.c: In function ‘__mmci_dma_prep_data’:
../drivers/mmc/host/mmci.c:578:7: error: ‘struct dma_slave_config’ has
no member named ‘direction’
conf.direction = DMA_DEV_TO_MEM;
^
../drivers/mmc/host/mmci.c:581:7: error: ‘struct dma_slave_config’ has
no member named ‘direction’
conf.direction = DMA_MEM_TO_DEV;
^
../drivers/mmc/host/mmci.c:604:14: error: ‘struct dma_slave_config’
has no member named ‘direction’
conf.direction, flags);
^
Am I missing some dependencies?
Best regards,
Krzysztof
^ permalink raw reply
* [v3,2/7] dt-bindings: stm32-dmamux: Add one cell to support DMA/MDMA chain
From: Pierre Yves MORDRET @ 2018-10-09 7:22 UTC (permalink / raw)
To: Vinod
Cc: Rob Herring, Mark Rutland, Alexandre Torgue, Maxime Coquelin,
Dan Williams, devicetree, dmaengine, linux-arm-kernel,
linux-kernel
On 10/07/2018 04:58 PM, Vinod wrote:
> On 28-09-18, 15:01, Pierre-Yves MORDRET wrote:
>> From: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
>>
>> Add one cell to support DMA/MDMA chaining.
>>
>> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
>> ---
>> Version history:
>> v3:
>> v2:
>> * rework content
>> v1:
>> * Initial
>> ---
>> ---
>> Documentation/devicetree/bindings/dma/stm32-dmamux.txt | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt
>> index 1b893b2..5e92b59 100644
>> --- a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt
>> +++ b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt
>> @@ -4,9 +4,9 @@ Required properties:
>> - compatible: "st,stm32h7-dmamux"
>> - reg: Memory map for accessing module
>> - #dma-cells: Should be set to <3>.
>> - First parameter is request line number.
>> - Second is DMA channel configuration
>> - Third is Fifo threshold
>> +- First parameter is request line number.
>> +- Second is DMA channel configuration
>> +- Third is a 32bit bitfield
>
> please separate out formatting changes and actual change proposed..
Yes. sorry. my bad.
>
>> For more details about the three cells, please see
>> stm32-dma.txt documentation binding file
>> - dma-masters: Phandle pointing to the DMA controllers.
>> --
>> 2.7.4
>
^ permalink raw reply
* [v2] dmaengine: fsl-edma: remove dma_slave_config direction usage
From: Vinod Koul @ 2018-10-09 7:30 UTC (permalink / raw)
To: Krzysztof Kozlowski; +Cc: dmaengine, angelo
On 09-10-18, 09:22, Krzysztof Kozlowski wrote:
> On Sun, 7 Oct 2018 at 16:15, Vinod Koul <vkoul@kernel.org> wrote:
> >
> > dma_slave_config direction was marked as deprecated quite some
> > time back, remove the usage from this driver so that the field
> > can be removed
> >
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > CC: Angelo Dureghello <angelo@sysam.it>
> > CC: Krzysztof Kozlowski <krzk@kernel.org>
> >
> > Angelo, Krzysztof,
> >
> > I have rebased this against the latest fsl-edma changes, can you
> > please verify this and let me know, thnx
>
> I applied it on top of linux next (20181008) and compilation fails:
>
> ../drivers/i2c/busses/i2c-imx.c: In function ‘i2c_imx_dma_request’:
> ../drivers/i2c/busses/i2c-imx.c:298:13: error: ‘struct
> dma_slave_config’ has no member named ‘direction’
> dma_sconfig.direction = DMA_MEM_TO_DEV;
> ^
> ../drivers/i2c/busses/i2c-imx.c:315:13: error: ‘struct
> dma_slave_config’ has no member named ‘direction’
> dma_sconfig.direction = DMA_DEV_TO_MEM;
> ^
>
> ../drivers/mmc/host/mmci.c: In function ‘__mmci_dma_prep_data’:
> ../drivers/mmc/host/mmci.c:578:7: error: ‘struct dma_slave_config’ has
> no member named ‘direction’
> conf.direction = DMA_DEV_TO_MEM;
> ^
> ../drivers/mmc/host/mmci.c:581:7: error: ‘struct dma_slave_config’ has
> no member named ‘direction’
> conf.direction = DMA_MEM_TO_DEV;
> ^
> ../drivers/mmc/host/mmci.c:604:14: error: ‘struct dma_slave_config’
> has no member named ‘direction’
> conf.direction, flags);
> ^
>
> Am I missing some dependencies?
Nope, the dmaengine.h change I used to verify removing off all instances
has crept up in this, sorry for that.
Can you remove the deletion and try again, I will post v3 as well
^ permalink raw reply
* [v3] dmaengine: fsl-edma: remove dma_slave_config direction usage
From: Vinod Koul @ 2018-10-09 7:31 UTC (permalink / raw)
To: dmaengine; +Cc: Vinod Koul, Angelo Dureghello, Krzysztof Kozlowski
dma_slave_config direction was marked as deprecated quite some
time back, remove the usage from this driver so that the field
can be removed
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
CC: Angelo Dureghello <angelo@sysam.it>
CC: Krzysztof Kozlowski <krzk@kernel.org>
drivers/dma/fsl-edma-common.c | 74 +++++++++++++++++++++++++------------------
drivers/dma/fsl-edma-common.h | 12 ++-----
2 files changed, 46 insertions(+), 40 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 8ba80f4b6f55..8876c4c1bb2c 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -178,19 +178,7 @@ int fsl_edma_slave_config(struct dma_chan *chan,
{
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
- fsl_chan->fsc.dir = cfg->direction;
- if (cfg->direction == DMA_DEV_TO_MEM) {
- fsl_chan->fsc.dev_addr = cfg->src_addr;
- fsl_chan->fsc.addr_width = cfg->src_addr_width;
- fsl_chan->fsc.burst = cfg->src_maxburst;
- fsl_chan->fsc.attr = fsl_edma_get_tcd_attr(cfg->src_addr_width);
- } else if (cfg->direction == DMA_MEM_TO_DEV) {
- fsl_chan->fsc.dev_addr = cfg->dst_addr;
- fsl_chan->fsc.addr_width = cfg->dst_addr_width;
- fsl_chan->fsc.burst = cfg->dst_maxburst;
- fsl_chan->fsc.attr = fsl_edma_get_tcd_attr(cfg->dst_addr_width);
- } else
- return -EINVAL;
+ memcpy(&fsl_chan->cfg, cfg, sizeof(*cfg));
return 0;
}
@@ -202,7 +190,7 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
struct fsl_edma_desc *edesc = fsl_chan->edesc;
struct edma_regs *regs = &fsl_chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- enum dma_transfer_direction dir = fsl_chan->fsc.dir;
+ enum dma_transfer_direction dir = edesc->dirn;
dma_addr_t cur_addr, dma_addr;
size_t len, size;
int i;
@@ -387,7 +375,7 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
u32 src_addr, dst_addr, last_sg, nbytes;
u16 soff, doff, iter;
- if (!is_slave_direction(fsl_chan->fsc.dir))
+ if (!is_slave_direction(direction))
return NULL;
sg_len = buf_len / period_len;
@@ -395,9 +383,21 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
if (!fsl_desc)
return NULL;
fsl_desc->iscyclic = true;
+ fsl_desc->dirn = direction;
dma_buf_next = dma_addr;
- nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst;
+ if (direction == DMA_MEM_TO_DEV) {
+ fsl_chan->attr =
+ fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width);
+ nbytes = fsl_chan->cfg.dst_addr_width *
+ fsl_chan->cfg.dst_maxburst;
+ } else {
+ fsl_chan->attr =
+ fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width);
+ nbytes = fsl_chan->cfg.src_addr_width *
+ fsl_chan->cfg.src_maxburst;
+ }
+
iter = period_len / nbytes;
for (i = 0; i < sg_len; i++) {
@@ -407,20 +407,20 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
/* get next sg's physical address */
last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
- if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) {
+ if (direction == DMA_MEM_TO_DEV) {
src_addr = dma_buf_next;
- dst_addr = fsl_chan->fsc.dev_addr;
- soff = fsl_chan->fsc.addr_width;
+ dst_addr = fsl_chan->cfg.dst_addr;
+ soff = fsl_chan->cfg.dst_addr_width;
doff = 0;
} else {
- src_addr = fsl_chan->fsc.dev_addr;
+ src_addr = fsl_chan->cfg.src_addr;
dst_addr = dma_buf_next;
soff = 0;
- doff = fsl_chan->fsc.addr_width;
+ doff = fsl_chan->cfg.src_addr_width;
}
fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr,
- fsl_chan->fsc.attr, soff, nbytes, 0, iter,
+ fsl_chan->attr, soff, nbytes, 0, iter,
iter, doff, last_sg, true, false, true);
dma_buf_next += period_len;
}
@@ -441,42 +441,54 @@ struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
u16 soff, doff, iter;
int i;
- if (!is_slave_direction(fsl_chan->fsc.dir))
+ if (!is_slave_direction(direction))
return NULL;
fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
if (!fsl_desc)
return NULL;
fsl_desc->iscyclic = false;
+ fsl_desc->dirn = direction;
+
+ if (direction == DMA_MEM_TO_DEV) {
+ fsl_chan->attr =
+ fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width);
+ nbytes = fsl_chan->cfg.dst_addr_width *
+ fsl_chan->cfg.dst_maxburst;
+ } else {
+ fsl_chan->attr =
+ fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width);
+ nbytes = fsl_chan->cfg.src_addr_width *
+ fsl_chan->cfg.src_maxburst;
+ }
- nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst;
for_each_sg(sgl, sg, sg_len, i) {
/* get next sg's physical address */
last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
- if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) {
+ if (direction == DMA_MEM_TO_DEV) {
src_addr = sg_dma_address(sg);
- dst_addr = fsl_chan->fsc.dev_addr;
- soff = fsl_chan->fsc.addr_width;
+ dst_addr = fsl_chan->cfg.dst_addr;
+ soff = fsl_chan->cfg.dst_addr_width;
doff = 0;
} else {
- src_addr = fsl_chan->fsc.dev_addr;
+ src_addr = fsl_chan->cfg.src_addr;
dst_addr = sg_dma_address(sg);
soff = 0;
- doff = fsl_chan->fsc.addr_width;
+ doff = fsl_chan->cfg.src_addr_width;
}
iter = sg_dma_len(sg) / nbytes;
if (i < sg_len - 1) {
last_sg = fsl_desc->tcd[(i + 1)].ptcd;
fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
- dst_addr, fsl_chan->fsc.attr, soff,
+ dst_addr, fsl_chan->attr, soff,
nbytes, 0, iter, iter, doff, last_sg,
false, false, true);
} else {
last_sg = 0;
fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
- dst_addr, fsl_chan->fsc.attr, soff,
+ dst_addr, fsl_chan->attr, soff,
nbytes, 0, iter, iter, doff, last_sg,
true, true, false);
}
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index a6f5b99ee95f..8917e8865959 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -109,14 +109,6 @@ struct fsl_edma_sw_tcd {
struct fsl_edma_hw_tcd *vtcd;
};
-struct fsl_edma_slave_config {
- enum dma_transfer_direction dir;
- enum dma_slave_buswidth addr_width;
- u32 dev_addr;
- u32 burst;
- u32 attr;
-};
-
struct fsl_edma_chan {
struct virt_dma_chan vchan;
enum dma_status status;
@@ -125,7 +117,8 @@ struct fsl_edma_chan {
u32 slave_id;
struct fsl_edma_engine *edma;
struct fsl_edma_desc *edesc;
- struct fsl_edma_slave_config fsc;
+ struct dma_slave_config cfg;
+ u32 attr;
struct dma_pool *tcd_pool;
};
@@ -133,6 +126,7 @@ struct fsl_edma_desc {
struct virt_dma_desc vdesc;
struct fsl_edma_chan *echan;
bool iscyclic;
+ enum dma_transfer_direction dirn;
unsigned int n_tcds;
struct fsl_edma_sw_tcd tcd[];
};
^ permalink raw reply related
* [v3] dmaengine: fsl-edma: remove dma_slave_config direction usage
From: Krzysztof Kozlowski @ 2018-10-09 7:48 UTC (permalink / raw)
To: vkoul; +Cc: dmaengine, angelo
On Tue, 9 Oct 2018 at 09:31, Vinod Koul <vkoul@kernel.org> wrote:
>
> dma_slave_config direction was marked as deprecated quite some
> time back, remove the usage from this driver so that the field
> can be removed
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> CC: Angelo Dureghello <angelo@sysam.it>
> CC: Krzysztof Kozlowski <krzk@kernel.org>
>
> drivers/dma/fsl-edma-common.c | 74 +++++++++++++++++++++++++------------------
> drivers/dma/fsl-edma-common.h | 12 ++-----
> 2 files changed, 46 insertions(+), 40 deletions(-)
Seems to work fine on Freescale Colibri VF50:
Tested-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply
* [v2] dmaengine: fsl-edma: remove dma_slave_config direction usage
From: Angelo Dureghello @ 2018-10-09 8:00 UTC (permalink / raw)
To: Vinod; +Cc: Krzysztof Kozlowski, dmaengine
Hi Vinod,
On Tue, Oct 09, 2018 at 01:00:01PM +0530, Vinod wrote:
> On 09-10-18, 09:22, Krzysztof Kozlowski wrote:
> > On Sun, 7 Oct 2018 at 16:15, Vinod Koul <vkoul@kernel.org> wrote:
> > >
> > > dma_slave_config direction was marked as deprecated quite some
> > > time back, remove the usage from this driver so that the field
> > > can be removed
> > >
> > > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > > ---
> > > CC: Angelo Dureghello <angelo@sysam.it>
> > > CC: Krzysztof Kozlowski <krzk@kernel.org>
> > >
> > > Angelo, Krzysztof,
> > >
> > > I have rebased this against the latest fsl-edma changes, can you
> > > please verify this and let me know, thnx
> >
> > I applied it on top of linux next (20181008) and compilation fails:
> >
> > ../drivers/i2c/busses/i2c-imx.c: In function ‘i2c_imx_dma_request’:
> > ../drivers/i2c/busses/i2c-imx.c:298:13: error: ‘struct
> > dma_slave_config’ has no member named ‘direction’
> > dma_sconfig.direction = DMA_MEM_TO_DEV;
> > ^
> > ../drivers/i2c/busses/i2c-imx.c:315:13: error: ‘struct
> > dma_slave_config’ has no member named ‘direction’
> > dma_sconfig.direction = DMA_DEV_TO_MEM;
> > ^
> >
> > ../drivers/mmc/host/mmci.c: In function ‘__mmci_dma_prep_data’:
> > ../drivers/mmc/host/mmci.c:578:7: error: ‘struct dma_slave_config’ has
> > no member named ‘direction’
> > conf.direction = DMA_DEV_TO_MEM;
> > ^
> > ../drivers/mmc/host/mmci.c:581:7: error: ‘struct dma_slave_config’ has
> > no member named ‘direction’
> > conf.direction = DMA_MEM_TO_DEV;
> > ^
> > ../drivers/mmc/host/mmci.c:604:14: error: ‘struct dma_slave_config’
> > has no member named ‘direction’
> > conf.direction, flags);
> > ^
> >
> > Am I missing some dependencies?
>
> Nope, the dmaengine.h change I used to verify removing off all instances
> has crept up in this, sorry for that.
>
> Can you remove the deletion and try again, I will post v3 as well
>
Thanks for the patch, looks like i left this out from my previous set.
I re-added direction to struct dma_slave_config and tested the patch on both
stmark2 (ColdFire mcf5441x) and Colibri VF50 with Krzysztof Kozlowski
proceq_vf_bck_defconfig + vf500-colibri-eval-v3.dtb.
At least for ColdFire DSPI + DMA, and console + DMA on Colibri, all seems
to work properly.
Tested-by: Angelo Dureghello <angelo@sysam.it>
> --
> ~Vinod
Regards,
Angelo
^ permalink raw reply
* [v3] dmaengine: fsl-edma: remove dma_slave_config direction usage
From: Angelo Dureghello @ 2018-10-09 8:02 UTC (permalink / raw)
To: Krzysztof Kozlowski; +Cc: vkoul, dmaengine
On Tue, Oct 09, 2018 at 09:48:05AM +0200, Krzysztof Kozlowski wrote:
> On Tue, 9 Oct 2018 at 09:31, Vinod Koul <vkoul@kernel.org> wrote:
> >
> > dma_slave_config direction was marked as deprecated quite some
> > time back, remove the usage from this driver so that the field
> > can be removed
> >
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > CC: Angelo Dureghello <angelo@sysam.it>
> > CC: Krzysztof Kozlowski <krzk@kernel.org>
> >
> > drivers/dma/fsl-edma-common.c | 74 +++++++++++++++++++++++++------------------
> > drivers/dma/fsl-edma-common.h | 12 ++-----
> > 2 files changed, 46 insertions(+), 40 deletions(-)
>
> Seems to work fine on Freescale Colibri VF50:
> Tested-by: Krzysztof Kozlowski <krzk@kernel.org>
>
> Best regards,
> Krzysztof
As already replied to v2,
Tested-by: Angelo Dureghello <angelo@sysam.it>
Regards,
Angelo Dureghello
^ permalink raw reply
* [v3,3/7] dt-bindings: stm32-mdma: Add DMA/MDMA chaining support bindings
From: Pierre Yves MORDRET @ 2018-10-09 8:17 UTC (permalink / raw)
To: Vinod
Cc: Rob Herring, Mark Rutland, Alexandre Torgue, Maxime Coquelin,
Dan Williams, devicetree, dmaengine, linux-arm-kernel,
linux-kernel
On 10/07/2018 04:59 PM, Vinod wrote:
> On 28-09-18, 15:01, Pierre-Yves MORDRET wrote:
>> From: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
>>
>> This patch adds the description of the 2 properties needed to support M2M
>> transfer triggered by STM32 DMA when his transfer is complete.
>>
>> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
>> ---
>> Version history:
>> v3:
>> v2:
>> * rework content
>> v1:
>> * Initial
>> ---
>> ---
>> Documentation/devicetree/bindings/dma/stm32-mdma.txt | 12 ++++++++----
>> 1 file changed, 8 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/dma/stm32-mdma.txt b/Documentation/devicetree/bindings/dma/stm32-mdma.txt
>> index d18772d..27c2812 100644
>> --- a/Documentation/devicetree/bindings/dma/stm32-mdma.txt
>> +++ b/Documentation/devicetree/bindings/dma/stm32-mdma.txt
>> @@ -10,7 +10,7 @@ Required properties:
>> - interrupts: Should contain the MDMA interrupt.
>> - clocks: Should contain the input clock of the DMA instance.
>> - resets: Reference to a reset controller asserting the DMA controller.
>> -- #dma-cells : Must be <5>. See DMA client paragraph for more details.
>> +- #dma-cells : Must be <6>. See DMA client paragraph for more details.
>
> can you update the example for 6 cells?
of course.
>
> Also what happens to dts using 5 cells..
They are not managed, but it should. I will update this flaw. Thanks for
pointing this out.
>
>>
>> Optional properties:
>> - dma-channels: Number of DMA channels supported by the controller.
>> @@ -26,7 +26,7 @@ Example:
>> interrupts = <122>;
>> clocks = <&timer_clk>;
>> resets = <&rcc 992>;
>> - #dma-cells = <5>;
>> + #dma-cells = <6>;
>> dma-channels = <16>;
>> dma-requests = <32>;
>> st,ahb-addr-masks = <0x20000000>, <0x00000000>;
>> @@ -35,8 +35,8 @@ Example:
>> * DMA client
>>
>> DMA clients connected to the STM32 MDMA controller must use the format
>> -described in the dma.txt file, using a five-cell specifier for each channel:
>> -a phandle to the MDMA controller plus the following five integer cells:
>> +described in the dma.txt file, using a six-cell specifier for each channel:
>> +a phandle to the MDMA controller plus the following six integer cells:
>>
>> 1. The request line number
>> 2. The priority level
>> @@ -76,6 +76,10 @@ a phandle to the MDMA controller plus the following five integer cells:
>> if no HW ack signal is used by the MDMA client
>> 5. A 32bit mask specifying the value to be written to acknowledge the request
>> if no HW ack signal is used by the MDMA client
>> +6. A bitfield value specifying if the MDMA client wants to generate M2M
>> + transfer with HW trigger (1) or not (0). This bitfield should be only
>> + enabled for M2M transfer triggered by STM32 DMA client. The memory devices
>> + involved in this kind of transfer are SRAM and DDR.
>>
>> Example:
>>
>> --
>> 2.7.4
>
^ permalink raw reply
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