* [v2,1/3] dmaengine: at_xdmac: remove BUG_ON macro in tasklet
From: Nicolas Ferre @ 2019-04-03 10:09 UTC (permalink / raw)
To: dmaengine, Vinod Koul
Cc: Ludovic Desroches, linux-arm-kernel, Alexandre Belloni,
linux-kernel, Nicolas Ferre
Even if this case shouldn't happen when controller is properly programmed,
it's still better to avoid dumping a kernel Oops for this.
As the sequence may happen only for debugging purposes, log the error and
just finish the tasklet call.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
---
v2: added Ludovic's tag
drivers/dma/at_xdmac.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index fe69dccfa0c0..37a269420435 100644
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -1606,7 +1606,11 @@ static void at_xdmac_tasklet(unsigned long data)
struct at_xdmac_desc,
xfer_node);
dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
- BUG_ON(!desc->active_xfer);
+ if (!desc->active_xfer) {
+ dev_err(chan2dev(&atchan->chan), "Xfer not active: exiting");
+ spin_unlock_bh(&atchan->lock);
+ return;
+ }
txd = &desc->tx_dma_desc;
^ permalink raw reply related
* [2/3] dmaengine: at_xdmac: enhance channel errors handling in tasklet
From: Nicolas Ferre @ 2019-04-03 10:05 UTC (permalink / raw)
To: vkoul
Cc: Ludovic.Desroches, linux-arm-kernel, dmaengine, alexandre.belloni,
linux-kernel
Vinod,
Thanks for your review, I'm preparing v2.
On 11/02/2019 at 12:58, Vinod Koul wrote:
> On 05-02-19, 12:03, Nicolas Ferre wrote:
>> Complement the identification of errors with stoping the channel and
>> dumping the descriptor that led to the error case.
>>
>> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
>> ---
>> drivers/dma/at_xdmac.c | 43 ++++++++++++++++++++++++++++++++++++------
>> 1 file changed, 37 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
>> index 37a269420435..ec7a29d8e448 100644
>> --- a/drivers/dma/at_xdmac.c
>> +++ b/drivers/dma/at_xdmac.c
>> @@ -1575,6 +1575,41 @@ static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan)
>> dmaengine_desc_get_callback_invoke(txd, NULL);
>> }
>>
>> +static void at_xdmac_handle_error(struct at_xdmac_chan *atchan)
>> +{
>> + struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
>> + struct at_xdmac_desc *bad_desc;
>> +
>> + /*
>> + * The descriptor currently at the head of the active list is
>> + * broked. Since we don't have any way to report errors, we'll
>
> You meant borked or broken...
Broken
>
>> + * just have to scream loudly and try to carry on.
>
> should we carry on or abort..?
Changed in:
* just have to scream loudly and try to continue with other
* descriptors queued (if any).
>> + */
>> + if (atchan->irq_status & AT_XDMAC_CIS_RBEIS)
>> + dev_err(chan2dev(&atchan->chan), "read bus error!!!");
>> + if (atchan->irq_status & AT_XDMAC_CIS_WBEIS)
>> + dev_err(chan2dev(&atchan->chan), "write bus error!!!");
>> + if (atchan->irq_status & AT_XDMAC_CIS_ROIS)
>> + dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
>> +
>> + spin_lock_bh(&atchan->lock);
>> + /* Channel must be disabled first as it's not done automatically */
>> + at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
>> + while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
>> + cpu_relax();
>> + bad_desc = list_first_entry(&atchan->xfers_list,
>> + struct at_xdmac_desc,
>> + xfer_node);
>> + spin_unlock_bh(&atchan->lock);
>> + /* Print bad descriptor's details if needed */
>
> Well this is not great to look and read at, please do consider adding
> empty line before comments or logical blocks..
True, indeed.
>> + dev_dbg(chan2dev(&atchan->chan),
>> + "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
>> + __func__, &bad_desc->lld.mbr_sa, &bad_desc->lld.mbr_da,
>> + bad_desc->lld.mbr_ubc);
>
> not dev_err?
Well, we have the dev_err at the beginning of the function, I think it's
enough: this is really debugging information that needs to be activated
to track the DMA configuration bug: it's not meant for production.
>> +
>> + /* Then continue with usual descriptor management */
>> +}
>> +
>> static void at_xdmac_tasklet(unsigned long data)
>> {
>> struct at_xdmac_chan *atchan = (struct at_xdmac_chan *)data;
>> @@ -1594,12 +1629,8 @@ static void at_xdmac_tasklet(unsigned long data)
>> || (atchan->irq_status & error_mask)) {
>> struct dma_async_tx_descriptor *txd;
>>
>> - if (atchan->irq_status & AT_XDMAC_CIS_RBEIS)
>> - dev_err(chan2dev(&atchan->chan), "read bus error!!!");
>> - if (atchan->irq_status & AT_XDMAC_CIS_WBEIS)
>> - dev_err(chan2dev(&atchan->chan), "write bus error!!!");
>> - if (atchan->irq_status & AT_XDMAC_CIS_ROIS)
>> - dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
>> + if (atchan->irq_status & error_mask)
>> + at_xdmac_handle_error(atchan);
>>
>> spin_lock(&atchan->lock);
>> desc = list_first_entry(&atchan->xfers_list,
>> --
>> 2.17.1
>
--
Nicolas Ferre
^ permalink raw reply
* Issues with i.MX SPI DMA transfers
From: Robin Gong @ 2019-04-03 7:38 UTC (permalink / raw)
To: Igor Plyatov
Cc: Uwe Kleine-König, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org,
dl-linux-imx, Fabio Estevam, Pengutronix Kernel Team,
Sascha Hauer, Shawn Guo, Mark Brown, dmaengine@vger.kernel.org,
Vinod Koul, Dan Williams, Andy Duan, Han Xu, Clark Wang
> -----Original Message-----
> From: Igor Plyatov <plyatov@gmail.com>
> Sent: 2019年4月2日 20:15
> To: Robin Gong <yibin.gong@nxp.com>
> Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>;
> linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-spi@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>; Fabio Estevam
> <festevam@gmail.com>; Pengutronix Kernel Team <kernel@pengutronix.de>;
> Sascha Hauer <s.hauer@pengutronix.de>; Shawn Guo
> <shawnguo@kernel.org>; Mark Brown <broonie@kernel.org>;
> dmaengine@vger.kernel.org; Vinod Koul <vkoul@kernel.org>; Dan Williams
> <dan.j.williams@intel.com>; Andy Duan <fugang.duan@nxp.com>; Han Xu
> <han.xu@nxp.com>; Clark Wang <xiaoning.wang@nxp.com>
> Subject: Re: Issues with i.MX SPI DMA transfers
>
> Dear Robin,
>
> >> now I have reverted patch ad0d92d7ba6a.
> >> Patches 0001-dma-engine-imx-sdma-add-mcu_2_ecspi-script.patch and
> >> 0002-spi-spi-imx-fix-ERR009165.patch are applied.
> >>
> >>
> >> Kernel log show messages
> >>
> >> [ 29.202639] imx-sdma 20ec000.sdma: loaded firmware 3.3 [
> >> 29.238595] spi_imx 2008000.spi: probed [ 29.242802] spi_imx
> >> 200c000.spi: probed [ 29.245217] spi_imx 2018000.spi: probed
> >>
> >> SPI DMA transfers still not work.
> >>
> >> If I test 32 byte transfers, then they work fine. But 64 byte
> >> transfers fails always and I see error messages
> >>
> >> root@cr7:~# spidev_test -D /dev/spidev4.1 -s 1200000 -b 8 -S 64 -I 1
> >> -l spi mode: 0x20 bits per word: 8 max speed: 1200000 Hz (1200 KHz) [
> >> 423.686736] spi_master spi4: I/O Error in DMA RX [ 423.691392]
> >> spidev spi4.1: SPI transfer failed: -110 [ 423.696382] spi_master
> >> spi4: failed to transfer one message from queue can't send spi
> >> message: Connection timed out Aborted (core dumped)
> >>
> >> I suppose, transfers shorter then 64 bytes made with help of PIO.
> >>
> >> Robin, is there any chance for you to find some time and look at this
> >> issue again?
> > I have quick test with spidev_test loopback, but didn't meet your
> > error, Is your code the almost latest code in linux-next as mine?
> >
> > root@imx6qpdlsolox:~# cat /proc/interrupts | grep sdma
> > 48: 37 GPC 2 Level sdma
> > -lt@imx6qpdlsolox:~# ./spidev_test -D /dev/spidev0.0 -s 1200000 -b 8
> > -S 64 -I 1 -l spi mode: 0x20 bits per word: 8 max speed: 1200000 Hz
> > (1200 KHz) root@imx6qpdlsolox:~# cat /proc/interrupts | grep sdma
> > 48: 43 GPC 2 Level sdma
> > ./spidev_test -D /dev/spidev0.0 -s 1200000 -b 8 -S 512 -I 1 -l spi
> > mode: 0x20 bits per word: 8 max speed: 1200000 Hz (1200 KHz)
> > total: tx 0.5KB, rx 0.5KB
>
>
> My previous test results based on kernel from "main" branch of
> git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git.
>
> Now I have tested kernel from "main" branch of
> git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git.
>
> Its latest commit is 05d08e2995cbe6efdb993482ee0d38a77040861a.
>
> Additionally, I have reverted patch ad0d92d7ba6a and apply yours patches
> 0001-dma-engine-imx-sdma-add-mcu_2_ecspi-script.patch and
> 0002-spi-spi-imx-fix-ERR009165.patch.
>
> Difference between 05d08e2995cbe6efdb993482ee0d38a77040861a and
> current state of drivers attached as spi-and-sdma-drivers.diff.
>
> SPI driver still not work. It has same result as from my previous email.
>
> Looks as you use either different GIT branch of kernel or you have forget to say
> me about some patch.
The same base as your side commit '05d08e2995cbe6efdb993482ee0d38a77040861a ' and
same diff, but did you revert another sdma patch about "clk_ratio" which broke sdma basic
function on non-i.mx8m chips?
commit 25aaa75df1e659901d77085bcdd25eaabf265688
Author: Angus Ainslie (Purism) <angus@akkea.ca>
Date: Mon Jan 28 09:03:21 2019 -0700
dmaengine: imx-sdma: add clock ratio 1:1 check
On i.mx8 mscale B0 chip, AHB/SDMA clock ratio 2:1 can't be supportted,
since SDMA clock ratio has to be increased to 250Mhz, AHB can't reach
to 500Mhz, so use 1:1 instead.
>
> Best wishes.
>
> --
>
> Igor Plyatov
^ permalink raw reply
* Issues with i.MX SPI DMA transfers
From: Igor Plyatov @ 2019-04-02 12:15 UTC (permalink / raw)
To: Robin Gong
Cc: Uwe Kleine-König, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org,
dl-linux-imx, Fabio Estevam, Pengutronix Kernel Team,
Sascha Hauer, Shawn Guo, Mark Brown, dmaengine@vger.kernel.org,
Vinod Koul, Dan Williams, Andy Duan, Han Xu, Clark Wang
Dear Robin,
>> now I have reverted patch ad0d92d7ba6a.
>> Patches 0001-dma-engine-imx-sdma-add-mcu_2_ecspi-script.patch and
>> 0002-spi-spi-imx-fix-ERR009165.patch are applied.
>>
>>
>> Kernel log show messages
>>
>> [ 29.202639] imx-sdma 20ec000.sdma: loaded firmware 3.3
>> [ 29.238595] spi_imx 2008000.spi: probed
>> [ 29.242802] spi_imx 200c000.spi: probed
>> [ 29.245217] spi_imx 2018000.spi: probed
>>
>> SPI DMA transfers still not work.
>>
>> If I test 32 byte transfers, then they work fine. But 64 byte transfers
>> fails always and I see error messages
>>
>> root@cr7:~# spidev_test -D /dev/spidev4.1 -s 1200000 -b 8 -S 64 -I 1 -l
>> spi mode: 0x20
>> bits per word: 8
>> max speed: 1200000 Hz (1200 KHz)
>> [ 423.686736] spi_master spi4: I/O Error in DMA RX
>> [ 423.691392] spidev spi4.1: SPI transfer failed: -110
>> [ 423.696382] spi_master spi4: failed to transfer one message from queue
>> can't send spi message: Connection timed out
>> Aborted (core dumped)
>>
>> I suppose, transfers shorter then 64 bytes made with help of PIO.
>>
>> Robin, is there any chance for you to find some time and look at this
>> issue again?
> I have quick test with spidev_test loopback, but didn't meet your error,
> Is your code the almost latest code in linux-next as mine?
>
> root@imx6qpdlsolox:~# cat /proc/interrupts | grep sdma
> 48: 37 GPC 2 Level sdma
> -lt@imx6qpdlsolox:~# ./spidev_test -D /dev/spidev0.0 -s 1200000 -b 8 -S 64 -I 1 -l
> spi mode: 0x20
> bits per word: 8
> max speed: 1200000 Hz (1200 KHz)
> root@imx6qpdlsolox:~# cat /proc/interrupts | grep sdma
> 48: 43 GPC 2 Level sdma
> ./spidev_test -D /dev/spidev0.0 -s 1200000 -b 8 -S 512 -I 1 -l
> spi mode: 0x20
> bits per word: 8
> max speed: 1200000 Hz (1200 KHz)
> total: tx 0.5KB, rx 0.5KB
My previous test results based on kernel from "main" branch of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git.
Now I have tested kernel from "main" branch of
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git.
Its latest commit is 05d08e2995cbe6efdb993482ee0d38a77040861a.
Additionally, I have reverted patch ad0d92d7ba6a and apply yours patches
0001-dma-engine-imx-sdma-add-mcu_2_ecspi-script.patch and
0002-spi-spi-imx-fix-ERR009165.patch.
Difference between 05d08e2995cbe6efdb993482ee0d38a77040861a and current
state of drivers attached as spi-and-sdma-drivers.diff.
SPI driver still not work. It has same result as from my previous email.
Looks as you use either different GIT branch of kernel or you have
forget to say me about some patch.
Best wishes.
---
Igor Plyatov
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 5f3c1378b90e..908507fa9526 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -377,7 +377,6 @@ struct sdma_channel {
unsigned long watermark_level;
u32 shp_addr, per_addr;
enum dma_status status;
- bool context_loaded;
struct imx_dma_data data;
struct work_struct terminate_worker;
};
@@ -913,6 +912,9 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
break;
case IMX_DMATYPE_CSPI:
+ per_2_emi = sdma->script_addrs->app_2_mcu_addr;
+ emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr;
+ break;
case IMX_DMATYPE_EXT:
case IMX_DMATYPE_SSI:
case IMX_DMATYPE_SAI:
@@ -976,9 +978,6 @@ static int sdma_load_context(struct sdma_channel *sdmac)
int ret;
unsigned long flags;
- if (sdmac->context_loaded)
- return 0;
-
if (sdmac->direction == DMA_DEV_TO_MEM)
load_address = sdmac->pc_from_device;
else if (sdmac->direction == DMA_DEV_TO_DEV)
@@ -1021,8 +1020,6 @@ static int sdma_load_context(struct sdma_channel *sdmac)
spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
- sdmac->context_loaded = true;
-
return ret;
}
@@ -1062,7 +1059,6 @@ static void sdma_channel_terminate_work(struct work_struct *work)
sdmac->desc = NULL;
spin_unlock_irqrestore(&sdmac->vc.lock, flags);
vchan_dma_desc_free_list(&sdmac->vc, &head);
- sdmac->context_loaded = false;
}
static int sdma_disable_channel_async(struct dma_chan *chan)
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 09c9a1edb2c6..27578158d922 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -585,8 +585,9 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
spi_imx->spi_bus_clk = clk;
+ /* ERR009165: work in XHC mode as PIO */
if (spi_imx->usedma)
- ctrl |= MX51_ECSPI_CTRL_SMC;
+ ctrl &= ~MX51_ECSPI_CTRL_SMC;
writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
@@ -1265,10 +1266,6 @@ static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
{
int ret;
- /* use pio mode for i.mx6dl chip TKT238285 */
- if (of_machine_is_compatible("fsl,imx6dl"))
- return 0;
-
spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
/* Prepare for TX DMA: */
diff --git a/include/linux/platform_data/dma-imx-sdma.h b/include/linux/platform_data/dma-imx-sdma.h
index 6eaa53cef0bd..f794fee8fc0f 100644
--- a/include/linux/platform_data/dma-imx-sdma.h
+++ b/include/linux/platform_data/dma-imx-sdma.h
@@ -51,6 +51,7 @@ struct sdma_script_start_addrs {
/* End of v2 array */
s32 zcanfd_2_mcu_addr;
s32 zqspi_2_mcu_addr;
+ s32 mcu_2_ecspi_addr;
/* End of v3 array */
};
^ permalink raw reply related
* [RFC] dmaengine: bcm2835: Avoid GFP_KERNEL in device_prep_slave_sg
From: Stefan Wahren @ 2019-04-01 18:38 UTC (permalink / raw)
To: Dan Williams, Vinod Koul, Florian Fainelli, Ray Jui,
Scott Branden, Eric Anholt
Cc: bcm-kernel-feedback-list, Aaro Koskinen, Lukas Wunner,
Florian Kauer, Martin Sperl, dmaengine, linux-arm-kernel,
linux-rpi-kernel, Stefan Wahren
The commit af19b7ce76ba ("mmc: bcm2835: Avoid possible races on
data requests") introduces a possible circular locking dependency,
which is triggered by swapping to the sdhost interface.
So instead of reintroduce the race condition again, we could also
avoid this situation by using GFP_NOWAIT for the allocation of the
DMA buffer descriptors.
Reported-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Fixes: af19b7ce76ba ("mmc: bcm2835: Avoid possible races on data requests")
Link: http://lists.infradead.org/pipermail/linux-rpi-kernel/2019-March/008615.html
---
drivers/dma/bcm2835-dma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
index ec8a291..54093ff 100644
--- a/drivers/dma/bcm2835-dma.c
+++ b/drivers/dma/bcm2835-dma.c
@@ -671,7 +671,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg(
d = bcm2835_dma_create_cb_chain(chan, direction, false,
info, extra,
frames, src, dst, 0, 0,
- GFP_KERNEL);
+ GFP_NOWAIT);
if (!d)
return NULL;
^ permalink raw reply related
* [2/2] dmaengine: sh: rcar-dmac: Fix glitch in dmaengine_tx_status
From: Dirk Behme @ 2019-04-01 12:47 UTC (permalink / raw)
To: linux-renesas-soc
Cc: dmaengine, vkoul, geert+renesas, niklas.soderlund+renesas,
laurent.pinchart+renesas, Achim.Dahlhoff, stable
Hi Renesas SoC team,
On 05.03.2019 06:56, Dirk Behme wrote:
> From: Achim Dahlhoff <Achim.Dahlhoff@de.bosch.com>
>
> The tx_status poll in the rcar_dmac driver reads the status register
> which indicates which chunk is busy (DMACHCRB). Afterwards the point
> inside the chunk is read from DMATCRB. It is possible that the chunk
> has changed between the two reads. The result is a non-monotonous
> increase of the residue. Fix this by introducing a 'safe read' logic.
>
> Fixes: 73a47bd0da66 ("dmaengine: rcar-dmac: use TCRB instead of TCR for residue")
> Signed-off-by: Achim Dahlhoff <Achim.Dahlhoff@de.bosch.com>
> Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
> Cc: <stable@vger.kernel.org> # v4.16+
> ---
> Note: Patch done against mainline v5.0
>
> Changes in v2: Switch goto/retry to for loop
Any status update on this and the first fix
[PATCH v2 1/2] dmaengine: sh: rcar-dmac: With cyclic DMA residue 0 is valid
?
I still think they are required to fix the rcar-dmac driver.
Best regards
Dirk
> drivers/dma/sh/rcar-dmac.c | 26 +++++++++++++++++++++++---
> 1 file changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
> index 2ea59229d7f5..cceddc7099b0 100644
> --- a/drivers/dma/sh/rcar-dmac.c
> +++ b/drivers/dma/sh/rcar-dmac.c
> @@ -1282,6 +1282,9 @@ static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan,
> enum dma_status status;
> unsigned int residue = 0;
> unsigned int dptr = 0;
> + unsigned int chcrb;
> + unsigned int tcrb;
> + unsigned int i;
>
> if (!desc)
> return 0;
> @@ -1329,6 +1332,24 @@ static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan,
> return 0;
> }
>
> + /*
> + * We need to read two registers.
> + * Make sure the control register does not skip to next chunk
> + * while reading the counter.
> + * Trying it 3 times should be enough: Initial read, retry, retry
> + * for the paranoid.
> + */
> + for (i = 0; i < 3; i++) {
> + chcrb = rcar_dmac_chan_read(chan, RCAR_DMACHCRB) &
> + RCAR_DMACHCRB_DPTR_MASK;
> + tcrb = rcar_dmac_chan_read(chan, RCAR_DMATCRB);
> + /* Still the same? */
> + if (chcrb == (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) &
> + RCAR_DMACHCRB_DPTR_MASK))
> + break;
> + }
> + WARN_ONCE(i >= 3, "residue might be not continuous!");
> +
> /*
> * In descriptor mode the descriptor running pointer is not maintained
> * by the interrupt handler, find the running descriptor from the
> @@ -1336,8 +1357,7 @@ static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan,
> * mode just use the running descriptor pointer.
> */
> if (desc->hwdescs.use) {
> - dptr = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) &
> - RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT;
> + dptr = chcrb >> RCAR_DMACHCRB_DPTR_SHIFT;
> if (dptr == 0)
> dptr = desc->nchunks;
> dptr--;
> @@ -1355,7 +1375,7 @@ static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan,
> }
>
> /* Add the residue for the current chunk. */
> - residue += rcar_dmac_chan_read(chan, RCAR_DMATCRB) << desc->xfer_shift;
> + residue += tcrb << desc->xfer_shift;
>
> return residue;
> }
^ permalink raw reply
* [v2,1/3] arm64: dts: imx8mq: Fix the fsl,imx8mq-sdma compatible string
From: Daniel Baluta @ 2019-03-30 16:55 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: Angus Ainslie, Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, dl-linux-imx,
Dan Williams, Vinod Koul, Lucas Stach, Carlo Caione,
Guido Günther, Devicetree List, linux-arm-kernel,
Linux Kernel Mailing List, dmaengine@vger.kernel.org
On Fri, Mar 29, 2019 at 5:22 PM Angus Ainslie (Purism) <angus@akkea.ca> wrote:
>
> Fix a typo in the compatible string
>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 81d5ce1b1ec1..06158625f24f 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -720,7 +720,7 @@
> };
>
> sdma1: sdma@30bd0000 {
> - compatible = "fsl, imx8mq-sdma","fsl,imx7d-sdma";
> + compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
> reg = <0x30bd0000 0x10000>;
> interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
> --
> 2.17.1
>
^ permalink raw reply
* [v2,3/3] arm64: dts: imx8mq: Change ahb clock for imx8mq
From: Angus Ainslie @ 2019-03-29 15:21 UTC (permalink / raw)
To: angus.ainslie
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Dan Williams, Vinod Koul, Lucas Stach, Angus Ainslie (Purism),
Carlo Caione, Daniel Baluta, Guido Günther, devicetree,
linux-arm-kernel, linux-kernel, dmaengine
Set ahb clock on sdma1 to get rid of "Timeout waiting for CH0"
on the imx8mq.
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 06158625f24f..7233d9a315b8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -724,7 +724,7 @@
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
- <&clk IMX8MQ_CLK_SDMA1_ROOT>;
+ <&clk IMX8MQ_CLK_AHB>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
^ permalink raw reply related
* [v2,2/3] dmaengine: imx-sdma: Only check ratio on parts that support 1:1
From: Angus Ainslie @ 2019-03-29 15:21 UTC (permalink / raw)
To: angus.ainslie
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Dan Williams, Vinod Koul, Lucas Stach, Angus Ainslie (Purism),
Carlo Caione, Daniel Baluta, Guido Günther, devicetree,
linux-arm-kernel, linux-kernel, dmaengine
On imx8mq B0 chip, AHB/SDMA clock ratio 2:1 can't be supported,
since SDMA clock ratio has to be increased to 250Mhz, AHB can't reach
to 500Mhz, so use 1:1 instead.
To limit this change to the imx8mq for now this patch also adds an
im8mq-sdma compatible string.
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
drivers/dma/imx-sdma.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 5f3c1378b90e..99d9f431ae2c 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -419,6 +419,7 @@ struct sdma_driver_data {
int chnenbl0;
int num_events;
struct sdma_script_start_addrs *script_addrs;
+ bool check_ratio;
};
struct sdma_engine {
@@ -557,6 +558,13 @@ static struct sdma_driver_data sdma_imx7d = {
.script_addrs = &sdma_script_imx7d,
};
+static struct sdma_driver_data sdma_imx8mq = {
+ .chnenbl0 = SDMA_CHNENBL0_IMX35,
+ .num_events = 48,
+ .script_addrs = &sdma_script_imx7d,
+ .check_ratio = 1,
+};
+
static const struct platform_device_id sdma_devtypes[] = {
{
.name = "imx25-sdma",
@@ -579,6 +587,9 @@ static const struct platform_device_id sdma_devtypes[] = {
}, {
.name = "imx7d-sdma",
.driver_data = (unsigned long)&sdma_imx7d,
+ }, {
+ .name = "imx8mq-sdma",
+ .driver_data = (unsigned long)&sdma_imx8mq,
}, {
/* sentinel */
}
@@ -593,6 +604,7 @@ static const struct of_device_id sdma_dt_ids[] = {
{ .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
{ .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
{ .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
+ { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sdma_dt_ids);
@@ -1852,7 +1864,8 @@ static int sdma_init(struct sdma_engine *sdma)
if (ret)
goto disable_clk_ipg;
- if (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))
+ if (sdma->drvdata->check_ratio &&
+ (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg)))
sdma->clk_ratio = 1;
/* Be sure SDMA has not started yet */
^ permalink raw reply related
* [v2,1/3] arm64: dts: imx8mq: Fix the fsl,imx8mq-sdma compatible string
From: Angus Ainslie @ 2019-03-29 15:21 UTC (permalink / raw)
To: angus.ainslie
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Dan Williams, Vinod Koul, Lucas Stach, Angus Ainslie (Purism),
Carlo Caione, Daniel Baluta, Guido Günther, devicetree,
linux-arm-kernel, linux-kernel, dmaengine
Fix a typo in the compatible string
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 81d5ce1b1ec1..06158625f24f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -720,7 +720,7 @@
};
sdma1: sdma@30bd0000 {
- compatible = "fsl, imx8mq-sdma","fsl,imx7d-sdma";
+ compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
^ permalink raw reply related
* [1/4] arm64: dts: imx8mq: Fix the fsl,imx8mq-sdma compatible string
From: Angus Ainslie @ 2019-03-29 14:09 UTC (permalink / raw)
To: Daniel Baluta
Cc: Aisheng Dong, Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, dl-linux-imx,
Dan Williams, Vinod Koul, Lucas Stach, Carlo Caione,
Daniel Baluta, Guido Günther, devicetree, linux-arm-kernel,
linux-kernel, dmaengine
On 2019-03-29 04:20, Daniel Baluta wrote:
> On Fri, Mar 29, 2019 at 11:11 AM Aisheng Dong <aisheng.dong@nxp.com>
> wrote:
>>
>> > From: Angus Ainslie (Purism) [mailto:angus@akkea.ca]
>> > Sent: Thursday, March 28, 2019 9:38 PM
>> >
>> > Fix a typo in the compatible string
>> >
>> > Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
>> > ---
>> > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
>> > 1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> > index 81d5ce1b1ec1..07099f82965e 100644
>> > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> > @@ -720,7 +720,7 @@
>> > };
>> >
>> > sdma1: sdma@30bd0000 {
>> > - compatible = "fsl, imx8mq-sdma","fsl,imx7d-sdma";
>> > + compatible = "fsl,mx8mq-sdma","fsl,imx7d-sdma";
>>
>> This is a bit strange.
>> If binding doc says like that, probably we'd better fix the typo in
>> binding doc
>> to use the same style.
>
> Oh, indeed.
>
> Angus, shouldn't this be fsl,imx8mq-sdma instead of fsl,mx8mq-sdma. I
> was just paying
> attention to the extra space in my patch.
Correct I took too many characters when I dropped the space. I'll fix it
for v2.
Angus
^ permalink raw reply
* dma: ti: fix a missing check in omap_dma_prep_dma_cyclic
From: Peter Ujfalusi @ 2019-03-29 13:21 UTC (permalink / raw)
To: Kangjie Lu
Cc: pakki001, Vinod Koul, Dan Williams, Janusz Krzysztofik, dmaengine,
linux-kernel
On 24/03/2019 0.39, Kangjie Lu wrote:
> It is invalid when "buf_len" is not aligned with "period_len".
>
> The fix adds a check for the alignment.
>
> Signed-off-by: Kangjie Lu <kjlu@umn.edu>
> ---
> drivers/dma/ti/omap-dma.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/dma/ti/omap-dma.c b/drivers/dma/ti/omap-dma.c
> index a4a931ddf6f6..5f0ce1975e52 100644
> --- a/drivers/dma/ti/omap-dma.c
> +++ b/drivers/dma/ti/omap-dma.c
> @@ -1065,6 +1065,9 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
> unsigned es;
> u32 burst;
>
> + if (buf_len % period_len)
> + return NULL;
> +
if it really happens, then it might be better to do the check in
dmaengine_prep_dma_cyclic() rather than fixing _all_ drivers?
> if (dir == DMA_DEV_TO_MEM) {
> dev_addr = c->cfg.src_addr;
> dev_width = c->cfg.src_addr_width;
>
- Péter
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply
* [1/4] arm64: dts: imx8mq: Fix the fsl,imx8mq-sdma compatible string
From: Daniel Baluta @ 2019-03-29 11:20 UTC (permalink / raw)
To: Aisheng Dong
Cc: Angus Ainslie (Purism), Rob Herring, Mark Rutland, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
dl-linux-imx, Dan Williams, Vinod Koul, Lucas Stach, Carlo Caione,
Daniel Baluta, Guido Günther, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org
On Fri, Mar 29, 2019 at 11:11 AM Aisheng Dong <aisheng.dong@nxp.com> wrote:
>
> > From: Angus Ainslie (Purism) [mailto:angus@akkea.ca]
> > Sent: Thursday, March 28, 2019 9:38 PM
> >
> > Fix a typo in the compatible string
> >
> > Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > index 81d5ce1b1ec1..07099f82965e 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > @@ -720,7 +720,7 @@
> > };
> >
> > sdma1: sdma@30bd0000 {
> > - compatible = "fsl, imx8mq-sdma","fsl,imx7d-sdma";
> > + compatible = "fsl,mx8mq-sdma","fsl,imx7d-sdma";
>
> This is a bit strange.
> If binding doc says like that, probably we'd better fix the typo in binding doc
> to use the same style.
Oh, indeed.
Angus, shouldn't this be fsl,imx8mq-sdma instead of fsl,mx8mq-sdma. I
was just paying
attention to the extra space in my patch.
^ permalink raw reply
* [1/4] arm64: dts: imx8mq: Fix the fsl,imx8mq-sdma compatible string
From: Dong Aisheng @ 2019-03-29 9:10 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, dl-linux-imx,
Dan Williams, Vinod Koul, Lucas Stach, Carlo Caione,
Daniel Baluta, Guido Günther, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org
> From: Angus Ainslie (Purism) [mailto:angus@akkea.ca]
> Sent: Thursday, March 28, 2019 9:38 PM
>
> Fix a typo in the compatible string
>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 81d5ce1b1ec1..07099f82965e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -720,7 +720,7 @@
> };
>
> sdma1: sdma@30bd0000 {
> - compatible = "fsl, imx8mq-sdma","fsl,imx7d-sdma";
> + compatible = "fsl,mx8mq-sdma","fsl,imx7d-sdma";
This is a bit strange.
If binding doc says like that, probably we'd better fix the typo in binding doc
to use the same style.
Regards
Dong Aisheng
> reg = <0x30bd0000 0x10000>;
> interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
> --
> 2.17.1
^ permalink raw reply
* [2/4] dmaengine: imx-sdma: Add clock ratio 1:1 check
From: Fabio Estevam @ 2019-03-28 22:52 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, NXP Linux Team, Dan Williams, Vinod Koul,
Lucas Stach, Carlo Caione, Daniel Baluta, Guido Günther,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel, dmaengine
Hi Angus,
On Thu, Mar 28, 2019 at 10:39 AM Angus Ainslie (Purism) <angus@akkea.ca> wrote:
>
> On imx8mq B0 chip, AHB/SDMA clock ratio 2:1 can't be supported,
> since SDMA clock ratio has to be increased to 250Mhz, AHB can't reach
> to 500Mhz, so use 1:1 instead.
>
> To limit this change to the imx8mq for now this patch also adds an
> im8mq-sdma compatible string.
>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
This has already been applied and it is in linux-next:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20190328&id=25aaa75df1e659901d77085bcdd25eaabf265688
Please send an incremental fix instead.
^ permalink raw reply
* [3/4] dt-bindings: Document the new imx8mq-sdma compatible string
From: Daniel Baluta @ 2019-03-28 15:18 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Dan Williams, Vinod Koul, Lucas Stach, Carlo Caione,
Daniel Baluta, Guido Günther, Devicetree List,
linux-arm-kernel, Linux Kernel Mailing List, dmaengine
On Thu, Mar 28, 2019 at 3:41 PM Angus Ainslie (Purism) <angus@akkea.ca> wrote:
>
> The imx8mq needs to be specified to check the clk ratio.
>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
> ---
> Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
> index 3c9a57a8443b..9d8bbac27d8b 100644
> --- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
> +++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
> @@ -9,6 +9,7 @@ Required properties:
> "fsl,imx53-sdma"
> "fsl,imx6q-sdma"
> "fsl,imx7d-sdma"
> + "fsl,imx8mq-sdma"
You can drop this patch. It is already in Shwan's for-next branch.
The joy of working in parallel on similar things.
thanks,
Daniel.
^ permalink raw reply
* [1/4] arm64: dts: imx8mq: Fix the fsl,imx8mq-sdma compatible string
From: Daniel Baluta @ 2019-03-28 14:56 UTC (permalink / raw)
To: angus@akkea.ca
Cc: dl-linux-imx, linux-kernel@vger.kernel.org, robh+dt@kernel.org,
ccaione@baylibre.com, devicetree@vger.kernel.org,
festevam@gmail.com, agx@sigxcpu.org, dan.j.williams@intel.com,
mark.rutland@arm.com, dmaengine@vger.kernel.org,
shawnguo@kernel.org, linux-arm-kernel@lists.infradead.org,
vkoul@kernel.org, l.stach@pengutronix.de, kernel@pengutronix.de,
s.hauer@pengutronix.de
On Thu, 2019-03-28 at 06:38 -0700, Angus Ainslie (Purism) wrote:
> Fix a typo in the compatible string
>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
Reviwed-by: Daniel Baluta <daniel.baluta@nxp.com>
^ permalink raw reply
* [4/4] arm64: dts: imx8mq: Change ahb clock for imx8mq
From: Angus Ainslie @ 2019-03-28 13:38 UTC (permalink / raw)
To: angus
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Dan Williams, Vinod Koul, Lucas Stach, Carlo Caione,
Daniel Baluta, Guido Günther, devicetree, linux-arm-kernel,
linux-kernel, dmaengine
Set ahb clock on sdma1 to get rid of "Timeout waiting for CH0"
on the imx8mq.
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 07099f82965e..cd0f9eed9e9c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -724,7 +724,7 @@
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
- <&clk IMX8MQ_CLK_SDMA1_ROOT>;
+ <&clk IMX8MQ_CLK_AHB>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
^ permalink raw reply related
* [3/4] dt-bindings: Document the new imx8mq-sdma compatible string
From: Angus Ainslie @ 2019-03-28 13:38 UTC (permalink / raw)
To: angus
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Dan Williams, Vinod Koul, Lucas Stach, Carlo Caione,
Daniel Baluta, Guido Günther, devicetree, linux-arm-kernel,
linux-kernel, dmaengine
The imx8mq needs to be specified to check the clk ratio.
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
index 3c9a57a8443b..9d8bbac27d8b 100644
--- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
@@ -9,6 +9,7 @@ Required properties:
"fsl,imx53-sdma"
"fsl,imx6q-sdma"
"fsl,imx7d-sdma"
+ "fsl,imx8mq-sdma"
The -to variants should be preferred since they allow to determine the
correct ROM script addresses needed for the driver to work without additional
firmware.
^ permalink raw reply related
* [2/4] dmaengine: imx-sdma: Add clock ratio 1:1 check
From: Angus Ainslie @ 2019-03-28 13:38 UTC (permalink / raw)
To: angus
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Dan Williams, Vinod Koul, Lucas Stach, Carlo Caione,
Daniel Baluta, Guido Günther, devicetree, linux-arm-kernel,
linux-kernel, dmaengine
On imx8mq B0 chip, AHB/SDMA clock ratio 2:1 can't be supported,
since SDMA clock ratio has to be increased to 250Mhz, AHB can't reach
to 500Mhz, so use 1:1 instead.
To limit this change to the imx8mq for now this patch also adds an
im8mq-sdma compatible string.
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
drivers/dma/imx-sdma.c | 31 +++++++++++++++++++++++++++----
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 7fae4bf885d5..99d9f431ae2c 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -419,6 +419,7 @@ struct sdma_driver_data {
int chnenbl0;
int num_events;
struct sdma_script_start_addrs *script_addrs;
+ bool check_ratio;
};
struct sdma_engine {
@@ -441,6 +442,8 @@ struct sdma_engine {
unsigned int irq;
dma_addr_t bd0_phys;
struct sdma_buffer_descriptor *bd0;
+ /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
+ bool clk_ratio;
};
static int sdma_config_write(struct dma_chan *chan,
@@ -555,6 +558,13 @@ static struct sdma_driver_data sdma_imx7d = {
.script_addrs = &sdma_script_imx7d,
};
+static struct sdma_driver_data sdma_imx8mq = {
+ .chnenbl0 = SDMA_CHNENBL0_IMX35,
+ .num_events = 48,
+ .script_addrs = &sdma_script_imx7d,
+ .check_ratio = 1,
+};
+
static const struct platform_device_id sdma_devtypes[] = {
{
.name = "imx25-sdma",
@@ -577,6 +587,9 @@ static const struct platform_device_id sdma_devtypes[] = {
}, {
.name = "imx7d-sdma",
.driver_data = (unsigned long)&sdma_imx7d,
+ }, {
+ .name = "imx8mq-sdma",
+ .driver_data = (unsigned long)&sdma_imx8mq,
}, {
/* sentinel */
}
@@ -591,6 +604,7 @@ static const struct of_device_id sdma_dt_ids[] = {
{ .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
{ .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
{ .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
+ { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sdma_dt_ids);
@@ -663,8 +677,11 @@ static int sdma_run_channel0(struct sdma_engine *sdma)
dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
/* Set bits of CONFIG register with dynamic context switching */
- if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
- writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
+ reg = readl(sdma->regs + SDMA_H_CONFIG);
+ if ((reg & SDMA_H_CONFIG_CSM) == 0) {
+ reg |= SDMA_H_CONFIG_CSM;
+ writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG);
+ }
return ret;
}
@@ -1847,6 +1864,10 @@ static int sdma_init(struct sdma_engine *sdma)
if (ret)
goto disable_clk_ipg;
+ if (sdma->drvdata->check_ratio &&
+ (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg)))
+ sdma->clk_ratio = 1;
+
/* Be sure SDMA has not started yet */
writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
@@ -1887,8 +1908,10 @@ static int sdma_init(struct sdma_engine *sdma)
writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
/* Set bits of CONFIG register but with static context switching */
- /* FIXME: Check whether to set ACR bit depending on clock ratios */
- writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
+ if (sdma->clk_ratio)
+ writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG);
+ else
+ writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
^ permalink raw reply related
* [1/4] arm64: dts: imx8mq: Fix the fsl,imx8mq-sdma compatible string
From: Angus Ainslie @ 2019-03-28 13:38 UTC (permalink / raw)
To: angus
Cc: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Dan Williams, Vinod Koul, Lucas Stach, Carlo Caione,
Daniel Baluta, Guido Günther, devicetree, linux-arm-kernel,
linux-kernel, dmaengine
Fix a typo in the compatible string
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 81d5ce1b1ec1..07099f82965e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -720,7 +720,7 @@
};
sdma1: sdma@30bd0000 {
- compatible = "fsl, imx8mq-sdma","fsl,imx7d-sdma";
+ compatible = "fsl,mx8mq-sdma","fsl,imx7d-sdma";
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
^ permalink raw reply related
* [1/6] dt-bindings: arm64: allwinner: h6: Add binding for DMA controller
From: Rob Herring @ 2019-03-27 23:47 UTC (permalink / raw)
To: Jernej Skrabec
Cc: maxime.ripard, wens, mark.rutland, devicetree, linux-sunxi,
linux-kernel, vkoul, robh+dt, dmaengine, dan.j.williams,
linux-arm-kernel
On Thu, 7 Mar 2019 17:58:24 +0100, Jernej Skrabec wrote:
> DMA in H6 is similar to other DMA controller, except it is first which
> supports more than 32 request sources and has 16 channels. It also needs
> additional clock to be enabled.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> ---
> Documentation/devicetree/bindings/dma/sun6i-dma.txt | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* dmaengine: stm32-dma: fix residue calculation in stm32-dma
From: Arnaud Pouliquen @ 2019-03-27 12:21 UTC (permalink / raw)
To: Vinod Koul
Cc: Dan Williams, arnaud.pouliquen, Pierre-Yves MORDRET, linux-stm32,
linux-kernel, dmaengine
During residue calculation. the DMA can switch to the next sg. When
this race condition occurs, the residue returned value is not valid.
Indeed the position in the sg returned by the hardware is the position
of the next sg, not the current sg.
Solution is to check the sg after the calculation to verify it.
If a transition is detected we consider that the DMA has switched to
the beginning of next sg.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
---
drivers/dma/stm32-dma.c | 70 ++++++++++++++++++++++++++++++++++++++++---------
1 file changed, 57 insertions(+), 13 deletions(-)
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index 4903a40..30309d2 100644
--- a/drivers/dma/stm32-dma.c
+++ b/drivers/dma/stm32-dma.c
@@ -1038,33 +1038,77 @@ static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan)
return ndtr << width;
}
+static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan)
+{
+ struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
+ struct stm32_dma_sg_req *sg_req;
+ u32 dma_scr, dma_smar, id;
+
+ id = chan->id;
+ dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
+
+ if (!(dma_scr & STM32_DMA_SCR_DBM))
+ return true;
+
+ sg_req = &chan->desc->sg_req[chan->next_sg];
+
+ if (dma_scr & STM32_DMA_SCR_CT) {
+ dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(id));
+ return (dma_smar == sg_req->chan_reg.dma_sm0ar);
+ }
+
+ dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(id));
+
+ return (dma_smar == sg_req->chan_reg.dma_sm1ar);
+}
+
static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,
struct stm32_dma_desc *desc,
u32 next_sg)
{
u32 modulo, burst_size;
- u32 residue = 0;
+ u32 residue;
+ u32 n_sg = next_sg;
+ struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg];
int i;
+ residue = stm32_dma_get_remaining_bytes(chan);
+
/*
- * In cyclic mode, for the last period, residue = remaining bytes from
- * NDTR
+ * Calculate the residue means compute the descriptors
+ * information:
+ * - the sg currently transferred
+ * - the remaining position in this sg (NDTR).
+ *
+ * The issue is that a race condition can occur if DMA is
+ * running. DMA can have started to transfer the next sg before
+ * the position in sg is read. In this case the remaing position
+ * can correspond to the new sg position.
+ * The strategy implemented in the stm32 driver is to check the
+ * sg transition. If detected we can not trust the SxNDTR register
+ * value, this register can not be up to date during the transition.
+ * In this case we can assume that the dma is at the beginning of next
+ * sg so we calculate the residue in consequence.
*/
- if (chan->desc->cyclic && next_sg == 0) {
- residue = stm32_dma_get_remaining_bytes(chan);
- goto end;
+
+ if (!stm32_dma_is_current_sg(chan)) {
+ n_sg++;
+ if (n_sg == chan->desc->num_sgs)
+ n_sg = 0;
+ residue = sg_req->len;
}
/*
- * For all other periods in cyclic mode, and in sg mode,
- * residue = remaining bytes from NDTR + remaining periods/sg to be
- * transferred
+ * In cyclic mode, for the last period, residue = remaining bytes
+ * from NDTR,
+ * else for all other periods in cyclic mode, and in sg mode,
+ * residue = remaining bytes from NDTR + remaining
+ * periods/sg to be transferred
*/
- for (i = next_sg; i < desc->num_sgs; i++)
- residue += desc->sg_req[i].len;
- residue += stm32_dma_get_remaining_bytes(chan);
+ if (!chan->desc->cyclic || n_sg != 0)
+ for (i = n_sg; i < desc->num_sgs; i++)
+ residue += desc->sg_req[i].len;
-end:
if (!chan->mem_burst)
return residue;
^ permalink raw reply related
* [V2,RESEND] dmaengine: axi-dmac: Enable DMA_INTERLEAVE capability
From: Alexandru Ardelean @ 2019-03-26 14:07 UTC (permalink / raw)
To: dmaengine; +Cc: Dragos Bogdan, Alexandru Ardelean
From: Dragos Bogdan <dragos.bogdan@analog.com>
Since device_prep_interleaved_dma() is already implemented, the
DMA_INTERLEAVE capability should be set.
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
V2 seems to have been omitted earlier.
Probably due to some patchwork thing.
drivers/dma/dma-axi-dmac.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c
index 0fe3a931d8d5..7fbb10003da8 100644
--- a/drivers/dma/dma-axi-dmac.c
+++ b/drivers/dma/dma-axi-dmac.c
@@ -693,6 +693,7 @@ static int axi_dmac_probe(struct platform_device *pdev)
dma_dev = &dmac->dma_dev;
dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
dma_cap_set(DMA_CYCLIC, dma_dev->cap_mask);
+ dma_cap_set(DMA_INTERLEAVE, dma_dev->cap_mask);
dma_dev->device_free_chan_resources = axi_dmac_free_chan_resources;
dma_dev->device_tx_status = dma_cookie_status;
dma_dev->device_issue_pending = axi_dmac_issue_pending;
^ permalink raw reply related
* [V3] dmaengine: axi-dmac: Don't check the number of frames for alignment
From: Alexandru Ardelean @ 2019-03-26 14:05 UTC (permalink / raw)
To: dmaengine; +Cc: Alexandru Ardelean
In 2D transfers (for the AXI DMAC), the number of frames (numf) represents
Y_LENGTH, and the length of a frame is X_LENGTH. 2D transfers are useful
for video transfers where screen resolutions ( X * Y ) are typically
aligned for X, but not for Y.
There is no requirement for Y_LENGTH to be aligned to the bus-width (or
anything), and this is also true for AXI DMAC.
Checking the Y_LENGTH for alignment causes false errors when initiating DMA
transfers. This change fixes this by checking only that the Y_LENGTH is
non-zero.
Fixes: 0e3b67b348b8 ("dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller")
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
Changelog v2->v3:
* Fixed typo in `Fixes` commit
drivers/dma/dma-axi-dmac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c
index 0fe3a931d8d5..0e0c457a7b27 100644
--- a/drivers/dma/dma-axi-dmac.c
+++ b/drivers/dma/dma-axi-dmac.c
@@ -526,7 +526,7 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_interleaved(
if (chan->hw_2d) {
if (!axi_dmac_check_len(chan, xt->sgl[0].size) ||
- !axi_dmac_check_len(chan, xt->numf))
+ xt->numf == 0)
return NULL;
if (xt->sgl[0].size + dst_icg > chan->max_length ||
xt->sgl[0].size + src_icg > chan->max_length)
^ permalink raw reply related
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