[PATCH 00/10] e1000 base code update

[PATCH 00/10] e1000 base code update

[Ciara Loftus]

Update the e1000 base code. The changes are mostly fixes, refactoring,
and code cleanup.

Ciara Loftus (1):
  net/e1000/base: update version info

Dima Ruinskiy (2):
  net/e1000/base: fix coding style issues
  net/e1000/base: propagate PHY control register write error

Lukasz Czapnik (1):
  net/e1000/base: fix possible variable overflow

Mateusz Fryze (1):
  net/e1000/base: auto-negotiation status for 1000BASE-T

Menachem Fogel (1):
  net/e1000/base: fix NVM loop bounds and pointer access

Vitaly Lifshits (4):
  net/e1000/base: refactor K1 exit timeout configuration
  net/e1000/base: fix typo in e1000 base code
  net/e1000/base: reclassify MAC type
  net/e1000/base: clear DPG enable bit post MAC reset

 .mailmap                                     |  1 +
 drivers/net/intel/e1000/base/README          |  4 +-
 drivers/net/intel/e1000/base/e1000_82575.c   |  5 +-
 drivers/net/intel/e1000/base/e1000_api.c     | 20 ++++-
 drivers/net/intel/e1000/base/e1000_api.h     |  1 +
 drivers/net/intel/e1000/base/e1000_defines.h | 23 ++++++
 drivers/net/intel/e1000/base/e1000_hw.h      |  9 ++
 drivers/net/intel/e1000/base/e1000_ich8lan.c | 28 +++++--
 drivers/net/intel/e1000/base/e1000_ich8lan.h |  3 +
 drivers/net/intel/e1000/base/e1000_mac.c     |  2 +-
 drivers/net/intel/e1000/base/e1000_manage.c  |  4 +-
 drivers/net/intel/e1000/base/e1000_phy.c     | 86 +++++++++++++++++++-
 drivers/net/intel/e1000/base/e1000_phy.h     |  2 +
 13 files changed, 169 insertions(+), 19 deletions(-)

-- 
2.43.0

[PATCH 01/10] net/e1000/base: refactor K1 exit timeout configuration

[Ciara Loftus]

From: Vitaly Lifshits <vitaly.lifshits@intel.com>

Replace magic numbers in the FEXTNVM12 register access with named bit
definitions to improve readability. Add a missing error path to ensure
ME activity blocking a PHY reset is correctly propagated to the caller.
Also improve some code formatting.

Fixes: 38db3f7f50bd ("e1000: update base driver")
Cc: stable@dpdk.org

Signed-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>
Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/e1000/base/e1000_ich8lan.c | 11 ++++++++---
 drivers/net/intel/e1000/base/e1000_ich8lan.h |  3 +++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/net/intel/e1000/base/e1000_ich8lan.c b/drivers/net/intel/e1000/base/e1000_ich8lan.c
index ece61650f7..58597cce8a 100644
--- a/drivers/net/intel/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/intel/e1000/base/e1000_ich8lan.c
@@ -305,8 +305,8 @@ STATIC s32 e1000_reconfigure_k1_exit_timeout(struct e1000_hw *hw)
 		return E1000_SUCCESS;
 
 	fextnvm12 = E1000_READ_REG(hw, E1000_FEXTNVM12);
-	fextnvm12 |= (1 << 23);
-	fextnvm12 &= ~((1 << 22));
+	fextnvm12 &= ~E1000_FEXTNVM12_PHYPD_CTRL_MASK;
+	fextnvm12 |= E1000_FEXTNVM12_PHYPD_CTRL_P1;
 	E1000_WRITE_REG(hw, E1000_FEXTNVM12, fextnvm12);
 
 	msec_delay_irq(1);
@@ -318,6 +318,9 @@ STATIC s32 e1000_reconfigure_k1_exit_timeout(struct e1000_hw *hw)
 	ret_val = hw->phy.ops.write_reg_locked(hw, E1000_PHY_TIMEOUTS_REG,
 					       phy_timeout);
 
+	DEBUGOUT1("e1000_reconfigure_k1_exit_timeout returns %d\n",
+		  ret_val);
+
 	return ret_val;
 }
 
@@ -460,8 +463,10 @@ STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 		 *  the PHY is in.
 		 */
 		ret_val = hw->phy.ops.check_reset_block(hw);
-		if (ret_val)
+		if (ret_val) {
 			ERROR_REPORT("ME blocked access to PHY after reset\n");
+			goto out;
+		}
 
 		if (hw->mac.type >= e1000_pch_mtp) {
 			ret_val = hw->phy.ops.acquire(hw);
diff --git a/drivers/net/intel/e1000/base/e1000_ich8lan.h b/drivers/net/intel/e1000/base/e1000_ich8lan.h
index f2ba910ea6..43360400bc 100644
--- a/drivers/net/intel/e1000/base/e1000_ich8lan.h
+++ b/drivers/net/intel/e1000/base/e1000_ich8lan.h
@@ -89,6 +89,9 @@
 #define E1000_FEXTNVM11_DISABLE_PB_READ		0x00000200
 #define E1000_FEXTNVM11_DISABLE_MULR_FIX	0x00002000
 #define E1000_FEXTNVM12_DONT_WAK_DPG_CLKREQ	0x00001000
+#define E1000_FEXTNVM12_PHYPD_CTRL_MASK		0x00C00000
+#define E1000_FEXTNVM12_PHYPD_CTRL_P1		0x00800000
+
 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
 #define E1000_RXDCTL_THRESH_UNIT_DESC	0x01000000
 
-- 
2.43.0

[PATCH 02/10] net/e1000/base: fix typo in e1000 base code

[Ciara Loftus]

From: Vitaly Lifshits <vitaly.lifshits@intel.com>

A typo was introduced in commit ba54bdc79d94 ("net/e1000/base: improve
clock synchronization workaround"). Fix it.

Fixes: ba54bdc79d94 ("net/e1000/base: improve clock synchronization workaround")
Cc: stable@dpdk.org

Signed-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>
Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/e1000/base/e1000_ich8lan.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/intel/e1000/base/e1000_ich8lan.c b/drivers/net/intel/e1000/base/e1000_ich8lan.c
index 58597cce8a..6190052368 100644
--- a/drivers/net/intel/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/intel/e1000/base/e1000_ich8lan.c
@@ -288,7 +288,7 @@ STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
  * e1000_reconfigure_k1_exit_timeout
  * @hw: pointer to the HW structure
  *
- * Reconfigure K1 exit timeout as a workaround to the PHY sycndhronization issue
+ * Reconfigure K1 exit timeout as a workaround to the PHY synchronization issue
  * on MTL, LNL, PTL and WCL.
  *
  * Assuming PHY semaphore is taken prior to this function call.
-- 
2.43.0

[PATCH 03/10] net/e1000/base: fix possible variable overflow

[Ciara Loftus]

From: Lukasz Czapnik <lukasz.czapnik@intel.com>

Bits can be lost as temporary math is done on signed variables and the
result is assigned to an unsigned variable. Cast to u32 to force the
compiler to do operations on unsigned temporary variables.

Fixes: af75078fece3 ("first public release")
Cc: stable@dpdk.org

Signed-off-by: Lukasz Czapnik <lukasz.czapnik@intel.com>
Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/e1000/base/e1000_mac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/intel/e1000/base/e1000_mac.c b/drivers/net/intel/e1000/base/e1000_mac.c
index 41aae86ffe..408e8e46e8 100644
--- a/drivers/net/intel/e1000/base/e1000_mac.c
+++ b/drivers/net/intel/e1000/base/e1000_mac.c
@@ -1970,7 +1970,7 @@ s32 e1000_blink_led_generic(struct e1000_hw *hw)
 			     (mode == E1000_LEDCTL_MODE_LED_OFF))) {
 				ledctl_blink &=
 				    ~(E1000_LEDCTL_LED0_MODE_MASK << i);
-				ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
+				ledctl_blink |= (u32)(E1000_LEDCTL_LED0_BLINK |
 						 E1000_LEDCTL_MODE_LED_ON) << i;
 			}
 		}
-- 
2.43.0

[PATCH 04/10] net/e1000/base: reclassify MAC type

[Ciara Loftus]

From: Vitaly Lifshits <vitaly.lifshits@intel.com>

Reclassify LM19/V19 from e1000_pch_mtp to e1000_pch_adp.

Signed-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>
Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/e1000/base/e1000_api.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/intel/e1000/base/e1000_api.c b/drivers/net/intel/e1000/base/e1000_api.c
index 7ff63414a7..a7877613e3 100644
--- a/drivers/net/intel/e1000/base/e1000_api.c
+++ b/drivers/net/intel/e1000/base/e1000_api.c
@@ -312,12 +312,12 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
 	case E1000_DEV_ID_PCH_ADL_I219_V17:
 	case E1000_DEV_ID_PCH_RPL_I219_LM22:
 	case E1000_DEV_ID_PCH_RPL_I219_V22:
+	case E1000_DEV_ID_PCH_MTP_I219_LM19:
+	case E1000_DEV_ID_PCH_MTP_I219_V19:
 		mac->type = e1000_pch_adp;
 		break;
 	case E1000_DEV_ID_PCH_MTP_I219_LM18:
 	case E1000_DEV_ID_PCH_MTP_I219_V18:
-	case E1000_DEV_ID_PCH_MTP_I219_LM19:
-	case E1000_DEV_ID_PCH_MTP_I219_V19:
 	case E1000_DEV_ID_PCH_LNL_I219_LM20:
 	case E1000_DEV_ID_PCH_LNL_I219_V20:
 	case E1000_DEV_ID_PCH_ARL_I219_LM24:
-- 
2.43.0

[PATCH 05/10] net/e1000/base: clear DPG enable bit post MAC reset

[Ciara Loftus]

From: Vitaly Lifshits <vitaly.lifshits@intel.com>

The GbE autonomous power gating feature was added to support G3 to S5
flow. However, this changed the reset value of DPG_EN bit to 1, causing
a possible autonomous transition to power gating state during D0. This
might result in undefined errors such as: packet loss, packet corruption
and Tx/Rx hangs. Therefore, clear DPG_EN bit after hardware reset flow.

Signed-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>
Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/e1000/base/e1000_defines.h | 1 +
 drivers/net/intel/e1000/base/e1000_ich8lan.c | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/net/intel/e1000/base/e1000_defines.h b/drivers/net/intel/e1000/base/e1000_defines.h
index eb93675823..6c710300a6 100644
--- a/drivers/net/intel/e1000/base/e1000_defines.h
+++ b/drivers/net/intel/e1000/base/e1000_defines.h
@@ -36,6 +36,7 @@
 
 /* Extended Device Control */
 #define E1000_CTRL_EXT_LPCD		0x00000004 /* LCD Power Cycle Done */
+#define E1000_CTRL_EXT_DPG_EN		0x00000008 /* Dynamic Power Gating Enable */
 #define E1000_CTRL_EXT_SDP4_DATA	0x00000010 /* SW Definable Pin 4 data */
 #define E1000_CTRL_EXT_SDP6_DATA	0x00000040 /* SW Definable Pin 6 data */
 #define E1000_CTRL_EXT_SDP3_DATA	0x00000080 /* SW Definable Pin 3 data */
diff --git a/drivers/net/intel/e1000/base/e1000_ich8lan.c b/drivers/net/intel/e1000/base/e1000_ich8lan.c
index 6190052368..96b9ad6a70 100644
--- a/drivers/net/intel/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/intel/e1000/base/e1000_ich8lan.c
@@ -5107,6 +5107,13 @@ STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
 	reg |= E1000_KABGTXD_BGSQLBIAS;
 	E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
 
+	if (hw->mac.type >= e1000_pch_ptp) {
+		DEBUGOUT("Clearing DPG EN bit post reset\n");
+		reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
+		reg &= ~E1000_CTRL_EXT_DPG_EN;
+		E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
+	}
+
 	return E1000_SUCCESS;
 }
 
-- 
2.43.0

Re: [PATCH 05/10] net/e1000/base: clear DPG enable bit post MAC reset

[Bruce Richardson]

On Wed, May 20, 2026 at 12:52:42PM +0000, Ciara Loftus wrote:
> From: Vitaly Lifshits <vitaly.lifshits@intel.com>
> 
> The GbE autonomous power gating feature was added to support G3 to S5
> flow. However, this changed the reset value of DPG_EN bit to 1, causing
> a possible autonomous transition to power gating state during D0. This
> might result in undefined errors such as: packet loss, packet corruption
> and Tx/Rx hangs. Therefore, clear DPG_EN bit after hardware reset flow.
> 
> Signed-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>
> Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
> ---

Seems like a bug fix needing backport. Will add fixes tag and CC stable on
apply.

Fixes: 5a32a257f957 ("e1000: more NICs in base driver")

>  drivers/net/intel/e1000/base/e1000_defines.h | 1 +
>  drivers/net/intel/e1000/base/e1000_ich8lan.c | 7 +++++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/net/intel/e1000/base/e1000_defines.h b/drivers/net/intel/e1000/base/e1000_defines.h
> index eb93675823..6c710300a6 100644
> --- a/drivers/net/intel/e1000/base/e1000_defines.h
> +++ b/drivers/net/intel/e1000/base/e1000_defines.h
> @@ -36,6 +36,7 @@
>  
>  /* Extended Device Control */
>  #define E1000_CTRL_EXT_LPCD		0x00000004 /* LCD Power Cycle Done */
> +#define E1000_CTRL_EXT_DPG_EN		0x00000008 /* Dynamic Power Gating Enable */
>  #define E1000_CTRL_EXT_SDP4_DATA	0x00000010 /* SW Definable Pin 4 data */
>  #define E1000_CTRL_EXT_SDP6_DATA	0x00000040 /* SW Definable Pin 6 data */
>  #define E1000_CTRL_EXT_SDP3_DATA	0x00000080 /* SW Definable Pin 3 data */
> diff --git a/drivers/net/intel/e1000/base/e1000_ich8lan.c b/drivers/net/intel/e1000/base/e1000_ich8lan.c
> index 6190052368..96b9ad6a70 100644
> --- a/drivers/net/intel/e1000/base/e1000_ich8lan.c
> +++ b/drivers/net/intel/e1000/base/e1000_ich8lan.c
> @@ -5107,6 +5107,13 @@ STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
>  	reg |= E1000_KABGTXD_BGSQLBIAS;
>  	E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
>  
> +	if (hw->mac.type >= e1000_pch_ptp) {
> +		DEBUGOUT("Clearing DPG EN bit post reset\n");
> +		reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
> +		reg &= ~E1000_CTRL_EXT_DPG_EN;
> +		E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
> +	}
> +
>  	return E1000_SUCCESS;
>  }
>  
> -- 
> 2.43.0
> 

[PATCH 06/10] net/e1000/base: fix coding style issues

[Ciara Loftus]

From: Dima Ruinskiy <dima.ruinskiy@intel.com>

Fix whitespace and tab inconsistencies.

Fixes: a3358d942fa9 ("net/e1000/base: enable new I219 devices")
Fixes: bdca22d62ff0 ("net/e1000/base: add PHY read/write retry mechanism")

Signed-off-by: Dima Ruinskiy <dima.ruinskiy@intel.com>
Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/e1000/base/e1000_ich8lan.c | 6 +++---
 drivers/net/intel/e1000/base/e1000_phy.c     | 5 ++---
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/net/intel/e1000/base/e1000_ich8lan.c b/drivers/net/intel/e1000/base/e1000_ich8lan.c
index 96b9ad6a70..e62847fb4e 100644
--- a/drivers/net/intel/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/intel/e1000/base/e1000_ich8lan.c
@@ -4178,7 +4178,7 @@ STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
 
 		usec_delay(100);
 
-		/* Write the data to the new bank. Offset in words*/
+		/* Write the data to the new bank. Offset in words */
 		act_offset = i + new_bank_offset;
 		ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
 								dword);
@@ -4201,7 +4201,7 @@ STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
 	 */
 	act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
 
-	/*offset in words but we read dword*/
+	/* offset in words but we read dword */
 	--act_offset;
 	ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
 
@@ -4214,7 +4214,7 @@ STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
 	if (ret_val)
 		goto release;
 
-	/* offset in words but we read dword*/
+	/* offset in words but we read dword */
 	act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
 	ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
 
diff --git a/drivers/net/intel/e1000/base/e1000_phy.c b/drivers/net/intel/e1000/base/e1000_phy.c
index b449c6ef42..31ef5089ba 100644
--- a/drivers/net/intel/e1000/base/e1000_phy.c
+++ b/drivers/net/intel/e1000/base/e1000_phy.c
@@ -253,7 +253,7 @@ s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
 	return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
 }
 
-void e1000_disable_phy_retry_mechanism(struct e1000_hw* hw, u32* phy_retries_original)
+void e1000_disable_phy_retry_mechanism(struct e1000_hw *hw, u32 *phy_retries_original)
 {
 	DEBUGFUNC("e1000_disable_phy_retry_mechanism");
 
@@ -262,7 +262,7 @@ void e1000_disable_phy_retry_mechanism(struct e1000_hw* hw, u32* phy_retries_ori
 	hw->phy.current_retry_counter = 0;
 }
 
-void e1000_enable_phy_retry_mechanism(struct e1000_hw* hw, u32 phy_retries_original)
+void e1000_enable_phy_retry_mechanism(struct e1000_hw *hw, u32 phy_retries_original)
 {
 	DEBUGFUNC("e1000_enable_phy_retry_mechanism");
 
@@ -346,7 +346,6 @@ s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
 		}
 	}
 
-
 	return -E1000_ERR_PHY;
 }
 
-- 
2.43.0

[PATCH 07/10] net/e1000/base: fix NVM loop bounds and pointer access

[Ciara Loftus]

From: Menachem Fogel <menachem.fogel@intel.com>

Improve the NVM checksum routines by ensuring loop bounds are compared
at the correct integer width. Use array indexing instead of explicit
pointer arithmetic.

Fixes: af75078fece3 ("first public release")
Cc: stable@dpdk.org

Signed-off-by: Menachem Fogel <menachem.fogel@intel.com>
Signed-off-by: Dima Ruinskiy <dima.ruinskiy@intel.com>
Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/e1000/base/e1000_82575.c  | 4 ++--
 drivers/net/intel/e1000/base/e1000_manage.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/intel/e1000/base/e1000_82575.c b/drivers/net/intel/e1000/base/e1000_82575.c
index c263f42ca1..8ae2b77d5f 100644
--- a/drivers/net/intel/e1000/base/e1000_82575.c
+++ b/drivers/net/intel/e1000/base/e1000_82575.c
@@ -2395,7 +2395,7 @@ s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
 
 	DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
 
-	for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
+	for (i = offset; i < (u16)((NVM_CHECKSUM_REG + offset) + 1); i++) {
 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
 		if (ret_val) {
 			DEBUGOUT("NVM Read Error\n");
@@ -2432,7 +2432,7 @@ s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
 
 	DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
 
-	for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
+	for (i = offset; i < (u16)(NVM_CHECKSUM_REG + offset); i++) {
 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
 		if (ret_val) {
 			DEBUGOUT("NVM Read Error while updating checksum.\n");
diff --git a/drivers/net/intel/e1000/base/e1000_manage.c b/drivers/net/intel/e1000/base/e1000_manage.c
index 4b81028302..71df2890f3 100644
--- a/drivers/net/intel/e1000/base/e1000_manage.c
+++ b/drivers/net/intel/e1000/base/e1000_manage.c
@@ -129,7 +129,7 @@ bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
 	len    = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
 	offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
 	for (i = 0; i < len; i++)
-		*(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
+		buffer[i] = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
 							   offset + i);
 	hdr_csum = hdr->checksum;
 	hdr->checksum = 0;
@@ -173,7 +173,7 @@ s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
 	/* Write the relevant command block into the ram area. */
 	for (i = 0; i < length; i++) {
 		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
-					    *((u32 *) hdr + i));
+						((u32 *)hdr)[i]);
 		E1000_WRITE_FLUSH(hw);
 	}
 
-- 
2.43.0

[PATCH 08/10] net/e1000/base: propagate PHY control register write error

[Ciara Loftus]

From: Dima Ruinskiy <dima.ruinskiy@intel.com>

During HV PHY workaround handling, a failure writing to the PHY control
register was silently discarded rather than returned to the caller. Add
the missing early return so the error is correctly propagated.

Fixes: 5a32a257f957 ("e1000: more NICs in base driver")
Cc: stable@dpdk.org

Signed-off-by: Dima Ruinskiy <dima.ruinskiy@intel.com>
Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/e1000/base/e1000_ich8lan.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/intel/e1000/base/e1000_ich8lan.c b/drivers/net/intel/e1000/base/e1000_ich8lan.c
index e62847fb4e..0290a7dcb4 100644
--- a/drivers/net/intel/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/intel/e1000/base/e1000_ich8lan.c
@@ -2696,6 +2696,8 @@ STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
 			e1000_phy_sw_reset_generic(hw);
 			ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
 							0x3140);
+			if (ret_val)
+				return ret_val;
 		}
 	}
 
-- 
2.43.0

[PATCH 09/10] net/e1000/base: auto-negotiation status for 1000BASE-T

[Ciara Loftus]

From: Mateusz Fryze <mateusz.fryze@intel.com>

Add functionality to find auto-negotiation status on 1000BASE-T PHYs
based on specific PHY registers.

Signed-off-by: Mateusz Fryze <mateusz.fryze@intel.com>
Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 .mailmap                                     |  1 +
 drivers/net/intel/e1000/base/e1000_82575.c   |  1 +
 drivers/net/intel/e1000/base/e1000_api.c     | 16 ++++
 drivers/net/intel/e1000/base/e1000_api.h     |  1 +
 drivers/net/intel/e1000/base/e1000_defines.h | 22 ++++++
 drivers/net/intel/e1000/base/e1000_hw.h      |  9 +++
 drivers/net/intel/e1000/base/e1000_phy.c     | 81 ++++++++++++++++++++
 drivers/net/intel/e1000/base/e1000_phy.h     |  2 +
 8 files changed, 133 insertions(+)

diff --git a/.mailmap b/.mailmap
index f3130df686..4a211b1211 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1033,6 +1033,7 @@ Masoud Hasanifard <masoudhasanifard@gmail.com>
 Masoumeh Farhadi Nia <masoumeh.farhadinia@gmail.com>
 Matan Azrad <matan@nvidia.com> <matan@mellanox.com>
 Matej Vido <matejvido@gmail.com> <vido@cesnet.cz>
+Mateusz Fryze <mateusz.fryze@intel.com>
 Mateusz Kowalski <mateusz.kowalski@intel.com>
 Mateusz Pacuszka <mateuszx.pacuszka@intel.com>
 Mateusz Polchlopek <mateusz.polchlopek@intel.com>
diff --git a/drivers/net/intel/e1000/base/e1000_82575.c b/drivers/net/intel/e1000/base/e1000_82575.c
index 8ae2b77d5f..a2b563975e 100644
--- a/drivers/net/intel/e1000/base/e1000_82575.c
+++ b/drivers/net/intel/e1000/base/e1000_82575.c
@@ -233,6 +233,7 @@ STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 		phy->ops.force_speed_duplex =
 				e1000_phy_force_speed_duplex_82577;
+		phy->ops.get_an_status = e1000_1gbase_t_autoneg_status;
 		break;
 	case I210_I_PHY_ID:
 		phy->type		= e1000_phy_i210;
diff --git a/drivers/net/intel/e1000/base/e1000_api.c b/drivers/net/intel/e1000/base/e1000_api.c
index a7877613e3..83b3d6c439 100644
--- a/drivers/net/intel/e1000/base/e1000_api.c
+++ b/drivers/net/intel/e1000/base/e1000_api.c
@@ -1138,6 +1138,22 @@ s32 e1000_get_phy_info(struct e1000_hw *hw)
 	return E1000_SUCCESS;
 }
 
+/**
+ *  e1000_get_an_status - Finds Auto-negotiation status based on PHY registers
+ *  @hw: pointer to the HW structure
+ *  @an_status: AN status
+ *
+ *  This function gets information from the PHY specific registers to determine
+ *  Auto-negotiation status.
+ **/
+s32 e1000_get_an_status(struct e1000_hw *hw, u8 *an_status)
+{
+	if (hw->phy.ops.get_an_status)
+		return hw->phy.ops.get_an_status(hw, an_status);
+
+	return E1000_SUCCESS;
+}
+
 /**
  *  e1000_phy_hw_reset - Hard PHY reset
  *  @hw: pointer to the HW structure
diff --git a/drivers/net/intel/e1000/base/e1000_api.h b/drivers/net/intel/e1000/base/e1000_api.h
index ca3248c214..1f81f49bd5 100644
--- a/drivers/net/intel/e1000/base/e1000_api.h
+++ b/drivers/net/intel/e1000/base/e1000_api.h
@@ -59,6 +59,7 @@ s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data);
 s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,
 			      u8 data);
 s32 e1000_get_phy_info(struct e1000_hw *hw);
+s32 e1000_get_an_status(struct e1000_hw *hw, u8 *an_status);
 void e1000_release_phy(struct e1000_hw *hw);
 s32 e1000_acquire_phy(struct e1000_hw *hw);
 s32 e1000_cfg_on_link_up(struct e1000_hw *hw);
diff --git a/drivers/net/intel/e1000/base/e1000_defines.h b/drivers/net/intel/e1000/base/e1000_defines.h
index 6c710300a6..ba12dde770 100644
--- a/drivers/net/intel/e1000/base/e1000_defines.h
+++ b/drivers/net/intel/e1000/base/e1000_defines.h
@@ -1103,6 +1103,28 @@
 #define PHY_1000T_STATUS	0x0A /* 1000Base-T Status Reg */
 #define PHY_EXT_STATUS		0x0F /* Extended Status Reg */
 
+/* PHY Status Register */
+#define PHY_STATUS_LINK_STATUS_SHIFT		2
+#define PHY_STATUS_AN_ABILITY_SHIFT			3
+#define PHY_STATUS_REMOTE_FAULT_SHIFT		4
+#define PHY_STATUS_AN_COMPLETE_SHIFT		5
+#define PHY_STATUS_LINK_STATUS_MASK			(0x01 << PHY_STATUS_LINK_STATUS_SHIFT)
+#define PHY_STATUS_AN_ABILITY_MASK			(0x01 << PHY_STATUS_AN_ABILITY_SHIFT)
+#define PHY_STATUS_REMOTE_FAULT_MASK		(0x01 << PHY_STATUS_REMOTE_FAULT_SHIFT)
+#define PHY_STATUS_AN_COMPLETE_MASK			(0x01 << PHY_STATUS_AN_COMPLETE_SHIFT)
+
+/* Auto negotiation Expansion Register */
+#define PHY_AUTONEG_EXP_LP_AN_ABLE_SHIFT			0
+#define PHY_AUTONEG_EXP_PAGE_RECVD_SHIFT			1
+#define PHY_AUTONEG_EXP_NEXT_PAGE_ABLE_SHIFT		2
+#define PHY_AUTONEG_EXP_LP_NEXT_PAGE_ABLE_SHIFT		3
+#define PHY_AUTONEG_EXP_PARALLEL_DETECT_FLT_SHIFT	4
+#define PHY_AUTONEG_EXP_LP_AN_ABLE_MASK			(0x01 << PHY_AUTONEG_EXP_LP_AN_ABLE_SHIFT)
+#define PHY_AUTONEG_EXP_PAGE_RECVD_MASK			(0x01 << PHY_AUTONEG_EXP_PAGE_RECVD_SHIFT)
+#define PHY_AUTONEG_EXP_NEXT_PAGE_ABLE_MASK	(0x01 << PHY_AUTONEG_EXP_NEXT_PAGE_ABLE_SHIFT)
+#define PHY_AUTONEG_EXP_LP_NEXT_PAGE_ABLE_MASK	(0x01 << PHY_AUTONEG_EXP_LP_NEXT_PAGE_ABLE_SHIFT)
+#define PHY_AUTONEG_EXP_PARALLEL_DETECT_FLT_MASK (0x01 << PHY_AUTONEG_EXP_PARALLEL_DETECT_FLT_SHIFT)
+
 /* PHY GPY 211 registers */
 #define STANDARD_AN_REG_MASK	0x0007 /* MMD */
 #define ANEG_MULTIGBT_AN_CTRL	0x0020 /* MULTI GBT AN Control Register */
diff --git a/drivers/net/intel/e1000/base/e1000_hw.h b/drivers/net/intel/e1000/base/e1000_hw.h
index 9b1fafd75c..99c2195916 100644
--- a/drivers/net/intel/e1000/base/e1000_hw.h
+++ b/drivers/net/intel/e1000/base/e1000_hw.h
@@ -409,6 +409,14 @@ enum e1000_serdes_link_state {
 	e1000_serdes_link_forced_up
 };
 
+enum e1000_autoneg_status {
+	e1000_an_off = 0,	/* No conn.; AN unsupported, disabled, or disabled on the LP */
+	e1000_an_failed,	/* Remote Fault or Parallel Detection Fault reported */
+	e1000_an_in_progress,
+	e1000_an_complete,
+	e1000_an_status_unavailable	/* AN status could not be obtained */
+};
+
 enum e1000_invm_structure_type {
 	e1000_invm_uninitialized_structure		= 0x00,
 	e1000_invm_word_autoload_structure		= 0x01,
@@ -803,6 +811,7 @@ struct e1000_phy_operations {
 	s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 	void (*power_up)(struct e1000_hw *);
 	void (*power_down)(struct e1000_hw *);
+	s32  (*get_an_status)(struct e1000_hw *, u8 *);
 	s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 	s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 };
diff --git a/drivers/net/intel/e1000/base/e1000_phy.c b/drivers/net/intel/e1000/base/e1000_phy.c
index 31ef5089ba..c66ae44e7a 100644
--- a/drivers/net/intel/e1000/base/e1000_phy.c
+++ b/drivers/net/intel/e1000/base/e1000_phy.c
@@ -63,6 +63,7 @@ void e1000_init_phy_ops_generic(struct e1000_hw *hw)
 	phy->ops.write_reg_page = e1000_null_write_reg;
 	phy->ops.power_up = e1000_null_phy_generic;
 	phy->ops.power_down = e1000_null_phy_generic;
+	phy->ops.get_an_status = e1000_null_an_status;
 	phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
 	phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
 	phy->ops.cfg_on_link_up = e1000_null_ops_generic;
@@ -133,6 +134,21 @@ s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
 	return E1000_SUCCESS;
 }
 
+/**
+ *  e1000_null_link_info - No-op function, return 0
+ *  @hw: pointer to the HW structure
+ *  @status: dummy variable
+ **/
+s32 e1000_null_an_status(struct e1000_hw E1000_UNUSEDARG *hw,
+			u8 *status)
+{
+	DEBUGFUNC("e1000_null_an_status");
+	UNREFERENCED_1PARAMETER(hw);
+	*status = e1000_an_status_unavailable;
+
+	return E1000_SUCCESS;
+}
+
 /**
  *  e1000_read_i2c_byte_null - No-op function, return 0
  *  @hw: pointer to hardware structure
@@ -2427,6 +2443,71 @@ STATIC s32 e1000_wait_autoneg(struct e1000_hw *hw)
 	return ret_val;
 }
 
+/**
+ *  e1000_1gbase_t_autoneg_status - Gets information on current AN status.
+ *  @hw: pointer to the HW structure
+ *  @an_status: pointer to the AN status
+ *
+ *  The function finds the Auto-negotiation status of 1000BASE-T PHY based on
+ *  the data from PHY Status (PSTATUS) and Auto–Negotiation Expansion (ANE)
+ *  PHY registers.
+ *
+ *  @note The function will report Auto-negotiation OFF when there is no
+ *  media connected to the port. When used during the PHY reset, it might not
+ *  report a valid status.
+ **/
+s32 e1000_1gbase_t_autoneg_status(struct e1000_hw *hw, u8 *an_status)
+{
+	s32 ret_val = E1000_SUCCESS;
+	u16 phy_reg = 0;
+
+	DEBUGFUNC("e1000_1gbase_t_autoneg_status\n");
+
+	do {
+		*an_status = e1000_an_status_unavailable;
+		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_reg);
+		if (ret_val) {
+			DEBUGOUT1("Reading PHY STATUS register returned error: %X\n", ret_val);
+			break;
+		}
+
+		if (!(phy_reg & PHY_STATUS_AN_ABILITY_MASK)) {
+			*an_status = e1000_an_off;
+			break;
+		}
+
+		if (phy_reg & (PHY_STATUS_AN_COMPLETE_MASK | PHY_STATUS_LINK_STATUS_MASK)) {
+			*an_status = e1000_an_complete;
+			break;
+		}
+
+		if (phy_reg & PHY_STATUS_REMOTE_FAULT_MASK) {
+			*an_status = e1000_an_failed;
+			break;
+		}
+
+		ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_reg);
+		if (ret_val) {
+			DEBUGOUT1("Reading PHY ANE register returned error: %X\n", ret_val);
+			break;
+		}
+
+		if (!(phy_reg & PHY_AUTONEG_EXP_LP_AN_ABLE_MASK)) {
+			*an_status = e1000_an_off;
+			break;
+		}
+
+		if (phy_reg & PHY_AUTONEG_EXP_PARALLEL_DETECT_FLT_MASK) {
+			*an_status = e1000_an_failed;
+			break;
+		}
+
+		*an_status = e1000_an_in_progress;
+	} while (0);
+
+	return ret_val;
+}
+
 /**
  *  e1000_phy_has_link_generic - Polls PHY for link
  *  @hw: pointer to the HW structure
diff --git a/drivers/net/intel/e1000/base/e1000_phy.h b/drivers/net/intel/e1000/base/e1000_phy.h
index 4c0b93c18f..d8fcc7ae10 100644
--- a/drivers/net/intel/e1000/base/e1000_phy.h
+++ b/drivers/net/intel/e1000/base/e1000_phy.h
@@ -11,6 +11,7 @@ void e1000_null_phy_generic(struct e1000_hw *hw);
 s32  e1000_null_lplu_state(struct e1000_hw *hw, bool active);
 s32  e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
 s32  e1000_null_set_page(struct e1000_hw *hw, u16 data);
+s32 e1000_null_an_status(struct e1000_hw *hw, u8 *status);
 s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
 			     u8 dev_addr, u8 *data);
 s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
@@ -22,6 +23,7 @@ s32  e1000_check_polarity_ife(struct e1000_hw *hw);
 s32  e1000_check_reset_block_generic(struct e1000_hw *hw);
 s32  e1000_phy_setup_autoneg(struct e1000_hw *hw);
 s32  e1000_copper_link_autoneg(struct e1000_hw *hw);
+s32  e1000_1gbase_t_autoneg_status(struct e1000_hw *hw, u8 *an_status);
 s32  e1000_copper_link_setup_igp(struct e1000_hw *hw);
 s32  e1000_copper_link_setup_m88(struct e1000_hw *hw);
 s32  e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw);
-- 
2.43.0

[PATCH 10/10] net/e1000/base: update version info

[Ciara Loftus]

Update the last shared code update date.

Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
 drivers/net/intel/e1000/base/README | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/intel/e1000/base/README b/drivers/net/intel/e1000/base/README
index 976391b170..f0c1e4af48 100644
--- a/drivers/net/intel/e1000/base/README
+++ b/drivers/net/intel/e1000/base/README
@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2010-2025 Intel Corporation
+ * Copyright(c) 2010-2026 Intel Corporation
  */
 
 This directory contains source code of the base driver code for em/igb/igc,
-with this snapshot generated on 2025-06-04-14.40.
+with this snapshot generated on 2026-05-07-13.50.
 
 This driver is valid for the product(s) listed below
 * Intel® Ethernet Controller 82540
-- 
2.43.0

Re: [PATCH 00/10] e1000 base code update

[Bruce Richardson]

On Wed, May 20, 2026 at 12:52:37PM +0000, Ciara Loftus wrote:
> Update the e1000 base code. The changes are mostly fixes, refactoring,
> and code cleanup.
> 
> Ciara Loftus (1):
>   net/e1000/base: update version info
> 
> Dima Ruinskiy (2):
>   net/e1000/base: fix coding style issues
>   net/e1000/base: propagate PHY control register write error
> 
> Lukasz Czapnik (1):
>   net/e1000/base: fix possible variable overflow
> 
> Mateusz Fryze (1):
>   net/e1000/base: auto-negotiation status for 1000BASE-T
> 
> Menachem Fogel (1):
>   net/e1000/base: fix NVM loop bounds and pointer access
> 
> Vitaly Lifshits (4):
>   net/e1000/base: refactor K1 exit timeout configuration
>   net/e1000/base: fix typo in e1000 base code
>   net/e1000/base: reclassify MAC type
>   net/e1000/base: clear DPG enable bit post MAC reset
> 
Series-acked-by: Bruce Richardson <bruce.richardson@intel.com>

Applied to next-net-intel.
Thanks,
/Bruce