* [PATCH 03/28] eal/tile: define I/O device memory barriers for tile
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Jerin Jacob, Zhigang Lu
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
The patch does not provide any functional change for tile.
I/O barriers are mapped to existing smp barriers.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Zhigang Lu <zlu@ezchip.com>
---
lib/librte_eal/common/include/arch/tile/rte_atomic.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/tile/rte_atomic.h b/lib/librte_eal/common/include/arch/tile/rte_atomic.h
index 28825ff..1f332ee 100644
--- a/lib/librte_eal/common/include/arch/tile/rte_atomic.h
+++ b/lib/librte_eal/common/include/arch/tile/rte_atomic.h
@@ -85,6 +85,12 @@ static inline void rte_rmb(void)
#define rte_smp_rmb() rte_compiler_barrier()
+#define rte_io_mb() rte_mb()
+
+#define rte_io_wmb() rte_compiler_barrier()
+
+#define rte_io_rmb() rte_compiler_barrier()
+
#ifdef __cplusplus
}
#endif
--
2.5.5
^ permalink raw reply related
* [PATCH 04/28] eal/ppc64: define I/O device memory barriers for ppc64
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Jerin Jacob, Chao Zhu
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
The patch does not provide any functional change for ppc_64.
I/O barriers are mapped to existing smp barriers.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Chao Zhu <chaozhu@linux.vnet.ibm.com>
---
lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
index fb4fccb..150810c 100644
--- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
@@ -87,6 +87,12 @@ extern "C" {
#define rte_smp_rmb() rte_rmb()
+#define rte_io_mb() rte_mb()
+
+#define rte_io_wmb() rte_wmb()
+
+#define rte_io_rmb() rte_rmb()
+
/*------------------------- 16 bit atomic operations -------------------------*/
/* To be compatible with Power7, use GCC built-in functions for 16 bit
* operations */
--
2.5.5
^ permalink raw reply related
* [PATCH 05/28] eal/arm: separate smp barrier definition for ARMv7 and ARMv8
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Jerin Jacob
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
Separate the smp barrier definition for arm and arm64 for fine
control on smp barrier definition for each architecture.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
lib/librte_eal/common/include/arch/arm/rte_atomic.h | 6 ------
lib/librte_eal/common/include/arch/arm/rte_atomic_32.h | 6 ++++++
lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 6 ++++++
3 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic.h b/lib/librte_eal/common/include/arch/arm/rte_atomic.h
index 454a12b..f3f3b6e 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic.h
@@ -39,10 +39,4 @@
#include <rte_atomic_32.h>
#endif
-#define rte_smp_mb() rte_mb()
-
-#define rte_smp_wmb() rte_wmb()
-
-#define rte_smp_rmb() rte_rmb()
-
#endif /* _RTE_ATOMIC_ARM_H_ */
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
index 9ae1e78..dd627a0 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
@@ -67,6 +67,12 @@ extern "C" {
*/
#define rte_rmb() __sync_synchronize()
+#define rte_smp_mb() rte_mb()
+
+#define rte_smp_wmb() rte_wmb()
+
+#define rte_smp_rmb() rte_rmb()
+
#ifdef __cplusplus
}
#endif
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index 671caa7..d854aac 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -81,6 +81,12 @@ static inline void rte_rmb(void)
dmb(ishld);
}
+#define rte_smp_mb() rte_mb()
+
+#define rte_smp_wmb() rte_wmb()
+
+#define rte_smp_rmb() rte_rmb()
+
#ifdef __cplusplus
}
#endif
--
2.5.5
^ permalink raw reply related
* [PATCH 02/28] eal/x86: define I/O device memory barriers for IA
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Jerin Jacob
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
The patch does not provide any functional change for IA.
I/O barriers are mapped to existing smp barriers.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Bruce Richardson <bruce.richardson@intel.com>
CC: Konstantin Ananyev <konstantin.ananyev@intel.com>
---
lib/librte_eal/common/include/arch/x86/rte_atomic.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic.h b/lib/librte_eal/common/include/arch/x86/rte_atomic.h
index 00b1cdf..4eac666 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_atomic.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_atomic.h
@@ -61,6 +61,12 @@ extern "C" {
#define rte_smp_rmb() rte_compiler_barrier()
+#define rte_io_mb() rte_mb()
+
+#define rte_io_wmb() rte_compiler_barrier()
+
+#define rte_io_rmb() rte_compiler_barrier()
+
/*------------------------- 16 bit atomic operations -------------------------*/
#ifndef RTE_FORCE_INTRINSICS
--
2.5.5
^ permalink raw reply related
* [PATCH 06/28] eal/armv7: define I/O device memory barriers for ARMv7
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Jerin Jacob
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
The patch does not provide any functional change for ARMv7.
I/O barriers are mapped to existing smp barriers.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Jan Viktorin <viktorin@rehivetech.com>
CC: Jianbo Liu <jianbo.liu@linaro.org>
---
lib/librte_eal/common/include/arch/arm/rte_atomic_32.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
index dd627a0..14c0486 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
@@ -73,6 +73,12 @@ extern "C" {
#define rte_smp_rmb() rte_rmb()
+#define rte_io_mb() rte_mb()
+
+#define rte_io_wmb() rte_wmb()
+
+#define rte_io_rmb() rte_rmb()
+
#ifdef __cplusplus
}
#endif
--
2.5.5
^ permalink raw reply related
* [PATCH 08/28] eal/arm64: define smp barrier definition for arm64
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Jerin Jacob
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
dmb instruction based barrier is used for smp version of memory barrier.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index bc7de64..78ebea2 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -82,11 +82,11 @@ static inline void rte_rmb(void)
dsb(ld);
}
-#define rte_smp_mb() rte_mb()
+#define rte_smp_mb() dmb(ish)
-#define rte_smp_wmb() rte_wmb()
+#define rte_smp_wmb() dmb(ishst)
-#define rte_smp_rmb() rte_rmb()
+#define rte_smp_rmb() dmb(ishld)
#ifdef __cplusplus
}
--
2.5.5
^ permalink raw reply related
* [PATCH 09/28] eal/arm64: define I/O device memory barriers for arm64
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Jerin Jacob
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Jianbo Liu <jianbo.liu@linaro.org>
---
lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index 78ebea2..ef0efc7 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -88,6 +88,12 @@ static inline void rte_rmb(void)
#define rte_smp_rmb() dmb(ishld)
+#define rte_io_mb() rte_mb()
+
+#define rte_io_wmb() rte_wmb()
+
+#define rte_io_rmb() rte_rmb()
+
#ifdef __cplusplus
}
#endif
--
2.5.5
^ permalink raw reply related
* [PATCH 10/28] eal: introduce I/O device memory read/write operations
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Jerin Jacob
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
This commit introduces 8-bit, 16-bit, 32bit, 64bit I/O device
memory read/write operations along with the relaxed versions.
The weakly-ordered machine like ARM needs additional I/O barrier for
device memory read/write access over PCI bus.
By introducing the eal abstraction for I/O device memory read/write access,
The drivers can access I/O device memory in architecture agnostic manner.
The relaxed version does not have additional I/O memory barrier, useful in
accessing the device registers of integrated controllers which
implicitly strongly ordered with respect to memory access.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
doc/api/doxy-api-index.md | 3 +-
lib/librte_eal/common/Makefile | 3 +-
lib/librte_eal/common/include/generic/rte_io.h | 263 +++++++++++++++++++++++++
3 files changed, 267 insertions(+), 2 deletions(-)
create mode 100644 lib/librte_eal/common/include/generic/rte_io.h
diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md
index 02d3a46..0ad3367 100644
--- a/doc/api/doxy-api-index.md
+++ b/doc/api/doxy-api-index.md
@@ -68,7 +68,8 @@ There are many libraries, so their headers may be grouped by topics:
[branch prediction] (@ref rte_branch_prediction.h),
[cache prefetch] (@ref rte_prefetch.h),
[byte order] (@ref rte_byteorder.h),
- [CPU flags] (@ref rte_cpuflags.h)
+ [CPU flags] (@ref rte_cpuflags.h),
+ [I/O access] (@ref rte_io.h)
- **CPU multicore**:
[interrupts] (@ref rte_interrupts.h),
diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile
index a92c984..6498c15 100644
--- a/lib/librte_eal/common/Makefile
+++ b/lib/librte_eal/common/Makefile
@@ -43,7 +43,8 @@ INC += rte_pci_dev_feature_defs.h rte_pci_dev_features.h
INC += rte_malloc.h rte_keepalive.h rte_time.h
GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h
-GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_rwlock.h
+GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_rwlock.h rte_io.h
+
# defined in mk/arch/$(RTE_ARCH)/rte.vars.mk
ARCH_DIR ?= $(RTE_ARCH)
ARCH_INC := $(notdir $(wildcard $(RTE_SDK)/lib/librte_eal/common/include/arch/$(ARCH_DIR)/*.h))
diff --git a/lib/librte_eal/common/include/generic/rte_io.h b/lib/librte_eal/common/include/generic/rte_io.h
new file mode 100644
index 0000000..d7ffbcd
--- /dev/null
+++ b/lib/librte_eal/common/include/generic/rte_io.h
@@ -0,0 +1,263 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016 Cavium networks. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_IO_H_
+#define _RTE_IO_H_
+
+/**
+ * @file
+ * I/O device memory operations
+ *
+ * This file defines the generic API for I/O device memory read/write operations
+ */
+
+#include <stdint.h>
+#include <rte_common.h>
+#include <rte_atomic.h>
+
+#ifdef __DOXYGEN__
+
+/**
+ * Read a 8-bit value from I/O device memory address *addr*.
+ *
+ * The relaxed version does not have additional I/O memory barrier, useful in
+ * accessing the device registers of integrated controllers which implicitly
+ * strongly ordered with respect to memory access.
+ *
+ * @param addr
+ * I/O memory address to read the value from
+ * @return
+ * read value
+ */
+static inline uint8_t
+rte_readb_relaxed(const volatile void *addr);
+
+/**
+ * Read a 16-bit value from I/O device memory address *addr*.
+ *
+ * The relaxed version does not have additional I/O memory barrier, useful in
+ * accessing the device registers of integrated controllers which implicitly
+ * strongly ordered with respect to memory access.
+ *
+ * @param addr
+ * I/O memory address to read the value from
+ * @return
+ * read value
+ */
+static inline uint16_t
+rte_readw_relaxed(const volatile void *addr);
+
+/**
+ * Read a 32-bit value from I/O device memory address *addr*.
+ *
+ * The relaxed version does not have additional I/O memory barrier, useful in
+ * accessing the device registers of integrated controllers which implicitly
+ * strongly ordered with respect to memory access.
+ *
+ * @param addr
+ * I/O memory address to read the value from
+ * @return
+ * read value
+ */
+static inline uint32_t
+rte_readl_relaxed(const volatile void *addr);
+
+/**
+ * Read a 64-bit value from I/O device memory address *addr*.
+ *
+ * The relaxed version does not have additional I/O memory barrier, useful in
+ * accessing the device registers of integrated controllers which implicitly
+ * strongly ordered with respect to memory access.
+ *
+ * @param addr
+ * I/O memory address to read the value from
+ * @return
+ * read value
+ */
+static inline uint64_t
+rte_readq_relaxed(const volatile void *addr);
+
+/**
+ * Write a 8-bit value to I/O device memory address *addr*.
+ *
+ * The relaxed version does not have additional I/O memory barrier, useful in
+ * accessing the device registers of integrated controllers which implicitly
+ * strongly ordered with respect to memory access.
+ *
+ * @param value
+ * Value to write
+ * @param addr
+ * I/O memory address to write the value to
+ */
+
+static inline void
+rte_writeb_relaxed(uint8_t value, volatile void *addr);
+
+/**
+ * Write a 16-bit value to I/O device memory address *addr*.
+ *
+ * The relaxed version does not have additional I/O memory barrier, useful in
+ * accessing the device registers of integrated controllers which implicitly
+ * strongly ordered with respect to memory access.
+ *
+ * @param value
+ * Value to write
+ * @param addr
+ * I/O memory address to write the value to
+ */
+static inline void
+rte_writew_relaxed(uint16_t value, volatile void *addr);
+
+/**
+ * Write a 32-bit value to I/O device memory address *addr*.
+ *
+ * The relaxed version does not have additional I/O memory barrier, useful in
+ * accessing the device registers of integrated controllers which implicitly
+ * strongly ordered with respect to memory access.
+ *
+ * @param value
+ * Value to write
+ * @param addr
+ * I/O memory address to write the value to
+ */
+static inline void
+rte_writel_relaxed(uint32_t value, volatile void *addr);
+
+/**
+ * Write a 64-bit value to I/O device memory address *addr*.
+ *
+ * The relaxed version does not have additional I/O memory barrier, useful in
+ * accessing the device registers of integrated controllers which implicitly
+ * strongly ordered with respect to memory access.
+ *
+ * @param value
+ * Value to write
+ * @param addr
+ * I/O memory address to write the value to
+ */
+static inline void
+rte_writeq_relaxed(uint64_t value, volatile void *addr);
+
+/**
+ * Read a 8-bit value from I/O device memory address *addr*.
+ *
+ * @param addr
+ * I/O memory address to read the value from
+ * @return
+ * read value
+ */
+static inline uint8_t
+rte_readb(const volatile void *addr);
+
+/**
+ * Read a 16-bit value from I/O device memory address *addr*.
+ *
+ *
+ * @param addr
+ * I/O memory address to read the value from
+ * @return
+ * read value
+ */
+static inline uint16_t
+rte_readw(const volatile void *addr);
+
+/**
+ * Read a 32-bit value from I/O device memory address *addr*.
+ *
+ * @param addr
+ * I/O memory address to read the value from
+ * @return
+ * read value
+ */
+static inline uint32_t
+rte_readl(const volatile void *addr);
+
+/**
+ * Read a 64-bit value from I/O device memory address *addr*.
+ *
+ * @param addr
+ * I/O memory address to read the value from
+ * @return
+ * read value
+ */
+static inline uint64_t
+rte_readq(const volatile void *addr);
+
+/**
+ * Write a 8-bit value to I/O device memory address *addr*.
+ *
+ * @param value
+ * Value to write
+ * @param addr
+ * I/O memory address to write the value to
+ */
+
+static inline void
+rte_writeb(uint8_t value, volatile void *addr);
+
+/**
+ * Write a 16-bit value to I/O device memory address *addr*.
+ *
+ * @param value
+ * Value to write
+ * @param addr
+ * I/O memory address to write the value to
+ */
+static inline void
+rte_writew(uint16_t value, volatile void *addr);
+
+/**
+ * Write a 32-bit value to I/O device memory address *addr*.
+ *
+ * @param value
+ * Value to write
+ * @param addr
+ * I/O memory address to write the value to
+ */
+static inline void
+rte_writel(uint32_t value, volatile void *addr);
+
+/**
+ * Write a 64-bit value to I/O device memory address *addr*.
+ *
+ * @param value
+ * Value to write
+ * @param addr
+ * I/O memory address to write the value to
+ */
+static inline void
+rte_writeq(uint64_t value, volatile void *addr);
+
+#endif /* __DOXYGEN__ */
+
+#endif /* _RTE_IO_H_ */
--
2.5.5
^ permalink raw reply related
* [PATCH 11/28] eal: generic implementation for I/O device read/write access
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Jerin Jacob
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
This patch implements the generic version of rte_read[b/w/l/q]_[relaxed]
and rte_write[b/w/l/q]_[relaxed] using rte_io_wmb() and rte_io_rmb()
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
lib/librte_eal/common/include/generic/rte_io.h | 54 ++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/lib/librte_eal/common/include/generic/rte_io.h b/lib/librte_eal/common/include/generic/rte_io.h
index d7ffbcd..f34c131 100644
--- a/lib/librte_eal/common/include/generic/rte_io.h
+++ b/lib/librte_eal/common/include/generic/rte_io.h
@@ -34,6 +34,8 @@
#ifndef _RTE_IO_H_
#define _RTE_IO_H_
+#include <rte_atomic.h>
+
/**
* @file
* I/O device memory operations
@@ -260,4 +262,56 @@ rte_writeq(uint64_t value, volatile void *addr);
#endif /* __DOXYGEN__ */
+#ifndef RTE_OVERRIDE_IO_H
+
+#define rte_readb_relaxed(addr) \
+ ({ uint8_t __v = *(const volatile uint8_t *)addr; __v; })
+
+#define rte_readw_relaxed(addr) \
+ ({ uint16_t __v = *(const volatile uint16_t *)addr; __v; })
+
+#define rte_readl_relaxed(addr) \
+ ({ uint32_t __v = *(const volatile uint32_t *)addr; __v; })
+
+#define rte_readq_relaxed(addr) \
+ ({ uint64_t __v = *(const volatile uint64_t *)addr; __v; })
+
+#define rte_writeb_relaxed(value, addr) \
+ ({ *(volatile uint8_t *)addr = value; })
+
+#define rte_writew_relaxed(value, addr) \
+ ({ *(volatile uint16_t *)addr = value; })
+
+#define rte_writel_relaxed(value, addr) \
+ ({ *(volatile uint32_t *)addr = value; })
+
+#define rte_writeq_relaxed(value, addr) \
+ ({ *(volatile uint64_t *)addr = value; })
+
+#define rte_readb(addr) \
+ ({ uint8_t __v = *(const volatile uint8_t *)addr; rte_io_rmb(); __v; })
+
+#define rte_readw(addr) \
+ ({uint16_t __v = *(const volatile uint16_t *)addr; rte_io_rmb(); __v; })
+
+#define rte_readl(addr) \
+ ({uint32_t __v = *(const volatile uint32_t *)addr; rte_io_rmb(); __v; })
+
+#define rte_readq(addr) \
+ ({uint64_t __v = *(const volatile uint64_t *)addr; rte_io_rmb(); __v; })
+
+#define rte_writeb(value, addr) \
+ ({ rte_io_wmb(); *(volatile uint8_t *)addr = value; })
+
+#define rte_writew(value, addr) \
+ ({ rte_io_wmb(); *(volatile uint16_t *)addr = value; })
+
+#define rte_writel(value, addr) \
+ ({ rte_io_wmb(); *(volatile uint32_t *)addr = value; })
+
+#define rte_writeq(value, addr) \
+ ({ rte_io_wmb(); *(volatile uint64_t *)addr = value; })
+
+#endif /* RTE_OVERRIDE_IO_H */
+
#endif /* _RTE_IO_H_ */
--
2.5.5
^ permalink raw reply related
* [PATCH 13/28] eal/arm64: override I/O device read/write access for arm64
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Jerin Jacob
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
Override the generic I/O device memory read/write access and implement it
using armv8 instructions for arm64.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
lib/librte_eal/common/include/arch/arm/rte_io.h | 4 +
lib/librte_eal/common/include/arch/arm/rte_io_64.h | 183 +++++++++++++++++++++
2 files changed, 187 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_io_64.h
diff --git a/lib/librte_eal/common/include/arch/arm/rte_io.h b/lib/librte_eal/common/include/arch/arm/rte_io.h
index 74c1f2c..9593b42 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_io.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_io.h
@@ -38,7 +38,11 @@
extern "C" {
#endif
+#ifdef RTE_ARCH_64
+#include "rte_io_64.h"
+#else
#include "generic/rte_io.h"
+#endif
#ifdef __cplusplus
}
diff --git a/lib/librte_eal/common/include/arch/arm/rte_io_64.h b/lib/librte_eal/common/include/arch/arm/rte_io_64.h
new file mode 100644
index 0000000..09e7a89
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_io_64.h
@@ -0,0 +1,183 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2016.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_IO_ARM64_H_
+#define _RTE_IO_ARM64_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define RTE_OVERRIDE_IO_H
+
+#include "generic/rte_io.h"
+#include "rte_atomic_64.h"
+
+static inline __attribute__((always_inline)) uint8_t
+__rte_arm64_readb(const volatile void *addr)
+{
+ uint8_t val;
+
+ asm volatile(
+ "ldrb %w[val], [%x[addr]]"
+ : [val] "=r" (val)
+ : [addr] "r" (addr));
+ return val;
+}
+
+static inline __attribute__((always_inline)) uint16_t
+__rte_arm64_readw(const volatile void *addr)
+{
+ uint16_t val;
+
+ asm volatile(
+ "ldrh %w[val], [%x[addr]]"
+ : [val] "=r" (val)
+ : [addr] "r" (addr));
+ return val;
+}
+
+static inline __attribute__((always_inline)) uint32_t
+__rte_arm64_readl(const volatile void *addr)
+{
+ uint32_t val;
+
+ asm volatile(
+ "ldr %w[val], [%x[addr]]"
+ : [val] "=r" (val)
+ : [addr] "r" (addr));
+ return val;
+}
+
+static inline __attribute__((always_inline)) uint64_t
+__rte_arm64_readq(const volatile void *addr)
+{
+ uint64_t val;
+
+ asm volatile(
+ "ldr %x[val], [%x[addr]]"
+ : [val] "=r" (val)
+ : [addr] "r" (addr));
+ return val;
+}
+
+static inline __attribute__((always_inline)) void
+__rte_arm64_writeb(uint8_t val, volatile void *addr)
+{
+ asm volatile(
+ "strb %w[val], [%x[addr]]"
+ :
+ : [val] "r" (val), [addr] "r" (addr));
+}
+
+static inline __attribute__((always_inline)) void
+__rte_arm64_writew(uint16_t val, volatile void *addr)
+{
+ asm volatile(
+ "strh %w[val], [%x[addr]]"
+ :
+ : [val] "r" (val), [addr] "r" (addr));
+}
+
+static inline __attribute__((always_inline)) void
+__rte_arm64_writel(uint32_t val, volatile void *addr)
+{
+ asm volatile(
+ "str %w[val], [%x[addr]]"
+ :
+ : [val] "r" (val), [addr] "r" (addr));
+}
+
+static inline __attribute__((always_inline)) void
+__rte_arm64_writeq(uint64_t val, volatile void *addr)
+{
+ asm volatile(
+ "str %x[val], [%x[addr]]"
+ :
+ : [val] "r" (val), [addr] "r" (addr));
+}
+
+#define rte_readb_relaxed(addr) \
+ ({ uint8_t __v = __rte_arm64_readb(addr); __v; })
+
+#define rte_readw_relaxed(addr) \
+ ({ uint16_t __v = __rte_arm64_readw(addr); __v; })
+
+#define rte_readl_relaxed(addr) \
+ ({ uint32_t __v = __rte_arm64_readl(addr); __v; })
+
+#define rte_readq_relaxed(addr) \
+ ({ uint64_t __v = __rte_arm64_readq(addr); __v; })
+
+#define rte_writeb_relaxed(value, addr) \
+ ({ __rte_arm64_writeb(value, addr); })
+
+#define rte_writew_relaxed(value, addr) \
+ ({ __rte_arm64_writew(value, addr); })
+
+#define rte_writel_relaxed(value, addr) \
+ ({ __rte_arm64_writel(value, addr); })
+
+#define rte_writeq_relaxed(value, addr) \
+ ({ __rte_arm64_writeq(value, addr); })
+
+#define rte_readb(addr) \
+ ({ uint8_t __v = __rte_arm64_readb(addr); rte_io_rmb(); __v; })
+
+#define rte_readw(addr) \
+ ({ uint16_t __v = __rte_arm64_readw(addr); rte_io_rmb(); __v; })
+
+#define rte_readl(addr) \
+ ({ uint32_t __v = __rte_arm64_readl(addr); rte_io_rmb(); __v; })
+
+#define rte_readq(addr) \
+ ({ uint64_t __v = __rte_arm64_readq(addr); rte_io_rmb(); __v; })
+
+#define rte_writeb(value, addr) \
+ ({ rte_io_wmb(); rte_writeb_relaxed(value, addr); })
+
+#define rte_writew(value, addr) \
+ ({ rte_io_wmb(); rte_writew_relaxed(value, addr); })
+
+#define rte_writel(value, addr) \
+ ({ rte_io_wmb(); rte_writel_relaxed(value, addr); })
+
+#define rte_writeq(value, addr) \
+ ({ rte_io_wmb(); rte_writeq_relaxed(value, addr); })
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_IO_ARM64_H_ */
--
2.5.5
^ permalink raw reply related
* [PATCH 12/28] eal: let all architectures use generic I/O implementation
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Jerin Jacob
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
lib/librte_eal/common/include/arch/arm/rte_io.h | 47 ++++++++++++++++++++++
lib/librte_eal/common/include/arch/ppc_64/rte_io.h | 47 ++++++++++++++++++++++
lib/librte_eal/common/include/arch/tile/rte_io.h | 47 ++++++++++++++++++++++
lib/librte_eal/common/include/arch/x86/rte_io.h | 47 ++++++++++++++++++++++
4 files changed, 188 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_io.h
create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_io.h
create mode 100644 lib/librte_eal/common/include/arch/tile/rte_io.h
create mode 100644 lib/librte_eal/common/include/arch/x86/rte_io.h
diff --git a/lib/librte_eal/common/include/arch/arm/rte_io.h b/lib/librte_eal/common/include/arch/arm/rte_io.h
new file mode 100644
index 0000000..74c1f2c
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_io.h
@@ -0,0 +1,47 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016 Cavium networks. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_IO_ARM_H_
+#define _RTE_IO_ARM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_io.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_IO_ARM_H_ */
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_io.h b/lib/librte_eal/common/include/arch/ppc_64/rte_io.h
new file mode 100644
index 0000000..be192da
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_io.h
@@ -0,0 +1,47 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016 Cavium networks. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_IO_PPC_64_H_
+#define _RTE_IO_PPC_64_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_io.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_IO_PPC_64_H_ */
diff --git a/lib/librte_eal/common/include/arch/tile/rte_io.h b/lib/librte_eal/common/include/arch/tile/rte_io.h
new file mode 100644
index 0000000..9c8588f
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/tile/rte_io.h
@@ -0,0 +1,47 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016 Cavium networks. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_IO_TILE_H_
+#define _RTE_IO_TILE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_io.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_IO_TILE_H_ */
diff --git a/lib/librte_eal/common/include/arch/x86/rte_io.h b/lib/librte_eal/common/include/arch/x86/rte_io.h
new file mode 100644
index 0000000..c8d1404
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/x86/rte_io.h
@@ -0,0 +1,47 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016 Cavium networks. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_IO_X86_H_
+#define _RTE_IO_X86_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_io.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_IO_X86_H_ */
--
2.5.5
^ permalink raw reply related
* [PATCH 14/28] crypto/qat: use eal I/O device memory read/write API
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Santosh Shukla, Jerin Jacob, John Griffin, Fiona Trahe,
Deepak Kumar Jain
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix portability
issues across different architectures.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: John Griffin <john.griffin@intel.com>
CC: Fiona Trahe <fiona.trahe@intel.com>
CC: Deepak Kumar Jain <deepak.k.jain@intel.com>
---
drivers/crypto/qat/qat_adf/adf_transport_access_macros.h | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h b/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h
index 47f1c91..a6e407d 100644
--- a/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h
+++ b/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h
@@ -47,14 +47,19 @@
#ifndef ADF_TRANSPORT_ACCESS_MACROS_H
#define ADF_TRANSPORT_ACCESS_MACROS_H
+#include <rte_io.h>
+
/* CSR write macro */
-#define ADF_CSR_WR(csrAddr, csrOffset, val) \
- (void)((*((volatile uint32_t *)(((uint8_t *)csrAddr) + csrOffset)) \
- = (val)))
+#define ADF_CSR_WR(csrAddr, csrOffset, val) ({ \
+ rte_writel(val, (((uint8_t *)csrAddr) + csrOffset)); \
+})
/* CSR read macro */
-#define ADF_CSR_RD(csrAddr, csrOffset) \
- (*((volatile uint32_t *)(((uint8_t *)csrAddr) + csrOffset)))
+#define ADF_CSR_RD(csrAddr, csrOffset) ({ \
+ uint32_t __val; \
+ __val = rte_readl(((uint8_t *)csrAddr) + csrOffset); \
+ __val; \
+})
#define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
#define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
--
2.5.5
^ permalink raw reply related
* [PATCH 15/28] net/bnx2x: use eal I/O device memory read/write API
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Santosh Shukla, Jerin Jacob, Harish Patil, Rasesh Mody
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Replace the raw I/O device memory read/write access with eal abstraction
for I/O device memory read/write access to fix portability issues across
different architectures.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Harish Patil <harish.patil@cavium.com>
CC: Rasesh Mody <rasesh.mody@cavium.com>
---
drivers/net/bnx2x/bnx2x.h | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 5cefea4..9b6e49a 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -40,6 +40,7 @@
#include "bnx2x_vfpf.h"
#include "elink.h"
+#include <rte_io.h>
#ifndef __FreeBSD__
#include <linux/pci_regs.h>
@@ -1419,8 +1420,7 @@ bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)
{
PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x",
(unsigned long)offset, val);
- *((volatile uint8_t*)
- ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
+ rte_writeb(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
}
static inline void
@@ -1433,8 +1433,8 @@ bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val)
#endif
PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%04x",
(unsigned long)offset, val);
- *((volatile uint16_t*)
- ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
+ rte_writew(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
+
}
static inline void
@@ -1448,8 +1448,7 @@ bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val)
PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
(unsigned long)offset, val);
- *((volatile uint32_t*)
- ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
+ rte_writel(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
}
static inline uint8_t
@@ -1457,8 +1456,7 @@ bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset)
{
uint8_t val;
- val = (uint8_t)(*((volatile uint8_t*)
- ((uintptr_t)sc->bar[BAR0].base_addr + offset)));
+ val = rte_readb((uint8_t *)sc->bar[BAR0].base_addr + offset);
PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x",
(unsigned long)offset, val);
@@ -1476,8 +1474,7 @@ bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset)
(unsigned long)offset);
#endif
- val = (uint16_t)(*((volatile uint16_t*)
- ((uintptr_t)sc->bar[BAR0].base_addr + offset)));
+ val = rte_readw(((uint8_t *)sc->bar[BAR0].base_addr + offset));
PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
(unsigned long)offset, val);
@@ -1495,8 +1492,7 @@ bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
(unsigned long)offset);
#endif
- val = (uint32_t)(*((volatile uint32_t*)
- ((uintptr_t)sc->bar[BAR0].base_addr + offset)));
+ val = rte_readl(((uint8_t *)sc->bar[BAR0].base_addr + offset));
PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x",
(unsigned long)offset, val);
@@ -1560,11 +1556,15 @@ bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
#define DPM_TRIGGER_TYPE 0x40
/* Doorbell macro */
-#define BNX2X_DB_WRITE(db_bar, val) \
- *((volatile uint32_t *)(db_bar)) = (val)
+#define BNX2X_DB_WRITE(db_bar, val) ({ \
+ rte_writel(val, db_bar); \
+})
-#define BNX2X_DB_READ(db_bar) \
- *((volatile uint32_t *)(db_bar))
+#define BNX2X_DB_READ(db_bar) ({ \
+ uint32_t __val; \
+ __val = rte_readl(db_bar); \
+ __val; \
+})
#define DOORBELL_ADDR(sc, offset) \
(volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset)))
--
2.5.5
^ permalink raw reply related
* [PATCH 16/28] net/bnxt: use eal I/O device memory read/write API
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Santosh Shukla, Jerin Jacob, Stephen Hurd,
Ajit Khaparde
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Replace the raw I/O device memory read/write access with eal abstraction
for I/O device memory read/write access to fix portability issues across
different architectures.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Stephen Hurd <stephen.hurd@broadcom.com>
CC: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_hwrm.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 07e7124..2067e15 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -50,6 +50,8 @@
#include "bnxt_vnic.h"
#include "hsi_struct_def_dpdk.h"
+#include <rte_io.h>
+
#define HWRM_CMD_TIMEOUT 2000
/*
@@ -72,19 +74,19 @@ static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
/* Write request msg to hwrm channel */
for (i = 0; i < msg_len; i += 4) {
bar = (uint8_t *)bp->bar0 + i;
- *(volatile uint32_t *)bar = *data;
+ rte_writel(*data, bar);
data++;
}
/* Zero the rest of the request space */
for (; i < bp->max_req_len; i += 4) {
bar = (uint8_t *)bp->bar0 + i;
- *(volatile uint32_t *)bar = 0;
+ rte_writel(0, bar);
}
/* Ring channel doorbell */
bar = (uint8_t *)bp->bar0 + 0x100;
- *(volatile uint32_t *)bar = 1;
+ rte_writel(1, bar);
/* Poll for the valid bit */
for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
--
2.5.5
^ permalink raw reply related
* [PATCH 17/28] net/cxgbe: use eal I/O device memory read/write API
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Santosh Shukla, Jerin Jacob, Rahul Lakkireddy
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
---
drivers/net/cxgbe/base/adapter.h | 13 +++++++++----
drivers/net/cxgbe/cxgbe_compat.h | 3 ++-
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h
index 5e3bd50..0ae4513 100644
--- a/drivers/net/cxgbe/base/adapter.h
+++ b/drivers/net/cxgbe/base/adapter.h
@@ -40,6 +40,7 @@
#include "cxgbe_compat.h"
#include "t4_regs_values.h"
+#include "rte_io.h"
enum {
MAX_ETH_QSETS = 64, /* # of Ethernet Tx/Rx queue sets */
@@ -324,7 +325,11 @@ struct adapter {
int use_unpacked_mode; /* unpacked rx mode state */
};
-#define CXGBE_PCI_REG(reg) (*((volatile uint32_t *)(reg)))
+#define CXGBE_PCI_REG(reg) ({ \
+ uint32_t __val; \
+ __val = rte_readl(reg); \
+ __val; \
+})
static inline uint64_t cxgbe_read_addr64(volatile void *addr)
{
@@ -351,15 +356,15 @@ static inline uint32_t cxgbe_read_addr(volatile void *addr)
cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
#define CXGBE_PCI_REG_WRITE(reg, value) ({ \
- CXGBE_PCI_REG((reg)) = (value); })
+ rte_writel(value, reg); })
#define CXGBE_WRITE_REG(adap, reg, value) \
CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)
{
- CXGBE_PCI_REG(addr) = val;
- CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4)) = (val >> 32);
+ CXGBE_PCI_REG_WRITE(addr, val);
+ CXGBE_PCI_REG_WRITE(((volatile uint8_t *)(addr) + 4), (val >> 32));
return val;
}
diff --git a/drivers/net/cxgbe/cxgbe_compat.h b/drivers/net/cxgbe/cxgbe_compat.h
index e68f8f5..95d8f27 100644
--- a/drivers/net/cxgbe/cxgbe_compat.h
+++ b/drivers/net/cxgbe/cxgbe_compat.h
@@ -45,6 +45,7 @@
#include <rte_cycles.h>
#include <rte_spinlock.h>
#include <rte_log.h>
+#include <rte_io.h>
#define dev_printf(level, fmt, args...) \
RTE_LOG(level, PMD, "rte_cxgbe_pmd: " fmt, ## args)
@@ -254,7 +255,7 @@ static inline unsigned long ilog2(unsigned long n)
static inline void writel(unsigned int val, volatile void __iomem *addr)
{
- *(volatile unsigned int *)addr = val;
+ rte_writel(val, addr);
}
static inline void writeq(u64 val, volatile void __iomem *addr)
--
2.5.5
^ permalink raw reply related
* [PATCH 18/28] net/e1000: use eal I/O device memory read/write API
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Santosh Shukla, Jerin Jacob, Wenzhuo Lu
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Wenzhuo Lu <wenzhuo.lu@intel.com>
---
drivers/net/e1000/base/e1000_osdep.h | 25 +++++++++++++++++--------
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/net/e1000/base/e1000_osdep.h b/drivers/net/e1000/base/e1000_osdep.h
index 47a1948..dd9a2d8 100644
--- a/drivers/net/e1000/base/e1000_osdep.h
+++ b/drivers/net/e1000/base/e1000_osdep.h
@@ -44,6 +44,7 @@
#include <rte_log.h>
#include <rte_debug.h>
#include <rte_byteorder.h>
+#include <rte_io.h>
#include "../e1000_logs.h"
@@ -94,17 +95,25 @@ typedef int bool;
#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
-#define E1000_PCI_REG(reg) (*((volatile uint32_t *)(reg)))
+#define E1000_PCI_REG(reg) ({ \
+ uint32_t __val; \
+ __val = rte_readl(reg); \
+ __val; \
+})
-#define E1000_PCI_REG16(reg) (*((volatile uint16_t *)(reg)))
+#define E1000_PCI_REG16(reg) ({ \
+ uint16_t __val; \
+ __val = rte_readw(reg); \
+ __val; \
+})
-#define E1000_PCI_REG_WRITE(reg, value) do { \
- E1000_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \
-} while (0)
+#define E1000_PCI_REG_WRITE(reg, value) ({ \
+ rte_writel(rte_cpu_to_le_32(value), reg); \
+})
-#define E1000_PCI_REG_WRITE16(reg, value) do { \
- E1000_PCI_REG16((reg)) = (rte_cpu_to_le_16(value)); \
-} while (0)
+#define E1000_PCI_REG_WRITE16(reg, value) ({ \
+ rte_writew(rte_cpu_to_le_16(value), reg); \
+})
#define E1000_PCI_REG_ADDR(hw, reg) \
((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
--
2.5.5
^ permalink raw reply related
* [PATCH 19/28] net/ena: use eal I/O device memory read/write API
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Santosh Shukla, Jerin Jacob, Jan Medala, Jakub Palider
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Jan Medala <jan@semihalf.com>
CC: Jakub Palider <jpa@semihalf.com>
---
drivers/net/ena/base/ena_plat_dpdk.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h
index 87c3bf1..4db07c7 100644
--- a/drivers/net/ena/base/ena_plat_dpdk.h
+++ b/drivers/net/ena/base/ena_plat_dpdk.h
@@ -50,6 +50,7 @@
#include <rte_spinlock.h>
#include <sys/time.h>
+#include <rte_io.h>
typedef uint64_t u64;
typedef uint32_t u32;
@@ -226,12 +227,12 @@ typedef uint64_t dma_addr_t;
static inline void writel(u32 value, volatile void *addr)
{
- *(volatile u32 *)addr = value;
+ rte_writel(value, addr);
}
static inline u32 readl(const volatile void *addr)
{
- return *(const volatile u32 *)addr;
+ return rte_readl(addr);
}
#define ENA_REG_WRITE32(value, reg) writel((value), (reg))
--
2.5.5
^ permalink raw reply related
* [PATCH 20/28] net/enic: use eal I/O device memory read/write API
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Santosh Shukla, Jerin Jacob, John Daley, Nelson Escobar
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix portability
issues across different architectures.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: John Daley <johndale@cisco.com>
CC: Nelson Escobar <neescoba@cisco.com>
---
drivers/net/enic/enic_compat.h | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/net/enic/enic_compat.h b/drivers/net/enic/enic_compat.h
index 5dbd983..1c9cdc6 100644
--- a/drivers/net/enic/enic_compat.h
+++ b/drivers/net/enic/enic_compat.h
@@ -41,6 +41,7 @@
#include <rte_atomic.h>
#include <rte_malloc.h>
#include <rte_log.h>
+#include <rte_io.h>
#define ENIC_PAGE_ALIGN 4096UL
#define ENIC_ALIGN ENIC_PAGE_ALIGN
@@ -95,42 +96,42 @@ typedef unsigned long long dma_addr_t;
static inline uint32_t ioread32(volatile void *addr)
{
- return *(volatile uint32_t *)addr;
+ return rte_readl(addr);
}
static inline uint16_t ioread16(volatile void *addr)
{
- return *(volatile uint16_t *)addr;
+ return rte_readw(addr);
}
static inline uint8_t ioread8(volatile void *addr)
{
- return *(volatile uint8_t *)addr;
+ return rte_readb(addr);
}
static inline void iowrite32(uint32_t val, volatile void *addr)
{
- *(volatile uint32_t *)addr = val;
+ rte_writel(val, addr);
}
static inline void iowrite16(uint16_t val, volatile void *addr)
{
- *(volatile uint16_t *)addr = val;
+ rte_writew(val, addr);
}
static inline void iowrite8(uint8_t val, volatile void *addr)
{
- *(volatile uint8_t *)addr = val;
+ rte_writeb(val, addr);
}
static inline unsigned int readl(volatile void __iomem *addr)
{
- return *(volatile unsigned int *)addr;
+ return rte_readl(addr);
}
static inline void writel(unsigned int val, volatile void __iomem *addr)
{
- *(volatile unsigned int *)addr = val;
+ rte_writel(val, addr);
}
#define min_t(type, x, y) ({ \
--
2.5.5
^ permalink raw reply related
* [PATCH 21/28] net/fm10k: use eal I/O device memory read/write API
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Santosh Shukla, Jerin Jacob, Jing Chen
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Jing Chen <jing.d.chen@intel.com>
---
drivers/net/fm10k/base/fm10k_osdep.h | 27 +++++++++++++++++++--------
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/net/fm10k/base/fm10k_osdep.h b/drivers/net/fm10k/base/fm10k_osdep.h
index a21daa2..d91ff41 100644
--- a/drivers/net/fm10k/base/fm10k_osdep.h
+++ b/drivers/net/fm10k/base/fm10k_osdep.h
@@ -39,6 +39,7 @@ POSSIBILITY OF SUCH DAMAGE.
#include <rte_atomic.h>
#include <rte_byteorder.h>
#include <rte_cycles.h>
+#include <rte_io.h>
#include "../fm10k_logs.h"
/* TODO: this does not look like it should be used... */
@@ -88,17 +89,27 @@ typedef int bool;
#endif
/* offsets are WORD offsets, not BYTE offsets */
-#define FM10K_WRITE_REG(hw, reg, val) \
- ((((volatile uint32_t *)(hw)->hw_addr)[(reg)]) = ((uint32_t)(val)))
-#define FM10K_READ_REG(hw, reg) \
- (((volatile uint32_t *)(hw)->hw_addr)[(reg)])
+#define FM10K_WRITE_REG(hw, reg, val) ({ \
+ rte_writel(val, ((hw)->hw_addr + (reg))); \
+})
+
+#define FM10K_READ_REG(hw, reg) ({ \
+ uint32_t __val; \
+ __val = rte_readl((hw)->hw_addr + (reg)); \
+ __val; \
+})
+
#define FM10K_WRITE_FLUSH(a) FM10K_READ_REG(a, FM10K_CTRL)
-#define FM10K_PCI_REG(reg) (*((volatile uint32_t *)(reg)))
+#define FM10K_PCI_REG(reg) ({ \
+ uint32_t __val; \
+ __val = rte_readl(reg); \
+ __val; \
+})
-#define FM10K_PCI_REG_WRITE(reg, value) do { \
- FM10K_PCI_REG((reg)) = (value); \
-} while (0)
+#define FM10K_PCI_REG_WRITE(reg, value) ({ \
+ rte_writel(value, reg); \
+})
/* not implemented */
#define FM10K_READ_PCI_WORD(hw, reg) 0
--
2.5.5
^ permalink raw reply related
* [PATCH 22/28] net/i40e: use eal I/O device memory read/write API
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Santosh Shukla, Satha Rao, Jerin Jacob, Helin Zhang,
Jingjing Wu
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Replace the raw I/O device memory read/write access with eal abstraction
for I/O device memory read/write access to fix portability issues across
different architectures.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Satha Rao <skoteshwar@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Helin Zhang <helin.zhang@intel.com>
CC: Jingjing Wu <jingjing.wu@intel.com>
---
drivers/net/i40e/base/i40e_osdep.h | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_osdep.h b/drivers/net/i40e/base/i40e_osdep.h
index 38e7ba5..8d5045a 100644
--- a/drivers/net/i40e/base/i40e_osdep.h
+++ b/drivers/net/i40e/base/i40e_osdep.h
@@ -44,6 +44,7 @@
#include <rte_cycles.h>
#include <rte_spinlock.h>
#include <rte_log.h>
+#include <rte_io.h>
#include "../i40e_logs.h"
@@ -153,15 +154,22 @@ do { \
* I40E_PRTQF_FD_MSK
*/
-#define I40E_PCI_REG(reg) (*((volatile uint32_t *)(reg)))
+#define I40E_PCI_REG(reg) ({ \
+ uint32_t __val; \
+ __val = rte_readl(reg); \
+ __val; \
+})
+
#define I40E_PCI_REG_ADDR(a, reg) \
((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))
static inline uint32_t i40e_read_addr(volatile void *addr)
{
return rte_le_to_cpu_32(I40E_PCI_REG(addr));
}
-#define I40E_PCI_REG_WRITE(reg, value) \
- do { I40E_PCI_REG((reg)) = rte_cpu_to_le_32(value); } while (0)
+
+#define I40E_PCI_REG_WRITE(reg, value) ({ \
+ rte_writel(rte_cpu_to_le_32(value), reg); \
+})
#define I40E_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_GLGEN_STAT)
#define I40EVF_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_VFGEN_RSTAT)
--
2.5.5
^ permalink raw reply related
* [PATCH 23/28] net/ixgbe: use eal I/O device memory read/write API
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Santosh Shukla, Jerin Jacob, Helin Zhang
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Helin Zhang <helin.zhang@intel.com>
CC: Konstantin Ananyev <konstantin.ananyev@intel.com>
---
drivers/net/ixgbe/base/ixgbe_osdep.h | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ixgbe/base/ixgbe_osdep.h b/drivers/net/ixgbe/base/ixgbe_osdep.h
index 77f0af5..9d16c21 100644
--- a/drivers/net/ixgbe/base/ixgbe_osdep.h
+++ b/drivers/net/ixgbe/base/ixgbe_osdep.h
@@ -44,6 +44,7 @@
#include <rte_cycles.h>
#include <rte_log.h>
#include <rte_byteorder.h>
+#include <rte_io.h>
#include "../ixgbe_logs.h"
#include "../ixgbe_bypass_defines.h"
@@ -121,16 +122,20 @@ typedef int bool;
#define prefetch(x) rte_prefetch0(x)
-#define IXGBE_PCI_REG(reg) (*((volatile uint32_t *)(reg)))
+#define IXGBE_PCI_REG(reg) ({ \
+ uint32_t __val; \
+ __val = rte_readl(reg); \
+ __val; \
+})
static inline uint32_t ixgbe_read_addr(volatile void* addr)
{
return rte_le_to_cpu_32(IXGBE_PCI_REG(addr));
}
-#define IXGBE_PCI_REG_WRITE(reg, value) do { \
- IXGBE_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \
-} while(0)
+#define IXGBE_PCI_REG_WRITE(reg, value) ({ \
+ rte_writel(rte_cpu_to_le_32(value), reg); \
+})
#define IXGBE_PCI_REG_ADDR(hw, reg) \
((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
--
2.5.5
^ permalink raw reply related
* [PATCH 24/28] net/nfp: use eal I/O device memory read/write API
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Santosh Shukla, Jerin Jacob, Alejandro Lucero
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Alejandro Lucero <alejandro.lucero@netronome.com>
---
drivers/net/nfp/nfp_net_pmd.h | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/net/nfp/nfp_net_pmd.h b/drivers/net/nfp/nfp_net_pmd.h
index c180972..ec3d35e 100644
--- a/drivers/net/nfp/nfp_net_pmd.h
+++ b/drivers/net/nfp/nfp_net_pmd.h
@@ -121,25 +121,26 @@ struct nfp_net_adapter;
#define NFD_CFG_MINOR_VERSION_of(x) (((x) >> 0) & 0xff)
#include <linux/types.h>
+#include <rte_io.h>
static inline uint8_t nn_readb(volatile const void *addr)
{
- return *((volatile const uint8_t *)(addr));
+ return rte_readb(addr);
}
static inline void nn_writeb(uint8_t val, volatile void *addr)
{
- *((volatile uint8_t *)(addr)) = val;
+ rte_writeb(val, addr);
}
static inline uint32_t nn_readl(volatile const void *addr)
{
- return *((volatile const uint32_t *)(addr));
+ return rte_readl(addr);
}
static inline void nn_writel(uint32_t val, volatile void *addr)
{
- *((volatile uint32_t *)(addr)) = val;
+ rte_writel(val, addr);
}
static inline uint64_t nn_readq(volatile void *addr)
--
2.5.5
^ permalink raw reply related
* [PATCH 25/28] net/qede: use eal I/O device memory read/write API
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Santosh Shukla, Jerin Jacob, Harish Patil, Rasesh Mody
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Harish Patil <harish.patil@cavium.com>
CC: Rasesh Mody <rasesh.mody@cavium.com>
---
drivers/net/qede/base/bcm_osal.h | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h
index 0b446f2..925660e 100644
--- a/drivers/net/qede/base/bcm_osal.h
+++ b/drivers/net/qede/base/bcm_osal.h
@@ -18,6 +18,7 @@
#include <rte_cycles.h>
#include <rte_debug.h>
#include <rte_ether.h>
+#include <rte_io.h>
/* Forward declaration */
struct ecore_dev;
@@ -113,18 +114,23 @@ void *osal_dma_alloc_coherent_aligned(struct ecore_dev *, dma_addr_t *,
/* HW reads/writes */
-#define DIRECT_REG_RD(_dev, _reg_addr) \
- (*((volatile u32 *) (_reg_addr)))
+#define DIRECT_REG_RD(_dev, _reg_addr) ({ \
+ uint32_t __val; \
+ __val = rte_readl((_reg_addr)); \
+ __val; \
+})
#define REG_RD(_p_hwfn, _reg_offset) \
DIRECT_REG_RD(_p_hwfn, \
((u8 *)(uintptr_t)(_p_hwfn->regview) + (_reg_offset)))
-#define DIRECT_REG_WR16(_reg_addr, _val) \
- (*((volatile u16 *)(_reg_addr)) = _val)
+#define DIRECT_REG_WR16(_reg_addr, _val) ({ \
+ rte_writew((_val), (_reg_addr)); \
+})
-#define DIRECT_REG_WR(_dev, _reg_addr, _val) \
- (*((volatile u32 *)(_reg_addr)) = _val)
+#define DIRECT_REG_WR(_dev, _reg_addr, _val) ({ \
+ rte_writel((_val), (_reg_addr)); \
+})
#define REG_WR(_p_hwfn, _reg_offset, _val) \
DIRECT_REG_WR(NULL, \
--
2.5.5
^ permalink raw reply related
* [PATCH 26/28] net/virtio: use eal I/O device memory read/write API
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Santosh Shukla, Jerin Jacob, Huawei Xie, Yuanhan Liu
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Huawei Xie <huawei.xie@intel.com>
CC: Yuanhan Liu <yuanhan.liu@linux.intel.com>
---
drivers/net/virtio/virtio_pci.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c
index 9b47165..47c5a2e 100644
--- a/drivers/net/virtio/virtio_pci.c
+++ b/drivers/net/virtio/virtio_pci.c
@@ -41,6 +41,8 @@
#include "virtio_logs.h"
#include "virtqueue.h"
+#include <rte_io.h>
+
/*
* Following macros are derived from linux/pci_regs.h, however,
* we can't simply include that header here, as there is no such
@@ -320,37 +322,37 @@ static const struct virtio_pci_ops legacy_ops = {
static inline uint8_t
io_read8(uint8_t *addr)
{
- return *(volatile uint8_t *)addr;
+ return rte_readb(addr);
}
static inline void
io_write8(uint8_t val, uint8_t *addr)
{
- *(volatile uint8_t *)addr = val;
+ rte_writeb(val, addr);
}
static inline uint16_t
io_read16(uint16_t *addr)
{
- return *(volatile uint16_t *)addr;
+ return rte_readw(addr);
}
static inline void
io_write16(uint16_t val, uint16_t *addr)
{
- *(volatile uint16_t *)addr = val;
+ rte_writew(val, addr);
}
static inline uint32_t
io_read32(uint32_t *addr)
{
- return *(volatile uint32_t *)addr;
+ return rte_readl(addr);
}
static inline void
io_write32(uint32_t val, uint32_t *addr)
{
- *(volatile uint32_t *)addr = val;
+ rte_writel(val, addr);
}
static inline void
--
2.5.5
^ permalink raw reply related
* [PATCH 27/28] net/vmxnet3: use eal I/O device memory read/write API
From: Jerin Jacob @ 2016-12-14 1:55 UTC (permalink / raw)
To: dev
Cc: konstantin.ananyev, thomas.monjalon, bruce.richardson, jianbo.liu,
viktorin, Santosh Shukla, Jerin Jacob, Yong Wang
In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
From: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
CC: Yong Wang <yongwang@vmware.com>
---
drivers/net/vmxnet3/vmxnet3_ethdev.h | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.h b/drivers/net/vmxnet3/vmxnet3_ethdev.h
index 7d3b11e..5b6501b 100644
--- a/drivers/net/vmxnet3/vmxnet3_ethdev.h
+++ b/drivers/net/vmxnet3/vmxnet3_ethdev.h
@@ -34,6 +34,8 @@
#ifndef _VMXNET3_ETHDEV_H_
#define _VMXNET3_ETHDEV_H_
+#include <rte_io.h>
+
#define VMXNET3_MAX_MAC_ADDRS 1
/* UPT feature to negotiate */
@@ -120,7 +122,11 @@ struct vmxnet3_hw {
/* Config space read/writes */
-#define VMXNET3_PCI_REG(reg) (*((volatile uint32_t *)(reg)))
+#define VMXNET3_PCI_REG(reg) ({ \
+ uint32_t __val; \
+ __val = rte_readl(reg); \
+ __val; \
+})
static inline uint32_t
vmxnet3_read_addr(volatile void *addr)
@@ -128,9 +134,9 @@ vmxnet3_read_addr(volatile void *addr)
return VMXNET3_PCI_REG(addr);
}
-#define VMXNET3_PCI_REG_WRITE(reg, value) do { \
- VMXNET3_PCI_REG((reg)) = (value); \
-} while(0)
+#define VMXNET3_PCI_REG_WRITE(reg, value) ({ \
+ rte_writel(value, reg); \
+})
#define VMXNET3_PCI_BAR0_REG_ADDR(hw, reg) \
((volatile uint32_t *)((char *)(hw)->hw_addr0 + (reg)))
--
2.5.5
^ permalink raw reply related
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