* [PATCH v2 0/4] net/mlx5: support flow_rte
From: Nelio Laranjeiro @ 2016-12-21 10:01 UTC (permalink / raw)
To: dev; +Cc: Adrien Mazarguil
In-Reply-To: <cover.1480096192.git.nelio.laranjeiro@6wind.com>
This series requires rte_flow [1].
It brings rte_flow support to the same level as flow director (FDIR) in mlx5.
[1] http://dpdk.org/ml/archives/dev/2016-December/052802.html
Changes in v2:
- Fix several issues.
- Support VLAN filtering.
Nelio Laranjeiro (4):
net/mlx5: add preliminary support for rte_flow
net/mlx5: add software support for rte_flow
net/mlx5: add rte_flow rule creation
net/mlx5: add VLAN filter support in rte_flow
drivers/net/mlx5/Makefile | 1 +
drivers/net/mlx5/mlx5.h | 19 +
drivers/net/mlx5/mlx5_fdir.c | 15 +
drivers/net/mlx5/mlx5_flow.c | 1030 +++++++++++++++++++++++++++++++++++++++
drivers/net/mlx5/mlx5_trigger.c | 4 +
5 files changed, 1069 insertions(+)
create mode 100644 drivers/net/mlx5/mlx5_flow.c
--
2.1.4
^ permalink raw reply
* [PATCH v2 2/4] net/mlx5: add software support for rte_flow
From: Nelio Laranjeiro @ 2016-12-21 10:01 UTC (permalink / raw)
To: dev; +Cc: Adrien Mazarguil
In-Reply-To: <cover.1482314020.git.nelio.laranjeiro@6wind.com>
Introduce initial software validation for rte_flow rules.
Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
---
drivers/net/mlx5/mlx5.h | 2 +
drivers/net/mlx5/mlx5_flow.c | 202 ++++++++++++++++++++++++++++++++++------
drivers/net/mlx5/mlx5_trigger.c | 2 +
3 files changed, 177 insertions(+), 29 deletions(-)
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 04f4eaa..ac995a0 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -136,6 +136,7 @@ struct priv {
unsigned int reta_idx_n; /* RETA index size. */
struct fdir_filter_list *fdir_filter_list; /* Flow director rules. */
struct fdir_queue *fdir_drop_queue; /* Flow director drop queue. */
+ LIST_HEAD(mlx5_flows, rte_flow) flows; /* RTE Flow rules. */
uint32_t link_speed_capa; /* Link speed capabilities. */
rte_spinlock_t lock; /* Lock for control functions. */
};
@@ -283,5 +284,6 @@ struct rte_flow *mlx5_flow_create(struct rte_eth_dev *,
int mlx5_flow_destroy(struct rte_eth_dev *, struct rte_flow *,
struct rte_flow_error *);
int mlx5_flow_flush(struct rte_eth_dev *, struct rte_flow_error *);
+void priv_flow_flush(struct priv *);
#endif /* RTE_PMD_MLX5_H_ */
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index a514dff..3e5098a 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -30,11 +30,119 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include <sys/queue.h>
+
#include <rte_ethdev.h>
#include <rte_flow.h>
#include <rte_flow_driver.h>
+#include <rte_malloc.h>
+
#include "mlx5.h"
+struct rte_flow {
+ LIST_ENTRY(rte_flow) next; /* Pointer to the next rte_flow structure. */
+};
+
+/**
+ * Validate a flow supported by the NIC.
+ *
+ * @param priv
+ * Pointer to private structure.
+ * @param[in] attr
+ * Flow rule attributes.
+ * @param[in] pattern
+ * Pattern specification (list terminated by the END pattern item).
+ * @param[in] actions
+ * Associated actions (list terminated by the END action).
+ * @param[out] error
+ * Perform verbose error reporting if not NULL.
+ *
+ * @return
+ * 0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+static int
+priv_flow_validate(struct priv *priv,
+ const struct rte_flow_attr *attr,
+ const struct rte_flow_item items[],
+ const struct rte_flow_action actions[],
+ struct rte_flow_error *error)
+{
+ (void)priv;
+ const struct rte_flow_item *ilast = NULL;
+
+ if (attr->group) {
+ rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
+ NULL,
+ "groups are not supported");
+ return -rte_errno;
+ }
+ if (attr->priority) {
+ rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
+ NULL,
+ "priorities are not supported");
+ return -rte_errno;
+ }
+ if (attr->egress) {
+ rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
+ NULL,
+ "egress is not supported");
+ return -rte_errno;
+ }
+ if (!attr->ingress) {
+ rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
+ NULL,
+ "only ingress is supported");
+ return -rte_errno;
+ }
+ for (; items->type != RTE_FLOW_ITEM_TYPE_END; ++items) {
+ if (items->type == RTE_FLOW_ITEM_TYPE_VOID) {
+ continue;
+ } else if (items->type == RTE_FLOW_ITEM_TYPE_ETH) {
+ if (ilast)
+ goto exit_item_not_supported;
+ ilast = items;
+ } else if ((items->type == RTE_FLOW_ITEM_TYPE_IPV4) ||
+ (items->type == RTE_FLOW_ITEM_TYPE_IPV6)) {
+ if (!ilast)
+ goto exit_item_not_supported;
+ else if (ilast->type != RTE_FLOW_ITEM_TYPE_ETH)
+ goto exit_item_not_supported;
+ ilast = items;
+ } else if ((items->type == RTE_FLOW_ITEM_TYPE_UDP) ||
+ (items->type == RTE_FLOW_ITEM_TYPE_TCP)) {
+ if (!ilast)
+ goto exit_item_not_supported;
+ else if ((ilast->type != RTE_FLOW_ITEM_TYPE_IPV4) &&
+ (ilast->type != RTE_FLOW_ITEM_TYPE_IPV6))
+ goto exit_item_not_supported;
+ ilast = items;
+ } else {
+ goto exit_item_not_supported;
+ }
+ }
+ for (; actions->type != RTE_FLOW_ACTION_TYPE_END; ++actions) {
+ if (actions->type == RTE_FLOW_ACTION_TYPE_VOID ||
+ actions->type == RTE_FLOW_ACTION_TYPE_QUEUE ||
+ actions->type == RTE_FLOW_ACTION_TYPE_DROP)
+ continue;
+ else
+ goto exit_action_not_supported;
+ }
+ return 0;
+exit_item_not_supported:
+ rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
+ items, "item not supported");
+ return -rte_errno;
+exit_action_not_supported:
+ rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
+ actions, "action not supported");
+ return -rte_errno;
+}
+
/**
* Validate a flow supported by the NIC.
*
@@ -48,15 +156,13 @@ mlx5_flow_validate(struct rte_eth_dev *dev,
const struct rte_flow_action actions[],
struct rte_flow_error *error)
{
- (void)dev;
- (void)attr;
- (void)items;
- (void)actions;
- (void)error;
- rte_flow_error_set(error, ENOTSUP,
- RTE_FLOW_ERROR_TYPE_NONE,
- NULL, "not implemented yet");
- return -rte_errno;
+ struct priv *priv = dev->data->dev_private;
+ int ret;
+
+ priv_lock(priv);
+ ret = priv_flow_validate(priv, attr, items, actions, error);
+ priv_unlock(priv);
+ return ret;
}
/**
@@ -72,15 +178,35 @@ mlx5_flow_create(struct rte_eth_dev *dev,
const struct rte_flow_action actions[],
struct rte_flow_error *error)
{
- (void)dev;
- (void)attr;
- (void)items;
- (void)actions;
- (void)error;
- rte_flow_error_set(error, ENOTSUP,
- RTE_FLOW_ERROR_TYPE_NONE,
- NULL, "not implemented yet");
- return NULL;
+ struct priv *priv = dev->data->dev_private;
+ struct rte_flow *flow;
+
+ priv_lock(priv);
+ if (priv_flow_validate(priv, attr, items, actions, error)) {
+ priv_unlock(priv);
+ return NULL;
+ }
+ flow = rte_malloc(__func__, sizeof(struct rte_flow), 0);
+ LIST_INSERT_HEAD(&priv->flows, flow, next);
+ priv_unlock(priv);
+ return flow;
+}
+
+/**
+ * Destroy a flow.
+ *
+ * @param priv
+ * Pointer to private structure.
+ * @param[in] flow
+ * Pointer to the flow to destroy.
+ */
+static void
+priv_flow_destroy(struct priv *priv,
+ struct rte_flow *flow)
+{
+ (void)priv;
+ LIST_REMOVE(flow, next);
+ rte_free(flow);
}
/**
@@ -94,13 +220,30 @@ mlx5_flow_destroy(struct rte_eth_dev *dev,
struct rte_flow *flow,
struct rte_flow_error *error)
{
- (void)dev;
- (void)flow;
+ struct priv *priv = dev->data->dev_private;
+
(void)error;
- rte_flow_error_set(error, ENOTSUP,
- RTE_FLOW_ERROR_TYPE_NONE,
- NULL, "not implemented yet");
- return -rte_errno;
+ priv_lock(priv);
+ priv_flow_destroy(priv, flow);
+ priv_unlock(priv);
+ return 0;
+}
+
+/**
+ * Destroy all flows.
+ *
+ * @param priv
+ * Pointer to private structure.
+ */
+void
+priv_flow_flush(struct priv *priv)
+{
+ while (!LIST_EMPTY(&priv->flows)) {
+ struct rte_flow *flow;
+
+ flow = LIST_FIRST(&priv->flows);
+ priv_flow_destroy(priv, flow);
+ }
}
/**
@@ -113,10 +256,11 @@ int
mlx5_flow_flush(struct rte_eth_dev *dev,
struct rte_flow_error *error)
{
- (void)dev;
+ struct priv *priv = dev->data->dev_private;
+
(void)error;
- rte_flow_error_set(error, ENOTSUP,
- RTE_FLOW_ERROR_TYPE_NONE,
- NULL, "not implemented yet");
- return -rte_errno;
+ priv_lock(priv);
+ priv_flow_flush(priv);
+ priv_unlock(priv);
+ return 0;
}
diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c
index d4dccd8..4a359d7 100644
--- a/drivers/net/mlx5/mlx5_trigger.c
+++ b/drivers/net/mlx5/mlx5_trigger.c
@@ -90,6 +90,7 @@ mlx5_dev_start(struct rte_eth_dev *dev)
if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE)
priv_fdir_enable(priv);
priv_dev_interrupt_handler_install(priv, dev);
+ LIST_INIT(&priv->flows);
priv_unlock(priv);
return -err;
}
@@ -120,6 +121,7 @@ mlx5_dev_stop(struct rte_eth_dev *dev)
priv_mac_addrs_disable(priv);
priv_destroy_hash_rxqs(priv);
priv_fdir_disable(priv);
+ priv_flow_flush(priv);
priv_dev_interrupt_handler_uninstall(priv, dev);
priv->started = 0;
priv_unlock(priv);
--
2.1.4
^ permalink raw reply related
* [PATCH v2 1/4] net/mlx5: add preliminary support for rte_flow
From: Nelio Laranjeiro @ 2016-12-21 10:01 UTC (permalink / raw)
To: dev; +Cc: Adrien Mazarguil
In-Reply-To: <cover.1482314020.git.nelio.laranjeiro@6wind.com>
Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
---
drivers/net/mlx5/Makefile | 1 +
drivers/net/mlx5/mlx5.h | 16 ++++++
drivers/net/mlx5/mlx5_fdir.c | 15 ++++++
drivers/net/mlx5/mlx5_flow.c | 122 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 154 insertions(+)
create mode 100644 drivers/net/mlx5/mlx5_flow.c
diff --git a/drivers/net/mlx5/Makefile b/drivers/net/mlx5/Makefile
index cf87f0b..6d1338a 100644
--- a/drivers/net/mlx5/Makefile
+++ b/drivers/net/mlx5/Makefile
@@ -48,6 +48,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += mlx5_stats.c
SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += mlx5_rss.c
SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += mlx5_fdir.c
SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += mlx5_mr.c
+SRCS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += mlx5_flow.c
# Dependencies.
DEPDIRS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += lib/librte_ether
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 79b7a60..04f4eaa 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -59,6 +59,7 @@
#include <rte_spinlock.h>
#include <rte_interrupts.h>
#include <rte_errno.h>
+#include <rte_flow.h>
#ifdef PEDANTIC
#pragma GCC diagnostic error "-Wpedantic"
#endif
@@ -268,4 +269,19 @@ void priv_fdir_enable(struct priv *);
int mlx5_dev_filter_ctrl(struct rte_eth_dev *, enum rte_filter_type,
enum rte_filter_op, void *);
+/* mlx5_flow.c */
+
+int mlx5_flow_validate(struct rte_eth_dev *, const struct rte_flow_attr *,
+ const struct rte_flow_item [],
+ const struct rte_flow_action [],
+ struct rte_flow_error *);
+struct rte_flow *mlx5_flow_create(struct rte_eth_dev *,
+ const struct rte_flow_attr *,
+ const struct rte_flow_item [],
+ const struct rte_flow_action [],
+ struct rte_flow_error *);
+int mlx5_flow_destroy(struct rte_eth_dev *, struct rte_flow *,
+ struct rte_flow_error *);
+int mlx5_flow_flush(struct rte_eth_dev *, struct rte_flow_error *);
+
#endif /* RTE_PMD_MLX5_H_ */
diff --git a/drivers/net/mlx5/mlx5_fdir.c b/drivers/net/mlx5/mlx5_fdir.c
index 1acf682..f80c58b 100644
--- a/drivers/net/mlx5/mlx5_fdir.c
+++ b/drivers/net/mlx5/mlx5_fdir.c
@@ -55,6 +55,8 @@
#include <rte_malloc.h>
#include <rte_ethdev.h>
#include <rte_common.h>
+#include <rte_flow.h>
+#include <rte_flow_driver.h>
#ifdef PEDANTIC
#pragma GCC diagnostic error "-Wpedantic"
#endif
@@ -1042,6 +1044,14 @@ priv_fdir_ctrl_func(struct priv *priv, enum rte_filter_op filter_op, void *arg)
return ret;
}
+static const struct rte_flow_ops mlx5_flow_ops = {
+ .validate = mlx5_flow_validate,
+ .create = mlx5_flow_create,
+ .destroy = mlx5_flow_destroy,
+ .flush = mlx5_flow_flush,
+ .query = NULL,
+};
+
/**
* Manage filter operations.
*
@@ -1067,6 +1077,11 @@ mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
struct priv *priv = dev->data->dev_private;
switch (filter_type) {
+ case RTE_ETH_FILTER_GENERIC:
+ if (filter_op != RTE_ETH_FILTER_GET)
+ return -EINVAL;
+ *(const void **)arg = &mlx5_flow_ops;
+ return 0;
case RTE_ETH_FILTER_FDIR:
priv_lock(priv);
ret = priv_fdir_ctrl_func(priv, filter_op, arg);
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
new file mode 100644
index 0000000..a514dff
--- /dev/null
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -0,0 +1,122 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright 2016 6WIND S.A.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of 6WIND S.A. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <rte_ethdev.h>
+#include <rte_flow.h>
+#include <rte_flow_driver.h>
+#include "mlx5.h"
+
+/**
+ * Validate a flow supported by the NIC.
+ *
+ * @see rte_flow_validate()
+ * @see rte_flow_ops
+ */
+int
+mlx5_flow_validate(struct rte_eth_dev *dev,
+ const struct rte_flow_attr *attr,
+ const struct rte_flow_item items[],
+ const struct rte_flow_action actions[],
+ struct rte_flow_error *error)
+{
+ (void)dev;
+ (void)attr;
+ (void)items;
+ (void)actions;
+ (void)error;
+ rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_NONE,
+ NULL, "not implemented yet");
+ return -rte_errno;
+}
+
+/**
+ * Create a flow.
+ *
+ * @see rte_flow_create()
+ * @see rte_flow_ops
+ */
+struct rte_flow *
+mlx5_flow_create(struct rte_eth_dev *dev,
+ const struct rte_flow_attr *attr,
+ const struct rte_flow_item items[],
+ const struct rte_flow_action actions[],
+ struct rte_flow_error *error)
+{
+ (void)dev;
+ (void)attr;
+ (void)items;
+ (void)actions;
+ (void)error;
+ rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_NONE,
+ NULL, "not implemented yet");
+ return NULL;
+}
+
+/**
+ * Destroy a flow.
+ *
+ * @see rte_flow_destroy()
+ * @see rte_flow_ops
+ */
+int
+mlx5_flow_destroy(struct rte_eth_dev *dev,
+ struct rte_flow *flow,
+ struct rte_flow_error *error)
+{
+ (void)dev;
+ (void)flow;
+ (void)error;
+ rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_NONE,
+ NULL, "not implemented yet");
+ return -rte_errno;
+}
+
+/**
+ * Destroy all flows.
+ *
+ * @see rte_flow_flush()
+ * @see rte_flow_ops
+ */
+int
+mlx5_flow_flush(struct rte_eth_dev *dev,
+ struct rte_flow_error *error)
+{
+ (void)dev;
+ (void)error;
+ rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_NONE,
+ NULL, "not implemented yet");
+ return -rte_errno;
+}
--
2.1.4
^ permalink raw reply related
* [PATCH v2 3/4] net/mlx5: add rte_flow rule creation
From: Nelio Laranjeiro @ 2016-12-21 10:01 UTC (permalink / raw)
To: dev; +Cc: Adrien Mazarguil
In-Reply-To: <cover.1482314020.git.nelio.laranjeiro@6wind.com>
Convert Ethernet, IPv4, IPv6, TCP, UDP layers into ibv_flow and create
those rules when after validation (i.e. NIC supports the rule).
VLAN is still not supported in this commit.
Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
---
drivers/net/mlx5/mlx5.h | 3 +-
drivers/net/mlx5/mlx5_flow.c | 737 +++++++++++++++++++++++++++++++++++++++-
drivers/net/mlx5/mlx5_trigger.c | 6 +-
3 files changed, 729 insertions(+), 17 deletions(-)
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index ac995a0..ca7e84c 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -284,6 +284,7 @@ struct rte_flow *mlx5_flow_create(struct rte_eth_dev *,
int mlx5_flow_destroy(struct rte_eth_dev *, struct rte_flow *,
struct rte_flow_error *);
int mlx5_flow_flush(struct rte_eth_dev *, struct rte_flow_error *);
-void priv_flow_flush(struct priv *);
+int priv_flow_apply(struct priv *);
+void priv_flow_remove(struct priv *);
#endif /* RTE_PMD_MLX5_H_ */
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 3e5098a..44e2fb8 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -31,6 +31,17 @@
*/
#include <sys/queue.h>
+#include <string.h>
+
+/* Verbs header. */
+/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+#include <infiniband/verbs.h>
+#ifdef PEDANTIC
+#pragma GCC diagnostic error "-Wpedantic"
+#endif
#include <rte_ethdev.h>
#include <rte_flow.h>
@@ -39,11 +50,82 @@
#include "mlx5.h"
+/** Define a value to use as index for the drop queue. */
+#define MLX5_FLOW_DROP_QUEUE ((uint32_t)-1)
+
struct rte_flow {
LIST_ENTRY(rte_flow) next; /* Pointer to the next rte_flow structure. */
+ struct ibv_exp_flow_attr *ibv_attr; /* Pointer to Verbs attributes. */
+ struct ibv_exp_rwq_ind_table *ind_table; /* Indirection table. */
+ struct ibv_qp *qp; /* Verbs Queue pair. */
+ struct ibv_exp_flow *ibv_flow; /* Verbs flow. */
+ struct ibv_exp_wq *wq; /* Verbs work queue. */
+ struct ibv_cq *cq; /* Verbs completion queue. */
+ uint8_t drop; /* 1 if this flow is associated to a drop queue. */
};
/**
+ * Check support for a given item.
+ *
+ * @param item[in]
+ * Item specification.
+ * @param mask[in]
+ * Bit-mask covering supported fields to compare with spec, last and mask in
+ * \item.
+ * @param size
+ * Bit-Mask size in bytes.
+ *
+ * @return
+ * 0 on success.
+ */
+static int
+mlx5_flow_item_validate(const struct rte_flow_item *item,
+ const uint8_t *mask, unsigned int size)
+{
+ int ret = 0;
+
+ if (item->spec && !item->mask) {
+ unsigned int i;
+ const uint8_t *spec = item->spec;
+
+ for (i = 0; i < size; ++i)
+ if ((spec[i] | mask[i]) != mask[i])
+ return -1;
+ }
+ if (item->last && !item->mask) {
+ unsigned int i;
+ const uint8_t *spec = item->last;
+
+ for (i = 0; i < size; ++i)
+ if ((spec[i] | mask[i]) != mask[i])
+ return -1;
+ }
+ if (item->mask) {
+ unsigned int i;
+ const uint8_t *spec = item->mask;
+
+ for (i = 0; i < size; ++i)
+ if ((spec[i] | mask[i]) != mask[i])
+ return -1;
+ }
+ if (item->spec && item->last) {
+ uint8_t spec[size];
+ uint8_t last[size];
+ const uint8_t *apply = mask;
+ unsigned int i;
+
+ if (item->mask)
+ apply = item->mask;
+ for (i = 0; i < size; ++i) {
+ spec[i] = ((const uint8_t *)item->spec)[i] & apply[i];
+ last[i] = ((const uint8_t *)item->last)[i] & apply[i];
+ }
+ ret = memcmp(spec, last, size);
+ }
+ return ret;
+}
+
+/**
* Validate a flow supported by the NIC.
*
* @param priv
@@ -67,8 +149,42 @@ priv_flow_validate(struct priv *priv,
const struct rte_flow_action actions[],
struct rte_flow_error *error)
{
- (void)priv;
const struct rte_flow_item *ilast = NULL;
+ const struct rte_flow_item_eth eth_mask = {
+ .dst.addr_bytes = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
+ .src.addr_bytes = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
+ .type = -1,
+ };
+ const struct rte_flow_item_ipv4 ipv4_mask = {
+ .hdr = {
+ .src_addr = -1,
+ .dst_addr = -1,
+ },
+ };
+ const struct rte_flow_item_ipv6 ipv6_mask = {
+ .hdr = {
+ .src_addr = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ },
+ .dst_addr = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ },
+ },
+ };
+ const struct rte_flow_item_udp udp_mask = {
+ .hdr = {
+ .src_port = -1,
+ .dst_port = -1,
+ },
+ };
+ const struct rte_flow_item_tcp tcp_mask = {
+ .hdr = {
+ .src_port = -1,
+ .dst_port = -1,
+ },
+ };
if (attr->group) {
rte_flow_error_set(error, ENOTSUP,
@@ -99,38 +215,93 @@ priv_flow_validate(struct priv *priv,
return -rte_errno;
}
for (; items->type != RTE_FLOW_ITEM_TYPE_END; ++items) {
+ int err = 0;
+
if (items->type == RTE_FLOW_ITEM_TYPE_VOID) {
continue;
} else if (items->type == RTE_FLOW_ITEM_TYPE_ETH) {
if (ilast)
goto exit_item_not_supported;
ilast = items;
- } else if ((items->type == RTE_FLOW_ITEM_TYPE_IPV4) ||
- (items->type == RTE_FLOW_ITEM_TYPE_IPV6)) {
+ err = mlx5_flow_item_validate(
+ items,
+ (const uint8_t *)ð_mask,
+ sizeof(eth_mask));
+ if (err)
+ goto exit_item_not_supported;
+ } else if (items->type == RTE_FLOW_ITEM_TYPE_IPV4) {
+ if (!ilast)
+ goto exit_item_not_supported;
+ else if (ilast->type != RTE_FLOW_ITEM_TYPE_ETH)
+ goto exit_item_not_supported;
+ ilast = items;
+ err = mlx5_flow_item_validate(
+ items,
+ (const uint8_t *)&ipv4_mask,
+ sizeof(ipv4_mask));
+ if (err)
+ goto exit_item_not_supported;
+ } else if (items->type == RTE_FLOW_ITEM_TYPE_IPV6) {
if (!ilast)
goto exit_item_not_supported;
else if (ilast->type != RTE_FLOW_ITEM_TYPE_ETH)
goto exit_item_not_supported;
ilast = items;
- } else if ((items->type == RTE_FLOW_ITEM_TYPE_UDP) ||
- (items->type == RTE_FLOW_ITEM_TYPE_TCP)) {
+ err = mlx5_flow_item_validate(
+ items,
+ (const uint8_t *)&ipv6_mask,
+ sizeof(ipv6_mask));
+ if (err)
+ goto exit_item_not_supported;
+ } else if (items->type == RTE_FLOW_ITEM_TYPE_UDP) {
+ if (!ilast)
+ goto exit_item_not_supported;
+ else if ((ilast->type != RTE_FLOW_ITEM_TYPE_IPV4) &&
+ (ilast->type != RTE_FLOW_ITEM_TYPE_IPV6))
+ goto exit_item_not_supported;
+ ilast = items;
+ err = mlx5_flow_item_validate(
+ items,
+ (const uint8_t *)&udp_mask,
+ sizeof(udp_mask));
+ if (err)
+ goto exit_item_not_supported;
+ } else if (items->type == RTE_FLOW_ITEM_TYPE_TCP) {
if (!ilast)
goto exit_item_not_supported;
else if ((ilast->type != RTE_FLOW_ITEM_TYPE_IPV4) &&
(ilast->type != RTE_FLOW_ITEM_TYPE_IPV6))
goto exit_item_not_supported;
ilast = items;
+ err = mlx5_flow_item_validate(
+ items,
+ (const uint8_t *)&tcp_mask,
+ sizeof(tcp_mask));
+ if (err)
+ goto exit_item_not_supported;
} else {
goto exit_item_not_supported;
}
}
for (; actions->type != RTE_FLOW_ACTION_TYPE_END; ++actions) {
if (actions->type == RTE_FLOW_ACTION_TYPE_VOID ||
- actions->type == RTE_FLOW_ACTION_TYPE_QUEUE ||
- actions->type == RTE_FLOW_ACTION_TYPE_DROP)
+ actions->type == RTE_FLOW_ACTION_TYPE_DROP) {
continue;
- else
+ } else if (actions->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
+ const struct rte_flow_action_queue *queue =
+ (const struct rte_flow_action_queue *)
+ actions->conf;
+
+ if (!queue || (queue->index > (priv->rxqs_n - 1))) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ACTION,
+ actions,
+ "queue index error");
+ goto exit;
+ }
+ } else {
goto exit_action_not_supported;
+ }
}
return 0;
exit_item_not_supported:
@@ -140,6 +311,7 @@ priv_flow_validate(struct priv *priv,
exit_action_not_supported:
rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
actions, "action not supported");
+exit:
return -rte_errno;
}
@@ -166,6 +338,479 @@ mlx5_flow_validate(struct rte_eth_dev *dev,
}
/**
+ * Convert Ethernet item to Verbs specification.
+ *
+ * @param item[in]
+ * Item specification.
+ * @param eth[in, out]
+ * Verbs Ethernet specification structure.
+ */
+static void
+mlx5_flow_create_eth(const struct rte_flow_item *item,
+ struct ibv_exp_flow_spec_eth *eth)
+{
+ const struct rte_flow_item_eth *spec = item->spec;
+ const struct rte_flow_item_eth *mask = item->mask;
+ unsigned int i;
+
+ *eth = (struct ibv_exp_flow_spec_eth) {
+ .type = IBV_EXP_FLOW_SPEC_ETH,
+ .size = sizeof(struct ibv_exp_flow_spec_eth),
+ };
+ if (spec) {
+ memcpy(eth->val.dst_mac, spec->dst.addr_bytes, ETHER_ADDR_LEN);
+ memcpy(eth->val.src_mac, spec->src.addr_bytes, ETHER_ADDR_LEN);
+ }
+ if (mask) {
+ memcpy(eth->mask.dst_mac, mask->dst.addr_bytes, ETHER_ADDR_LEN);
+ memcpy(eth->mask.src_mac, mask->src.addr_bytes, ETHER_ADDR_LEN);
+ }
+ eth->val.ether_type = spec->type;
+ eth->mask.ether_type = mask->type;
+ /* Remove unwanted bits from values. */
+ for (i = 0; i < ETHER_ADDR_LEN; ++i) {
+ eth->val.dst_mac[i] &= eth->mask.dst_mac[i];
+ eth->val.src_mac[i] &= eth->mask.src_mac[i];
+ }
+ eth->val.ether_type &= eth->mask.ether_type;
+}
+
+/**
+ * Convert IPv4 item to Verbs specification.
+ *
+ * @param item[in]
+ * Item specification.
+ * @param ipv4[in, out]
+ * Verbs IPv4 specification structure.
+ */
+static void
+mlx5_flow_create_ipv4(const struct rte_flow_item *item,
+ struct ibv_exp_flow_spec_ipv4 *ipv4)
+{
+ const struct rte_flow_item_ipv4 *spec = item->spec;
+ const struct rte_flow_item_ipv4 *mask = item->mask;
+
+ *ipv4 = (struct ibv_exp_flow_spec_ipv4) {
+ .type = IBV_EXP_FLOW_SPEC_IPV4,
+ .size = sizeof(struct ibv_exp_flow_spec_ipv4),
+ };
+ if (spec) {
+ ipv4->val = (struct ibv_exp_flow_ipv4_filter){
+ .src_ip = spec->hdr.src_addr,
+ .dst_ip = spec->hdr.dst_addr,
+ };
+ }
+ if (mask) {
+ ipv4->mask = (struct ibv_exp_flow_ipv4_filter){
+ .src_ip = mask->hdr.src_addr,
+ .dst_ip = mask->hdr.dst_addr,
+ };
+ }
+ /* Remove unwanted bits from values. */
+ ipv4->val.src_ip &= ipv4->mask.src_ip;
+ ipv4->val.dst_ip &= ipv4->mask.dst_ip;
+}
+
+/**
+ * Convert IPv6 item to Verbs specification.
+ *
+ * @param item[in]
+ * Item specification.
+ * @param ipv6[in, out]
+ * Verbs IPv6 specification structure.
+ */
+static void
+mlx5_flow_create_ipv6(const struct rte_flow_item *item,
+ struct ibv_exp_flow_spec_ipv6 *ipv6)
+{
+ const struct rte_flow_item_ipv6 *spec = item->spec;
+ const struct rte_flow_item_ipv6 *mask = item->mask;
+ unsigned int i;
+
+ *ipv6 = (struct ibv_exp_flow_spec_ipv6) {
+ .type = IBV_EXP_FLOW_SPEC_IPV6,
+ .size = sizeof(struct ibv_exp_flow_spec_ipv6),
+ };
+ if (spec) {
+ memcpy(ipv6->val.src_ip, spec->hdr.src_addr,
+ RTE_DIM(ipv6->val.src_ip));
+ memcpy(ipv6->val.dst_ip, spec->hdr.dst_addr,
+ RTE_DIM(ipv6->val.dst_ip));
+ }
+ if (mask) {
+ memcpy(ipv6->mask.src_ip, mask->hdr.src_addr,
+ RTE_DIM(ipv6->mask.src_ip));
+ memcpy(ipv6->mask.dst_ip, mask->hdr.dst_addr,
+ RTE_DIM(ipv6->mask.dst_ip));
+ }
+ /* Remove unwanted bits from values. */
+ for (i = 0; i < RTE_DIM(ipv6->val.src_ip); ++i) {
+ ipv6->val.src_ip[i] &= ipv6->mask.src_ip[i];
+ ipv6->val.dst_ip[i] &= ipv6->mask.dst_ip[i];
+ }
+}
+
+/**
+ * Convert UDP item to Verbs specification.
+ *
+ * @param item[in]
+ * Item specification.
+ * @param udp[in, out]
+ * Verbs UDP specification structure.
+ */
+static void
+mlx5_flow_create_udp(const struct rte_flow_item *item,
+ struct ibv_exp_flow_spec_tcp_udp *udp)
+{
+ const struct rte_flow_item_udp *spec = item->spec;
+ const struct rte_flow_item_udp *mask = item->mask;
+
+ *udp = (struct ibv_exp_flow_spec_tcp_udp) {
+ .type = IBV_EXP_FLOW_SPEC_UDP,
+ .size = sizeof(struct ibv_exp_flow_spec_tcp_udp),
+ };
+ udp->type = IBV_EXP_FLOW_SPEC_UDP;
+ if (spec) {
+ udp->val.dst_port = spec->hdr.dst_port;
+ udp->val.src_port = spec->hdr.src_port;
+ }
+ if (mask) {
+ udp->mask.dst_port = mask->hdr.dst_port;
+ udp->mask.src_port = mask->hdr.src_port;
+ }
+ /* Remove unwanted bits from values. */
+ udp->val.src_port &= udp->mask.src_port;
+ udp->val.dst_port &= udp->mask.dst_port;
+}
+
+/**
+ * Convert TCP item to Verbs specification.
+ *
+ * @param item[in]
+ * Item specification.
+ * @param tcp[in, out]
+ * Verbs TCP specification structure.
+ */
+static void
+mlx5_flow_create_tcp(const struct rte_flow_item *item,
+ struct ibv_exp_flow_spec_tcp_udp *tcp)
+{
+ const struct rte_flow_item_tcp *spec = item->spec;
+ const struct rte_flow_item_tcp *mask = item->mask;
+
+ *tcp = (struct ibv_exp_flow_spec_tcp_udp) {
+ .type = IBV_EXP_FLOW_SPEC_TCP,
+ .size = sizeof(struct ibv_exp_flow_spec_tcp_udp),
+ };
+ tcp->type = IBV_EXP_FLOW_SPEC_TCP;
+ if (spec) {
+ tcp->val.dst_port = spec->hdr.dst_port;
+ tcp->val.src_port = spec->hdr.src_port;
+ }
+ if (mask) {
+ tcp->mask.dst_port = mask->hdr.dst_port;
+ tcp->mask.src_port = mask->hdr.src_port;
+ }
+ /* Remove unwanted bits from values. */
+ tcp->val.src_port &= tcp->mask.src_port;
+ tcp->val.dst_port &= tcp->mask.dst_port;
+}
+
+/**
+ * Complete flow rule creation.
+ *
+ * @param priv
+ * Pointer to private structure.
+ * @param ibv_attr
+ * Verbs flow attributes.
+ * @param queue
+ * Destination queue.
+ * @param[out] error
+ * Perform verbose error reporting if not NULL.
+ *
+ * @return
+ * A flow if the rule could be created.
+ */
+static struct rte_flow *
+priv_flow_create_action_queue(struct priv *priv,
+ struct ibv_exp_flow_attr *ibv_attr,
+ uint32_t queue,
+ struct rte_flow_error *error)
+{
+ struct rxq_ctrl *rxq;
+ struct rte_flow *rte_flow;
+
+ assert(priv->pd);
+ assert(priv->ctx);
+ rte_flow = rte_calloc(__func__, 1, sizeof(*rte_flow), 0);
+ if (!rte_flow) {
+ rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL, "cannot allocate flow memory");
+ return NULL;
+ }
+ if (queue == MLX5_FLOW_DROP_QUEUE) {
+ rte_flow->drop = 1;
+ rte_flow->cq =
+ ibv_exp_create_cq(priv->ctx, 1, NULL, NULL, 0,
+ &(struct ibv_exp_cq_init_attr){
+ .comp_mask = 0,
+ });
+ if (!rte_flow->cq) {
+ rte_flow_error_set(error, ENOMEM,
+ RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL, "cannot allocate CQ");
+ goto error;
+ }
+ rte_flow->wq = ibv_exp_create_wq(
+ priv->ctx,
+ &(struct ibv_exp_wq_init_attr){
+ .wq_type = IBV_EXP_WQT_RQ,
+ .max_recv_wr = 1,
+ .max_recv_sge = 1,
+ .pd = priv->pd,
+ .cq = rte_flow->cq,
+ });
+ } else {
+ rxq = container_of((*priv->rxqs)[queue], struct rxq_ctrl, rxq);
+ rte_flow->drop = 0;
+ rte_flow->wq = rxq->wq;
+ }
+ rte_flow->ibv_attr = ibv_attr;
+ rte_flow->ind_table = ibv_exp_create_rwq_ind_table(
+ priv->ctx,
+ &(struct ibv_exp_rwq_ind_table_init_attr){
+ .pd = priv->pd,
+ .log_ind_tbl_size = 0,
+ .ind_tbl = &rte_flow->wq,
+ .comp_mask = 0,
+ });
+ if (!rte_flow->ind_table) {
+ rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL, "cannot allocate indirection table");
+ goto error;
+ }
+ rte_flow->qp = ibv_exp_create_qp(
+ priv->ctx,
+ &(struct ibv_exp_qp_init_attr){
+ .qp_type = IBV_QPT_RAW_PACKET,
+ .comp_mask =
+ IBV_EXP_QP_INIT_ATTR_PD |
+ IBV_EXP_QP_INIT_ATTR_PORT |
+ IBV_EXP_QP_INIT_ATTR_RX_HASH,
+ .pd = priv->pd,
+ .rx_hash_conf = &(struct ibv_exp_rx_hash_conf){
+ .rx_hash_function =
+ IBV_EXP_RX_HASH_FUNC_TOEPLITZ,
+ .rx_hash_key_len = rss_hash_default_key_len,
+ .rx_hash_key = rss_hash_default_key,
+ .rx_hash_fields_mask = 0,
+ .rwq_ind_tbl = rte_flow->ind_table,
+ },
+ .port_num = priv->port,
+ });
+ if (!rte_flow->qp) {
+ rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL, "cannot allocate QP");
+ goto error;
+ }
+ rte_flow->ibv_flow = ibv_exp_create_flow(rte_flow->qp,
+ rte_flow->ibv_attr);
+ if (!rte_flow->ibv_flow) {
+ rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ACTION,
+ NULL, "flow rule creation failure");
+ goto error;
+ }
+ return rte_flow;
+error:
+ assert(rte_flow);
+ if (rte_flow->qp)
+ ibv_destroy_qp(rte_flow->qp);
+ if (rte_flow->ind_table)
+ ibv_exp_destroy_rwq_ind_table(rte_flow->ind_table);
+ if (rte_flow->drop && rte_flow->wq)
+ ibv_exp_destroy_wq(rte_flow->wq);
+ if (rte_flow->drop && rte_flow->cq)
+ ibv_destroy_cq(rte_flow->cq);
+ rte_free(rte_flow->ibv_attr);
+ rte_free(rte_flow);
+ return NULL;
+}
+
+/**
+ * Convert a flow.
+ *
+ * @param priv
+ * Pointer to private structure.
+ * @param[in] attr
+ * Flow rule attributes.
+ * @param[in] pattern
+ * Pattern specification (list terminated by the END pattern item).
+ * @param[in] actions
+ * Associated actions (list terminated by the END action).
+ * @param[out] error
+ * Perform verbose error reporting if not NULL.
+ *
+ * @return
+ * a flow on success, null otherwise.
+ */
+static struct rte_flow *
+priv_flow_create(struct priv *priv,
+ const struct rte_flow_attr *attr,
+ const struct rte_flow_item items[],
+ const struct rte_flow_action actions[],
+ struct rte_flow_error *error)
+{
+ struct rte_flow *rte_flow = NULL;
+ struct ibv_exp_flow_attr *ibv_attr;
+ unsigned int flow_size = sizeof(struct ibv_exp_flow_attr);
+ struct action {
+ int queue;
+ int drop;
+ } action;
+ unsigned int queue = MLX5_FLOW_DROP_QUEUE;
+
+ if (priv_flow_validate(priv, attr, items, actions, error))
+ goto exit;
+ ibv_attr = rte_malloc(__func__, flow_size, 0);
+ if (!ibv_attr) {
+ rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE,
+ NULL, "cannot allocate ibv_attr memory");
+ goto exit;
+ }
+ *ibv_attr = (struct ibv_exp_flow_attr){
+ .type = IBV_EXP_FLOW_ATTR_NORMAL,
+ .size = sizeof(struct ibv_exp_flow_attr),
+ .priority = attr->priority,
+ .num_of_specs = 0,
+ .port = 0,
+ .flags = 0,
+ .reserved = 0,
+ };
+ /* Update ibv_flow_spec. */
+ for (; items->type != RTE_FLOW_ITEM_TYPE_END; ++items) {
+ if (items->type == RTE_FLOW_ITEM_TYPE_VOID) {
+ continue;
+ } else if (items->type == RTE_FLOW_ITEM_TYPE_ETH) {
+ struct ibv_exp_flow_spec_eth *eth;
+ unsigned int eth_size =
+ sizeof(struct ibv_exp_flow_spec_eth);
+
+ ibv_attr = rte_realloc(ibv_attr,
+ flow_size + eth_size, 0);
+ if (!ibv_attr)
+ goto error_no_memory;
+ eth = (void *)((uintptr_t)ibv_attr + flow_size);
+ mlx5_flow_create_eth(items, eth);
+ flow_size += eth_size;
+ ++ibv_attr->num_of_specs;
+ ibv_attr->priority = 2;
+ } else if (items->type == RTE_FLOW_ITEM_TYPE_IPV4) {
+ struct ibv_exp_flow_spec_ipv4 *ipv4;
+ unsigned int ipv4_size =
+ sizeof(struct ibv_exp_flow_spec_ipv4);
+
+ ibv_attr = rte_realloc(ibv_attr,
+ flow_size + ipv4_size, 0);
+ if (!ibv_attr)
+ goto error_no_memory;
+ ipv4 = (void *)((uintptr_t)ibv_attr + flow_size);
+ mlx5_flow_create_ipv4(items, ipv4);
+ flow_size += ipv4_size;
+ ++ibv_attr->num_of_specs;
+ ibv_attr->priority = 1;
+ } else if (items->type == RTE_FLOW_ITEM_TYPE_IPV6) {
+ struct ibv_exp_flow_spec_ipv6 *ipv6;
+ unsigned int ipv6_size =
+ sizeof(struct ibv_exp_flow_spec_ipv6);
+
+ ibv_attr = rte_realloc(ibv_attr,
+ flow_size + ipv6_size, 0);
+ if (!ibv_attr)
+ goto error_no_memory;
+ ipv6 = (void *)((uintptr_t)ibv_attr + flow_size);
+ mlx5_flow_create_ipv6(items, ipv6);
+ flow_size += ipv6_size;
+ ++ibv_attr->num_of_specs;
+ ibv_attr->priority = 1;
+ } else if (items->type == RTE_FLOW_ITEM_TYPE_UDP) {
+ struct ibv_exp_flow_spec_tcp_udp *udp;
+ unsigned int udp_size =
+ sizeof(struct ibv_exp_flow_spec_tcp_udp);
+
+ ibv_attr = rte_realloc(ibv_attr,
+ flow_size + udp_size, 0);
+ if (!ibv_attr)
+ goto error_no_memory;
+ udp = (void *)((uintptr_t)ibv_attr + flow_size);
+ mlx5_flow_create_udp(items, udp);
+ flow_size += udp_size;
+ ++ibv_attr->num_of_specs;
+ ibv_attr->priority = 0;
+ } else if (items->type == RTE_FLOW_ITEM_TYPE_TCP) {
+ struct ibv_exp_flow_spec_tcp_udp *tcp;
+ unsigned int tcp_size =
+ sizeof(struct ibv_exp_flow_spec_tcp_udp);
+
+ ibv_attr = rte_realloc(ibv_attr,
+ flow_size + tcp_size, 0);
+ if (!ibv_attr)
+ goto error_no_memory;
+ tcp = (void *)((uintptr_t)ibv_attr + flow_size);
+ mlx5_flow_create_tcp(items, tcp);
+ flow_size += tcp_size;
+ ++ibv_attr->num_of_specs;
+ ibv_attr->priority = 0;
+ } else {
+ /* This default rule should not happen. */
+ rte_free(ibv_attr);
+ rte_flow_error_set(
+ error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
+ items, "unsupported item");
+ goto exit;
+ }
+ }
+ action = (struct action) {
+ .queue = -1,
+ .drop = 0,
+ };
+ for (; actions->type != RTE_FLOW_ACTION_TYPE_END; ++actions) {
+ if (actions->type == RTE_FLOW_ACTION_TYPE_VOID) {
+ continue;
+ } else if (actions->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
+ action.queue = ((const struct rte_flow_action_queue *)
+ actions->conf)->index;
+ } else if (actions->type == RTE_FLOW_ACTION_TYPE_DROP) {
+ action.drop = 1;
+ } else {
+ rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ACTION,
+ actions, "unsupported action");
+ goto exit;
+ }
+ }
+ if (action.queue >= 0) {
+ queue = action.queue;
+ } else if (action.drop) {
+ queue = MLX5_FLOW_DROP_QUEUE;
+ } else {
+ rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ACTION,
+ actions,
+ "no possible action found");
+ goto exit;
+ }
+ rte_flow = priv_flow_create_action_queue(priv, ibv_attr, queue, error);
+ return rte_flow;
+error_no_memory:
+ rte_flow_error_set(error, ENOMEM,
+ RTE_FLOW_ERROR_TYPE_ITEM,
+ items,
+ "cannot allocate memory");
+exit:
+ return NULL;
+}
+
+/**
* Create a flow.
*
* @see rte_flow_create()
@@ -182,12 +827,11 @@ mlx5_flow_create(struct rte_eth_dev *dev,
struct rte_flow *flow;
priv_lock(priv);
- if (priv_flow_validate(priv, attr, items, actions, error)) {
- priv_unlock(priv);
- return NULL;
+ flow = priv_flow_create(priv, attr, items, actions, error);
+ if (flow) {
+ LIST_INSERT_HEAD(&priv->flows, flow, next);
+ DEBUG("Flow created %p", (void *)flow);
}
- flow = rte_malloc(__func__, sizeof(struct rte_flow), 0);
- LIST_INSERT_HEAD(&priv->flows, flow, next);
priv_unlock(priv);
return flow;
}
@@ -206,6 +850,20 @@ priv_flow_destroy(struct priv *priv,
{
(void)priv;
LIST_REMOVE(flow, next);
+ if (flow->ibv_flow)
+ claim_zero(ibv_exp_destroy_flow(flow->ibv_flow));
+ if (flow->qp)
+ claim_zero(ibv_destroy_qp(flow->qp));
+ if (flow->ind_table)
+ claim_zero(
+ ibv_exp_destroy_rwq_ind_table(
+ flow->ind_table));
+ if (flow->drop && flow->wq)
+ claim_zero(ibv_exp_destroy_wq(flow->wq));
+ if (flow->drop && flow->cq)
+ claim_zero(ibv_destroy_cq(flow->cq));
+ rte_free(flow->ibv_attr);
+ DEBUG("Flow destroyed %p", (void *)flow);
rte_free(flow);
}
@@ -235,7 +893,7 @@ mlx5_flow_destroy(struct rte_eth_dev *dev,
* @param priv
* Pointer to private structure.
*/
-void
+static void
priv_flow_flush(struct priv *priv)
{
while (!LIST_EMPTY(&priv->flows)) {
@@ -264,3 +922,54 @@ mlx5_flow_flush(struct rte_eth_dev *dev,
priv_unlock(priv);
return 0;
}
+
+/**
+ * Remove all flows.
+ *
+ * Called by dev_stop() to remove all flows.
+ *
+ * @param priv
+ * Pointer to private structure.
+ */
+void
+priv_flow_remove(struct priv *priv)
+{
+ struct rte_flow *flow;
+
+ for (flow = LIST_FIRST(&priv->flows);
+ flow;
+ flow = LIST_NEXT(flow, next)) {
+ claim_zero(ibv_exp_destroy_flow(flow->ibv_flow));
+ flow->ibv_flow = NULL;
+ DEBUG("Flow %p removed", (void *)flow);
+ }
+}
+
+/**
+ * Add all flows.
+ *
+ * @param priv
+ * Pointer to private structure.
+ *
+ * @return
+ * 0 on success, a errno value otherwise and rte_errno is set.
+ */
+int
+priv_flow_apply(struct priv *priv)
+{
+ struct rte_flow *flow;
+
+ for (flow = LIST_FIRST(&priv->flows);
+ flow;
+ flow = LIST_NEXT(flow, next)) {
+ flow->ibv_flow = ibv_exp_create_flow(flow->qp,
+ flow->ibv_attr);
+ if (!flow->ibv_flow) {
+ DEBUG("Flow %p cannot be applied", (void *)flow);
+ rte_errno = EINVAL;
+ return rte_errno;
+ }
+ DEBUG("Flow %p applied", (void *)flow);
+ }
+ return 0;
+}
diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c
index 4a359d7..e17960e 100644
--- a/drivers/net/mlx5/mlx5_trigger.c
+++ b/drivers/net/mlx5/mlx5_trigger.c
@@ -90,7 +90,9 @@ mlx5_dev_start(struct rte_eth_dev *dev)
if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE)
priv_fdir_enable(priv);
priv_dev_interrupt_handler_install(priv, dev);
- LIST_INIT(&priv->flows);
+ if (LIST_EMPTY(&priv->flows))
+ LIST_INIT(&priv->flows);
+ err = priv_flow_apply(priv);
priv_unlock(priv);
return -err;
}
@@ -121,7 +123,7 @@ mlx5_dev_stop(struct rte_eth_dev *dev)
priv_mac_addrs_disable(priv);
priv_destroy_hash_rxqs(priv);
priv_fdir_disable(priv);
- priv_flow_flush(priv);
+ priv_flow_remove(priv);
priv_dev_interrupt_handler_uninstall(priv, dev);
priv->started = 0;
priv_unlock(priv);
--
2.1.4
^ permalink raw reply related
* [PATCH v2 4/4] net/mlx5: add VLAN filter support in rte_flow
From: Nelio Laranjeiro @ 2016-12-21 10:01 UTC (permalink / raw)
To: dev; +Cc: Adrien Mazarguil
In-Reply-To: <cover.1482314020.git.nelio.laranjeiro@6wind.com>
Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
---
drivers/net/mlx5/mlx5_flow.c | 59 ++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 57 insertions(+), 2 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 44e2fb8..fec1950 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -185,6 +185,9 @@ priv_flow_validate(struct priv *priv,
.dst_port = -1,
},
};
+ const struct rte_flow_item_vlan vlan_mask = {
+ .tci = -1,
+ };
if (attr->group) {
rte_flow_error_set(error, ENOTSUP,
@@ -229,11 +232,32 @@ priv_flow_validate(struct priv *priv,
sizeof(eth_mask));
if (err)
goto exit_item_not_supported;
- } else if (items->type == RTE_FLOW_ITEM_TYPE_IPV4) {
+ } else if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
if (!ilast)
goto exit_item_not_supported;
else if (ilast->type != RTE_FLOW_ITEM_TYPE_ETH)
goto exit_item_not_supported;
+ if (((const struct rte_flow_item_vlan *)items)->tci >
+ ETHER_MAX_VLAN_ID) {
+ rte_flow_error_set(error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ITEM,
+ items,
+ "wrong VLAN tci value");
+ goto exit;
+ }
+ ilast = items;
+ err = mlx5_flow_item_validate(
+ items,
+ (const uint8_t *)&vlan_mask,
+ sizeof(vlan_mask));
+ if (err)
+ goto exit_item_not_supported;
+ } else if (items->type == RTE_FLOW_ITEM_TYPE_IPV4) {
+ if (!ilast)
+ goto exit_item_not_supported;
+ else if (ilast->type != RTE_FLOW_ITEM_TYPE_ETH &&
+ ilast->type != RTE_FLOW_ITEM_TYPE_VLAN)
+ goto exit_item_not_supported;
ilast = items;
err = mlx5_flow_item_validate(
items,
@@ -244,7 +268,8 @@ priv_flow_validate(struct priv *priv,
} else if (items->type == RTE_FLOW_ITEM_TYPE_IPV6) {
if (!ilast)
goto exit_item_not_supported;
- else if (ilast->type != RTE_FLOW_ITEM_TYPE_ETH)
+ else if (ilast->type != RTE_FLOW_ITEM_TYPE_ETH &&
+ ilast->type != RTE_FLOW_ITEM_TYPE_VLAN)
goto exit_item_not_supported;
ilast = items;
err = mlx5_flow_item_validate(
@@ -376,6 +401,28 @@ mlx5_flow_create_eth(const struct rte_flow_item *item,
}
/**
+ * Convert VLAN item to Verbs specification.
+ *
+ * @param item[in]
+ * Item specification.
+ * @param eth[in, out]
+ * Verbs Ethernet specification structure.
+ */
+static void
+mlx5_flow_create_vlan(const struct rte_flow_item *item,
+ struct ibv_exp_flow_spec_eth *eth)
+{
+ const struct rte_flow_item_vlan *spec = item->spec;
+ const struct rte_flow_item_vlan *mask = item->mask;
+
+ if (spec)
+ eth->val.vlan_tag = spec->tci;
+ if (mask)
+ eth->mask.vlan_tag = mask->tci;
+ eth->val.vlan_tag &= eth->mask.vlan_tag;
+}
+
+/**
* Convert IPv4 item to Verbs specification.
*
* @param item[in]
@@ -704,6 +751,14 @@ priv_flow_create(struct priv *priv,
flow_size += eth_size;
++ibv_attr->num_of_specs;
ibv_attr->priority = 2;
+ } else if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
+ struct ibv_exp_flow_spec_eth *eth;
+ unsigned int eth_size =
+ sizeof(struct ibv_exp_flow_spec_eth);
+
+ eth = (void *)((uintptr_t)ibv_attr + flow_size -
+ eth_size);
+ mlx5_flow_create_vlan(items, eth);
} else if (items->type == RTE_FLOW_ITEM_TYPE_IPV4) {
struct ibv_exp_flow_spec_ipv4 *ipv4;
unsigned int ipv4_size =
--
2.1.4
^ permalink raw reply related
* Re: [PATCH 2/2] net/ixgbe: calculate correct number of received packets for ARM NEON-version vPMD
From: Jerin Jacob @ 2016-12-21 10:08 UTC (permalink / raw)
To: Jianbo Liu; +Cc: dev, helin.zhang, konstantin.ananyev
In-Reply-To: <1482127758-4904-2-git-send-email-jianbo.liu@linaro.org>
On Mon, Dec 19, 2016 at 11:39:18AM +0530, Jianbo Liu wrote:
Hi Jianbo,
> vPMD will check 4 descriptors in one time, but the statuses are not consistent
> because the memory allocated for RX descriptors is cacheable huagepage.
Is it different in X86 case ?i.e Is x86 creating non cacheable hugepages?
I am just looking at what it takes to fix similar issues for all drivers wrt armv8.
Are you able to reproduce this issue any armv8 platform. If so, could
you please the platform detail and commands to reproduce this issue?
> This patch is to calculate the number of received packets by scanning DD bit
> sequentially, and stops when meeting the first packet with DD bit unset.
>
> Signed-off-by: Jianbo Liu <jianbo.liu@linaro.org>
> ---
> drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c b/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c
> index f96cc85..0b1338d 100644
> --- a/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c
> +++ b/drivers/net/ixgbe/ixgbe_rxtx_vec_neon.c
> @@ -196,7 +196,6 @@ _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
> struct ixgbe_rx_entry *sw_ring;
> uint16_t nb_pkts_recd;
> int pos;
> - uint64_t var;
> uint8x16_t shuf_msk = {
> 0xFF, 0xFF,
> 0xFF, 0xFF, /* skip 32 bits pkt_type */
> @@ -255,6 +254,7 @@ _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
> uint64x2_t mbp1, mbp2;
> uint8x16_t staterr;
> uint16x8_t tmp;
> + uint32_t var = 0;
> uint32_t stat;
>
> /* B.1 load 1 mbuf point */
> @@ -349,11 +349,19 @@ _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
> vst1q_u8((uint8_t *)&rx_pkts[pos]->rx_descriptor_fields1,
> pkt_mb1);
>
> + stat &= IXGBE_VPMD_DESC_DD_MASK;
> +
> /* C.4 calc avaialbe number of desc */
> - var = __builtin_popcount(stat & IXGBE_VPMD_DESC_DD_MASK);
> - nb_pkts_recd += var;
> - if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
> + if (likely(var != IXGBE_VPMD_DESC_DD_MASK)) {
> + while (stat & 0x01) {
> + ++var;
> + stat = stat >> 8;
> + }
> + nb_pkts_recd += var;
> break;
> + } else {
> + nb_pkts_recd += RTE_IXGBE_DESCS_PER_LOOP;
> + }
> }
>
> /* Update our internal tail pointer */
> --
> 2.4.11
>
^ permalink raw reply
* Re: dpdk.org server maintenance
From: Thomas Monjalon @ 2016-12-21 10:17 UTC (permalink / raw)
To: dev, users
In-Reply-To: <1812633.288nILBVBH@xps13>
2016-12-19 15:52, Thomas Monjalon:
> Hi all,
>
> On Wednesday December 21, 2016, between 6:00 and 9:00 UTC, there will be
> an upgrade of our hosting platform.
> Unfortunately it is announced a downtime of an hour or more.
> It will affect every hosted services: web, mail, git, patchwork.
>
> It is unavoidable so we will have to be patient.
There was no disturbance in the Force as the operation has been cancelled :)
Hard to predict hosting service operations, is it. Yes hmmm
^ permalink raw reply
* Re: [PATCH 24/29] net/ixgbe/base: add EEE support for DNL-controlled PHYs
From: Dai, Wei @ 2016-12-21 10:17 UTC (permalink / raw)
To: Yigit, Ferruh, Zhang, Helin, Ananyev, Konstantin; +Cc: dev@dpdk.org
In-Reply-To: <b38677f7-67a0-89c8-8813-09a8586d885c@intel.com>
> -----Original Message-----
> From: Yigit, Ferruh
> Sent: Tuesday, December 6, 2016 3:41 AM
> To: Dai, Wei <wei.dai@intel.com>; Zhang, Helin <helin.zhang@intel.com>;
> Ananyev, Konstantin <konstantin.ananyev@intel.com>
> Cc: dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 24/29] net/ixgbe/base: add EEE support for
> DNL-controlled PHYs
>
> On 12/4/2016 6:31 AM, Wei Dai wrote:
> > This patch adds EEE support for DNL-controlled PHYs. Because DNL
>
> What is DNL?
DNL is short for name of some method to control Marvel PHY.
This git log message will be revised in v2 patch set.
>
> > does not indicate EEE capability or status, this patch simply assumes
> > that it is supported. As soon as there is a DNL-supported PHY that
> > does not support EEE, there will be defects in this area because the
> > driver will not report the EEE status correctly.
> > This also deletes some now-unused definitions from an earlier Marvell
> > PHY implementation and combines a device ID check into a switch
> > statement.
> >
> > Signed-off-by: Wei Dai <wei.dai@intel.com>
> > ---
> > drivers/net/ixgbe/base/ixgbe_type.h | 8 --------
> > drivers/net/ixgbe/base/ixgbe_x550.c | 15 +++++++--------
> > 2 files changed, 7 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/net/ixgbe/base/ixgbe_type.h
> > b/drivers/net/ixgbe/base/ixgbe_type.h
> > index 9ec17a9..f1761a3 100644
> > --- a/drivers/net/ixgbe/base/ixgbe_type.h
> > +++ b/drivers/net/ixgbe/base/ixgbe_type.h
> > @@ -3720,14 +3720,6 @@ enum ixgbe_fc_mode {
> > ixgbe_fc_default
> > };
> >
> > -/* Master/slave control */
> > -enum ixgbe_ms_type {
> > - ixgbe_ms_hw_default = 0,
> > - ixgbe_ms_force_master,
> > - ixgbe_ms_force_slave,
> > - ixgbe_ms_auto
> > -};
> > -
>
> This seems not related to this patchset, also patch 15/29 has [1] again seems
> unrelated to that patch, does it make sense to make these a separate patch?
Yes, in v2 patch set, removing of above enum type will be in a separate one.
>
> [1]
> "
> @@ -4046,8 +4112,8 @@ struct ixgbe_phy_info {
> bool reset_disable;
> ixgbe_autoneg_advertised autoneg_advertised;
> ixgbe_link_speed speeds_supported;
> - enum ixgbe_ms_type ms_type;
> - enum ixgbe_ms_type original_ms_type;
>
>
^ permalink raw reply
* Re: [PATCH 27/29] net/ixgbe/base: add write flush required by Inphi
From: Dai, Wei @ 2016-12-21 10:31 UTC (permalink / raw)
To: Yigit, Ferruh, Zhang, Helin, Ananyev, Konstantin; +Cc: dev@dpdk.org
In-Reply-To: <10604e95-4011-00d4-cc4f-42bf0feacf3d@intel.com>
> -----Original Message-----
> From: Yigit, Ferruh
> Sent: Tuesday, December 6, 2016 3:41 AM
> To: Dai, Wei <wei.dai@intel.com>; Zhang, Helin <helin.zhang@intel.com>;
> Ananyev, Konstantin <konstantin.ananyev@intel.com>
> Cc: dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 27/29] net/ixgbe/base: add write flush required
> by Inphi
>
> On 12/4/2016 6:31 AM, Wei Dai wrote:
> > This patch updates Inphi configuration to flush the register write
> > with
>
> Do we really need to mention from Inphi here? If so, can you please explain
> what it is?
Inphi (www.inphi.com) is a company which provides PHYs.
So I will use "Inphi PHY" instead of "Inphi" in v2 patch set.
>
> > a reg read. Inphi is configured in ixgbe_setup_mac_link_sfp_x550a.
> > The Inphy setup flow has been updated to read configuration reg, write
> > only linear/non-linear, and then read (write flush).
>
> Also patch does [1] seems not mentioned in the commit log, can you please add
> information for it?
Yes, following statement is redundant, but in order to simplify the process to
keep up with the shared code provided by another team (Intel Network Division),
I'd like to keep it here. Anyway it is harmless.
>
> [1]
> > + reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
> > + (IXGBE_CS4227_EDC_MODE_SR << 1));
>
> >
> > Signed-off-by: Wei Dai <wei.dai@intel.com>
> > ---
> > drivers/net/ixgbe/base/ixgbe_x550.c | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c
> > b/drivers/net/ixgbe/base/ixgbe_x550.c
> > index 4a98530..a57ba74 100644
> > --- a/drivers/net/ixgbe/base/ixgbe_x550.c
> > +++ b/drivers/net/ixgbe/base/ixgbe_x550.c
> > @@ -2834,12 +2834,26 @@ s32 ixgbe_setup_mac_link_sfp_x550a(struct
> > ixgbe_hw *hw,
> >
> > /* Configure CS4227/CS4223 LINE side to proper mode. */
> > reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
> > +
> > + ret_val = hw->phy.ops.read_reg(hw, reg_slice,
> > + IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
> > +
> > + if (ret_val != IXGBE_SUCCESS)
> > + return ret_val;
> > +
> > + reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
> > + (IXGBE_CS4227_EDC_MODE_SR << 1));
> > +
> > if (setup_linear)
> > reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
> > else
> > reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
> > ret_val = hw->phy.ops.write_reg(hw, reg_slice,
> > IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
> > +
> > + /* Flush previous write with a read */
> > + ret_val = hw->phy.ops.read_reg(hw, reg_slice,
> > + IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
> > }
> > return ret_val;
> > }
> >
^ permalink raw reply
* Re: [PATCH 29/29] net/ixgbe/base: update version of basical codes in README
From: Dai, Wei @ 2016-12-21 10:32 UTC (permalink / raw)
To: Yigit, Ferruh, Zhang, Helin, Ananyev, Konstantin; +Cc: dev@dpdk.org
In-Reply-To: <910f9ad0-9e06-3152-4c1a-a6b3d5111f7f@intel.com>
Thanks for your correcting.
> -----Original Message-----
> From: Yigit, Ferruh
> Sent: Tuesday, December 6, 2016 3:41 AM
> To: Dai, Wei <wei.dai@intel.com>; Zhang, Helin <helin.zhang@intel.com>;
> Ananyev, Konstantin <konstantin.ananyev@intel.com>
> Cc: dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 29/29] net/ixgbe/base: update version of basical
> codes in README
>
> On 12/4/2016 6:31 AM, Wei Dai wrote:
> > update the version of shared codes to cid-ixgbe.2016.11.21.tar.gz, all
> > files in net/ixgbe/base are developped by another team and DPDK PMD
> > uses them accordingly.
> >
> > Signed-off-by: Wei Dai <wei.dai@intel.com>
> > ---
> > drivers/net/ixgbe/base/README | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/ixgbe/base/README
> > b/drivers/net/ixgbe/base/README index 6b54c31..84773ff 100644
> > --- a/drivers/net/ixgbe/base/README
> > +++ b/drivers/net/ixgbe/base/README
> > @@ -34,7 +34,8 @@ Intel® IXGBE driver
> > ===================
> >
> > This directory contains source code of FreeBSD ixgbe driver of
> > version
> > -cid-10g-shared-code.2016.08.15 released by ND. The sub-directory of
> > base/
> > +cid-10g-shared-code.2016.08.15 released by the team which develop
>
> I guess version needs to be updated to 2016.11.21 ?
Yes, it should be 2016.11.21.
It will be corrected in v2 patch.
>
> > +basical drivers for any ixgbe NIC. The sub-directory of base/
> > contains the original source package.
> > This driver is valid for the product(s) listed below
> >
> >
^ permalink raw reply
* Re: [PATCH v4 02/25] doc: add rte_flow prog guide
From: Mcnamara, John @ 2016-12-21 10:55 UTC (permalink / raw)
To: Adrien Mazarguil, dev@dpdk.org
In-Reply-To: <016063c97ffac7b759ded3d075abb960c97c450d.1482257521.git.adrien.mazarguil@6wind.com>
Hi Adrien,
You missed out the changes I suggested to the table_rte_flow_migration_fdir
which means that the pdf build is still broken. Also, the changes to
table_rte_flow_migration_l2tunnel also break the PDF bulid.
You can test as follows:
make doc-guides-pdf -j
I'd suggest the following tables which retain the information and format
that you are trying to achieve but which should compile:
.. _table_rte_flow_migration_fdir:
.. table:: FDIR conversion
+----------------------------------------+-----------------------+
| Pattern | Actions |
+===+===================+==========+=====+=======================+
| 0 | ETH, RAW | ``spec`` | any | QUEUE, DROP, PASSTHRU |
| | +----------+-----+ |
| | | ``last`` | N/A | |
| | +----------+-----+ |
| | | ``mask`` | any | |
+---+-------------------+----------+-----+-----------------------+
| 1 | IPV4, IPv6 | ``spec`` | any | MARK |
| | +----------+-----+ |
| | | ``last`` | N/A | |
| | +----------+-----+ |
| | | ``mask`` | any | |
+---+-------------------+----------+-----+-----------------------+
| 2 | TCP, UDP, SCTP | ``spec`` | any | END |
| | +----------+-----+ |
| | | ``last`` | N/A | |
| | +----------+-----+ |
| | | ``mask`` | any | |
+---+-------------------+----------+-----+ |
| 3 | VF, PF (optional) | ``spec`` | any | |
| | +----------+-----+ |
| | | ``last`` | N/A | |
| | +----------+-----+ |
| | | ``mask`` | any | |
+---+-------------------+----------+-----+ |
| 4 | END | |
+---+------------------------------------+-----------------------+
.. _table_rte_flow_migration_l2tunnel:
.. table:: L2_TUNNEL conversion
+---------------------------+--------------------+
| Pattern | Actions |
+===+======+==========+=====+====================+
| 0 | VOID | ``spec`` | N/A | VXLAN, GENEVE, ... |
| | | | | |
| | | | | |
| | +----------+-----+ |
| | | ``last`` | N/A | |
| | +----------+-----+ |
| | | ``mask`` | N/A | |
| | | | | |
+---+------+----------+-----+--------------------+
| 1 | END | VF (optional) |
+---+ +--------------------+
| 2 | | END |
+---+-----------------------+--------------------+
^ permalink raw reply
* Re: [PATCH 2/2] net/ixgbe: calculate correct number of received packets for ARM NEON-version vPMD
From: Bruce Richardson @ 2016-12-21 11:03 UTC (permalink / raw)
To: Jerin Jacob; +Cc: Jianbo Liu, dev, helin.zhang, konstantin.ananyev
In-Reply-To: <20161221100848.GA4506@localhost.localdomain>
On Wed, Dec 21, 2016 at 03:38:51PM +0530, Jerin Jacob wrote:
> On Mon, Dec 19, 2016 at 11:39:18AM +0530, Jianbo Liu wrote:
>
> Hi Jianbo,
>
> > vPMD will check 4 descriptors in one time, but the statuses are not consistent
> > because the memory allocated for RX descriptors is cacheable huagepage.
> Is it different in X86 case ?i.e Is x86 creating non cacheable hugepages?
This is not a problem on IA, because the instruction ordering rules on
IA guarantee that the reads will be done in the correct program order,
and we never get stale cache data.
/Bruce
^ permalink raw reply
* Re: [PATCH v3] app/testpmd: supported offload capabilities query
From: Yang, Qiming @ 2016-12-21 11:09 UTC (permalink / raw)
To: Yuanhan Liu; +Cc: dev@dpdk.org, Wu, Jingjing
In-Reply-To: <20161221023718.GU18991@yliu-dev.sh.intel.com>
That's a good advice. Thanks.
-----Original Message-----
From: Yuanhan Liu [mailto:yuanhan.liu@linux.intel.com]
Sent: Wednesday, December 21, 2016 10:37 AM
To: Yang, Qiming <qiming.yang@intel.com>
Cc: dev@dpdk.org; Wu, Jingjing <jingjing.wu@intel.com>
Subject: Re: [dpdk-dev] [PATCH v3] app/testpmd: supported offload capabilities query
On Wed, Dec 21, 2016 at 10:20:26AM +0800, Qiming Yang wrote:
> Add two new commands "show port capa <port>" and "show
I think 'cap' is a more well-known shortening for capability than "capa"?
--yliu
^ permalink raw reply
* Re: [PATCH v4 02/25] doc: add rte_flow prog guide
From: Adrien Mazarguil @ 2016-12-21 11:31 UTC (permalink / raw)
To: Mcnamara, John; +Cc: dev@dpdk.org
In-Reply-To: <B27915DBBA3421428155699D51E4CFE20268B562@IRSMSX103.ger.corp.intel.com>
Hi John,
On Wed, Dec 21, 2016 at 10:55:39AM +0000, Mcnamara, John wrote:
> Hi Adrien,
>
> You missed out the changes I suggested to the table_rte_flow_migration_fdir
> which means that the pdf build is still broken. Also, the changes to
> table_rte_flow_migration_l2tunnel also break the PDF bulid.
>
> You can test as follows:
>
> make doc-guides-pdf -j
OK, I'm unable to generate pdf documentation on my setup even though I've
installed the dependencies, I usually rely on HTML output only, that's why I
did not see the remaining issue.
> I'd suggest the following tables which retain the information and format
> that you are trying to achieve but which should compile:
>
> .. _table_rte_flow_migration_fdir:
>
> .. table:: FDIR conversion
>
> +----------------------------------------+-----------------------+
> | Pattern | Actions |
> +===+===================+==========+=====+=======================+
> | 0 | ETH, RAW | ``spec`` | any | QUEUE, DROP, PASSTHRU |
> | | +----------+-----+ |
> | | | ``last`` | N/A | |
> | | +----------+-----+ |
> | | | ``mask`` | any | |
> +---+-------------------+----------+-----+-----------------------+
> | 1 | IPV4, IPv6 | ``spec`` | any | MARK |
> | | +----------+-----+ |
> | | | ``last`` | N/A | |
> | | +----------+-----+ |
> | | | ``mask`` | any | |
> +---+-------------------+----------+-----+-----------------------+
> | 2 | TCP, UDP, SCTP | ``spec`` | any | END |
> | | +----------+-----+ |
> | | | ``last`` | N/A | |
> | | +----------+-----+ |
> | | | ``mask`` | any | |
> +---+-------------------+----------+-----+ |
> | 3 | VF, PF (optional) | ``spec`` | any | |
> | | +----------+-----+ |
> | | | ``last`` | N/A | |
> | | +----------+-----+ |
> | | | ``mask`` | any | |
> +---+-------------------+----------+-----+ |
> | 4 | END | |
> +---+------------------------------------+-----------------------+
>
>
> .. _table_rte_flow_migration_l2tunnel:
>
> .. table:: L2_TUNNEL conversion
>
> +---------------------------+--------------------+
> | Pattern | Actions |
> +===+======+==========+=====+====================+
> | 0 | VOID | ``spec`` | N/A | VXLAN, GENEVE, ... |
> | | | | | |
> | | | | | |
> | | +----------+-----+ |
> | | | ``last`` | N/A | |
> | | +----------+-----+ |
> | | | ``mask`` | N/A | |
> | | | | | |
> +---+------+----------+-----+--------------------+
> | 1 | END | VF (optional) |
> +---+ +--------------------+
> | 2 | | END |
> +---+-----------------------+--------------------+
No problem, I'll include those changes along with a remaining bugfix and
testpmd support for additional protocol fields (requested by several
people). Brace yourself for v5!
Thanks for all the reviews.
--
Adrien Mazarguil
6WIND
^ permalink raw reply
* Re: [PATCH v3] drivers: advertise kmod dependencies in pmdinfo
From: Neil Horman @ 2016-12-21 11:37 UTC (permalink / raw)
To: Andrew Rybchenko
Cc: Thomas Monjalon, Olivier Matz, Adrien Mazarguil, dev, vido,
fiona.trahe, stephen
In-Reply-To: <96cb80d2-d0ff-b233-3e0a-226f0ec6109a@solarflare.com>
On Wed, Dec 21, 2016 at 12:21:14PM +0300, Andrew Rybchenko wrote:
> On 12/20/2016 08:26 PM, Thomas Monjalon wrote:
> > > > Add a new macro RTE_PMD_REGISTER_KMOD_DEP() that allows a driver to
> > > > declare the list of kernel modules required to run properly.
> > > >
> > > > Today, most PCI drivers require uio/vfio.
> > > >
> > > > Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
> > > > Acked-by: Fiona Trahe <fiona.trahe@intel.com>
> > > Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
> > Applied in main tree, thanks
>
> Is there any plan on how it will be done/solved for a new drivers in
> dpdk-next-net?
> Should I care about it for sfc?
>
Given that all pmdinfo information is opt-in (that is to say not obligatory),
you can now wait until net-next does its next rebase, and as you continue your
development of the sfc driver, you can add the use of this macro in at your
leisure. As more people do that, we will arrive at 100% coverage
Neil
> Andrew.
>
>
^ permalink raw reply
* Re: [PATCH v3] drivers: advertise kmod dependencies in pmdinfo
From: Andrew Rybchenko @ 2016-12-21 11:40 UTC (permalink / raw)
To: Neil Horman
Cc: Thomas Monjalon, Olivier Matz, Adrien Mazarguil, dev, vido,
fiona.trahe, stephen
In-Reply-To: <20161221113702.GA23197@hmsreliant.think-freely.org>
On 12/21/2016 02:37 PM, Neil Horman wrote:
> On Wed, Dec 21, 2016 at 12:21:14PM +0300, Andrew Rybchenko wrote:
>> On 12/20/2016 08:26 PM, Thomas Monjalon wrote:
>>>>> Add a new macro RTE_PMD_REGISTER_KMOD_DEP() that allows a driver to
>>>>> declare the list of kernel modules required to run properly.
>>>>>
>>>>> Today, most PCI drivers require uio/vfio.
>>>>>
>>>>> Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
>>>>> Acked-by: Fiona Trahe <fiona.trahe@intel.com>
>>>> Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
>>> Applied in main tree, thanks
>> Is there any plan on how it will be done/solved for a new drivers in
>> dpdk-next-net?
>> Should I care about it for sfc?
>>
> Given that all pmdinfo information is opt-in (that is to say not obligatory),
> you can now wait until net-next does its next rebase, and as you continue your
> development of the sfc driver, you can add the use of this macro in at your
> leisure. As more people do that, we will arrive at 100% coverage
I see. Will do. Thanks.
Andrew.
> Neil
>
>> Andrew.
>>
>>
^ permalink raw reply
* Re: [PATCH 0/3] Add DES capability to Intel QuickAssist Technology driver
From: Trahe, Fiona @ 2016-12-21 11:47 UTC (permalink / raw)
To: Kusztal, ArkadiuszX, dev@dpdk.org
Cc: De Lara Guarch, Pablo, Griffin, John, Jain, Deepak K
In-Reply-To: <1480688162-27474-1-git-send-email-arkadiuszx.kusztal@intel.com>
> -----Original Message-----
> From: Kusztal, ArkadiuszX
> Sent: Friday, December 2, 2016 2:16 PM
> To: dev@dpdk.org
> Cc: Trahe, Fiona <fiona.trahe@intel.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; Griffin, John <john.griffin@intel.com>;
> Jain, Deepak K <deepak.k.jain@intel.com>; Kusztal, ArkadiuszX
> <arkadiuszx.kusztal@intel.com>
> Subject: [PATCH 0/3] Add DES capability to Intel QuickAssist Technology driver
>
> This patchset adds Data Encryption Standard (DES) capability to Intel
> QuickAssist
> Technology driver and corresponding tests to test files.
>
> Arek Kusztal (3):
> lib/librte_cryptodev: add DES CBC cipher algorithm
> crypto/qat: add DES capability to Intel QAT driver
> app/test: add DES tests to Intel QAT crypto test suite
>
> app/test/test_cryptodev.c | 18 ++++
> app/test/test_cryptodev_blockcipher.c | 5 ++
> app/test/test_cryptodev_blockcipher.h | 3 +-
> app/test/test_cryptodev_des_test_vectors.h | 110
> +++++++++++++++++++++++
> doc/guides/cryptodevs/qat.rst | 1 +
> doc/guides/rel_notes/release_17_02.rst | 6 ++
> drivers/crypto/qat/qat_adf/qat_algs.h | 1 +
> drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 16 ++++
> drivers/crypto/qat/qat_crypto.c | 29 +++++-
> lib/librte_cryptodev/rte_crypto_sym.h | 4 +
> 10 files changed, 191 insertions(+), 2 deletions(-)
>
> --
> 2.1.0
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
^ permalink raw reply
* Re: [PATCH 2/3] crypto/qat: add DES capability to Intel QAT driver
From: Trahe, Fiona @ 2016-12-21 11:49 UTC (permalink / raw)
To: Kusztal, ArkadiuszX, dev@dpdk.org
Cc: De Lara Guarch, Pablo, Griffin, John, Jain, Deepak K
In-Reply-To: <1480688162-27474-3-git-send-email-arkadiuszx.kusztal@intel.com>
> -----Original Message-----
> From: Kusztal, ArkadiuszX
> Sent: Friday, December 2, 2016 2:16 PM
> To: dev@dpdk.org
> Cc: Trahe, Fiona <fiona.trahe@intel.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; Griffin, John <john.griffin@intel.com>;
> Jain, Deepak K <deepak.k.jain@intel.com>; Kusztal, ArkadiuszX
> <arkadiuszx.kusztal@intel.com>
> Subject: [PATCH 2/3] crypto/qat: add DES capability to Intel QAT driver
>
> This commit adds DES capability to Intel QuickAssist
> Technology Driver
>
> Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
^ permalink raw reply
* Re: [PATCH 3/3] app/test: add DES tests to Intel QAT crypto test suite
From: Trahe, Fiona @ 2016-12-21 11:49 UTC (permalink / raw)
To: Kusztal, ArkadiuszX, dev@dpdk.org
Cc: De Lara Guarch, Pablo, Griffin, John, Jain, Deepak K
In-Reply-To: <1480688162-27474-4-git-send-email-arkadiuszx.kusztal@intel.com>
> -----Original Message-----
> From: Kusztal, ArkadiuszX
> Sent: Friday, December 2, 2016 2:16 PM
> To: dev@dpdk.org
> Cc: Trahe, Fiona <fiona.trahe@intel.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; Griffin, John <john.griffin@intel.com>;
> Jain, Deepak K <deepak.k.jain@intel.com>; Kusztal, ArkadiuszX
> <arkadiuszx.kusztal@intel.com>
> Subject: [PATCH 3/3] app/test: add DES tests to Intel QAT crypto test suite
>
> This commit adds tests of Data Encryption Standard (DES)
> algorithm to Intel QuickAssist technology crypto test suites
>
> Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
^ permalink raw reply
* Re: [PATCH 1/3] lib/librte_cryptodev: add DES CBC cipher algorithm
From: Trahe, Fiona @ 2016-12-21 11:49 UTC (permalink / raw)
To: Kusztal, ArkadiuszX, dev@dpdk.org
Cc: De Lara Guarch, Pablo, Griffin, John, Jain, Deepak K
In-Reply-To: <1480688162-27474-2-git-send-email-arkadiuszx.kusztal@intel.com>
> -----Original Message-----
> From: Kusztal, ArkadiuszX
> Sent: Friday, December 2, 2016 2:16 PM
> To: dev@dpdk.org
> Cc: Trahe, Fiona <fiona.trahe@intel.com>; De Lara Guarch, Pablo
> <pablo.de.lara.guarch@intel.com>; Griffin, John <john.griffin@intel.com>;
> Jain, Deepak K <deepak.k.jain@intel.com>; Kusztal, ArkadiuszX
> <arkadiuszx.kusztal@intel.com>
> Subject: [PATCH 1/3] lib/librte_cryptodev: add DES CBC cipher algorithm
>
> This commit adds DES CBC ciper algorithm to available algorithms
>
> Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
^ permalink raw reply
* Re: [PATCH RFC 0/2] Allow vectorized Rx with 4096 desc ring size on Intel NICs.
From: Ilya Maximets @ 2016-12-21 12:33 UTC (permalink / raw)
To: Ferruh Yigit, dev, Helin Zhang, Konstantin Ananyev, Jingjing Wu
Cc: Heetae Ahn, Bruce Richardson, Wenzhuo Lu
In-Reply-To: <10330ae4-55fb-7ee0-0263-ad684ad2b931@intel.com>
Ping.
Best regards, Ilya Maximets.
On 21.11.2016 16:53, Ferruh Yigit wrote:
> On 10/19/2016 3:30 PM, Ferruh Yigit wrote:
>> On 10/19/2016 3:07 PM, Ilya Maximets wrote:
>>> Ilya Maximets (2):
>>> net/i40e: allow bulk alloc for the max size desc ring
>>> net/ixgbe: allow bulk alloc for the max size desc ring
>>>
>>> drivers/net/i40e/i40e_rxtx.c | 24 +++++++++++++-----------
>>> drivers/net/ixgbe/ixgbe_rxtx.c | 17 +----------------
>>> drivers/net/ixgbe/ixgbe_rxtx.h | 2 +-
>>> 3 files changed, 15 insertions(+), 28 deletions(-)
>>>
>>
>> Hi Ilya,
>>
>> Thank you for the patch, we are in post rc1 phase and this is a new
>> feature, so this patchset will be considered for next release (v17.02).
>>
>
> Reminder for this patch (RFC) which has been sent in 16.11 time frame
> and we postponed to 17.02 release.
>
> Thanks,
> ferruh
>
>
>
^ permalink raw reply
* Re: [PATCH 6/8] crypto/dpaa2_sec: add sec procssing functionality
From: De Lara Guarch, Pablo @ 2016-12-21 12:39 UTC (permalink / raw)
To: Akhil Goyal, dev@dpdk.org
Cc: thomas.monjalon@6wind.com, eclan.doherty@intel.com,
hemant.agrawal@nxp.com
In-Reply-To: <20161205125540.6419-7-akhil.goyal@nxp.com>
> -----Original Message-----
> From: Akhil Goyal [mailto:akhil.goyal@nxp.com]
> Sent: Monday, December 05, 2016 12:56 PM
> To: dev@dpdk.org
> Cc: thomas.monjalon@6wind.com; eclan.doherty@intel.com; De Lara
> Guarch, Pablo; hemant.agrawal@nxp.com; Akhil Goyal
> Subject: [PATCH 6/8] crypto/dpaa2_sec: add sec procssing functionality
>
> Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
> Reviewed-by: Hemant Agrawal <hemant.agrawal@nxp.com>
> ---
> config/defconfig_arm64-dpaa2-linuxapp-gcc | 6 +
> drivers/crypto/dpaa2_sec/Makefile | 1 -
> drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 1337
> +++++++++++++++++++++++++++
> drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h | 516 +++++++++++
> drivers/net/dpaa2/base/dpaa2_hw_pvt.h | 25 +
For the whole patch, there are some checkpatch errors that you should fix for the v2:
http://dpdk.org/ml/archives/test-report/2016-December/005244.html
Make sure that you fix also the other patches.
Also, a comment below about the capabilities structure.
Thanks,
Pablo
> diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h
> b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h
> new file mode 100644
> index 0000000..01fae77
> --- /dev/null
> +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h
> @@ -0,0 +1,516 @@
...
As far as I could see, this PMD supports AES-CBC, 3DES-CBC and SHA1 and SHA2 with HMAC algorithms,
but you are including here more algorithms that this PMD looks like does not support (such as AES XCBC, GCM, etc...)
> + { /* AES XCBC MAC */
> + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> + {.sym = {
> + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
> + {.auth = {
> + .algo =
> RTE_CRYPTO_AUTH_AES_XCBC_MAC,
> + .block_size = 16,
> + .key_size = {
> + .min = 16,
> + .max = 16,
> + .increment = 0
> + },
> + .digest_size = {
> + .min = 16,
> + .max = 16,
> + .increment = 0
> + },
> + .aad_size = { 0 }
> + }, }
> + }, }
> + },
^ permalink raw reply
* Re: [PATCH 6/8] crypto/dpaa2_sec: add sec procssing functionality
From: Akhil Goyal @ 2016-12-21 12:45 UTC (permalink / raw)
To: De Lara Guarch, Pablo, dev@dpdk.org
Cc: thomas.monjalon@6wind.com, Hemant Agrawal,
declan.doherty@intel.com
In-Reply-To: <E115CCD9D858EF4F90C690B0DCB4D897476B7882@IRSMSX108.ger.corp.intel.com>
> -----Original Message-----
> From: Akhil Goyal [mailto:akhil.goyal@nxp.com]
> Sent: Monday, December 05, 2016 12:56 PM
> To: dev@dpdk.org
> Cc: thomas.monjalon@6wind.com; eclan.doherty@intel.com; De Lara
> Guarch, Pablo; hemant.agrawal@nxp.com; Akhil Goyal
> Subject: [PATCH 6/8] crypto/dpaa2_sec: add sec procssing functionality
>
> Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
> Reviewed-by: Hemant Agrawal <hemant.agrawal@nxp.com>
> ---
> config/defconfig_arm64-dpaa2-linuxapp-gcc | 6 +
> drivers/crypto/dpaa2_sec/Makefile | 1 -
> drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 1337
> +++++++++++++++++++++++++++
> drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h | 516 +++++++++++
> drivers/net/dpaa2/base/dpaa2_hw_pvt.h | 25 +
For the whole patch, there are some checkpatch errors that you should fix for the v2:
http://dpdk.org/ml/archives/test-report/2016-December/005244.html
[Akhil] ok. Will try to resolve as much as I could.
Make sure that you fix also the other patches.
[Akhil] ok
Also, a comment below about the capabilities structure.
Thanks,
Pablo
> diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h
> b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h
> new file mode 100644
> index 0000000..01fae77
> --- /dev/null
> +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h
> @@ -0,0 +1,516 @@
...
As far as I could see, this PMD supports AES-CBC, 3DES-CBC and SHA1 and SHA2 with HMAC algorithms,
but you are including here more algorithms that this PMD looks like does not support (such as AES XCBC, GCM, etc...)
[Akhil] ok I will remove it for now. It will be added in future.
> + { /* AES XCBC MAC */
> + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
> + {.sym = {
> + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
> + {.auth = {
> + .algo =
> RTE_CRYPTO_AUTH_AES_XCBC_MAC,
> + .block_size = 16,
> + .key_size = {
> + .min = 16,
> + .max = 16,
> + .increment = 0
> + },
> + .digest_size = {
> + .min = 16,
> + .max = 16,
> + .increment = 0
> + },
> + .aad_size = { 0 }
> + }, }
> + }, }
> + },
^ permalink raw reply
* Re: [PATCH] rte_eal: clarify the argc and argv documentation
From: Thomas Monjalon @ 2016-12-21 14:24 UTC (permalink / raw)
To: Aaron Conole; +Cc: dev
In-Reply-To: <1481212605-3857-1-git-send-email-aconole@redhat.com>
2016-12-08 10:56, Aaron Conole:
> It's been a source of confusion in the past, and even with this update
> may continue to be a source of confusion. However, the original
> language seems to imply that the DPDK EAL will take ownership of the
> array passed in. Loosening the language up a bit might give a better
> understanding for what is actually happening.
>
> Signed-off-by: Aaron Conole <aconole@redhat.com>
Applied, thanks
^ permalink raw reply
* Re: [PATCH v4] eal: restrict cores auto detection
From: Thomas Monjalon @ 2016-12-21 14:31 UTC (permalink / raw)
To: Jianfeng Tan; +Cc: Bruce Richardson, dev, david.marchand, pmatilai
In-Reply-To: <20161209151451.GB14536@bricha3-MOBL3.ger.corp.intel.com>
2016-12-09 15:14, Bruce Richardson:
> On Thu, Dec 08, 2016 at 07:19:41PM +0100, Thomas Monjalon wrote:
> > 2016-12-02 17:48, Jianfeng Tan:
> > > This patch uses pthread_getaffinity_np() to narrow down used
> > > cores when none of below options is specified:
> > > * coremask (-c)
> > > * corelist (-l)
> > > * and coremap (--lcores)
> > >
> > > The purpose of this patch is to leave out these core related options
> > > when DPDK applications are deployed under container env, so that
> > > users do not need decide the core related parameters when developing
> > > applications. Instead, when applications are deployed in containers,
> > > use cpu-set to constrain which cores can be used inside this container
> > > instance. And DPDK application inside containers just rely on this
> > > auto detect mechanism to start polling threads.
> > >
> > > Note: previously, some users are using isolated CPUs, which could
> > > be excluded by default. Please add commands like taskset to use
> > > those cores.
> > >
> > > Test example:
> > > $ taskset 0xc0000 ./examples/helloworld/build/helloworld -m 1024
> >
> > Bruce, what do you think of this version?
> > It requires taskset only if -c, -l and --lcores are not used.
> >
> I'm fine with that since it maintains backward compatibilty for those
> options.
>
> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Applied with "s/specified/parsed/", thanks
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