* RE: [PATCH] examples/ipsec-secgw: drop packets in poll mode
From: Akhil Goyal @ 2026-06-20 18:57 UTC (permalink / raw)
To: Rakesh Kudurumalla, Radu Nicolau
Cc: dev@dpdk.org, Jerin Jacob, Nithin Kumar Dabilpuram,
Rakesh Kudurumalla, dpdk stable
In-Reply-To: <20260601042946.89719-1-rkudurumalla@marvell.com>
> Subject: [PATCH] examples/ipsec-secgw: drop packets in poll mode
>
> During antireplay test packets are forwarded despite
> errors in poll mode instead of dropping.This patch
> fixes the same.
>
> Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
> ---
Fixes: dcbf9ad5fdf4 ("examples/ipsec-secgw: move fast path helper functions")
Cc: stable@dpdk.org
Acked-by: Akhil Goyal <gakhil@marvell.com>
Applied to dpdk-next-crypto
^ permalink raw reply
* RE: [PATCH 1/2] crypto/ipsec_mb: allow aesni_mb and aesni_gcm vdevs on Arm
From: Akhil Goyal @ 2026-06-20 18:43 UTC (permalink / raw)
To: Hemant Agrawal, Wathsala Vithanage, Kai Ji, Pablo de Lara
Cc: dev@dpdk.org, nd@arm.com, Paul.Elliott@arm.com,
Dhruv.Tripathi@arm.com, Shebu.VargheseKuriakose@arm.com
In-Reply-To: <GV1PR04MB10750F42B67E6112BE4F0466789122@GV1PR04MB10750.eurprd04.prod.outlook.com>
>
>
> > -----Original Message-----
> > From: Wathsala Vithanage <wathsala.vithanage@arm.com>
> > Sent: 30 May 2026 02:25
> > To: Kai Ji <kai.ji@intel.com>; Pablo de Lara <pablo.de.lara.guarch@intel.com>
> > Cc: dev@dpdk.org; nd@arm.com; Paul.Elliott@arm.com;
> > Dhruv.Tripathi@arm.com; Shebu.VargheseKuriakose@arm.com; Wathsala
> > Vithanage <wathsala.vithanage@arm.com>
> > Subject: [PATCH 1/2] crypto/ipsec_mb: allow aesni_mb and aesni_gcm vdevs
> > on Arm
> >
> > Extend Arm PMD gating in ipsec_mb_create() to permit
> > IPSEC_MB_PMD_TYPE_AESNI_MB and IPSEC_MB_PMD_TYPE_AESNI_GCM in
> > addition to existing SNOW3G and ZUC.
> >
> > This removes -ENOTSUP rejection for crypto_aesni_mb and crypto_aesni_gcm
> > on Arm, enabling these vdevs to probe and run when backed by a compatible
> > ipsec-mb library.
> >
> > Signed-off-by: Wathsala Vithanage <wathsala.vithanage@arm.com>
> > ---
> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Series applied to dpdk-next-crypto
^ permalink raw reply
* RE: [EXTERNAL] [v2] crypto/qat: require IPsec MB for HMAC precomputes
From: Akhil Goyal @ 2026-06-20 18:37 UTC (permalink / raw)
To: Emma Finn, Kai Ji; +Cc: dev@dpdk.org
In-Reply-To: <20260619135330.1821985-1-emma.finn@intel.com>
> if (ret) {
> QAT_LOG(ERR, "(MD5)precompute failed");
> return -EFAULT;
> @@ -3197,6 +2828,11 @@ qat_security_session_create(void *dev,
> sess_private_data,
> SECURITY_GET_SESS_PRIV_IOVA(sess));
> if (ret != 0) {
> QAT_LOG(ERR, "Failed to configure session parameters");
> +#ifdef RTE_QAT_OPENSSL
> +#if (OPENSSL_VERSION_NUMBER >= 0x30000000L)
> + ossl_legacy_provider_unload();
> +#endif
> +#endif
Why is this openssl version check required now?
Version < 3.0 is not supported in dpdk.
^ permalink raw reply
* RE: [EXTERNAL] [v2] crypto/openssl: update to OpenSSL 3.0 minimum version
From: Akhil Goyal @ 2026-06-20 18:28 UTC (permalink / raw)
To: Emma Finn, Kai Ji; +Cc: dev@dpdk.org
In-Reply-To: <20260528080320.650260-1-emma.finn@intel.com>
> Update the OpenSSL PMD to require OpenSSL 3.0.0 as the minimum
> supported version, removing all compatibility code for earlier
> versions (1.0.1, 1.1.0, 1.1.1).
>
> Signed-off-by: Emma Finn <emma.finn@intel.com>
> ---
> *v2: skip build if openssl v3.0 dependency is not met.
> ---
> doc/guides/cryptodevs/openssl.rst | 4 +-
> doc/guides/rel_notes/release_26_07.rst | 5 +
> drivers/crypto/openssl/compat.h | 203 ------
> drivers/crypto/openssl/meson.build | 4 +-
> drivers/crypto/openssl/openssl_pmd_private.h | 30 -
> drivers/crypto/openssl/rte_openssl_pmd.c | 648 +------------------
> drivers/crypto/openssl/rte_openssl_pmd_ops.c | 206 ------
> 7 files changed, 21 insertions(+), 1079 deletions(-)
>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Thanks for the cleanup. You missed to remove the deprecation notice.
Removed deprecation notice while applying.
Applied to dpdk-next-crypto
^ permalink raw reply
* RE: [PATCH 1/2] test/crypto: validate ML crypto keys
From: Akhil Goyal @ 2026-06-20 18:17 UTC (permalink / raw)
To: Gowrishankar Muthukrishnan, dev@dpdk.org, Fan Zhang,
Gowrishankar Muthukrishnan
Cc: stable@dpdk.org
In-Reply-To: <20260527085257.1933-1-gmuthukrishn@marvell.com>
> -----Original Message-----
> From: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>
> Sent: Wednesday, May 27, 2026 2:23 PM
> To: dev@dpdk.org; Akhil Goyal <gakhil@marvell.com>; Fan Zhang
> <fanzhang.oss@gmail.com>; Gowrishankar Muthukrishnan
> <gmuthukrishn@marvell.com>
> Cc: stable@dpdk.org
> Subject: [PATCH 1/2] test/crypto: validate ML crypto keys
>
> Validate ML-KEM and ML-DSA keys.
>
> Fixes: 76a5877072c ("test/crypto: add ML-KEM and ML-DSA cases")
> Cc: stable@dpdk.org
>
> Signed-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>
Series Acked-by: Akhil Goyal <gakhil@marvell.com>
Applied to dpdk-next-crypto
^ permalink raw reply
* RE: [PATCH] test: sync soft expiry check in inline IPsec
From: Akhil Goyal @ 2026-06-20 18:08 UTC (permalink / raw)
To: Aarnav JP, dev@dpdk.org, Anoob Joseph, Vamsi Krishna Attunuru
Cc: Jerin Jacob, Nithin Kumar Dabilpuram, Rahul Bhansali, Aarnav JP,
stable@dpdk.org
In-Reply-To: <20260505104351.2678817-1-ajp@marvell.com>
> Subject: [PATCH] test: sync soft expiry check in inline IPsec
>
> Soft expiry events are delivered asynchronously via
> the err-ring polling thread. The test checked notify_event
> right after the RX loop, before the polling thread could
> process the err-ring entry — causing intermittent failures
> with fast algorithms where TX/RX completes faster than the
> polling thread's usleep() wake-up.
>
> Add a bounded poll loop after RX for soft expiry cases, using
> rte_io_rmb() to ensure cross-core visibility. Fix store ordering
> in the callback with rte_io_wmb() so that the event subtype is
> visible before notify_event is set.
>
> Fixes: 34e8a9d9b4f2 ("test/security: add inline IPsec SA soft expiry cases")
> Cc: stable@dpdk.org
>
> Signed-off-by: Aarnav JP <ajp@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Applied to dpdk-next-crypto
Thanks.
^ permalink raw reply
* RE: [PATCH] common/qat: add asym crypto disable option
From: Akhil Goyal @ 2026-06-20 18:02 UTC (permalink / raw)
To: Ji, Kai, Nicolau, Radu, dev@dpdk.org
In-Reply-To: <DS0PR11MB745842CEBFACEDBA05C1CE6181232@DS0PR11MB7458.namprd11.prod.outlook.com>
> Acked-by: Kai Ji <kai.ji@intel.com>
Applied to dpdk-next-crypto
^ permalink raw reply
* Re: ARM v8 rte_power_pause
From: Wathsala Vithanage @ 2026-06-20 17:38 UTC (permalink / raw)
To: Hemant Agrawal, Morten Brørup
Cc: dev@dpdk.org, Maxime Leroy, Gagandeep Singh
In-Reply-To: <GV1PR04MB10750F8AC96BEFB29C1DD13BD89E32@GV1PR04MB10750.eurprd04.prod.outlook.com>
On 6/18/26 01:17, Hemant Agrawal wrote:
> Hi Watshala,
> I think WFET is not available on A72 core.
> Can you update your answer w.r.t Cortex-A72/Arm v8.0 architecture?
WFET is not available on A72. We enabled it in DPDK selectively for this
reason.
>
> Regards
> Hemant
>
>
>> -----Original Message-----
>> From: Wathsala Vithanage <wathsala.vithanage@arm.com>
>> Sent: 17 June 2026 17:27
>> To: Hemant Agrawal <hemant.agrawal@nxp.com>; Morten Brørup
>> <mb@smartsharesystems.com>
>> Cc: dev@dpdk.org; Maxime Leroy <maxime@leroys.fr>; Gagandeep Singh
>> <G.Singh@nxp.com>
>> Subject: Re: ARM v8 rte_power_pause
>> Importance: High
>>
>> Hi Morten and Hemant,
>>
>> YIELD is a NOP on non-SMT CPUs, such as Neoverse.
>>
>> WFE is universally available on AArch64, but it comes with a caveat: the CPU
>> can remain in a low-power state indefinitely unless an event is triggered. That
>> event can be generated explicitly via SEV/SEVL by a different CPU, or implicitly
>> through address monitoring (LDAXR).
>>
>> WFET is the safer variant because it includes a timeout, so explicit or implicit
>> event-register manipulation is not required.
>>
>> --wathsala
>>
>> On 6/12/26 01:11, Hemant Agrawal wrote:
>>> Hi Morten,
>>> On Cortex‑A72 (ARMv8), the only architectural primitives available are
>> YIELD, WFE, and WFI:
>>> YIELD is the only deterministic, low-overhead option (pure CPU relax,
>> no entry into low-power state)
>>> WFE can be used as a low-power idle hint, but it is event-driven and
>> not time-based (it may return immediately)
>>> WFI depends on interrupt wakeup and is therefore not suitable for
>>> tight latency loops
>>>
>>> For ~1 µs latency targets, the practical approach is a hybrid strategy:
>>>
>>> Short waits → spin using YIELD
>>> Slightly longer waits → opportunistically use WFE for power reduction
>>>
>>> A simple implementation could look like (not tested):
>>>
>>> static inline void rte_armv8_pause(unsigned int iters) {
>>> if (iters < 64) {
>>> for (unsigned int i = 0; i < iters; i++)
>>> asm volatile("yield");
>>> } else {
>>> asm volatile("sevl");
>>> asm volatile("wfe");
>>> }
>>> }
>>>
>>> @Wathsala Vithanage — would appreciate your thoughts, especially if there
>> are any micro-architectural nuances we should consider.
>>> Regards,
>>> Hemant
>>>
>>>> -----Original Message-----
>>>> From: Morten Brørup <mb@smartsharesystems.com>
>>>> Sent: 03 June 2026 17:26
>>>> To: Wathsala Vithanage <wathsala.vithanage@arm.com>; Hemant Agrawal
>>>> <hemant.agrawal@nxp.com>; Sachin Saxena (OSS)
>>>> <sachin.saxena@oss.nxp.com>
>>>> Cc: dev@dpdk.org; Maxime Leroy <maxime@leroys.fr>
>>>> Subject: ARM v8 rte_power_pause
>>>> Importance: High
>>>>
>>>> Hi Wathsala, Hemant and Sachin,
>>>>
>>>> Over at the Grout project, we are discussing power management in the
>>>> context of 100 Gbit/s latency deadlines [1].
>>>>
>>>> rte_power_pause() is not implemented for ARM v8 / Cortex-A72.
>>>> Syscalls such as nanosleep() have too much overhead, and cannot be used.
>>>>
>>>> Any suggestions for a power-reducing method to make a CPU core "sleep"
>> (i.e.
>>>> do nothing) for durations in the order of 1 microsecond?
>>>>
>>>> [1]:
>>>> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit
>>>>
>> hu%2F&data=05%7C02%7Chemant.agrawal%40nxp.com%7C06a651571db
>> 545d47d7a0
>> 8decc67908e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C639
>> 172942353
>> 967617%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYi
>> OiIwLjAuMD
>> AwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7
>> C%7C&s
>> data=7NCh3%2BS3TAu1sRLYgqGNAaTwqdgwjqhAs2awPixIeEM%3D&reserve
>> d=0
>>>> b.com%2FDPDK%2Fgrout%2Fpull%2F624%23issuecomment-
>>>>
>> 4602036364&data=05%7C02%7Chemant.agrawal%40nxp.com%7Cdbff5f2e
>> 8db1406f0c4008dec1671791%7C686ea1d3bc2b4c6fa92cd99c5c301635%7
>> C0%7C0%7C639160845728472826%7CUnknown%7CTWFpbGZsb3d8eyJFb
>> XB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTW
>> FpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=DRpJWjm2yaF3Cnhk0b
>>>> bFFhmGbKRweOOiWdsWco2NbX0%3D&reserved=0
>>>>
>>>> -Morten
^ permalink raw reply
* Re: [PATCH v1 0/5] prefix lcore role enum values
From: Stephen Hemminger @ 2026-06-20 16:42 UTC (permalink / raw)
To: Morten Brørup
Cc: Thomas Monjalon, Huisong Li, andrew.rybchenko, dev, zhanjie9
In-Reply-To: <98CBD80474FA8B44BF855DF32C47DC35F6592C@smartserver.smartshare.dk>
On Fri, 19 Jun 2026 22:11:02 +0200
Morten Brørup <mb@smartsharesystems.com> wrote:
> > From: Stephen Hemminger [mailto:stephen@networkplumber.org]
> > Sent: Friday, 19 June 2026 17.40
> >
> > On Fri, 19 Jun 2026 09:54:51 +0200
> > Morten Brørup <mb@smartsharesystems.com> wrote:
> >
> > > > > The problem with this patch it causes build failures now with abi
> > > > diff.
> > > >
> > > > It is probably a bug of an old version of abidiff.
> > > > I recommend updating.
> > >
> > > With the #define's the ABI has not changed. It's probably too
> > indirect for abidiff to understand.
> > > If we absolutely want to please abidiff, we could keep the existing
> > enums and #define RTE_LCORE_ROLE_RTE ROLE_RTE for now.
> > > But I'm in favor of what was done already.
> >
> > The build failures on github, not in my local builds.
> > https://github.com/ovsrobot/dpdk/actions/runs/27789889172/job/822359650
> > 90
> >
> > It makes looking at patchwork dashboard difficult, all patches show up
> > with red mark
>
> So maybe we can choose the path of pleasing abidiff...
> Keep the existing enums, and #define the new RTE_LCORE_ prefixed variants, and use those in the code.
>
> Later, with an ABI breaking release, we can swap.
> Or maybe we just wait until an ABI breaking release to fix this.
>
Since change is cosmetic, not functional. I think it should be reverted for 26.07
to get github CI to pass on all platforms.
It can be added back in 26.11
^ permalink raw reply
* [PATCH] MAINTAINERS: update for ena
From: Stephen Hemminger @ 2026-06-20 16:40 UTC (permalink / raw)
To: dev; +Cc: shaibran, evgenys, amitbern, atrwajee, Stephen Hemminger
Email to Ron Beider <rbeider@amazon.com> bounced.
I assume he is no longer available and other listed maintainers
for ena driver will be enough.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4a68a19b32..700f607db0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -691,7 +691,6 @@ F: doc/guides/nics/features/af_xdp.ini
Amazon ENA
M: Shai Brandes <shaibran@amazon.com>
M: Evgeny Schemeilin <evgenys@amazon.com>
-M: Ron Beider <rbeider@amazon.com>
M: Amit Bernstein <amitbern@amazon.com>
M: Wajeeh Atrash <atrwajee@amazon.com>
F: drivers/net/ena/
--
2.53.0
^ permalink raw reply related
* [PATCH v5 24/24] eal: deprecate rte_atomicNN functions
From: Stephen Hemminger @ 2026-06-20 2:28 UTC (permalink / raw)
To: dev
Cc: Stephen Hemminger, Konstantin Ananyev, Thomas Monjalon,
Wathsala Vithanage, Bibo Mao, David Christensen, Sun Yuechi,
Bruce Richardson
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
This deprecates existing rte_atomic functions that are not used
anywhere after this patch series. Rather than keeping platform
specific versions; just use the interinsic versions.
Now the compiler checks for these functions, no longer need
the check in checkpatches.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Konstantin Ananyev <konstantin.ananyev@huawei.com>
---
devtools/checkpatches.sh | 8 -
doc/guides/rel_notes/deprecation.rst | 4 +-
doc/guides/rel_notes/release_26_07.rst | 5 +
lib/eal/arm/include/rte_atomic_32.h | 4 -
lib/eal/arm/include/rte_atomic_64.h | 4 -
lib/eal/include/generic/rte_atomic.h | 243 ++++++-------------------
lib/eal/include/rte_common.h | 2 +
lib/eal/loongarch/include/rte_atomic.h | 4 -
lib/eal/ppc/include/rte_atomic.h | 173 ------------------
lib/eal/riscv/include/rte_atomic.h | 4 -
lib/eal/x86/include/rte_atomic.h | 172 -----------------
lib/eal/x86/include/rte_atomic_32.h | 188 -------------------
lib/eal/x86/include/rte_atomic_64.h | 157 ----------------
13 files changed, 68 insertions(+), 900 deletions(-)
diff --git a/devtools/checkpatches.sh b/devtools/checkpatches.sh
index f5dd77443f..13a2247ad5 100755
--- a/devtools/checkpatches.sh
+++ b/devtools/checkpatches.sh
@@ -113,14 +113,6 @@ check_forbidden_additions() { # <patch>
-f $(dirname $(readlink -f $0))/check-forbidden-tokens.awk \
"$1" || res=1
- # refrain from new additions of 16/32/64 bits rte_atomicNN_xxx()
- awk -v FOLDERS="lib drivers app examples" \
- -v EXPRESSIONS="rte_atomic[0-9][0-9]_.*\\\(" \
- -v RET_ON_FAIL=1 \
- -v MESSAGE='Using rte_atomicNN_xxx' \
- -f $(dirname $(readlink -f $0))/check-forbidden-tokens.awk \
- "$1" || res=1
-
# refrain from new additions of rte_smp_[r/w]mb()
awk -v FOLDERS="lib drivers app examples" \
-v EXPRESSIONS="rte_smp_(r|w)?mb\\\(" \
diff --git a/doc/guides/rel_notes/deprecation.rst b/doc/guides/rel_notes/deprecation.rst
index c7f8230278..9a9870226f 100644
--- a/doc/guides/rel_notes/deprecation.rst
+++ b/doc/guides/rel_notes/deprecation.rst
@@ -43,9 +43,7 @@ Deprecation Notices
* rte_atomicNN_xxx: These APIs do not take memory order parameter. This does
not allow for writing optimized code for all the CPU architectures supported
in DPDK. DPDK has adopted the atomic operations from
- https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html. These
- operations must be used for patches that need to be merged in 20.08 onwards.
- This change will not introduce any performance degradation.
+ https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html.
* rte_smp_*mb: These APIs provide full barrier functionality. However, many
use cases do not require full barriers. To support such use cases, DPDK has
diff --git a/doc/guides/rel_notes/release_26_07.rst b/doc/guides/rel_notes/release_26_07.rst
index 5d7aa8d1bf..e8092fc87b 100644
--- a/doc/guides/rel_notes/release_26_07.rst
+++ b/doc/guides/rel_notes/release_26_07.rst
@@ -204,6 +204,11 @@ API Changes
- ``rte_pmd_mlx5_enable_steering``
- ``rte_pmd_mlx5_disable_steering``
+* **atomic: Marked the ``rte_atomicNN`` functions as deprecated.**
+
+ As previously announced these functions were intended to be deprecated
+ but was not being enforced.
+
ABI Changes
-----------
diff --git a/lib/eal/arm/include/rte_atomic_32.h b/lib/eal/arm/include/rte_atomic_32.h
index 0b9a0dfa30..696a539fef 100644
--- a/lib/eal/arm/include/rte_atomic_32.h
+++ b/lib/eal/arm/include/rte_atomic_32.h
@@ -5,10 +5,6 @@
#ifndef _RTE_ATOMIC_ARM32_H_
#define _RTE_ATOMIC_ARM32_H_
-#ifndef RTE_FORCE_INTRINSICS
-# error Platform must be built with RTE_FORCE_INTRINSICS
-#endif
-
#include "generic/rte_atomic.h"
#ifdef __cplusplus
diff --git a/lib/eal/arm/include/rte_atomic_64.h b/lib/eal/arm/include/rte_atomic_64.h
index 181bb60929..9f790238df 100644
--- a/lib/eal/arm/include/rte_atomic_64.h
+++ b/lib/eal/arm/include/rte_atomic_64.h
@@ -6,10 +6,6 @@
#ifndef _RTE_ATOMIC_ARM64_H_
#define _RTE_ATOMIC_ARM64_H_
-#ifndef RTE_FORCE_INTRINSICS
-# error Platform must be built with RTE_FORCE_INTRINSICS
-#endif
-
#include "generic/rte_atomic.h"
#include <rte_branch_prediction.h>
#include <rte_debug.h>
diff --git a/lib/eal/include/generic/rte_atomic.h b/lib/eal/include/generic/rte_atomic.h
index 0a4f3f8528..07b262895f 100644
--- a/lib/eal/include/generic/rte_atomic.h
+++ b/lib/eal/include/generic/rte_atomic.h
@@ -164,6 +164,13 @@ static inline void rte_io_rmb(void);
*/
static inline void rte_atomic_thread_fence(rte_memory_order memorder);
+/*
+ * The rte_atomicNN_* APIs defined below are deprecated in favour of C11 atomics.
+ * Suppress the deprecation warnings for the inlines to allow inter-related usage.
+ */
+__rte_diagnostic_push
+__rte_allow_deprecated
+
/*------------------------- 16 bit atomic operations -------------------------*/
#ifndef RTE_TOOLCHAIN_MSVC
@@ -184,16 +191,11 @@ static inline void rte_atomic_thread_fence(rte_memory_order memorder);
* @return
* Non-zero on success; 0 on failure.
*/
-static inline int
-rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline int
+static __rte_deprecated inline int
rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
{
return __sync_bool_compare_and_swap(dst, exp, src);
}
-#endif
/**
* Atomic exchange.
@@ -210,16 +212,12 @@ rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
* @return
* The original value at that location
*/
-static inline uint16_t
-rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline uint16_t
+static __rte_deprecated inline uint16_t
rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
{
- return rte_atomic_exchange_explicit(dst, val, rte_memory_order_seq_cst);
+ return rte_atomic_exchange_explicit((volatile __rte_atomic uint16_t *)dst,
+ val, rte_memory_order_seq_cst);
}
-#endif
/**
* The atomic counter structure.
@@ -239,7 +237,7 @@ typedef struct {
* @param v
* A pointer to the atomic counter.
*/
-static inline void
+static __rte_deprecated inline void
rte_atomic16_init(rte_atomic16_t *v)
{
v->cnt = 0;
@@ -253,7 +251,7 @@ rte_atomic16_init(rte_atomic16_t *v)
* @return
* The value of the counter.
*/
-static inline int16_t
+static __rte_deprecated inline int16_t
rte_atomic16_read(const rte_atomic16_t *v)
{
return v->cnt;
@@ -267,7 +265,7 @@ rte_atomic16_read(const rte_atomic16_t *v)
* @param new_value
* The new value for the counter.
*/
-static inline void
+static __rte_deprecated inline void
rte_atomic16_set(rte_atomic16_t *v, int16_t new_value)
{
v->cnt = new_value;
@@ -281,7 +279,7 @@ rte_atomic16_set(rte_atomic16_t *v, int16_t new_value)
* @param inc
* The value to be added to the counter.
*/
-static inline void
+static __rte_deprecated inline void
rte_atomic16_add(rte_atomic16_t *v, int16_t inc)
{
rte_atomic_fetch_add_explicit((volatile __rte_atomic int16_t *)&v->cnt, inc,
@@ -296,7 +294,7 @@ rte_atomic16_add(rte_atomic16_t *v, int16_t inc)
* @param dec
* The value to be subtracted from the counter.
*/
-static inline void
+static __rte_deprecated inline void
rte_atomic16_sub(rte_atomic16_t *v, int16_t dec)
{
rte_atomic_fetch_sub_explicit((volatile __rte_atomic int16_t *)&v->cnt, dec,
@@ -309,16 +307,11 @@ rte_atomic16_sub(rte_atomic16_t *v, int16_t dec)
* @param v
* A pointer to the atomic counter.
*/
-static inline void
-rte_atomic16_inc(rte_atomic16_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline void
+static __rte_deprecated inline void
rte_atomic16_inc(rte_atomic16_t *v)
{
rte_atomic16_add(v, 1);
}
-#endif
/**
* Atomically decrement a counter by one.
@@ -326,16 +319,11 @@ rte_atomic16_inc(rte_atomic16_t *v)
* @param v
* A pointer to the atomic counter.
*/
-static inline void
-rte_atomic16_dec(rte_atomic16_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline void
+static __rte_deprecated inline void
rte_atomic16_dec(rte_atomic16_t *v)
{
rte_atomic16_sub(v, 1);
}
-#endif
/**
* Atomically add a 16-bit value to a counter and return the result.
@@ -350,7 +338,7 @@ rte_atomic16_dec(rte_atomic16_t *v)
* @return
* The value of v after the addition.
*/
-static inline int16_t
+static __rte_deprecated inline int16_t
rte_atomic16_add_return(rte_atomic16_t *v, int16_t inc)
{
return rte_atomic_fetch_add_explicit((volatile __rte_atomic int16_t *)&v->cnt, inc,
@@ -371,7 +359,7 @@ rte_atomic16_add_return(rte_atomic16_t *v, int16_t inc)
* @return
* The value of v after the subtraction.
*/
-static inline int16_t
+static __rte_deprecated inline int16_t
rte_atomic16_sub_return(rte_atomic16_t *v, int16_t dec)
{
return rte_atomic_fetch_sub_explicit((volatile __rte_atomic int16_t *)&v->cnt, dec,
@@ -389,15 +377,11 @@ rte_atomic16_sub_return(rte_atomic16_t *v, int16_t dec)
* @return
* True if the result after the increment operation is 0; false otherwise.
*/
-static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
+static __rte_deprecated inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
{
return rte_atomic_fetch_add_explicit((volatile __rte_atomic int16_t *)&v->cnt, 1,
rte_memory_order_seq_cst) + 1 == 0;
}
-#endif
/**
* Atomically decrement a 16-bit counter by one and test.
@@ -410,15 +394,11 @@ static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
* @return
* True if the result after the decrement operation is 0; false otherwise.
*/
-static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
+static __rte_deprecated inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
{
return rte_atomic_fetch_sub_explicit((volatile __rte_atomic int16_t *)&v->cnt, 1,
rte_memory_order_seq_cst) - 1 == 0;
}
-#endif
/**
* Atomically test and set a 16-bit atomic counter.
@@ -431,14 +411,10 @@ static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
* @return
* 0 if failed; else 1, success.
*/
-static inline int rte_atomic16_test_and_set(rte_atomic16_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
+static __rte_deprecated inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
{
return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
}
-#endif
/**
* Atomically set a 16-bit counter to 0.
@@ -446,7 +422,7 @@ static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
* @param v
* A pointer to the atomic counter.
*/
-static inline void rte_atomic16_clear(rte_atomic16_t *v)
+static __rte_deprecated inline void rte_atomic16_clear(rte_atomic16_t *v)
{
v->cnt = 0;
}
@@ -469,16 +445,11 @@ static inline void rte_atomic16_clear(rte_atomic16_t *v)
* @return
* Non-zero on success; 0 on failure.
*/
-static inline int
-rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline int
+static __rte_deprecated inline int
rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
{
return __sync_bool_compare_and_swap(dst, exp, src);
}
-#endif
/**
* Atomic exchange.
@@ -495,16 +466,12 @@ rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
* @return
* The original value at that location
*/
-static inline uint32_t
-rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline uint32_t
+static __rte_deprecated inline uint32_t
rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
{
- return rte_atomic_exchange_explicit(dst, val, rte_memory_order_seq_cst);
+ return rte_atomic_exchange_explicit((volatile __rte_atomic uint32_t *)dst,
+ val, rte_memory_order_seq_cst);
}
-#endif
/**
* The atomic counter structure.
@@ -524,7 +491,7 @@ typedef struct {
* @param v
* A pointer to the atomic counter.
*/
-static inline void
+static __rte_deprecated inline void
rte_atomic32_init(rte_atomic32_t *v)
{
v->cnt = 0;
@@ -538,7 +505,7 @@ rte_atomic32_init(rte_atomic32_t *v)
* @return
* The value of the counter.
*/
-static inline int32_t
+static __rte_deprecated inline int32_t
rte_atomic32_read(const rte_atomic32_t *v)
{
return v->cnt;
@@ -552,7 +519,7 @@ rte_atomic32_read(const rte_atomic32_t *v)
* @param new_value
* The new value for the counter.
*/
-static inline void
+static __rte_deprecated inline void
rte_atomic32_set(rte_atomic32_t *v, int32_t new_value)
{
v->cnt = new_value;
@@ -566,7 +533,7 @@ rte_atomic32_set(rte_atomic32_t *v, int32_t new_value)
* @param inc
* The value to be added to the counter.
*/
-static inline void
+static __rte_deprecated inline void
rte_atomic32_add(rte_atomic32_t *v, int32_t inc)
{
rte_atomic_fetch_add_explicit((volatile __rte_atomic int32_t *)&v->cnt, inc,
@@ -581,7 +548,7 @@ rte_atomic32_add(rte_atomic32_t *v, int32_t inc)
* @param dec
* The value to be subtracted from the counter.
*/
-static inline void
+static __rte_deprecated inline void
rte_atomic32_sub(rte_atomic32_t *v, int32_t dec)
{
rte_atomic_fetch_sub_explicit((volatile __rte_atomic int32_t *)&v->cnt, dec,
@@ -594,16 +561,11 @@ rte_atomic32_sub(rte_atomic32_t *v, int32_t dec)
* @param v
* A pointer to the atomic counter.
*/
-static inline void
-rte_atomic32_inc(rte_atomic32_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline void
+static __rte_deprecated inline void
rte_atomic32_inc(rte_atomic32_t *v)
{
rte_atomic32_add(v, 1);
}
-#endif
/**
* Atomically decrement a counter by one.
@@ -611,16 +573,11 @@ rte_atomic32_inc(rte_atomic32_t *v)
* @param v
* A pointer to the atomic counter.
*/
-static inline void
-rte_atomic32_dec(rte_atomic32_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline void
+static __rte_deprecated inline void
rte_atomic32_dec(rte_atomic32_t *v)
{
rte_atomic32_sub(v,1);
}
-#endif
/**
* Atomically add a 32-bit value to a counter and return the result.
@@ -635,7 +592,7 @@ rte_atomic32_dec(rte_atomic32_t *v)
* @return
* The value of v after the addition.
*/
-static inline int32_t
+static __rte_deprecated inline int32_t
rte_atomic32_add_return(rte_atomic32_t *v, int32_t inc)
{
return rte_atomic_fetch_add_explicit((volatile __rte_atomic int32_t *)&v->cnt, inc,
@@ -656,7 +613,7 @@ rte_atomic32_add_return(rte_atomic32_t *v, int32_t inc)
* @return
* The value of v after the subtraction.
*/
-static inline int32_t
+static __rte_deprecated inline int32_t
rte_atomic32_sub_return(rte_atomic32_t *v, int32_t dec)
{
return rte_atomic_fetch_sub_explicit((volatile __rte_atomic int32_t *)&v->cnt, dec,
@@ -674,15 +631,11 @@ rte_atomic32_sub_return(rte_atomic32_t *v, int32_t dec)
* @return
* True if the result after the increment operation is 0; false otherwise.
*/
-static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
+static __rte_deprecated inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
{
return rte_atomic_fetch_add_explicit((volatile __rte_atomic int32_t *)&v->cnt, 1,
rte_memory_order_seq_cst) + 1 == 0;
}
-#endif
/**
* Atomically decrement a 32-bit counter by one and test.
@@ -695,15 +648,11 @@ static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
* @return
* True if the result after the decrement operation is 0; false otherwise.
*/
-static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
+static __rte_deprecated inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
{
return rte_atomic_fetch_sub_explicit((volatile __rte_atomic int32_t *)&v->cnt, 1,
rte_memory_order_seq_cst) - 1 == 0;
}
-#endif
/**
* Atomically test and set a 32-bit atomic counter.
@@ -716,14 +665,10 @@ static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
* @return
* 0 if failed; else 1, success.
*/
-static inline int rte_atomic32_test_and_set(rte_atomic32_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
+static __rte_deprecated inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
{
return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
}
-#endif
/**
* Atomically set a 32-bit counter to 0.
@@ -731,7 +676,7 @@ static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
* @param v
* A pointer to the atomic counter.
*/
-static inline void rte_atomic32_clear(rte_atomic32_t *v)
+static __rte_deprecated inline void rte_atomic32_clear(rte_atomic32_t *v)
{
v->cnt = 0;
}
@@ -753,16 +698,11 @@ static inline void rte_atomic32_clear(rte_atomic32_t *v)
* @return
* Non-zero on success; 0 on failure.
*/
-static inline int
-rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline int
+static __rte_deprecated inline int
rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
{
return __sync_bool_compare_and_swap(dst, exp, src);
}
-#endif
/**
* Atomic exchange.
@@ -779,16 +719,12 @@ rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
* @return
* The original value at that location
*/
-static inline uint64_t
-rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline uint64_t
+static __rte_deprecated inline uint64_t
rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
{
- return rte_atomic_exchange_explicit(dst, val, rte_memory_order_seq_cst);
+ return rte_atomic_exchange_explicit((volatile __rte_atomic uint64_t *)dst,
+ val, rte_memory_order_seq_cst);
}
-#endif
/**
* The atomic counter structure.
@@ -808,11 +744,7 @@ typedef struct {
* @param v
* A pointer to the atomic counter.
*/
-static inline void
-rte_atomic64_init(rte_atomic64_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline void
+static __rte_deprecated inline void
rte_atomic64_init(rte_atomic64_t *v)
{
#ifdef __LP64__
@@ -828,7 +760,6 @@ rte_atomic64_init(rte_atomic64_t *v)
}
#endif
}
-#endif
/**
* Atomically read a 64-bit counter.
@@ -838,11 +769,7 @@ rte_atomic64_init(rte_atomic64_t *v)
* @return
* The value of the counter.
*/
-static inline int64_t
-rte_atomic64_read(rte_atomic64_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline int64_t
+static __rte_deprecated inline int64_t
rte_atomic64_read(rte_atomic64_t *v)
{
#ifdef __LP64__
@@ -860,7 +787,6 @@ rte_atomic64_read(rte_atomic64_t *v)
return tmp;
#endif
}
-#endif
/**
* Atomically set a 64-bit counter.
@@ -870,11 +796,7 @@ rte_atomic64_read(rte_atomic64_t *v)
* @param new_value
* The new value of the counter.
*/
-static inline void
-rte_atomic64_set(rte_atomic64_t *v, int64_t new_value);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline void
+static __rte_deprecated inline void
rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
{
#ifdef __LP64__
@@ -890,7 +812,6 @@ rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
}
#endif
}
-#endif
/**
* Atomically add a 64-bit value to a counter.
@@ -900,17 +821,12 @@ rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
* @param inc
* The value to be added to the counter.
*/
-static inline void
-rte_atomic64_add(rte_atomic64_t *v, int64_t inc);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline void
+static __rte_deprecated inline void
rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
{
rte_atomic_fetch_add_explicit((volatile __rte_atomic int64_t *)&v->cnt, inc,
rte_memory_order_seq_cst);
}
-#endif
/**
* Atomically subtract a 64-bit value from a counter.
@@ -920,17 +836,12 @@ rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
* @param dec
* The value to be subtracted from the counter.
*/
-static inline void
-rte_atomic64_sub(rte_atomic64_t *v, int64_t dec);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline void
+static __rte_deprecated inline void
rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
{
rte_atomic_fetch_sub_explicit((volatile __rte_atomic int64_t *)&v->cnt, dec,
rte_memory_order_seq_cst);
}
-#endif
/**
* Atomically increment a 64-bit counter by one and test.
@@ -938,16 +849,11 @@ rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
* @param v
* A pointer to the atomic counter.
*/
-static inline void
-rte_atomic64_inc(rte_atomic64_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline void
+static __rte_deprecated inline void
rte_atomic64_inc(rte_atomic64_t *v)
{
rte_atomic64_add(v, 1);
}
-#endif
/**
* Atomically decrement a 64-bit counter by one and test.
@@ -955,16 +861,11 @@ rte_atomic64_inc(rte_atomic64_t *v)
* @param v
* A pointer to the atomic counter.
*/
-static inline void
-rte_atomic64_dec(rte_atomic64_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline void
+static __rte_deprecated inline void
rte_atomic64_dec(rte_atomic64_t *v)
{
rte_atomic64_sub(v, 1);
}
-#endif
/**
* Add a 64-bit value to an atomic counter and return the result.
@@ -979,17 +880,12 @@ rte_atomic64_dec(rte_atomic64_t *v)
* @return
* The value of v after the addition.
*/
-static inline int64_t
-rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline int64_t
+static __rte_deprecated inline int64_t
rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
{
return rte_atomic_fetch_add_explicit((volatile __rte_atomic int64_t *)&v->cnt, inc,
rte_memory_order_seq_cst) + inc;
}
-#endif
/**
* Subtract a 64-bit value from an atomic counter and return the result.
@@ -1004,17 +900,12 @@ rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
* @return
* The value of v after the subtraction.
*/
-static inline int64_t
-rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline int64_t
+static __rte_deprecated inline int64_t
rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
{
return rte_atomic_fetch_sub_explicit((volatile __rte_atomic int64_t *)&v->cnt, dec,
rte_memory_order_seq_cst) - dec;
}
-#endif
/**
* Atomically increment a 64-bit counter by one and test.
@@ -1027,14 +918,10 @@ rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
* @return
* True if the result after the addition is 0; false otherwise.
*/
-static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
+static __rte_deprecated inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
{
return rte_atomic64_add_return(v, 1) == 0;
}
-#endif
/**
* Atomically decrement a 64-bit counter by one and test.
@@ -1047,14 +934,10 @@ static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
* @return
* True if the result after subtraction is 0; false otherwise.
*/
-static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
+static __rte_deprecated inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
{
return rte_atomic64_sub_return(v, 1) == 0;
}
-#endif
/**
* Atomically test and set a 64-bit atomic counter.
@@ -1067,14 +950,10 @@ static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
* @return
* 0 if failed; else 1, success.
*/
-static inline int rte_atomic64_test_and_set(rte_atomic64_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
+static __rte_deprecated inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
{
return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
}
-#endif
/**
* Atomically set a 64-bit counter to 0.
@@ -1082,17 +961,15 @@ static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
* @param v
* A pointer to the atomic counter.
*/
-static inline void rte_atomic64_clear(rte_atomic64_t *v);
-
-#ifdef RTE_FORCE_INTRINSICS
-static inline void rte_atomic64_clear(rte_atomic64_t *v)
+static __rte_deprecated inline void rte_atomic64_clear(rte_atomic64_t *v)
{
rte_atomic64_set(v, 0);
}
-#endif
#endif
+__rte_diagnostic_pop
+
/*------------------------ 128 bit atomic operations -------------------------*/
/**
diff --git a/lib/eal/include/rte_common.h b/lib/eal/include/rte_common.h
index 2eb21d74d1..e73dc83b88 100644
--- a/lib/eal/include/rte_common.h
+++ b/lib/eal/include/rte_common.h
@@ -172,9 +172,11 @@ typedef uint16_t unaligned_uint16_t;
#ifdef RTE_TOOLCHAIN_MSVC
#define __rte_deprecated
#define __rte_deprecated_msg(msg)
+#define __rte_allow_deprecated
#else
#define __rte_deprecated __attribute__((__deprecated__))
#define __rte_deprecated_msg(msg) __attribute__((__deprecated__(msg)))
+#define __rte_allow_deprecated _Pragma("GCC diagnostic ignored \"-Wdeprecated-declarations\"")
#endif
/**
diff --git a/lib/eal/loongarch/include/rte_atomic.h b/lib/eal/loongarch/include/rte_atomic.h
index c8066a4612..785a452c9e 100644
--- a/lib/eal/loongarch/include/rte_atomic.h
+++ b/lib/eal/loongarch/include/rte_atomic.h
@@ -5,10 +5,6 @@
#ifndef RTE_ATOMIC_LOONGARCH_H
#define RTE_ATOMIC_LOONGARCH_H
-#ifndef RTE_FORCE_INTRINSICS
-# error Platform must be built with RTE_FORCE_INTRINSICS
-#endif
-
#include <rte_common.h>
#include "generic/rte_atomic.h"
diff --git a/lib/eal/ppc/include/rte_atomic.h b/lib/eal/ppc/include/rte_atomic.h
index 10acc238f9..64f4c3d670 100644
--- a/lib/eal/ppc/include/rte_atomic.h
+++ b/lib/eal/ppc/include/rte_atomic.h
@@ -43,179 +43,6 @@ rte_atomic_thread_fence(rte_memory_order memorder)
}
/*------------------------- 16 bit atomic operations -------------------------*/
-#ifndef RTE_FORCE_INTRINSICS
-static inline int
-rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
-{
- return rte_atomic_compare_exchange_strong_explicit(dst, &exp, src, rte_memory_order_acquire,
- rte_memory_order_acquire) ? 1 : 0;
-}
-
-static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
-{
- return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
-}
-
-static inline void
-rte_atomic16_inc(rte_atomic16_t *v)
-{
- rte_atomic_fetch_add_explicit(&v->cnt, 1, rte_memory_order_acquire);
-}
-
-static inline void
-rte_atomic16_dec(rte_atomic16_t *v)
-{
- rte_atomic_fetch_sub_explicit(&v->cnt, 1, rte_memory_order_acquire);
-}
-
-static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
-{
- return rte_atomic_fetch_add_explicit(&v->cnt, 1, rte_memory_order_acquire) + 1 == 0;
-}
-
-static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
-{
- return rte_atomic_fetch_sub_explicit(&v->cnt, 1, rte_memory_order_acquire) - 1 == 0;
-}
-
-static inline uint16_t
-rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
-{
- return __atomic_exchange_2(dst, val, rte_memory_order_seq_cst);
-}
-
-/*------------------------- 32 bit atomic operations -------------------------*/
-
-static inline int
-rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
-{
- return rte_atomic_compare_exchange_strong_explicit(dst, &exp, src, rte_memory_order_acquire,
- rte_memory_order_acquire) ? 1 : 0;
-}
-
-static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
-{
- return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
-}
-
-static inline void
-rte_atomic32_inc(rte_atomic32_t *v)
-{
- rte_atomic_fetch_add_explicit(&v->cnt, 1, rte_memory_order_acquire);
-}
-
-static inline void
-rte_atomic32_dec(rte_atomic32_t *v)
-{
- rte_atomic_fetch_sub_explicit(&v->cnt, 1, rte_memory_order_acquire);
-}
-
-static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
-{
- return rte_atomic_fetch_add_explicit(&v->cnt, 1, rte_memory_order_acquire) + 1 == 0;
-}
-
-static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
-{
- return rte_atomic_fetch_sub_explicit(&v->cnt, 1, rte_memory_order_acquire) - 1 == 0;
-}
-
-static inline uint32_t
-rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
-{
- return __atomic_exchange_4(dst, val, rte_memory_order_seq_cst);
-}
-
-/*------------------------- 64 bit atomic operations -------------------------*/
-
-static inline int
-rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
-{
- return rte_atomic_compare_exchange_strong_explicit(dst, &exp, src, rte_memory_order_acquire,
- rte_memory_order_acquire) ? 1 : 0;
-}
-
-static inline void
-rte_atomic64_init(rte_atomic64_t *v)
-{
- v->cnt = 0;
-}
-
-static inline int64_t
-rte_atomic64_read(rte_atomic64_t *v)
-{
- return v->cnt;
-}
-
-static inline void
-rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
-{
- v->cnt = new_value;
-}
-
-static inline void
-rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
-{
- rte_atomic_fetch_add_explicit(&v->cnt, inc, rte_memory_order_acquire);
-}
-
-static inline void
-rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
-{
- rte_atomic_fetch_sub_explicit(&v->cnt, dec, rte_memory_order_acquire);
-}
-
-static inline void
-rte_atomic64_inc(rte_atomic64_t *v)
-{
- rte_atomic_fetch_add_explicit(&v->cnt, 1, rte_memory_order_acquire);
-}
-
-static inline void
-rte_atomic64_dec(rte_atomic64_t *v)
-{
- rte_atomic_fetch_sub_explicit(&v->cnt, 1, rte_memory_order_acquire);
-}
-
-static inline int64_t
-rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
-{
- return rte_atomic_fetch_add_explicit(&v->cnt, inc, rte_memory_order_acquire) + inc;
-}
-
-static inline int64_t
-rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
-{
- return rte_atomic_fetch_sub_explicit(&v->cnt, dec, rte_memory_order_acquire) - dec;
-}
-
-static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
-{
- return rte_atomic_fetch_add_explicit(&v->cnt, 1, rte_memory_order_acquire) + 1 == 0;
-}
-
-static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
-{
- return rte_atomic_fetch_sub_explicit(&v->cnt, 1, rte_memory_order_acquire) - 1 == 0;
-}
-
-static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
-{
- return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
-}
-
-static inline void rte_atomic64_clear(rte_atomic64_t *v)
-{
- v->cnt = 0;
-}
-
-static inline uint64_t
-rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
-{
- return __atomic_exchange_8(dst, val, rte_memory_order_seq_cst);
-}
-
-#endif
#ifdef __cplusplus
}
diff --git a/lib/eal/riscv/include/rte_atomic.h b/lib/eal/riscv/include/rte_atomic.h
index 66346ad474..061b175f33 100644
--- a/lib/eal/riscv/include/rte_atomic.h
+++ b/lib/eal/riscv/include/rte_atomic.h
@@ -8,10 +8,6 @@
#ifndef RTE_ATOMIC_RISCV_H
#define RTE_ATOMIC_RISCV_H
-#ifndef RTE_FORCE_INTRINSICS
-# error Platform must be built with RTE_FORCE_INTRINSICS
-#endif
-
#include <stdint.h>
#include <rte_common.h>
#include <rte_config.h>
diff --git a/lib/eal/x86/include/rte_atomic.h b/lib/eal/x86/include/rte_atomic.h
index e071e4234e..4f05302c9f 100644
--- a/lib/eal/x86/include/rte_atomic.h
+++ b/lib/eal/x86/include/rte_atomic.h
@@ -111,178 +111,6 @@ rte_atomic_thread_fence(rte_memory_order memorder)
extern "C" {
#endif
-#ifndef RTE_FORCE_INTRINSICS
-static inline int
-rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
-{
- uint8_t res;
-
- asm volatile(
- MPLOCKED
- "cmpxchgw %[src], %[dst];"
- "sete %[res];"
- : [res] "=a" (res), /* output */
- [dst] "=m" (*dst)
- : [src] "r" (src), /* input */
- "a" (exp),
- "m" (*dst)
- : "memory"); /* no-clobber list */
- return res;
-}
-
-static inline uint16_t
-rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
-{
- asm volatile(
- MPLOCKED
- "xchgw %0, %1;"
- : "=r" (val), "=m" (*dst)
- : "0" (val), "m" (*dst)
- : "memory"); /* no-clobber list */
- return val;
-}
-
-static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
-{
- return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
-}
-
-static inline void
-rte_atomic16_inc(rte_atomic16_t *v)
-{
- asm volatile(
- MPLOCKED
- "incw %[cnt]"
- : [cnt] "=m" (v->cnt) /* output */
- : "m" (v->cnt) /* input */
- );
-}
-
-static inline void
-rte_atomic16_dec(rte_atomic16_t *v)
-{
- asm volatile(
- MPLOCKED
- "decw %[cnt]"
- : [cnt] "=m" (v->cnt) /* output */
- : "m" (v->cnt) /* input */
- );
-}
-
-static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
-{
- uint8_t ret;
-
- asm volatile(
- MPLOCKED
- "incw %[cnt] ; "
- "sete %[ret]"
- : [cnt] "+m" (v->cnt), /* output */
- [ret] "=qm" (ret)
- );
- return ret != 0;
-}
-
-static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
-{
- uint8_t ret;
-
- asm volatile(MPLOCKED
- "decw %[cnt] ; "
- "sete %[ret]"
- : [cnt] "+m" (v->cnt), /* output */
- [ret] "=qm" (ret)
- );
- return ret != 0;
-}
-
-/*------------------------- 32 bit atomic operations -------------------------*/
-
-static inline int
-rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
-{
- uint8_t res;
-
- asm volatile(
- MPLOCKED
- "cmpxchgl %[src], %[dst];"
- "sete %[res];"
- : [res] "=a" (res), /* output */
- [dst] "=m" (*dst)
- : [src] "r" (src), /* input */
- "a" (exp),
- "m" (*dst)
- : "memory"); /* no-clobber list */
- return res;
-}
-
-static inline uint32_t
-rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
-{
- asm volatile(
- MPLOCKED
- "xchgl %0, %1;"
- : "=r" (val), "=m" (*dst)
- : "0" (val), "m" (*dst)
- : "memory"); /* no-clobber list */
- return val;
-}
-
-static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
-{
- return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
-}
-
-static inline void
-rte_atomic32_inc(rte_atomic32_t *v)
-{
- asm volatile(
- MPLOCKED
- "incl %[cnt]"
- : [cnt] "=m" (v->cnt) /* output */
- : "m" (v->cnt) /* input */
- );
-}
-
-static inline void
-rte_atomic32_dec(rte_atomic32_t *v)
-{
- asm volatile(
- MPLOCKED
- "decl %[cnt]"
- : [cnt] "=m" (v->cnt) /* output */
- : "m" (v->cnt) /* input */
- );
-}
-
-static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
-{
- uint8_t ret;
-
- asm volatile(
- MPLOCKED
- "incl %[cnt] ; "
- "sete %[ret]"
- : [cnt] "+m" (v->cnt), /* output */
- [ret] "=qm" (ret)
- );
- return ret != 0;
-}
-
-static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
-{
- uint8_t ret;
-
- asm volatile(MPLOCKED
- "decl %[cnt] ; "
- "sete %[ret]"
- : [cnt] "+m" (v->cnt), /* output */
- [ret] "=qm" (ret)
- );
- return ret != 0;
-}
-
-#endif /* !RTE_FORCE_INTRINSICS */
#ifdef __cplusplus
}
diff --git a/lib/eal/x86/include/rte_atomic_32.h b/lib/eal/x86/include/rte_atomic_32.h
index 0f25863aa5..37d139f30d 100644
--- a/lib/eal/x86/include/rte_atomic_32.h
+++ b/lib/eal/x86/include/rte_atomic_32.h
@@ -20,193 +20,5 @@
/*------------------------- 64 bit atomic operations -------------------------*/
-#ifndef RTE_FORCE_INTRINSICS
-static inline int
-rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
-{
- uint8_t res;
- union {
- struct {
- uint32_t l32;
- uint32_t h32;
- };
- uint64_t u64;
- } _exp, _src;
-
- _exp.u64 = exp;
- _src.u64 = src;
-
-#ifndef __PIC__
- asm volatile (
- MPLOCKED
- "cmpxchg8b (%[dst]);"
- "setz %[res];"
- : [res] "=a" (res) /* result in eax */
- : [dst] "S" (dst), /* esi */
- "b" (_src.l32), /* ebx */
- "c" (_src.h32), /* ecx */
- "a" (_exp.l32), /* eax */
- "d" (_exp.h32) /* edx */
- : "memory" ); /* no-clobber list */
-#else
- asm volatile (
- "xchgl %%ebx, %%edi;\n"
- MPLOCKED
- "cmpxchg8b (%[dst]);"
- "setz %[res];"
- "xchgl %%ebx, %%edi;\n"
- : [res] "=a" (res) /* result in eax */
- : [dst] "S" (dst), /* esi */
- "D" (_src.l32), /* ebx */
- "c" (_src.h32), /* ecx */
- "a" (_exp.l32), /* eax */
- "d" (_exp.h32) /* edx */
- : "memory" ); /* no-clobber list */
-#endif
-
- return res;
-}
-
-static inline uint64_t
-rte_atomic64_exchange(volatile uint64_t *dest, uint64_t val)
-{
- uint64_t old;
-
- do {
- old = *dest;
- } while (rte_atomic64_cmpset(dest, old, val) == 0);
-
- return old;
-}
-
-static inline void
-rte_atomic64_init(rte_atomic64_t *v)
-{
- int success = 0;
- uint64_t tmp;
-
- while (success == 0) {
- tmp = v->cnt;
- success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
- tmp, 0);
- }
-}
-
-static inline int64_t
-rte_atomic64_read(rte_atomic64_t *v)
-{
- int success = 0;
- uint64_t tmp;
-
- while (success == 0) {
- tmp = v->cnt;
- /* replace the value by itself */
- success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
- tmp, tmp);
- }
- return tmp;
-}
-
-static inline void
-rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
-{
- int success = 0;
- uint64_t tmp;
-
- while (success == 0) {
- tmp = v->cnt;
- success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
- tmp, new_value);
- }
-}
-
-static inline void
-rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
-{
- int success = 0;
- uint64_t tmp;
-
- while (success == 0) {
- tmp = v->cnt;
- success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
- tmp, tmp + inc);
- }
-}
-
-static inline void
-rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
-{
- int success = 0;
- uint64_t tmp;
-
- while (success == 0) {
- tmp = v->cnt;
- success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
- tmp, tmp - dec);
- }
-}
-
-static inline void
-rte_atomic64_inc(rte_atomic64_t *v)
-{
- rte_atomic64_add(v, 1);
-}
-
-static inline void
-rte_atomic64_dec(rte_atomic64_t *v)
-{
- rte_atomic64_sub(v, 1);
-}
-
-static inline int64_t
-rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
-{
- int success = 0;
- uint64_t tmp;
-
- while (success == 0) {
- tmp = v->cnt;
- success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
- tmp, tmp + inc);
- }
-
- return tmp + inc;
-}
-
-static inline int64_t
-rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
-{
- int success = 0;
- uint64_t tmp;
-
- while (success == 0) {
- tmp = v->cnt;
- success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
- tmp, tmp - dec);
- }
-
- return tmp - dec;
-}
-
-static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
-{
- return rte_atomic64_add_return(v, 1) == 0;
-}
-
-static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
-{
- return rte_atomic64_sub_return(v, 1) == 0;
-}
-
-static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
-{
- return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
-}
-
-static inline void rte_atomic64_clear(rte_atomic64_t *v)
-{
- rte_atomic64_set(v, 0);
-}
-#endif
#endif /* _RTE_ATOMIC_I686_H_ */
diff --git a/lib/eal/x86/include/rte_atomic_64.h b/lib/eal/x86/include/rte_atomic_64.h
index 0a7a2131e0..1cd12695a2 100644
--- a/lib/eal/x86/include/rte_atomic_64.h
+++ b/lib/eal/x86/include/rte_atomic_64.h
@@ -22,163 +22,6 @@
/*------------------------- 64 bit atomic operations -------------------------*/
-#ifndef RTE_FORCE_INTRINSICS
-static inline int
-rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
-{
- uint8_t res;
-
-
- asm volatile(
- MPLOCKED
- "cmpxchgq %[src], %[dst];"
- "sete %[res];"
- : [res] "=a" (res), /* output */
- [dst] "=m" (*dst)
- : [src] "r" (src), /* input */
- "a" (exp),
- "m" (*dst)
- : "memory"); /* no-clobber list */
-
- return res;
-}
-
-static inline uint64_t
-rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
-{
- asm volatile(
- MPLOCKED
- "xchgq %0, %1;"
- : "=r" (val), "=m" (*dst)
- : "0" (val), "m" (*dst)
- : "memory"); /* no-clobber list */
- return val;
-}
-
-static inline void
-rte_atomic64_init(rte_atomic64_t *v)
-{
- v->cnt = 0;
-}
-
-static inline int64_t
-rte_atomic64_read(rte_atomic64_t *v)
-{
- return v->cnt;
-}
-
-static inline void
-rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
-{
- v->cnt = new_value;
-}
-
-static inline void
-rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
-{
- asm volatile(
- MPLOCKED
- "addq %[inc], %[cnt]"
- : [cnt] "=m" (v->cnt) /* output */
- : [inc] "ir" (inc), /* input */
- "m" (v->cnt)
- );
-}
-
-static inline void
-rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
-{
- asm volatile(
- MPLOCKED
- "subq %[dec], %[cnt]"
- : [cnt] "=m" (v->cnt) /* output */
- : [dec] "ir" (dec), /* input */
- "m" (v->cnt)
- );
-}
-
-static inline void
-rte_atomic64_inc(rte_atomic64_t *v)
-{
- asm volatile(
- MPLOCKED
- "incq %[cnt]"
- : [cnt] "=m" (v->cnt) /* output */
- : "m" (v->cnt) /* input */
- );
-}
-
-static inline void
-rte_atomic64_dec(rte_atomic64_t *v)
-{
- asm volatile(
- MPLOCKED
- "decq %[cnt]"
- : [cnt] "=m" (v->cnt) /* output */
- : "m" (v->cnt) /* input */
- );
-}
-
-static inline int64_t
-rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
-{
- int64_t prev = inc;
-
- asm volatile(
- MPLOCKED
- "xaddq %[prev], %[cnt]"
- : [prev] "+r" (prev), /* output */
- [cnt] "=m" (v->cnt)
- : "m" (v->cnt) /* input */
- );
- return prev + inc;
-}
-
-static inline int64_t
-rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
-{
- return rte_atomic64_add_return(v, -dec);
-}
-
-static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
-{
- uint8_t ret;
-
- asm volatile(
- MPLOCKED
- "incq %[cnt] ; "
- "sete %[ret]"
- : [cnt] "+m" (v->cnt), /* output */
- [ret] "=qm" (ret)
- );
-
- return ret != 0;
-}
-
-static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
-{
- uint8_t ret;
-
- asm volatile(
- MPLOCKED
- "decq %[cnt] ; "
- "sete %[ret]"
- : [cnt] "+m" (v->cnt), /* output */
- [ret] "=qm" (ret)
- );
- return ret != 0;
-}
-
-static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
-{
- return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
-}
-
-static inline void rte_atomic64_clear(rte_atomic64_t *v)
-{
- v->cnt = 0;
-}
-#endif
/*------------------------ 128 bit atomic operations -------------------------*/
--
2.53.0
^ permalink raw reply related
* [PATCH v5 23/24] test/atomic: suppress deprecation warnings for legacy APIs
From: Stephen Hemminger @ 2026-06-20 2:28 UTC (permalink / raw)
To: dev; +Cc: Stephen Hemminger
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
The rte_atomicNN_* APIs are now marked __rte_deprecated.
Wrap the whole file with __rte_diagnostic_push / pop and a
GCC pragma -Wdeprecated-declarations.
In future, when the APIs are removed this test collapses to just the
128-bit compare-and-swap case and the suppression goes with it.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
app/test/test_atomic.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/app/test/test_atomic.c b/app/test/test_atomic.c
index 2a4531b833..f32a1aeff4 100644
--- a/app/test/test_atomic.c
+++ b/app/test/test_atomic.c
@@ -100,6 +100,15 @@
* - At the end of the test, the number of corrupted tokens must be 0.
*/
+/*
+ * The rte_atomicNN_* APIs exercised below are deprecated in favour of C11 atomics.
+ * Suppress the deprecation warnings for the whole file;
+ * when the APIs are removed this test collapses to the 128-bit
+ * compare-and-swap case and the suppression goes with it.
+ */
+__rte_diagnostic_push
+_Pragma("GCC diagnostic ignored \"-Wdeprecated-declarations\"")
+
#define NUM_ATOMIC_TYPES 3
#define N_BASE 1000000u
@@ -645,4 +654,7 @@ test_atomic(void)
return 0;
}
REGISTER_FAST_TEST(atomic_autotest, NOHUGE_SKIP, ASAN_OK, test_atomic);
+
+__rte_diagnostic_pop
+
#endif /* RTE_TOOLCHAIN_MSVC */
--
2.53.0
^ permalink raw reply related
* [PATCH v5 22/24] vdpa/ifc: replace rte_atomic32 with stdatomic
From: Stephen Hemminger @ 2026-06-20 2:28 UTC (permalink / raw)
To: dev; +Cc: Stephen Hemminger
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
Last in-tree caller of rte_atomic32_*(), blocking deprecation of the
rte_atomicNN_*() family.
Replace rte_atomic32_read/set() with rte_atomic_load_explicit() and
rte_atomic_store_explicit() on the started, dev_attached, and running
flags. Narrow them to bool (only ever hold 0/1) and group with the
existing bools to reduce padding in struct ifcvf_internal.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
drivers/vdpa/ifc/ifcvf_vdpa.c | 37 ++++++++++++++++++-----------------
1 file changed, 19 insertions(+), 18 deletions(-)
diff --git a/drivers/vdpa/ifc/ifcvf_vdpa.c b/drivers/vdpa/ifc/ifcvf_vdpa.c
index f319d455ba..e5da11a2ba 100644
--- a/drivers/vdpa/ifc/ifcvf_vdpa.c
+++ b/drivers/vdpa/ifc/ifcvf_vdpa.c
@@ -25,6 +25,7 @@
#include <rte_log.h>
#include <rte_kvargs.h>
#include <rte_devargs.h>
+#include <rte_stdatomic.h>
#include "base/ifcvf.h"
@@ -68,10 +69,10 @@ struct ifcvf_internal {
struct rte_vdpa_device *vdev;
uint16_t max_queues;
uint64_t features;
- rte_atomic32_t started;
- rte_atomic32_t dev_attached;
- rte_atomic32_t running;
rte_spinlock_t lock;
+ RTE_ATOMIC(bool) started;
+ RTE_ATOMIC(bool) dev_attached;
+ RTE_ATOMIC(bool) running;
bool sw_lm;
bool sw_fallback_running;
/* mediated vring for sw fallback */
@@ -712,9 +713,9 @@ update_datapath(struct ifcvf_internal *internal)
rte_spinlock_lock(&internal->lock);
- if (!rte_atomic32_read(&internal->running) &&
- (rte_atomic32_read(&internal->started) &&
- rte_atomic32_read(&internal->dev_attached))) {
+ if (!rte_atomic_load_explicit(&internal->running, rte_memory_order_seq_cst) &&
+ (rte_atomic_load_explicit(&internal->started, rte_memory_order_seq_cst) &&
+ rte_atomic_load_explicit(&internal->dev_attached, rte_memory_order_seq_cst))) {
ret = ifcvf_dma_map(internal, true);
if (ret)
goto err;
@@ -735,10 +736,10 @@ update_datapath(struct ifcvf_internal *internal)
if (ret)
goto err;
- rte_atomic32_set(&internal->running, 1);
- } else if (rte_atomic32_read(&internal->running) &&
- (!rte_atomic32_read(&internal->started) ||
- !rte_atomic32_read(&internal->dev_attached))) {
+ rte_atomic_store_explicit(&internal->running, true, rte_memory_order_seq_cst);
+ } else if (rte_atomic_load_explicit(&internal->running, rte_memory_order_seq_cst) &&
+ (!rte_atomic_load_explicit(&internal->started, rte_memory_order_seq_cst) ||
+ !rte_atomic_load_explicit(&internal->dev_attached, rte_memory_order_seq_cst))) {
unset_intr_relay(internal);
ret = unset_notify_relay(internal);
@@ -755,7 +756,7 @@ update_datapath(struct ifcvf_internal *internal)
if (ret)
goto err;
- rte_atomic32_set(&internal->running, 0);
+ rte_atomic_store_explicit(&internal->running, false, rte_memory_order_seq_cst);
}
rte_spinlock_unlock(&internal->lock);
@@ -1058,7 +1059,7 @@ ifcvf_sw_fallback_switchover(struct ifcvf_internal *internal)
vdpa_disable_vfio_intr(internal);
- rte_atomic32_set(&internal->running, 0);
+ rte_atomic_store_explicit(&internal->running, false, rte_memory_order_seq_cst);
ret = rte_vhost_host_notifier_ctrl(vid, RTE_VHOST_QUEUE_ALL, false);
if (ret && ret != -ENOTSUP)
@@ -1113,11 +1114,11 @@ ifcvf_dev_config(int vid)
internal = list->internal;
internal->vid = vid;
- rte_atomic32_set(&internal->dev_attached, 1);
+ rte_atomic_store_explicit(&internal->dev_attached, true, rte_memory_order_seq_cst);
if (update_datapath(internal) < 0) {
DRV_LOG(ERR, "failed to update datapath for vDPA device %s",
vdev->device->name);
- rte_atomic32_set(&internal->dev_attached, 0);
+ rte_atomic_store_explicit(&internal->dev_attached, false, rte_memory_order_seq_cst);
return -1;
}
@@ -1166,7 +1167,7 @@ ifcvf_dev_close(int vid)
internal->sw_fallback_running = false;
} else {
- rte_atomic32_set(&internal->dev_attached, 0);
+ rte_atomic_store_explicit(&internal->dev_attached, false, rte_memory_order_seq_cst);
if (update_datapath(internal) < 0) {
DRV_LOG(ERR, "failed to update datapath for vDPA device %s",
vdev->device->name);
@@ -1782,10 +1783,10 @@ ifcvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
goto error;
}
- rte_atomic32_set(&internal->started, 1);
+ rte_atomic_store_explicit(&internal->started, true, rte_memory_order_seq_cst);
if (update_datapath(internal) < 0) {
DRV_LOG(ERR, "failed to update datapath %s", pci_dev->name);
- rte_atomic32_set(&internal->started, 0);
+ rte_atomic_store_explicit(&internal->started, false, rte_memory_order_seq_cst);
rte_vdpa_unregister_device(internal->vdev);
pthread_mutex_lock(&internal_list_lock);
TAILQ_REMOVE(&internal_list, list, next);
@@ -1819,7 +1820,7 @@ ifcvf_pci_remove(struct rte_pci_device *pci_dev)
}
internal = list->internal;
- rte_atomic32_set(&internal->started, 0);
+ rte_atomic_store_explicit(&internal->started, false, rte_memory_order_seq_cst);
if (update_datapath(internal) < 0)
DRV_LOG(ERR, "failed to update datapath %s", pci_dev->name);
--
2.53.0
^ permalink raw reply related
* [PATCH v5 21/24] net/vhost: use stdatomic instead of rte_atomic32
From: Stephen Hemminger @ 2026-06-20 2:28 UTC (permalink / raw)
To: dev; +Cc: Stephen Hemminger, Maxime Coquelin, Chenbo Xia
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
Convert allow_queuing, while_queuing, started, and dev_attached from
rte_atomic32_t to RTE_ATOMIC(uint32_t) and replace rte_atomic32_*()
with rte_atomic_*_explicit().
The data-path / control-thread handshake on allow_queuing and
while_queuing is a Dekker-style mutual-visibility pattern: each side
stores its own flag and then loads the peer's. Both legs must be
seq_cst to forbid store-load reordering; anything weaker permits both
sides to miss each other. The previous rte_atomic32_set/read compiled
to plain volatile stores/loads and provided no such ordering, so this
also closes a latent ordering hole on weakly-ordered ISAs.
The data-path exit store of while_queuing=0 is release, ordering
preceding slot accesses before the control thread observes the data
path as idle.
The flags started and dev_attached are consulted only inside
update_queuing_status, where the per-queue handshake provides the
real synchronization; their loads and stores are relaxed.
Factor the per-queue allow_queuing store and while_queuing wait into
a small update_queue() helper used by both rx and tx loops.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
drivers/net/vhost/rte_eth_vhost.c | 103 +++++++++++++++++++-----------
1 file changed, 65 insertions(+), 38 deletions(-)
diff --git a/drivers/net/vhost/rte_eth_vhost.c b/drivers/net/vhost/rte_eth_vhost.c
index 05940f2461..3b1eedfe42 100644
--- a/drivers/net/vhost/rte_eth_vhost.c
+++ b/drivers/net/vhost/rte_eth_vhost.c
@@ -73,8 +73,8 @@ struct vhost_stats {
struct vhost_queue {
int vid;
- rte_atomic32_t allow_queuing;
- rte_atomic32_t while_queuing;
+ RTE_ATOMIC(uint32_t) allow_queuing;
+ RTE_ATOMIC(uint32_t) while_queuing;
struct pmd_internal *internal;
struct rte_mempool *mb_pool;
uint16_t port;
@@ -86,14 +86,14 @@ struct vhost_queue {
};
struct pmd_internal {
- rte_atomic32_t dev_attached;
+ RTE_ATOMIC(uint32_t) dev_attached;
char *iface_name;
uint64_t flags;
uint64_t disable_flags;
uint64_t features;
uint16_t max_queues;
int vid;
- rte_atomic32_t started;
+ RTE_ATOMIC(uint32_t) started;
bool vlan_strip;
bool rx_sw_csum;
bool tx_sw_csum;
@@ -406,12 +406,19 @@ eth_vhost_rx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)
uint16_t i, nb_rx = 0;
uint16_t nb_receive = nb_bufs;
- if (unlikely(rte_atomic32_read(&r->allow_queuing) == 0))
+ /* Fast-path early exit; racy load is fine here -- if we miss a
+ * transition we get caught by the seq_cst check below.
+ */
+ if (unlikely(rte_atomic_load_explicit(&r->allow_queuing, rte_memory_order_relaxed) == 0))
return 0;
- rte_atomic32_set(&r->while_queuing, 1);
-
- if (unlikely(rte_atomic32_read(&r->allow_queuing) == 0))
+ /* Announce presence, then re-check. The store and the following
+ * load MUST both be seq_cst so they are totally ordered with the
+ * control thread's store-to-allow_queuing / load-of-while_queuing
+ * pair. Anything weaker permits both sides to miss each other.
+ */
+ rte_atomic_store_explicit(&r->while_queuing, 1, rte_memory_order_seq_cst);
+ if (unlikely(rte_atomic_load_explicit(&r->allow_queuing, rte_memory_order_seq_cst) == 0))
goto out;
/* Dequeue packets from guest TX queue */
@@ -446,7 +453,7 @@ eth_vhost_rx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)
}
out:
- rte_atomic32_set(&r->while_queuing, 0);
+ rte_atomic_store_explicit(&r->while_queuing, 0, rte_memory_order_release);
return nb_rx;
}
@@ -460,12 +467,19 @@ eth_vhost_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)
uint64_t nb_bytes = 0;
uint64_t nb_missed = 0;
- if (unlikely(rte_atomic32_read(&r->allow_queuing) == 0))
+ /* Fast-path early exit; racy load is fine here -- if we miss a
+ * transition we get caught by the seq_cst check below.
+ */
+ if (unlikely(rte_atomic_load_explicit(&r->allow_queuing, rte_memory_order_relaxed) == 0))
return 0;
- rte_atomic32_set(&r->while_queuing, 1);
-
- if (unlikely(rte_atomic32_read(&r->allow_queuing) == 0))
+ /* Announce presence, then re-check. The store and the following
+ * load MUST both be seq_cst so they are totally ordered with the
+ * control thread's store-to-allow_queuing / load-of-while_queuing
+ * pair. Anything weaker permits both sides to miss each other.
+ */
+ rte_atomic_store_explicit(&r->while_queuing, 1, rte_memory_order_seq_cst);
+ if (unlikely(rte_atomic_load_explicit(&r->allow_queuing, rte_memory_order_seq_cst) == 0))
goto out;
for (i = 0; i < nb_bufs; i++) {
@@ -515,7 +529,7 @@ eth_vhost_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)
for (i = 0; likely(i < nb_tx); i++)
rte_pktmbuf_free(bufs[i]);
out:
- rte_atomic32_set(&r->while_queuing, 0);
+ rte_atomic_store_explicit(&r->while_queuing, 0, rte_memory_order_release);
return nb_tx;
}
@@ -744,6 +758,19 @@ eth_vhost_unconfigure_intr(struct rte_eth_dev *eth_dev)
}
}
+static inline void
+update_queue(struct vhost_queue *vq, uint32_t allow, bool wait_queuing)
+{
+ /* seq_cst: pairs with the data-path's seq_cst store of
+ * while_queuing and seq_cst load of allow_queuing. See
+ * eth_vhost_rx().
+ */
+ rte_atomic_store_explicit(&vq->allow_queuing, allow, rte_memory_order_seq_cst);
+ if (wait_queuing)
+ rte_wait_until_equal_32((volatile uint32_t *)(uintptr_t)&vq->while_queuing,
+ 0, rte_memory_order_seq_cst);
+}
+
static void
update_queuing_status(struct rte_eth_dev *dev, bool wait_queuing)
{
@@ -751,14 +778,18 @@ update_queuing_status(struct rte_eth_dev *dev, bool wait_queuing)
struct vhost_queue *vq;
struct rte_vhost_vring_state *state;
unsigned int i;
- int allow_queuing = 1;
+ bool allow_queuing = true;
if (!dev->data->rx_queues || !dev->data->tx_queues)
return;
- if (rte_atomic32_read(&internal->started) == 0 ||
- rte_atomic32_read(&internal->dev_attached) == 0)
- allow_queuing = 0;
+ /* These are control-plane flags consulted only here;
+ * the real data-path handshake is on vq->allow_queuing below.
+ * Relaxed is sufficient.
+ */
+ if (rte_atomic_load_explicit(&internal->started, rte_memory_order_relaxed) == 0 ||
+ rte_atomic_load_explicit(&internal->dev_attached, rte_memory_order_relaxed) == 0)
+ allow_queuing = false;
state = vring_states[dev->data->port_id];
@@ -767,24 +798,18 @@ update_queuing_status(struct rte_eth_dev *dev, bool wait_queuing)
vq = dev->data->rx_queues[i];
if (vq == NULL)
continue;
- if (allow_queuing && state->cur[vq->virtqueue_id])
- rte_atomic32_set(&vq->allow_queuing, 1);
- else
- rte_atomic32_set(&vq->allow_queuing, 0);
- while (wait_queuing && rte_atomic32_read(&vq->while_queuing))
- rte_pause();
+
+ update_queue(vq, !!(allow_queuing && state->cur[vq->virtqueue_id]),
+ wait_queuing);
}
for (i = 0; i < dev->data->nb_tx_queues; i++) {
vq = dev->data->tx_queues[i];
if (vq == NULL)
continue;
- if (allow_queuing && state->cur[vq->virtqueue_id])
- rte_atomic32_set(&vq->allow_queuing, 1);
- else
- rte_atomic32_set(&vq->allow_queuing, 0);
- while (wait_queuing && rte_atomic32_read(&vq->while_queuing))
- rte_pause();
+
+ update_queue(vq, !!(allow_queuing && state->cur[vq->virtqueue_id]),
+ wait_queuing);
}
}
@@ -848,7 +873,7 @@ new_device(int vid)
}
internal->vid = vid;
- if (rte_atomic32_read(&internal->started) == 1) {
+ if (rte_atomic_load_explicit(&internal->started, rte_memory_order_relaxed) == 1) {
queue_setup(eth_dev, internal);
if (dev_conf->intr_conf.rxq)
eth_vhost_configure_intr(eth_dev);
@@ -863,7 +888,7 @@ new_device(int vid)
vhost_dev_csum_configure(eth_dev);
- rte_atomic32_set(&internal->dev_attached, 1);
+ rte_atomic_store_explicit(&internal->dev_attached, 1, rte_memory_order_relaxed);
update_queuing_status(eth_dev, false);
VHOST_LOG_LINE(INFO, "Vhost device %d created", vid);
@@ -893,7 +918,7 @@ destroy_device(int vid)
eth_dev = list->eth_dev;
internal = eth_dev->data->dev_private;
- rte_atomic32_set(&internal->dev_attached, 0);
+ rte_atomic_store_explicit(&internal->dev_attached, 0, rte_memory_order_relaxed);
update_queuing_status(eth_dev, true);
eth_vhost_unconfigure_intr(eth_dev);
@@ -1148,11 +1173,11 @@ eth_dev_start(struct rte_eth_dev *eth_dev)
}
queue_setup(eth_dev, internal);
- if (rte_atomic32_read(&internal->dev_attached) == 1 &&
+ if (rte_atomic_load_explicit(&internal->dev_attached, rte_memory_order_relaxed) == 1 &&
dev_conf->intr_conf.rxq)
eth_vhost_configure_intr(eth_dev);
- rte_atomic32_set(&internal->started, 1);
+ rte_atomic_store_explicit(&internal->started, 1, rte_memory_order_relaxed);
update_queuing_status(eth_dev, false);
for (i = 0; i < eth_dev->data->nb_rx_queues; i++)
@@ -1170,7 +1195,7 @@ eth_dev_stop(struct rte_eth_dev *dev)
uint16_t i;
dev->data->dev_started = 0;
- rte_atomic32_set(&internal->started, 0);
+ rte_atomic_store_explicit(&internal->started, 0, rte_memory_order_relaxed);
update_queuing_status(dev, true);
for (i = 0; i < dev->data->nb_rx_queues; i++)
@@ -1471,8 +1496,10 @@ vhost_dev_priv_dump(struct rte_eth_dev *dev, FILE *f)
fprintf(f, "features: 0x%" PRIx64 "\n", internal->features);
fprintf(f, "max_queues: %u\n", internal->max_queues);
fprintf(f, "vid: %d\n", internal->vid);
- fprintf(f, "started: %d\n", rte_atomic32_read(&internal->started));
- fprintf(f, "dev_attached: %d\n", rte_atomic32_read(&internal->dev_attached));
+ fprintf(f, "started: %u\n",
+ rte_atomic_load_explicit(&internal->started, rte_memory_order_relaxed));
+ fprintf(f, "dev_attached: %u\n",
+ rte_atomic_load_explicit(&internal->dev_attached, rte_memory_order_relaxed));
fprintf(f, "vlan_strip: %d\n", internal->vlan_strip);
fprintf(f, "rx_sw_csum: %d\n", internal->rx_sw_csum);
fprintf(f, "tx_sw_csum: %d\n", internal->tx_sw_csum);
--
2.53.0
^ permalink raw reply related
* [PATCH v5 20/24] net/txgbe: replace rte_atomic32 with stdatomic
From: Stephen Hemminger @ 2026-06-20 2:28 UTC (permalink / raw)
To: dev; +Cc: Stephen Hemminger, Jiawen Wu, Zaiyu Wang
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
The swfw_busy flag guarding the AML SW-FW mailbox is a one-bit lock,
so convert it to RTE_ATOMIC(bool) and replace the legacy
test-and-set / clear pair with explicit acquire-release:
rte_atomic32_test_and_set ->
rte_atomic_exchange_explicit(.., true, acquire)
rte_atomic32_clear ->
rte_atomic_store_explicit(.., false, release)
Acquire on the take pairs with release on the drop, so accesses
inside the critical section are synchronized between successive
holders. Default zero-initialization of struct txgbe_hw still
gives swfw_busy = false, so no init site needs updating.
Note:
The previous rte_atomic32_test_and_set return value was
inverted relative to what this code expected; this patch
incidentally corrects that. A standalone Fixes: patch is
queued in net-next.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
drivers/net/txgbe/base/txgbe_mng.c | 4 ++--
drivers/net/txgbe/base/txgbe_type.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_mng.c b/drivers/net/txgbe/base/txgbe_mng.c
index a1974820b6..c58e1d6589 100644
--- a/drivers/net/txgbe/base/txgbe_mng.c
+++ b/drivers/net/txgbe/base/txgbe_mng.c
@@ -185,7 +185,7 @@ txgbe_host_interface_command_aml(struct txgbe_hw *hw, u32 *buffer,
}
/* try to get lock */
- while (rte_atomic32_test_and_set(&hw->swfw_busy)) {
+ while (rte_atomic_exchange_explicit(&hw->swfw_busy, true, rte_memory_order_acquire)) {
timeout--;
if (!timeout)
return TXGBE_ERR_TIMEOUT;
@@ -266,7 +266,7 @@ txgbe_host_interface_command_aml(struct txgbe_hw *hw, u32 *buffer,
/* index++, index replace txgbe_hic_hdr.checksum */
hw->swfw_index = resp->index == TXGBE_HIC_HDR_INDEX_MAX ?
0 : resp->index + 1;
- rte_atomic32_clear(&hw->swfw_busy);
+ rte_atomic_store_explicit(&hw->swfw_busy, false, rte_memory_order_release);
return err;
}
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index ede780321f..d3c82d51a4 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -880,7 +880,7 @@ struct txgbe_hw {
rte_spinlock_t phy_lock;
/*amlite: new SW-FW mbox */
u8 swfw_index;
- rte_atomic32_t swfw_busy;
+ RTE_ATOMIC(bool) swfw_busy;
u32 fec_mode;
u32 cur_fec_link;
};
--
2.53.0
^ permalink raw reply related
* [PATCH v5 19/24] net/hinic: replace rte_atomic32 with stdatomic
From: Stephen Hemminger @ 2026-06-20 2:28 UTC (permalink / raw)
To: dev; +Cc: Stephen Hemminger, Xiaoyun Wang
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
Convert dma_pool::inuse and hinic_os_dep::dma_alloc_cnt to
RTE_ATOMIC(uint32_t) and replace rte_atomic32_*() with the
rte_atomic_*_explicit() equivalents. The matching local variable
and log format change from int/%d to uint32_t/%u.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
drivers/net/hinic/base/hinic_compat.h | 2 +-
drivers/net/hinic/base/hinic_pmd_hwdev.c | 24 ++++++++++++++----------
drivers/net/hinic/base/hinic_pmd_hwdev.h | 4 ++--
3 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/net/hinic/base/hinic_compat.h b/drivers/net/hinic/base/hinic_compat.h
index 707a3b92b9..c53b88b96d 100644
--- a/drivers/net/hinic/base/hinic_compat.h
+++ b/drivers/net/hinic/base/hinic_compat.h
@@ -15,7 +15,7 @@
#include <rte_memzone.h>
#include <rte_memcpy.h>
#include <rte_malloc.h>
-#include <rte_atomic.h>
+#include <rte_stdatomic.h>
#include <rte_spinlock.h>
#include <rte_cycles.h>
#include <rte_log.h>
diff --git a/drivers/net/hinic/base/hinic_pmd_hwdev.c b/drivers/net/hinic/base/hinic_pmd_hwdev.c
index 818698dcb3..9a1b126632 100644
--- a/drivers/net/hinic/base/hinic_pmd_hwdev.c
+++ b/drivers/net/hinic/base/hinic_pmd_hwdev.c
@@ -116,7 +116,8 @@ static void *hinic_dma_mem_zalloc(struct hinic_hwdev *hwdev, size_t size,
dma_addr_t *dma_handle, unsigned int align,
unsigned int socket_id)
{
- int rc, alloc_cnt;
+ int rc;
+ uint32_t alloc_cnt;
const struct rte_memzone *mz;
char z_name[RTE_MEMZONE_NAMESIZE];
hash_sig_t sig;
@@ -125,8 +126,9 @@ static void *hinic_dma_mem_zalloc(struct hinic_hwdev *hwdev, size_t size,
if (dma_handle == NULL || 0 == size)
return NULL;
- alloc_cnt = rte_atomic32_add_return(&hwdev->os_dep.dma_alloc_cnt, 1);
- snprintf(z_name, sizeof(z_name), "%s_%d",
+ alloc_cnt = rte_atomic_fetch_add_explicit(&hwdev->os_dep.dma_alloc_cnt,
+ 1, rte_memory_order_relaxed);
+ snprintf(z_name, sizeof(z_name), "%s_%u",
hwdev->pcidev_hdl->name, alloc_cnt);
mz = rte_memzone_reserve_aligned(z_name, size, socket_id,
@@ -282,7 +284,6 @@ struct dma_pool *dma_pool_create(const char *name, void *dev,
if (!pool)
return NULL;
- rte_atomic32_set(&pool->inuse, 0);
pool->elem_size = size;
pool->align = align;
pool->boundary = boundary;
@@ -294,12 +295,15 @@ struct dma_pool *dma_pool_create(const char *name, void *dev,
void dma_pool_destroy(struct dma_pool *pool)
{
+ uint32_t inuse;
+
if (!pool)
return;
- if (rte_atomic32_read(&pool->inuse) != 0) {
- PMD_DRV_LOG(ERR, "Leak memory, dma_pool: %s, inuse_count: %d",
- pool->name, rte_atomic32_read(&pool->inuse));
+ inuse = rte_atomic_load_explicit(&pool->inuse, rte_memory_order_relaxed);
+ if (inuse != 0) {
+ PMD_DRV_LOG(ERR, "Leak memory, dma_pool: %s, inuse_count: %u",
+ pool->name, inuse);
}
rte_free(pool);
@@ -312,14 +316,14 @@ void *dma_pool_alloc(struct pci_pool *pool, dma_addr_t *dma_addr)
buf = hinic_dma_mem_zalloc(pool->hwdev, pool->elem_size, dma_addr,
(u32)pool->align, SOCKET_ID_ANY);
if (buf)
- rte_atomic32_inc(&pool->inuse);
+ rte_atomic_fetch_add_explicit(&pool->inuse, 1, rte_memory_order_relaxed);
return buf;
}
void dma_pool_free(struct pci_pool *pool, void *vaddr, dma_addr_t dma)
{
- rte_atomic32_dec(&pool->inuse);
+ rte_atomic_fetch_sub_explicit(&pool->inuse, 1, rte_memory_order_relaxed);
hinic_dma_mem_free(pool->hwdev, pool->elem_size, vaddr, dma);
}
@@ -329,7 +333,7 @@ int hinic_osdep_init(struct hinic_hwdev *hwdev)
struct rte_hash_parameters dh_params = { 0 };
struct rte_hash *paddr_hash = NULL;
- rte_atomic32_set(&hwdev->os_dep.dma_alloc_cnt, 0);
+ hwdev->os_dep.dma_alloc_cnt = 0;
rte_spinlock_init(&hwdev->os_dep.dma_hash_lock);
dh_params.name = hwdev->pcidev_hdl->name;
diff --git a/drivers/net/hinic/base/hinic_pmd_hwdev.h b/drivers/net/hinic/base/hinic_pmd_hwdev.h
index d6896b3f13..ad30ddd72e 100644
--- a/drivers/net/hinic/base/hinic_pmd_hwdev.h
+++ b/drivers/net/hinic/base/hinic_pmd_hwdev.h
@@ -18,7 +18,7 @@
/* dma pool */
struct dma_pool {
- rte_atomic32_t inuse;
+ RTE_ATOMIC(uint32_t) inuse;
size_t elem_size;
size_t align;
size_t boundary;
@@ -402,7 +402,7 @@ struct hinic_hilink_link_info {
/* dma os dependency implementation */
struct hinic_os_dep {
/* kernel dma alloc api */
- rte_atomic32_t dma_alloc_cnt;
+ RTE_ATOMIC(uint32_t) dma_alloc_cnt;
rte_spinlock_t dma_hash_lock;
struct rte_hash *dma_addr_hash;
};
--
2.53.0
^ permalink raw reply related
* [PATCH v5 18/24] drivers/event: replace rte_atomic32 in selftests
From: Stephen Hemminger @ 2026-06-20 2:28 UTC (permalink / raw)
To: dev; +Cc: Stephen Hemminger, Hemant Agrawal, Sachin Saxena, Jerin Jacob
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
Last callers in these selftests of the rte_atomicNN_*() family,
which is being deprecated.
Convert total_events from rte_atomic32_t to RTE_ATOMIC(uint32_t)
for the stack-local instance and __rte_atomic uint32_t * for the
pointer in test_core_param. Switch reads and updates to
rte_atomic_*_explicit().
Reads in the busy-loop checks and progress logs use relaxed: the
counter is purely a "drained yet?" signal and no data is published
through it. The fetch_sub on the dequeue path uses release in
octeontx (preserving the publish-after-mbuf-free ordering already
implied by the seq_cst sub it replaces) and relaxed in dpaa2.
The stack-local atomic_total_events is initialized by direct
assignment instead of rte_atomic32_set(), since it is written
before any worker is launched.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
drivers/event/dpaa2/dpaa2_eventdev_selftest.c | 26 ++++----
drivers/event/octeontx/ssovf_evdev_selftest.c | 61 ++++++++++---------
2 files changed, 47 insertions(+), 40 deletions(-)
diff --git a/drivers/event/dpaa2/dpaa2_eventdev_selftest.c b/drivers/event/dpaa2/dpaa2_eventdev_selftest.c
index 9d4938efe6..2c688bd194 100644
--- a/drivers/event/dpaa2/dpaa2_eventdev_selftest.c
+++ b/drivers/event/dpaa2/dpaa2_eventdev_selftest.c
@@ -2,7 +2,7 @@
* Copyright 2018-2019 NXP
*/
-#include <rte_atomic.h>
+#include <rte_stdatomic.h>
#include <rte_common.h>
#include <rte_cycles.h>
#include <rte_debug.h>
@@ -49,7 +49,7 @@ struct event_attr {
};
struct test_core_param {
- rte_atomic32_t *total_events;
+ __rte_atomic uint32_t *total_events;
uint64_t dequeue_tmo_ticks;
uint8_t port;
uint8_t sched_type;
@@ -444,10 +444,10 @@ worker_multi_port_fn(void *arg)
struct rte_event ev;
uint16_t valid_event;
uint8_t port = param->port;
- rte_atomic32_t *total_events = param->total_events;
+ __rte_atomic uint32_t *total_events = param->total_events;
int ret;
- while (rte_atomic32_read(total_events) > 0) {
+ while (rte_atomic_load_explicit(total_events, rte_memory_order_relaxed) > 0) {
valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0);
if (!valid_event)
continue;
@@ -455,13 +455,15 @@ worker_multi_port_fn(void *arg)
ret = validate_event(&ev);
RTE_TEST_ASSERT_SUCCESS(ret, "Failed to validate event");
rte_pktmbuf_free(ev.mbuf);
- rte_atomic32_sub(total_events, 1);
+
+ rte_atomic_fetch_sub_explicit(total_events, 1,
+ rte_memory_order_relaxed);
}
return 0;
}
static int
-wait_workers_to_join(int lcore, const rte_atomic32_t *count)
+wait_workers_to_join(int lcore, const __rte_atomic uint32_t *count)
{
uint64_t cycles, print_cycles;
@@ -472,15 +474,15 @@ wait_workers_to_join(int lcore, const rte_atomic32_t *count)
uint64_t new_cycles = rte_get_timer_cycles();
if (new_cycles - print_cycles > rte_get_timer_hz()) {
- dpaa2_evdev_dbg("\r%s: events %d", __func__,
- rte_atomic32_read(count));
+ dpaa2_evdev_dbg("\r%s: events %u", __func__,
+ rte_atomic_load_explicit(count, rte_memory_order_relaxed));
print_cycles = new_cycles;
}
if (new_cycles - cycles > rte_get_timer_hz() * 10) {
dpaa2_evdev_info(
- "%s: No schedules for seconds, deadlock (%d)",
+ "%s: No schedules for seconds, deadlock (%u)",
__func__,
- rte_atomic32_read(count));
+ rte_atomic_load_explicit(count, rte_memory_order_relaxed));
rte_event_dev_dump(evdev, stdout);
cycles = new_cycles;
return -1;
@@ -500,13 +502,13 @@ launch_workers_and_wait(int (*main_worker)(void *),
int w_lcore;
int ret;
struct test_core_param *param;
- rte_atomic32_t atomic_total_events;
+ RTE_ATOMIC(uint32_t) atomic_total_events;
uint64_t dequeue_tmo_ticks;
if (!nb_workers)
return 0;
- rte_atomic32_set(&atomic_total_events, total_events);
+ atomic_total_events = total_events;
RTE_BUILD_BUG_ON(NUM_PACKETS < MAX_EVENTS);
param = malloc(sizeof(struct test_core_param) * nb_workers);
diff --git a/drivers/event/octeontx/ssovf_evdev_selftest.c b/drivers/event/octeontx/ssovf_evdev_selftest.c
index b54ae126d2..5eeed2b2ce 100644
--- a/drivers/event/octeontx/ssovf_evdev_selftest.c
+++ b/drivers/event/octeontx/ssovf_evdev_selftest.c
@@ -4,7 +4,7 @@
#include <stdlib.h>
-#include <rte_atomic.h>
+#include <rte_stdatomic.h>
#include <rte_common.h>
#include <rte_cycles.h>
#include <rte_debug.h>
@@ -84,7 +84,7 @@ seqn_list_check(int limit)
}
struct test_core_param {
- rte_atomic32_t *total_events;
+ __rte_atomic uint32_t *total_events;
uint64_t dequeue_tmo_ticks;
uint8_t port;
uint8_t sched_type;
@@ -558,10 +558,10 @@ worker_multi_port_fn(void *arg)
struct rte_event ev;
uint16_t valid_event;
uint8_t port = param->port;
- rte_atomic32_t *total_events = param->total_events;
+ __rte_atomic uint32_t *total_events = param->total_events;
int ret;
- while (rte_atomic32_read(total_events) > 0) {
+ while (rte_atomic_load_explicit(total_events, rte_memory_order_relaxed) > 0) {
valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0);
if (!valid_event)
continue;
@@ -569,13 +569,14 @@ worker_multi_port_fn(void *arg)
ret = validate_event(&ev);
RTE_TEST_ASSERT_SUCCESS(ret, "Failed to validate event");
rte_pktmbuf_free(ev.mbuf);
- rte_atomic32_sub(total_events, 1);
+
+ rte_atomic_fetch_sub_explicit(total_events, 1, rte_memory_order_release);
}
return 0;
}
static inline int
-wait_workers_to_join(int lcore, const rte_atomic32_t *count)
+wait_workers_to_join(int lcore, const __rte_atomic uint32_t *count)
{
uint64_t cycles, print_cycles;
RTE_SET_USED(count);
@@ -583,17 +584,16 @@ wait_workers_to_join(int lcore, const rte_atomic32_t *count)
print_cycles = cycles = rte_get_timer_cycles();
while (rte_eal_get_lcore_state(lcore) != WAIT) {
uint64_t new_cycles = rte_get_timer_cycles();
+ uint32_t cur_count = rte_atomic_load_explicit(count, rte_memory_order_relaxed);
if (new_cycles - print_cycles > rte_get_timer_hz()) {
- ssovf_log_dbg("\r%s: events %d", __func__,
- rte_atomic32_read(count));
+ ssovf_log_dbg("\r%s: events %u", __func__, cur_count);
print_cycles = new_cycles;
}
if (new_cycles - cycles > rte_get_timer_hz() * 10) {
ssovf_log_dbg(
- "%s: No schedules for seconds, deadlock (%d)",
- __func__,
- rte_atomic32_read(count));
+ "%s: No schedules for seconds, deadlock (%u)",
+ __func__, cur_count);
rte_event_dev_dump(evdev, stdout);
cycles = new_cycles;
return -1;
@@ -613,13 +613,13 @@ launch_workers_and_wait(int (*main_worker)(void *),
int w_lcore;
int ret;
struct test_core_param *param;
- rte_atomic32_t atomic_total_events;
+ RTE_ATOMIC(uint32_t) atomic_total_events;
uint64_t dequeue_tmo_ticks;
if (!nb_workers)
return 0;
- rte_atomic32_set(&atomic_total_events, total_events);
+ atomic_total_events = total_events;
seqn_list_init();
param = malloc(sizeof(struct test_core_param) * nb_workers);
@@ -889,10 +889,10 @@ worker_flow_based_pipeline(void *arg)
uint16_t valid_event;
uint8_t port = param->port;
uint8_t new_sched_type = param->sched_type;
- rte_atomic32_t *total_events = param->total_events;
+ __rte_atomic uint32_t *total_events = param->total_events;
uint64_t dequeue_tmo_ticks = param->dequeue_tmo_ticks;
- while (rte_atomic32_read(total_events) > 0) {
+ while (rte_atomic_load_explicit(total_events, rte_memory_order_relaxed) > 0) {
valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1,
dequeue_tmo_ticks);
if (!valid_event)
@@ -910,7 +910,8 @@ worker_flow_based_pipeline(void *arg)
} else if (ev.sub_event_type == 1) { /* Events from stage 1*/
if (seqn_list_update(*rte_event_pmd_selftest_seqn(ev.mbuf)) == 0) {
rte_pktmbuf_free(ev.mbuf);
- rte_atomic32_sub(total_events, 1);
+ rte_atomic_fetch_sub_explicit(total_events, 1,
+ rte_memory_order_release);
} else {
ssovf_log_dbg("Failed to update seqn_list");
return -1;
@@ -1044,10 +1045,10 @@ worker_group_based_pipeline(void *arg)
uint16_t valid_event;
uint8_t port = param->port;
uint8_t new_sched_type = param->sched_type;
- rte_atomic32_t *total_events = param->total_events;
+ __rte_atomic uint32_t *total_events = param->total_events;
uint64_t dequeue_tmo_ticks = param->dequeue_tmo_ticks;
- while (rte_atomic32_read(total_events) > 0) {
+ while (rte_atomic_load_explicit(total_events, rte_memory_order_relaxed) > 0) {
valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1,
dequeue_tmo_ticks);
if (!valid_event)
@@ -1065,7 +1066,8 @@ worker_group_based_pipeline(void *arg)
} else if (ev.queue_id == 1) { /* Events from stage 1(group 1)*/
if (seqn_list_update(*rte_event_pmd_selftest_seqn(ev.mbuf)) == 0) {
rte_pktmbuf_free(ev.mbuf);
- rte_atomic32_sub(total_events, 1);
+ rte_atomic_fetch_sub_explicit(total_events, 1,
+ rte_memory_order_release);
} else {
ssovf_log_dbg("Failed to update seqn_list");
return -1;
@@ -1203,16 +1205,17 @@ worker_flow_based_pipeline_max_stages_rand_sched_type(void *arg)
struct rte_event ev;
uint16_t valid_event;
uint8_t port = param->port;
- rte_atomic32_t *total_events = param->total_events;
+ __rte_atomic uint32_t *total_events = param->total_events;
- while (rte_atomic32_read(total_events) > 0) {
+ while (rte_atomic_load_explicit(total_events, rte_memory_order_relaxed) > 0) {
valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0);
if (!valid_event)
continue;
if (ev.sub_event_type == 255) { /* last stage */
rte_pktmbuf_free(ev.mbuf);
- rte_atomic32_sub(total_events, 1);
+ rte_atomic_fetch_sub_explicit(total_events, 1,
+ rte_memory_order_release);
} else {
ev.event_type = RTE_EVENT_TYPE_CPU;
ev.sub_event_type++;
@@ -1278,16 +1281,17 @@ worker_queue_based_pipeline_max_stages_rand_sched_type(void *arg)
RTE_EVENT_DEV_ATTR_QUEUE_COUNT,
&queue_count), "Queue count get failed");
uint8_t nr_queues = queue_count;
- rte_atomic32_t *total_events = param->total_events;
+ __rte_atomic uint32_t *total_events = param->total_events;
- while (rte_atomic32_read(total_events) > 0) {
+ while (rte_atomic_load_explicit(total_events, rte_memory_order_relaxed) > 0) {
valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0);
if (!valid_event)
continue;
if (ev.queue_id == nr_queues - 1) { /* last stage */
rte_pktmbuf_free(ev.mbuf);
- rte_atomic32_sub(total_events, 1);
+ rte_atomic_fetch_sub_explicit(total_events, 1,
+ rte_memory_order_release);
} else {
ev.event_type = RTE_EVENT_TYPE_CPU;
ev.queue_id++;
@@ -1320,16 +1324,17 @@ worker_mixed_pipeline_max_stages_rand_sched_type(void *arg)
RTE_EVENT_DEV_ATTR_QUEUE_COUNT,
&queue_count), "Queue count get failed");
uint8_t nr_queues = queue_count;
- rte_atomic32_t *total_events = param->total_events;
+ __rte_atomic uint32_t *total_events = param->total_events;
- while (rte_atomic32_read(total_events) > 0) {
+ while (rte_atomic_load_explicit(total_events, rte_memory_order_relaxed) > 0) {
valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0);
if (!valid_event)
continue;
if (ev.queue_id == nr_queues - 1) { /* Last stage */
rte_pktmbuf_free(ev.mbuf);
- rte_atomic32_sub(total_events, 1);
+ rte_atomic_fetch_sub_explicit(total_events, 1,
+ rte_memory_order_release);
} else {
ev.event_type = RTE_EVENT_TYPE_CPU;
ev.queue_id++;
--
2.53.0
^ permalink raw reply related
* [PATCH v5 17/24] bus/fslmc: replace rte_atomic32 with stdatomic
From: Stephen Hemminger @ 2026-06-20 2:28 UTC (permalink / raw)
To: dev; +Cc: Stephen Hemminger, Hemant Agrawal, Sachin Saxena
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
The atomic wrappers here are easily converted to stdatomic.
Drop any unused macros.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
drivers/bus/fslmc/qbman/include/compat.h | 21 ++++++++-------------
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/drivers/bus/fslmc/qbman/include/compat.h b/drivers/bus/fslmc/qbman/include/compat.h
index 5a57bd8ed1..9c87f0b639 100644
--- a/drivers/bus/fslmc/qbman/include/compat.h
+++ b/drivers/bus/fslmc/qbman/include/compat.h
@@ -81,18 +81,13 @@ do { \
#define dma_wmb() rte_io_wmb()
-#define atomic_t rte_atomic32_t
-#define atomic_read(v) rte_atomic32_read(v)
-#define atomic_set(v, i) rte_atomic32_set(v, i)
-
-#define atomic_inc(v) rte_atomic32_add(v, 1)
-#define atomic_dec(v) rte_atomic32_sub(v, 1)
-
-#define atomic_inc_and_test(v) rte_atomic32_inc_and_test(v)
-#define atomic_dec_and_test(v) rte_atomic32_dec_and_test(v)
-
-#define atomic_inc_return(v) rte_atomic32_add_return(v, 1)
-#define atomic_dec_return(v) rte_atomic32_sub_return(v, 1)
-#define atomic_sub_and_test(i, v) (rte_atomic32_sub_return(v, i) == 0)
+typedef RTE_ATOMIC(uint32_t) atomic_t;
+
+#define atomic_read(v) rte_atomic_load_explicit((v), rte_memory_order_relaxed)
+#define atomic_set(v, i) rte_atomic_store_explicit((v), (i), rte_memory_order_relaxed)
+#define atomic_inc(v) ((void)rte_atomic_fetch_add_explicit((v), 1, rte_memory_order_seq_cst))
+#define atomic_dec(v) ((void)rte_atomic_fetch_sub_explicit((v), 1, rte_memory_order_seq_cst))
+#define atomic_inc_and_test(v) (rte_atomic_fetch_add_explicit((v), 1, rte_memory_order_seq_cst) == -1)
+#define atomic_dec_and_test(v) (rte_atomic_fetch_sub_explicit((v), 1, rte_memory_order_seq_cst) == 1)
#endif /* HEADER_COMPAT_H */
--
2.53.0
^ permalink raw reply related
* [PATCH v5 16/24] net/bnx2x: convert from rte_atomic32 to stdatomic
From: Stephen Hemminger @ 2026-06-20 2:28 UTC (permalink / raw)
To: dev; +Cc: Stephen Hemminger, Julien Aube
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
Replace the legacy rte_atomic32_* API on sc->scan_fp with the
equivalent rte_atomic_*_explicit C11 helpers, ahead of the
deprecation of rte_atomicNN_t and its associated wrappers.
All accesses use rte_memory_order_seq_cst, matching the semantics
of the legacy API. No functional change.
The scan_fp field is a notification flag between the slow-path
command poster (bnx2x_sp_post) and the fastpath task that reaps
ramrod completions (bnx2x_handle_fp_tq), also cleared from
ecore_state_wait on success, panic, and timeout.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
drivers/net/bnx2x/bnx2x.c | 6 +++---
drivers/net/bnx2x/bnx2x.h | 2 +-
drivers/net/bnx2x/ecore_sp.c | 6 +++---
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
index 8790c858d5..027a0a50d5 100644
--- a/drivers/net/bnx2x/bnx2x.c
+++ b/drivers/net/bnx2x/bnx2x.c
@@ -1098,7 +1098,7 @@ bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
* Ask bnx2x_intr_intr() to process RAMROD
* completion whenever it gets scheduled.
*/
- rte_atomic32_set(&sc->scan_fp, 1);
+ rte_atomic_store_explicit(&sc->scan_fp, 1, rte_memory_order_seq_cst);
bnx2x_sp_prod_update(sc);
return 0;
@@ -4575,7 +4575,7 @@ static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp)
/* update the fastpath index */
bnx2x_update_fp_sb_idx(fp);
- if (rte_atomic32_read(&sc->scan_fp) == 1) {
+ if (rte_atomic_load_explicit(&sc->scan_fp, rte_memory_order_seq_cst)) {
if (bnx2x_has_rx_work(fp)) {
more_rx = bnx2x_rxeof(sc, fp);
}
@@ -4586,7 +4586,7 @@ static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp)
return;
}
/* We have completed slow path completion, clear the flag */
- rte_atomic32_set(&sc->scan_fp, 0);
+ rte_atomic_store_explicit(&sc->scan_fp, 0, rte_memory_order_seq_cst);
}
bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 35206b4758..c5de4b71aa 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -1043,7 +1043,7 @@ struct bnx2x_softc {
#define PERIODIC_STOP 0
#define PERIODIC_GO 1
volatile unsigned long periodic_flags;
- rte_atomic32_t scan_fp;
+ RTE_ATOMIC(uint32_t) scan_fp;
struct bnx2x_fastpath fp[MAX_RSS_CHAINS];
struct bnx2x_sp_objs sp_objs[MAX_RSS_CHAINS];
diff --git a/drivers/net/bnx2x/ecore_sp.c b/drivers/net/bnx2x/ecore_sp.c
index c6c3857778..33a40dea6e 100644
--- a/drivers/net/bnx2x/ecore_sp.c
+++ b/drivers/net/bnx2x/ecore_sp.c
@@ -299,21 +299,21 @@ static int ecore_state_wait(struct bnx2x_softc *sc, int state,
#ifdef ECORE_STOP_ON_ERROR
ECORE_MSG(sc, "exit (cnt %d)", 5000 - cnt);
#endif
- rte_atomic32_set(&sc->scan_fp, 0);
+ rte_atomic_store_explicit(&sc->scan_fp, 0, rte_memory_order_seq_cst);
return ECORE_SUCCESS;
}
ECORE_WAIT(sc, delay_us);
if (sc->panic) {
- rte_atomic32_set(&sc->scan_fp, 0);
+ rte_atomic_store_explicit(&sc->scan_fp, 0, rte_memory_order_seq_cst);
return ECORE_IO;
}
}
/* timeout! */
PMD_DRV_LOG(ERR, sc, "timeout waiting for state %d", state);
- rte_atomic32_set(&sc->scan_fp, 0);
+ rte_atomic_store_explicit(&sc->scan_fp, 0, rte_memory_order_seq_cst);
#ifdef ECORE_STOP_ON_ERROR
ecore_panic();
#endif
--
2.53.0
^ permalink raw reply related
* [PATCH v5 15/24] common/dpaax: use stdatomic instead of rte_atomic
From: Stephen Hemminger @ 2026-06-20 2:28 UTC (permalink / raw)
To: dev; +Cc: Stephen Hemminger, Hemant Agrawal, Sachin Saxena
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
The driver debug code uses local atomic wrappers;
convert them to DPDK rte_atomic wrappers for C11 stdatomic.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
drivers/common/dpaax/compat.h | 21 ++++++++-------------
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/drivers/common/dpaax/compat.h b/drivers/common/dpaax/compat.h
index d0635255da..793616e095 100644
--- a/drivers/common/dpaax/compat.h
+++ b/drivers/common/dpaax/compat.h
@@ -365,19 +365,14 @@ static inline unsigned long get_zeroed_page(gfp_t __foo __rte_unused)
#define spin_lock_irqsave(x, f) spin_lock_irq(x)
#define spin_unlock_irqrestore(x, f) spin_unlock_irq(x)
-#define atomic_t rte_atomic32_t
-#define atomic_read(v) rte_atomic32_read(v)
-#define atomic_set(v, i) rte_atomic32_set(v, i)
-
-#define atomic_inc(v) rte_atomic32_add(v, 1)
-#define atomic_dec(v) rte_atomic32_sub(v, 1)
-
-#define atomic_inc_and_test(v) rte_atomic32_inc_and_test(v)
-#define atomic_dec_and_test(v) rte_atomic32_dec_and_test(v)
-
-#define atomic_inc_return(v) rte_atomic32_add_return(v, 1)
-#define atomic_dec_return(v) rte_atomic32_sub_return(v, 1)
-#define atomic_sub_and_test(i, v) (rte_atomic32_sub_return(v, i) == 0)
+typedef RTE_ATOMIC(uint32_t) atomic_t;
+
+#define atomic_read(v) rte_atomic_load_explicit((v), rte_memory_order_relaxed)
+#define atomic_set(v, i) rte_atomic_store_explicit((v), (i), rte_memory_order_relaxed)
+#define atomic_inc(v) ((void)rte_atomic_fetch_add_explicit((v), 1, rte_memory_order_seq_cst))
+#define atomic_dec(v) ((void)rte_atomic_fetch_sub_explicit((v), 1, rte_memory_order_seq_cst))
+#define atomic_inc_and_test(v) (rte_atomic_fetch_add_explicit((v), 1, rte_memory_order_seq_cst) == -1)
+#define atomic_dec_and_test(v) (rte_atomic_fetch_sub_explicit((v), 1, rte_memory_order_seq_cst) == 1)
/* Interface name len*/
#define IF_NAME_MAX_LEN 16
--
2.53.0
^ permalink raw reply related
* [PATCH v5 14/24] bus/vmbus: convert from rte_atomic to stdatomic
From: Stephen Hemminger @ 2026-06-20 2:28 UTC (permalink / raw)
To: dev; +Cc: Stephen Hemminger, Long Li, Wei Hu
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
Replace deprecated rte_atomic32 operations in the vmbus ring buffer
producer with stdatomic equivalents, and replace the smp_wmb + CAS-spin
publish with rte_wait_until_equal_32 + release-store.
The two-cursor design is preserved: tbr->windex is the driver-private
reservation cursor that lets producers reserve slots concurrently
without a lock; vbr->windex is the host-visible commit cursor, updated
in reservation order so the host never observes windex pointing past
unwritten data. This is the lockless analogue of the spinlock-around-
single-cursor pattern used by the Linux (drivers/hv/ring_buffer.c
hv_ringbuffer_write) and FreeBSD (sys/dev/hyperv/vmbus/vmbus_br.c
vmbus_txbr_write) implementations of the same host contract.
The memory ordering mirrors __rte_ring_headtail_move_head and
__rte_ring_update_tail in lib/ring/rte_ring_c11_pvt.h: relaxed wait
for the previous producer's commit, release-store to publish. The
rte_smp_wmb before the publish is folded into the release ordering
on the store itself.
The host-shared vbr->windex remains volatile uint32_t in the packed
bufring struct; the atomic qualifier is added via cast at the access
site. The (uintptr_t) launder on the store-side cast suppresses a
spurious misaligned-atomic warning from the packed-struct attribute
(windex is 4-byte aligned in practice, at offset 0 of a page-aligned
struct).
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
drivers/bus/vmbus/private.h | 2 +-
drivers/bus/vmbus/vmbus_bufring.c | 39 +++++++++++++++++--------------
2 files changed, 23 insertions(+), 18 deletions(-)
diff --git a/drivers/bus/vmbus/private.h b/drivers/bus/vmbus/private.h
index 6efac86b77..6b7782724f 100644
--- a/drivers/bus/vmbus/private.h
+++ b/drivers/bus/vmbus/private.h
@@ -25,7 +25,7 @@ extern int vmbus_logtype_bus;
struct vmbus_br {
struct vmbus_bufring *vbr;
uint32_t dsize;
- uint32_t windex; /* next available location */
+ RTE_ATOMIC(uint32_t) windex; /* next available location */
};
#define UIO_NAME_MAX 64
diff --git a/drivers/bus/vmbus/vmbus_bufring.c b/drivers/bus/vmbus/vmbus_bufring.c
index fcb97287dc..624fe8b6c5 100644
--- a/drivers/bus/vmbus/vmbus_bufring.c
+++ b/drivers/bus/vmbus/vmbus_bufring.c
@@ -15,7 +15,7 @@
#include <rte_tailq.h>
#include <rte_log.h>
#include <rte_malloc.h>
-#include <rte_atomic.h>
+#include <rte_stdatomic.h>
#include <rte_memory.h>
#include <rte_pause.h>
#include <rte_bus_vmbus.h>
@@ -114,6 +114,7 @@ vmbus_txbr_write(struct vmbus_br *tbr, const struct iovec iov[], int iovlen,
uint32_t ring_size = tbr->dsize;
uint32_t old_windex, next_windex, windex, total;
uint64_t save_windex;
+ bool success;
int i;
total = 0;
@@ -121,17 +122,13 @@ vmbus_txbr_write(struct vmbus_br *tbr, const struct iovec iov[], int iovlen,
total += iov[i].iov_len;
total += sizeof(save_windex);
+ /* Get current free location */
+ old_windex = rte_atomic_load_explicit(&tbr->windex,
+ rte_memory_order_relaxed);
+
/* Reserve space in ring */
do {
- uint32_t avail;
-
- /* Get current free location */
- old_windex = tbr->windex;
-
- /* Prevent compiler reordering this with calculation */
- rte_compiler_barrier();
-
- avail = vmbus_br_availwrite(tbr, old_windex);
+ uint32_t avail = vmbus_br_availwrite(tbr, old_windex);
/* If not enough space in ring, then tell caller. */
if (avail <= total)
@@ -139,8 +136,13 @@ vmbus_txbr_write(struct vmbus_br *tbr, const struct iovec iov[], int iovlen,
next_windex = vmbus_br_idxinc(old_windex, total, ring_size);
- /* Atomic update of next write_index for other threads */
- } while (!rte_atomic32_cmpset(&tbr->windex, old_windex, next_windex));
+ /* Atomic update of next write_index for other threads
+ * Can use weak since easy to recompute and retry.
+ */
+ success = rte_atomic_compare_exchange_weak_explicit(
+ &tbr->windex, &old_windex, next_windex,
+ rte_memory_order_acquire, rte_memory_order_relaxed);
+ } while (unlikely(!success));
/* Space from old..new is now reserved */
windex = old_windex;
@@ -157,12 +159,15 @@ vmbus_txbr_write(struct vmbus_br *tbr, const struct iovec iov[], int iovlen,
/* The region reserved should match region used */
RTE_ASSERT(windex == next_windex);
- /* Ensure that data is available before updating host index */
- rte_smp_wmb();
+ /* Wait for previous producer to publish their windex update */
+ rte_wait_until_equal_32(&vbr->windex, old_windex, rte_memory_order_relaxed);
- /* Checkin for our reservation. wait for our turn to update host */
- while (!rte_atomic32_cmpset(&vbr->windex, old_windex, next_windex))
- rte_pause();
+ /* Publish our windex update; prior data writes ordered via release.
+ * windex is 4-byte aligned in practice (struct is page-aligned, windex
+ * at offset 0); cast launders the packed-struct alignment-1 attribute.
+ */
+ rte_atomic_store_explicit((volatile __rte_atomic uint32_t *)(uintptr_t)&vbr->windex,
+ next_windex, rte_memory_order_release);
/* If host had read all data before this, then need to signal */
*need_sig |= vmbus_txbr_need_signal(vbr, old_windex);
--
2.53.0
^ permalink raw reply related
* [PATCH v5 13/24] event/sw: convert from rte_atomic32 to stdatomic
From: Stephen Hemminger @ 2026-06-20 2:28 UTC (permalink / raw)
To: dev; +Cc: Stephen Hemminger
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
Use stdatomic to keep track of inflights.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
drivers/event/sw/sw_evdev.c | 8 +++++---
drivers/event/sw/sw_evdev.h | 4 ++--
drivers/event/sw/sw_evdev_worker.c | 16 +++++++++++-----
3 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/event/sw/sw_evdev.c b/drivers/event/sw/sw_evdev.c
index 3ad82e94ac..a2f760a98d 100644
--- a/drivers/event/sw/sw_evdev.c
+++ b/drivers/event/sw/sw_evdev.c
@@ -153,7 +153,9 @@ sw_port_setup(struct rte_eventdev *dev, uint8_t port_id,
* the sum to no leak credits
*/
int possible_inflights = p->inflight_credits + p->inflights;
- rte_atomic32_sub(&sw->inflights, possible_inflights);
+ rte_atomic_fetch_sub_explicit(&sw->inflights,
+ possible_inflights,
+ rte_memory_order_release);
}
*p = (struct sw_port){0}; /* zero entire structure */
@@ -512,7 +514,7 @@ sw_dev_configure(const struct rte_eventdev *dev)
sw->qid_count = conf->nb_event_queues;
sw->port_count = conf->nb_event_ports;
sw->nb_events_limit = conf->nb_events_limit;
- rte_atomic32_set(&sw->inflights, 0);
+ sw->inflights = 0;
/* Number of chunks sized for worst-case spread of events across IQs */
num_chunks = ((SW_INFLIGHT_EVENTS_TOTAL/SW_EVS_PER_Q_CHUNK)+1) +
@@ -633,7 +635,7 @@ sw_dump(struct rte_eventdev *dev, FILE *f)
fprintf(f, "\tsched cq/qid call: %"PRIu64"\n", sw->sched_cq_qid_called);
fprintf(f, "\tsched no IQ enq: %"PRIu64"\n", sw->sched_no_iq_enqueues);
fprintf(f, "\tsched no CQ enq: %"PRIu64"\n", sw->sched_no_cq_enqueues);
- uint32_t inflights = rte_atomic32_read(&sw->inflights);
+ uint32_t inflights = rte_atomic_load_explicit(&sw->inflights, rte_memory_order_relaxed);
uint32_t credits = sw->nb_events_limit - inflights;
fprintf(f, "\tinflight %d, credits: %d\n", inflights, credits);
diff --git a/drivers/event/sw/sw_evdev.h b/drivers/event/sw/sw_evdev.h
index c159be21be..5e49b08030 100644
--- a/drivers/event/sw/sw_evdev.h
+++ b/drivers/event/sw/sw_evdev.h
@@ -8,7 +8,7 @@
#include "sw_evdev_log.h"
#include <rte_eventdev.h>
#include <eventdev_pmd_vdev.h>
-#include <rte_atomic.h>
+#include <rte_stdatomic.h>
#define SW_DEFAULT_CREDIT_QUANTA 32
#define SW_DEFAULT_SCHED_QUANTA 128
@@ -233,7 +233,7 @@ struct sw_evdev {
/* Contains all ports - load balanced and directed */
alignas(RTE_CACHE_LINE_SIZE) struct sw_port ports[SW_PORTS_MAX];
- alignas(RTE_CACHE_LINE_SIZE) rte_atomic32_t inflights;
+ alignas(RTE_CACHE_LINE_SIZE) RTE_ATOMIC(uint32_t) inflights;
/*
* max events in this instance. Cached here for performance.
diff --git a/drivers/event/sw/sw_evdev_worker.c b/drivers/event/sw/sw_evdev_worker.c
index 4215726513..0755def367 100644
--- a/drivers/event/sw/sw_evdev_worker.c
+++ b/drivers/event/sw/sw_evdev_worker.c
@@ -56,7 +56,7 @@ sw_event_enqueue_burst(void *port, const struct rte_event ev[], uint16_t num)
uint8_t new_ops[PORT_ENQUEUE_MAX_BURST_SIZE];
struct sw_port *p = port;
struct sw_evdev *sw = (void *)p->sw;
- uint32_t sw_inflights = rte_atomic32_read(&sw->inflights);
+ uint32_t sw_inflights = rte_atomic_load_explicit(&sw->inflights, rte_memory_order_relaxed);
uint32_t credit_update_quanta = sw->credit_update_quanta;
int new = 0;
@@ -74,8 +74,10 @@ sw_event_enqueue_burst(void *port, const struct rte_event ev[], uint16_t num)
if (sw_inflights + credit_update_quanta > sw->nb_events_limit)
return 0;
- rte_atomic32_add(&sw->inflights, credit_update_quanta);
- p->inflight_credits += (credit_update_quanta);
+ rte_atomic_fetch_add_explicit(&sw->inflights,
+ credit_update_quanta,
+ rte_memory_order_acquire);
+ p->inflight_credits += credit_update_quanta;
/* If there are fewer inflight credits than new events, limit
* the number of enqueued events.
@@ -124,7 +126,9 @@ sw_event_enqueue_burst(void *port, const struct rte_event ev[], uint16_t num)
/* Replenish credits if enough releases are performed */
if (p->inflight_credits >= credit_update_quanta * 2) {
- rte_atomic32_sub(&sw->inflights, credit_update_quanta);
+ rte_atomic_fetch_sub_explicit(&sw->inflights,
+ credit_update_quanta,
+ rte_memory_order_release);
p->inflight_credits -= credit_update_quanta;
}
@@ -150,7 +154,9 @@ sw_event_dequeue_burst(void *port, struct rte_event *ev, uint16_t num,
/* Replenish credits if enough releases are performed */
if (p->inflight_credits >= credit_update_quanta * 2) {
- rte_atomic32_sub(&sw->inflights, credit_update_quanta);
+ rte_atomic_fetch_sub_explicit(&sw->inflights,
+ credit_update_quanta,
+ rte_memory_order_release);
p->inflight_credits -= credit_update_quanta;
}
}
--
2.53.0
^ permalink raw reply related
* [PATCH v5 12/24] net/netvsc: replace rte_atomic32 with stdatomic
From: Stephen Hemminger @ 2026-06-20 2:28 UTC (permalink / raw)
To: dev; +Cc: Stephen Hemminger, Long Li, Wei Hu
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
Change the rndis transaction id and buffer usage to use
stdatomic functions.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
drivers/net/netvsc/hn_rndis.c | 28 +++++++++++++++++++---------
drivers/net/netvsc/hn_rxtx.c | 12 +++++++-----
drivers/net/netvsc/hn_var.h | 6 +++---
3 files changed, 29 insertions(+), 17 deletions(-)
diff --git a/drivers/net/netvsc/hn_rndis.c b/drivers/net/netvsc/hn_rndis.c
index 7c54eebcef..4b1d3d5539 100644
--- a/drivers/net/netvsc/hn_rndis.c
+++ b/drivers/net/netvsc/hn_rndis.c
@@ -17,7 +17,7 @@
#include <rte_string_fns.h>
#include <rte_memzone.h>
#include <rte_malloc.h>
-#include <rte_atomic.h>
+#include <rte_stdatomic.h>
#include <rte_alarm.h>
#include <rte_branch_prediction.h>
#include <rte_ether.h>
@@ -59,7 +59,8 @@ hn_rndis_rid(struct hn_data *hv)
uint32_t rid;
do {
- rid = rte_atomic32_add_return(&hv->rndis_req_id, 1);
+ rid = rte_atomic_fetch_add_explicit(&hv->rndis_req_id, 1,
+ rte_memory_order_seq_cst);
} while (rid == 0);
return rid;
@@ -357,12 +358,14 @@ void hn_rndis_receive_response(struct hn_data *hv,
memcpy(hv->rndis_resp, data, len);
/* make sure response copied before update */
- rte_smp_wmb();
-
- if (rte_atomic32_cmpset(&hv->rndis_pending, hdr->rid, 0) == 0) {
+ uint32_t expected = hdr->rid;
+ if (!rte_atomic_compare_exchange_strong_explicit(&hv->rndis_pending,
+ &expected, 0,
+ rte_memory_order_release,
+ rte_memory_order_relaxed)) {
PMD_DRV_LOG(NOTICE,
"received id %#x pending id %#x",
- hdr->rid, (uint32_t)hv->rndis_pending);
+ hdr->rid, expected);
}
}
@@ -388,8 +391,11 @@ static int hn_rndis_exec1(struct hn_data *hv,
return -EINVAL;
}
+ uint32_t expected = 0;
if (comp != NULL &&
- rte_atomic32_cmpset(&hv->rndis_pending, 0, rid) == 0) {
+ !rte_atomic_compare_exchange_strong_explicit(
+ &hv->rndis_pending, &expected, rid,
+ rte_memory_order_acquire, rte_memory_order_relaxed)) {
PMD_DRV_LOG(ERR,
"Request already pending");
return -EBUSY;
@@ -405,7 +411,8 @@ static int hn_rndis_exec1(struct hn_data *hv,
time_t start = time(NULL);
/* Poll primary channel until response received */
- while (hv->rndis_pending == rid) {
+ while (rte_atomic_load_explicit(&hv->rndis_pending,
+ rte_memory_order_acquire) == rid) {
if (hv->closed)
return -ENETDOWN;
@@ -413,7 +420,10 @@ static int hn_rndis_exec1(struct hn_data *hv,
PMD_DRV_LOG(ERR,
"RNDIS response timed out");
- rte_atomic32_cmpset(&hv->rndis_pending, rid, 0);
+ expected = rid;
+ rte_atomic_compare_exchange_strong_explicit(
+ &hv->rndis_pending, &expected, 0,
+ rte_memory_order_release, rte_memory_order_relaxed);
return -ETIMEDOUT;
}
diff --git a/drivers/net/netvsc/hn_rxtx.c b/drivers/net/netvsc/hn_rxtx.c
index 0d770d1b25..6f536610f2 100644
--- a/drivers/net/netvsc/hn_rxtx.c
+++ b/drivers/net/netvsc/hn_rxtx.c
@@ -17,7 +17,7 @@
#include <rte_string_fns.h>
#include <rte_memzone.h>
#include <rte_malloc.h>
-#include <rte_atomic.h>
+#include <rte_stdatomic.h>
#include <rte_bitmap.h>
#include <rte_branch_prediction.h>
#include <rte_ether.h>
@@ -558,7 +558,8 @@ static void hn_rx_buf_free_cb(void *buf __rte_unused, void *opaque)
struct hn_rx_queue *rxq = rxb->rxq;
struct hn_data *hv = rxq->hv;
- rte_atomic32_dec(&rxq->rxbuf_outstanding);
+ rte_atomic_fetch_sub_explicit(&rxq->rxbuf_outstanding, 1,
+ rte_memory_order_release);
hn_nvs_ack_rxbuf(hv, rxb->chan, rxb->xactid);
}
@@ -602,8 +603,8 @@ static void hn_rxpkt(struct hn_rx_queue *rxq, struct hn_rx_bufinfo *rxb,
* some space available in receive area for later packets.
*/
if (hv->rx_extmbuf_enable && dlen > hv->rx_copybreak &&
- (uint32_t)rte_atomic32_read(&rxq->rxbuf_outstanding) <
- hv->rxbuf_section_cnt / 2) {
+ rte_atomic_load_explicit(&rxq->rxbuf_outstanding,
+ rte_memory_order_relaxed) < hv->rxbuf_section_cnt / 2) {
struct rte_mbuf_ext_shared_info *shinfo;
const void *rxbuf;
rte_iova_t iova;
@@ -619,7 +620,8 @@ static void hn_rxpkt(struct hn_rx_queue *rxq, struct hn_rx_bufinfo *rxb,
/* shinfo is already set to 1 by the caller */
if (rte_mbuf_ext_refcnt_update(shinfo, 1) == 2)
- rte_atomic32_inc(&rxq->rxbuf_outstanding);
+ rte_atomic_fetch_add_explicit(&rxq->rxbuf_outstanding, 1,
+ rte_memory_order_acquire);
rte_pktmbuf_attach_extbuf(m, data, iova,
dlen + headroom, shinfo);
diff --git a/drivers/net/netvsc/hn_var.h b/drivers/net/netvsc/hn_var.h
index 574b909c82..d7124a7df9 100644
--- a/drivers/net/netvsc/hn_var.h
+++ b/drivers/net/netvsc/hn_var.h
@@ -85,7 +85,7 @@ struct hn_rx_queue {
void *event_buf;
struct hn_rx_bufinfo *rxbuf_info;
- rte_atomic32_t rxbuf_outstanding;
+ RTE_ATOMIC(uint32_t) rxbuf_outstanding;
};
@@ -167,8 +167,8 @@ struct hn_data {
uint32_t rndis_agg_pkts;
uint32_t rndis_agg_align;
- volatile uint32_t rndis_pending;
- rte_atomic32_t rndis_req_id;
+ RTE_ATOMIC(uint32_t) rndis_pending;
+ RTE_ATOMIC(uint32_t) rndis_req_id;
uint8_t rndis_resp[256];
uint32_t rss_hash;
--
2.53.0
^ permalink raw reply related
* [PATCH v5 11/24] drivers: replace rte_atomic16 with stdatomic
From: Stephen Hemminger @ 2026-06-20 2:28 UTC (permalink / raw)
To: dev; +Cc: Stephen Hemminger, Hemant Agrawal, Sachin Saxena
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
The rte_atomicNN functions and types are deprecated.
The in_use and reference counts flag can be converted to stdatomic.
Also drop the unneeded NULL check in the loop body: TAILQ_FOREACH
terminates when the iterator becomes NULL, so var is guaranteed
non-NULL inside the loop.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c | 10 +++++++---
drivers/bus/fslmc/portal/dpaa2_hw_dpci.c | 10 +++++++---
drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 12 ++++++++----
drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 8 ++++----
drivers/event/dpaa2/dpaa2_hw_dpcon.c | 11 +++++++----
5 files changed, 33 insertions(+), 18 deletions(-)
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c
index 925e83e97d..7b08593338 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpbp.c
@@ -84,7 +84,7 @@ dpaa2_create_dpbp_device(int vdev_fd __rte_unused,
}
dpbp_node->dpbp_id = dpbp_id;
- rte_atomic16_init(&dpbp_node->in_use);
+ dpbp_node->in_use = 0;
TAILQ_INSERT_TAIL(&dpbp_dev_list, dpbp_node, next);
@@ -103,7 +103,10 @@ struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void)
/* Get DPBP dev handle from list using index */
TAILQ_FOREACH(dpbp_dev, &dpbp_dev_list, next) {
- if (dpbp_dev && rte_atomic16_test_and_set(&dpbp_dev->in_use))
+ uint16_t expected = 0;
+ if (rte_atomic_compare_exchange_strong_explicit(
+ &dpbp_dev->in_use, &expected, 1,
+ rte_memory_order_acquire, rte_memory_order_relaxed))
break;
}
@@ -118,7 +121,8 @@ void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp)
/* Match DPBP handle and mark it free */
TAILQ_FOREACH(dpbp_dev, &dpbp_dev_list, next) {
if (dpbp_dev == dpbp) {
- rte_atomic16_dec(&dpbp_dev->in_use);
+ rte_atomic_store_explicit(&dpbp_dev->in_use, 0,
+ rte_memory_order_release);
return;
}
}
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpci.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpci.c
index b546da82f6..0e36fcdcd4 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpci.c
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpci.c
@@ -135,7 +135,7 @@ rte_dpaa2_create_dpci_device(int vdev_fd __rte_unused,
}
dpci_node->dpci_id = dpci_id;
- rte_atomic16_init(&dpci_node->in_use);
+ dpci_node->in_use = 0;
TAILQ_INSERT_TAIL(&dpci_dev_list, dpci_node, next);
@@ -159,7 +159,10 @@ struct dpaa2_dpci_dev *rte_dpaa2_alloc_dpci_dev(void)
/* Get DPCI dev handle from list using index */
TAILQ_FOREACH(dpci_dev, &dpci_dev_list, next) {
- if (dpci_dev && rte_atomic16_test_and_set(&dpci_dev->in_use))
+ uint16_t expected = 0;
+ if (rte_atomic_compare_exchange_strong_explicit(
+ &dpci_dev->in_use, &expected, 1,
+ rte_memory_order_acquire, rte_memory_order_relaxed))
break;
}
@@ -174,7 +177,8 @@ void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci)
/* Match DPCI handle and mark it free */
TAILQ_FOREACH(dpci_dev, &dpci_dev_list, next) {
if (dpci_dev == dpci) {
- rte_atomic16_dec(&dpci_dev->in_use);
+ rte_atomic_store_explicit(&dpci_dev->in_use, 0,
+ rte_memory_order_release);
return;
}
}
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
index 2a9e519668..06ddb366d8 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
@@ -293,7 +293,7 @@ static void dpaa2_put_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
#ifdef RTE_EVENT_DPAA2
dpaa2_dpio_intr_deinit(dpio_dev);
#endif
- rte_atomic16_clear(&dpio_dev->ref_count);
+ rte_atomic_store_explicit(&dpio_dev->ref_count, 0, rte_memory_order_release);
}
}
@@ -305,7 +305,10 @@ static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
/* Get DPIO dev handle from list using index */
TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
- if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
+ uint16_t expected = 0;
+ if (rte_atomic_compare_exchange_strong_explicit(
+ &dpio_dev->ref_count, &expected, 1,
+ rte_memory_order_acquire, rte_memory_order_relaxed))
break;
}
if (!dpio_dev) {
@@ -326,7 +329,8 @@ static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void)
ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
if (ret) {
DPAA2_BUS_ERR("dpaa2_configure_stashing failed");
- rte_atomic16_clear(&dpio_dev->ref_count);
+ rte_atomic_store_explicit(&dpio_dev->ref_count, 0,
+ rte_memory_order_release);
return NULL;
}
}
@@ -441,7 +445,7 @@ dpaa2_create_dpio_device(int vdev_fd,
dpio_dev->dpio = NULL;
dpio_dev->hw_id = object_id;
- rte_atomic16_init(&dpio_dev->ref_count);
+
/* Using single portal for all devices */
dpio_dev->mc_portal = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
index e625a5c035..f2298b18e5 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
@@ -112,7 +112,7 @@ struct dpaa2_dpio_dev {
TAILQ_ENTRY(dpaa2_dpio_dev) next;
/**< Pointer to Next device instance */
uint16_t index; /**< Index of a instance in the list */
- rte_atomic16_t ref_count;
+ RTE_ATOMIC(uint16_t) ref_count;
/**< How many thread contexts are sharing this.*/
uint16_t eqresp_ci;
uint16_t eqresp_pi;
@@ -141,7 +141,7 @@ struct dpaa2_dpbp_dev {
/**< Pointer to Next device instance */
struct fsl_mc_io dpbp; /** handle to DPBP portal object */
uint16_t token;
- rte_atomic16_t in_use;
+ RTE_ATOMIC(uint16_t) in_use;
uint32_t dpbp_id; /*HW ID for DPBP object */
};
@@ -257,7 +257,7 @@ struct dpaa2_dpci_dev {
/**< Pointer to Next device instance */
struct fsl_mc_io dpci; /** handle to DPCI portal object */
uint16_t token;
- rte_atomic16_t in_use;
+ RTE_ATOMIC(uint16_t) in_use;
uint32_t dpci_id; /*HW ID for DPCI object */
struct dpaa2_queue rx_queue[DPAA2_DPCI_MAX_QUEUES];
struct dpaa2_queue tx_queue[DPAA2_DPCI_MAX_QUEUES];
@@ -267,7 +267,7 @@ struct dpaa2_dpcon_dev {
TAILQ_ENTRY(dpaa2_dpcon_dev) next;
struct fsl_mc_io dpcon;
uint16_t token;
- rte_atomic16_t in_use;
+ RTE_ATOMIC(uint16_t) in_use;
uint32_t dpcon_id;
uint16_t qbman_ch_id;
uint8_t num_priorities;
diff --git a/drivers/event/dpaa2/dpaa2_hw_dpcon.c b/drivers/event/dpaa2/dpaa2_hw_dpcon.c
index ea5b0d4b85..4d1d55eace 100644
--- a/drivers/event/dpaa2/dpaa2_hw_dpcon.c
+++ b/drivers/event/dpaa2/dpaa2_hw_dpcon.c
@@ -15,6 +15,7 @@
#include <rte_malloc.h>
#include <rte_memcpy.h>
#include <rte_string_fns.h>
+#include <rte_stdatomic.h>
#include <rte_cycles.h>
#include <rte_kvargs.h>
#include <dev_driver.h>
@@ -53,7 +54,7 @@ rte_dpaa2_create_dpcon_device(int dev_fd __rte_unused,
int ret, dpcon_id = obj->object_id;
/* Allocate DPAA2 dpcon handle */
- dpcon_node = rte_malloc(NULL, sizeof(struct dpaa2_dpcon_dev), 0);
+ dpcon_node = rte_zmalloc(NULL, sizeof(struct dpaa2_dpcon_dev), 0);
if (!dpcon_node) {
DPAA2_EVENTDEV_ERR(
"Memory allocation failed for dpcon device");
@@ -85,7 +86,6 @@ rte_dpaa2_create_dpcon_device(int dev_fd __rte_unused,
dpcon_node->qbman_ch_id = attr.qbman_ch_id;
dpcon_node->num_priorities = attr.num_priorities;
dpcon_node->dpcon_id = dpcon_id;
- rte_atomic16_init(&dpcon_node->in_use);
TAILQ_INSERT_TAIL(&dpcon_dev_list, dpcon_node, next);
@@ -98,7 +98,10 @@ struct dpaa2_dpcon_dev *rte_dpaa2_alloc_dpcon_dev(void)
/* Get DPCON dev handle from list using index */
TAILQ_FOREACH(dpcon_dev, &dpcon_dev_list, next) {
- if (dpcon_dev && rte_atomic16_test_and_set(&dpcon_dev->in_use))
+ uint16_t expected = 0;
+ if (rte_atomic_compare_exchange_strong_explicit(
+ &dpcon_dev->in_use, &expected, 1,
+ rte_memory_order_acquire, rte_memory_order_relaxed))
break;
}
@@ -112,7 +115,7 @@ void rte_dpaa2_free_dpcon_dev(struct dpaa2_dpcon_dev *dpcon)
/* Match DPCON handle and mark it free */
TAILQ_FOREACH(dpcon_dev, &dpcon_dev_list, next) {
if (dpcon_dev == dpcon) {
- rte_atomic16_dec(&dpcon_dev->in_use);
+ rte_atomic_store_explicit(&dpcon_dev->in_use, 0, rte_memory_order_release);
return;
}
}
--
2.53.0
^ permalink raw reply related
* [PATCH v5 10/24] bus/dpaa: replace rte_atomic16 with stdatomic
From: Stephen Hemminger @ 2026-06-20 2:28 UTC (permalink / raw)
To: dev; +Cc: Stephen Hemminger, Hemant Agrawal, Sachin Saxena
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
This is simple inuse flag which can be done with stdatomic
exchange logic.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
drivers/bus/dpaa/base/qbman/qman.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/bus/dpaa/base/qbman/qman.c b/drivers/bus/dpaa/base/qbman/qman.c
index 5534e1846c..82a976141a 100644
--- a/drivers/bus/dpaa/base/qbman/qman.c
+++ b/drivers/bus/dpaa/base/qbman/qman.c
@@ -11,6 +11,7 @@
#include <rte_eventdev.h>
#include <rte_byteorder.h>
#include <rte_dpaa_logs.h>
+#include <rte_stdatomic.h>
#include <eal_export.h>
#include <dpaa_bits.h>
@@ -683,7 +684,7 @@ qman_init_portal(struct qman_portal *portal,
#define MAX_GLOBAL_PORTALS 8
static struct qman_portal global_portals[MAX_GLOBAL_PORTALS];
-static rte_atomic16_t global_portals_used[MAX_GLOBAL_PORTALS];
+static RTE_ATOMIC(bool) global_portals_used[MAX_GLOBAL_PORTALS];
struct qman_portal *
qman_alloc_global_portal(struct qm_portal_config *q_pcfg)
@@ -691,7 +692,8 @@ qman_alloc_global_portal(struct qm_portal_config *q_pcfg)
unsigned int i;
for (i = 0; i < MAX_GLOBAL_PORTALS; i++) {
- if (rte_atomic16_test_and_set(&global_portals_used[i])) {
+ if (!rte_atomic_exchange_explicit(&global_portals_used[i], true,
+ rte_memory_order_acquire)) {
global_portals[i].config = q_pcfg;
return &global_portals[i];
}
@@ -708,7 +710,8 @@ qman_free_global_portal(struct qman_portal *portal)
for (i = 0; i < MAX_GLOBAL_PORTALS; i++) {
if (&global_portals[i] == portal) {
- rte_atomic16_clear(&global_portals_used[i]);
+ rte_atomic_store_explicit(&global_portals_used[i], false,
+ rte_memory_order_release);
return 0;
}
}
--
2.53.0
^ permalink raw reply related
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