From: Hyungwon Hwang <human.hwang@samsung.com>
To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
inki.dae@samsung.com, daniel@fooishbar.org
Cc: dh09.lee@samsung.com, sw0312.kim@samsung.com,
Hyungwon Hwang <human.hwang@samsung.com>,
cw00.choi@samsung.com
Subject: [PATCH v5 09/12] drm/exynos: dsi: add the backward compatibility for the renamed clock
Date: Fri, 10 Apr 2015 14:55:27 +0900 [thread overview]
Message-ID: <1428645330-1043-10-git-send-email-human.hwang@samsung.com> (raw)
In-Reply-To: <1428645330-1043-1-git-send-email-human.hwang@samsung.com>
From the commit a45abd04a46048a4956408543cdbdd8bdedd3215
("drm/exynos: dsi: rename pll_clk to sclk_clk'), the compiled dtb
which contains 'pll_clk' becomes not compatible with the current DSI
driver. This patch adds the backward compatibility for this issue.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
---
Changes for v5:
- Newly added
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 5f03680..ddcb77e 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -211,6 +211,8 @@
REG_ADDR((dsi), (reg_idx)))
#define DSI_READ(dsi, reg_idx) readl(REG_ADDR((dsi), (reg_idx)))
+#define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
+
static char *clk_names[5] = { "bus_clk", "sclk_mipi",
"phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0",
"sclk_rgb_vclk_to_dsim0" };
@@ -1866,6 +1868,12 @@ static int exynos_dsi_probe(struct platform_device *pdev)
for (i = 0; i < dsi->driver_data->num_clks; i++) {
dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
if (IS_ERR(dsi->clks[i])) {
+ if (strcmp(clk_names[i], "sclk_mipi") == 0) {
+ strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME);
+ i--;
+ continue;
+ }
+
dev_info(dev, "failed to get the clock: %s\n",
clk_names[i]);
ret = PTR_ERR(dsi->clks[i]);
--
1.9.1
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next prev parent reply other threads:[~2015-04-10 5:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-10 5:55 [PATCH v5 00/12] Add drivers for Exynos5433 display Hyungwon Hwang
[not found] ` <1428645330-1043-1-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2015-04-10 5:55 ` [PATCH v5 01/12] drm/exynos: add Exynos5433 decon driver Hyungwon Hwang
[not found] ` <1428645330-1043-2-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2015-04-10 6:05 ` Varka Bhadram
2015-04-10 6:38 ` Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 02/12] of: add helper for getting endpoint node of specific identifiers Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 10/12] drm/exynos: dsi: add support for MIC driver as a bridge Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 03/12] drm/exynos: mic: add MIC driver Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 04/12] drm/exynos: dsi: rename pll_clk to sclk_clk Hyungwon Hwang
2015-04-15 1:24 ` Inki Dae
2015-04-10 5:55 ` [PATCH v5 05/12] drm/exynos: dsi: add macros for register access Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 06/12] drm/exynos: dsi: make use of driver data for static values Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 07/12] drm/exynos: dsi: make use of array for clock access Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 08/12] drm/exynos: dsi: add support for Exynos5433 Hyungwon Hwang
2015-04-10 5:55 ` Hyungwon Hwang [this message]
2015-04-10 5:55 ` [PATCH v5 11/12] drm/exynos: dsi: do not set TE GPIO direction by input Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 12/12] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi' Hyungwon Hwang
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