From: Hyungwon Hwang <human.hwang@samsung.com>
To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
inki.dae@samsung.com, daniel@fooishbar.org
Cc: dh09.lee@samsung.com, sw0312.kim@samsung.com,
Hyungwon Hwang <human.hwang@samsung.com>,
cw00.choi@samsung.com
Subject: [PATCH v5 12/12] ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
Date: Fri, 10 Apr 2015 14:55:30 +0900 [thread overview]
Message-ID: <1428645330-1043-13-git-send-email-human.hwang@samsung.com> (raw)
In-Reply-To: <1428645330-1043-1-git-send-email-human.hwang@samsung.com>
The clock which was named as 'pll_clk' is actually not the clock source
of PLL in MIPI DSI. This patch fixes this disagreement.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
---
Changes for v5:
- Newly added
arch/arm/boot/dts/exynos4.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 77ea547..ad23675 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -164,7 +164,7 @@
phys = <&mipi_phy 1>;
phy-names = "dsim";
clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
- clock-names = "bus_clk", "pll_clk";
+ clock-names = "bus_clk", "sclk_mipi";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
--
1.9.1
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prev parent reply other threads:[~2015-04-10 5:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-10 5:55 [PATCH v5 00/12] Add drivers for Exynos5433 display Hyungwon Hwang
[not found] ` <1428645330-1043-1-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2015-04-10 5:55 ` [PATCH v5 01/12] drm/exynos: add Exynos5433 decon driver Hyungwon Hwang
[not found] ` <1428645330-1043-2-git-send-email-human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2015-04-10 6:05 ` Varka Bhadram
2015-04-10 6:38 ` Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 02/12] of: add helper for getting endpoint node of specific identifiers Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 10/12] drm/exynos: dsi: add support for MIC driver as a bridge Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 03/12] drm/exynos: mic: add MIC driver Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 04/12] drm/exynos: dsi: rename pll_clk to sclk_clk Hyungwon Hwang
2015-04-15 1:24 ` Inki Dae
2015-04-10 5:55 ` [PATCH v5 05/12] drm/exynos: dsi: add macros for register access Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 06/12] drm/exynos: dsi: make use of driver data for static values Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 07/12] drm/exynos: dsi: make use of array for clock access Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 08/12] drm/exynos: dsi: add support for Exynos5433 Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 09/12] drm/exynos: dsi: add the backward compatibility for the renamed clock Hyungwon Hwang
2015-04-10 5:55 ` [PATCH v5 11/12] drm/exynos: dsi: do not set TE GPIO direction by input Hyungwon Hwang
2015-04-10 5:55 ` Hyungwon Hwang [this message]
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