From: Thomas Zimmermann <tzimmermann@suse.de>
To: airlied@redhat.com, jfalempe@redhat.com
Cc: dri-devel@lists.freedesktop.org, Thomas Zimmermann <tzimmermann@suse.de>
Subject: [PATCH 7/8] drm/ast: Merge TX-chip detection code for Gen4 and later
Date: Fri, 17 Jan 2025 11:29:12 +0100 [thread overview]
Message-ID: <20250117103450.28692-8-tzimmermann@suse.de> (raw)
In-Reply-To: <20250117103450.28692-1-tzimmermann@suse.de>
Gens 4 to 6 and Gen7 use the same pattern for detecting the installed
TX chips. Merge the code into a single branch.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
---
drivers/gpu/drm/ast/ast_main.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index 40d3b7770cf18..b0d1b99ed532b 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -110,15 +110,18 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
if (vgacra3 & AST_IO_VGACRA3_DVO_ENABLED)
ast->tx_chip = AST_TX_SIL164;
}
- } else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {
+ } else {
/*
- * On AST GEN4+, look the configuration set by the SoC in
+ * On AST GEN4+, look at the configuration set by the SoC in
* the SOC scratch register #1 bits 11:8 (interestingly marked
* as "reserved" in the spec)
*/
jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1,
AST_IO_VGACRD1_TX_TYPE_MASK);
switch (jreg) {
+ /*
+ * GEN4 to GEN6
+ */
case AST_IO_VGACRD1_TX_SIL164_VBIOS:
ast->tx_chip = AST_TX_SIL164;
break;
@@ -134,11 +137,13 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
fallthrough;
case AST_IO_VGACRD1_TX_FW_EMBEDDED_FW:
ast->tx_chip = AST_TX_DP501;
- }
- } else if (IS_AST_GEN7(ast)) {
- if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, AST_IO_VGACRD1_TX_TYPE_MASK) ==
- AST_IO_VGACRD1_TX_ASTDP) {
+ break;
+ /*
+ * GEN7+
+ */
+ case AST_IO_VGACRD1_TX_ASTDP:
ast->tx_chip = AST_TX_ASTDP;
+ break;
}
}
--
2.47.1
next prev parent reply other threads:[~2025-01-17 10:35 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-17 10:29 [PATCH 0/8] drm/ast: Reorganize TX-chip detection and init Thomas Zimmermann
2025-01-17 10:29 ` [PATCH 1/8] drm/ast: Detect wide-screen support before creating modeset pipeline Thomas Zimmermann
2025-01-20 10:34 ` Jocelyn Falempe
2025-01-17 10:29 ` [PATCH 2/8] drm/ast: Detect DRAM before TX-chip Thomas Zimmermann
2025-01-20 10:35 ` Jocelyn Falempe
2025-01-17 10:29 ` [PATCH 3/8] drm/ast: Refactor ast_post_gpu() by Gen Thomas Zimmermann
2025-01-20 10:35 ` Jocelyn Falempe
2025-01-17 10:29 ` [PATCH 4/8] drm/ast: Initialize ASTDP in ast_post_gpu() Thomas Zimmermann
2025-01-20 10:37 ` Jocelyn Falempe
2025-01-17 10:29 ` [PATCH 5/8] drm/ast: Hide Gens 1 to 3 TX detection in branch Thomas Zimmermann
2025-01-20 10:37 ` Jocelyn Falempe
2025-01-17 10:29 ` [PATCH 6/8] drm/ast: Align Gen1 DVO detection to register manual Thomas Zimmermann
2025-01-20 10:37 ` Jocelyn Falempe
2025-01-17 10:29 ` Thomas Zimmermann [this message]
2025-01-20 10:37 ` [PATCH 7/8] drm/ast: Merge TX-chip detection code for Gen4 and later Jocelyn Falempe
2025-01-17 10:29 ` [PATCH 8/8] drm/ast: Only warn about unsupported TX chips on " Thomas Zimmermann
2025-01-20 10:37 ` Jocelyn Falempe
2025-01-21 13:21 ` Thomas Zimmermann
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