* [igt-dev] [PATCH i-g-t v7 0/2] tests/kms_ccs: CCS Clear Color test
@ 2020-10-23 13:05 Mika Kahola
2020-10-23 13:05 ` [igt-dev] [PATCH i-g-t v7 1/2] tests/kms_ccs: Add debug information on format modifier Mika Kahola
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: Mika Kahola @ 2020-10-23 13:05 UTC (permalink / raw)
To: igt-dev
The patch proposes a method to test CCS with clear color
capability.
The test paints a solid color on primary fb and a small sprite fb.
These are cleared with fast clear feature. A crc is captured and
compared against the reference.
v2: Modify _gen9_render_copyfunc to support fast clear (Matt)
Enable fast clear bit on 3D sequence (Matt)
Add helper function to figure out clear color modifier (Matt)
v3: Remove unrelated line additions/removes
v4: Fast clear with color (Imre)
v5: Write raw 32-bit color values to register (Imre)
Require 32-bit color format
v6: Rebase to use batchbuffer without libdrm dependency
v7: Enable clear color (Nanley)
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Mika Kahola (2):
tests/kms_ccs: Add debug information on format modifier
tests/kms_ccs: CCS Clear Color test
lib/gen8_render.h | 1 +
lib/gen9_render.h | 6 ++-
lib/intel_batchbuffer.c | 10 ++++
lib/intel_batchbuffer.h | 6 +++
lib/rendercopy.h | 4 ++
lib/rendercopy_gen9.c | 79 +++++++++++++++++++++++-----
tests/kms_ccs.c | 112 +++++++++++++++++++++++++++++++++++-----
7 files changed, 192 insertions(+), 26 deletions(-)
--
2.25.1
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^ permalink raw reply [flat|nested] 13+ messages in thread* [igt-dev] [PATCH i-g-t v7 1/2] tests/kms_ccs: Add debug information on format modifier 2020-10-23 13:05 [igt-dev] [PATCH i-g-t v7 0/2] tests/kms_ccs: CCS Clear Color test Mika Kahola @ 2020-10-23 13:05 ` Mika Kahola 2020-10-23 13:05 ` [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test Mika Kahola ` (2 subsequent siblings) 3 siblings, 0 replies; 13+ messages in thread From: Mika Kahola @ 2020-10-23 13:05 UTC (permalink / raw) To: igt-dev We could benefit on information on what format modifier is in use when running the test. This in mind, let's add informative string along with the list of ccs modifiers. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> --- tests/kms_ccs.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index b60e4908..53abecce 100644 --- a/tests/kms_ccs.c +++ b/tests/kms_ccs.c @@ -81,12 +81,15 @@ static const uint32_t formats[] = { DRM_FORMAT_P016, }; -static const uint64_t ccs_modifiers[] = { - LOCAL_I915_FORMAT_MOD_Y_TILED_CCS, - LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS, - LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, - LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, - LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, +static const struct { + uint64_t modifier; + const char *str; +} ccs_modifiers[5] = { + {LOCAL_I915_FORMAT_MOD_Y_TILED_CCS, "LOCAL_I915_FORMAT_MOD_Y_TILED_CCS"}, + {LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS, "LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS"}, + {LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, "LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS"}, + {LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, "LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC"}, + {LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, "LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS"}, }; static bool check_ccs_planes; @@ -422,7 +425,8 @@ static int __test_output(data_t *data) for (i = 0; i < ARRAY_SIZE(ccs_modifiers); i++) { int j; - data->ccs_modifier = ccs_modifiers[i]; + data->ccs_modifier = ccs_modifiers[i].modifier; + igt_debug("Modifier in use: %s\n", ccs_modifiers[i].str); for (j = 0; j < ARRAY_SIZE(formats); j++) { data->format = formats[j]; valid_tests += test_ccs(data); -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test 2020-10-23 13:05 [igt-dev] [PATCH i-g-t v7 0/2] tests/kms_ccs: CCS Clear Color test Mika Kahola 2020-10-23 13:05 ` [igt-dev] [PATCH i-g-t v7 1/2] tests/kms_ccs: Add debug information on format modifier Mika Kahola @ 2020-10-23 13:05 ` Mika Kahola 2020-11-02 17:27 ` Imre Deak 2020-10-23 13:36 ` [igt-dev] ✓ Fi.CI.BAT: success for tests/kms_ccs: CCS Clear Color test (rev8) Patchwork 2020-10-23 16:22 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 3 siblings, 1 reply; 13+ messages in thread From: Mika Kahola @ 2020-10-23 13:05 UTC (permalink / raw) To: igt-dev The patch proposes a method to test CCS with clear color capability. The test paints a solid color on primary fb and a small sprite fb. These are cleared with fast clear feature. A crc is captured and compared against the reference. v2: Modify _gen9_render_copyfunc to support fast clear (Matt) Enable fast clear bit on 3D sequence (Matt) Add helper function to figure out clear color modifier (Matt) v3: Remove unrelated line additions/removes v4: Fast clear with color (Imre) v5: Write raw 32-bit color values to register (Imre) Require 32-bit color format v6: Rebase to use batchbuffer without libdrm dependency v7: Enable clear color (Nanley) Signed-off-by: Mika Kahola <mika.kahola@intel.com> --- lib/gen8_render.h | 1 + lib/gen9_render.h | 6 ++- lib/intel_batchbuffer.c | 10 +++++ lib/intel_batchbuffer.h | 6 +++ lib/rendercopy.h | 4 ++ lib/rendercopy_gen9.c | 79 ++++++++++++++++++++++++++++------ tests/kms_ccs.c | 94 ++++++++++++++++++++++++++++++++++++++--- 7 files changed, 181 insertions(+), 19 deletions(-) diff --git a/lib/gen8_render.h b/lib/gen8_render.h index 31dc01bc..1b0f527e 100644 --- a/lib/gen8_render.h +++ b/lib/gen8_render.h @@ -26,6 +26,7 @@ # define GEN8_VS_FLOATING_POINT_MODE_ALTERNATE (1 << 16) +#define GEN8_3DSTATE_FAST_CLEAR_ENABLE (1 << 8) #define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP \ GEN4_3D(3, 0, 0x21) #define GEN8_3DSTATE_PS_BLEND GEN4_3D(3, 0, 0x4d) diff --git a/lib/gen9_render.h b/lib/gen9_render.h index 6274e902..b4cdf18a 100644 --- a/lib/gen9_render.h +++ b/lib/gen9_render.h @@ -131,7 +131,11 @@ struct gen9_surface_state { } ss10; struct { - uint32_t aux_base_addr_hi; + uint32_t aux_base_addr_hi:20; + uint32_t procedual_texture:1; + uint32_t clearvalue_addr_enable:1; + uint32_t quilt_height:5; + uint32_t quilt_width:5; } ss11; /* register can be used for either diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c index fc73495c..905f69ff 100644 --- a/lib/intel_batchbuffer.c +++ b/lib/intel_batchbuffer.c @@ -1096,6 +1096,16 @@ igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid) return copy; } +igt_render_clearfunc_t igt_get_render_clearfunc(int devid) +{ + igt_render_clearfunc_t clear = NULL; + + if (IS_GEN12(devid)) + clear = gen12_render_clearfunc; + + return clear; +} + /** * igt_get_media_fillfunc: * @devid: pci device id diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h index ab1b0c28..4f0b33ee 100644 --- a/lib/intel_batchbuffer.h +++ b/lib/intel_batchbuffer.h @@ -374,6 +374,12 @@ typedef void (*igt_vebox_copyfunc_t)(struct intel_bb *ibb, igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid); +typedef void (*igt_render_clearfunc_t)(struct intel_bb *ibb, + struct intel_buf *dst, unsigned int dst_x, unsigned int dst_y, + unsigned int width, unsigned int height, + uint32_t r, uint32_t g, uint32_t b); +igt_render_clearfunc_t igt_get_render_clearfunc(int devid); + /** * igt_fillfunc_t: * @i915: drm fd diff --git a/lib/rendercopy.h b/lib/rendercopy.h index 7d5f0802..394fc94e 100644 --- a/lib/rendercopy.h +++ b/lib/rendercopy.h @@ -23,6 +23,10 @@ static inline void emit_vertex_normalized(struct intel_bb *ibb, intel_bb_out(ibb, u.ui); } +void gen12_render_clearfunc(struct intel_bb *ibb, + struct intel_buf *dst, unsigned int dst_x, unsigned int dst_y, + unsigned int width, unsigned int height, + uint32_t r, uint32_t g, uint32_t b); void gen12_render_copyfunc(struct intel_bb *ibb, struct intel_buf *src, uint32_t src_x, uint32_t src_y, uint32_t width, uint32_t height, diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index ef6855c9..fb6f6ba3 100644 --- a/lib/rendercopy_gen9.c +++ b/lib/rendercopy_gen9.c @@ -117,7 +117,7 @@ static const uint32_t gen12_render_copy[][4] = { /* Mostly copy+paste from gen6, except height, width, pitch moved */ static uint32_t -gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) { +gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst, bool fast_clear) { struct gen9_surface_state *ss; uint32_t write_domain, read_domain; uint64_t address; @@ -190,6 +190,9 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) { buf->addr.offset); ss->ss10.aux_base_addr = (address + buf->ccs[0].offset); ss->ss11.aux_base_addr_hi = (address + buf->ccs[0].offset) >> 32; + + if (fast_clear) + ss->ss11.clearvalue_addr_enable = 1; } if (buf->cc.offset) { @@ -217,8 +220,10 @@ gen8_bind_surfaces(struct intel_bb *ibb, binding_table = intel_bb_ptr_align(ibb, 32); binding_table_offset = intel_bb_ptr_add_return_prev_offset(ibb, 32); - binding_table[0] = gen8_bind_buf(ibb, dst, 1); - binding_table[1] = gen8_bind_buf(ibb, src, 0); + binding_table[0] = gen8_bind_buf(ibb, dst, 1, 1); + + if (src != NULL) + binding_table[1] = gen8_bind_buf(ibb, src, 1, 0); return binding_table_offset; } @@ -274,16 +279,25 @@ gen7_fill_vertex_buffer_data(struct intel_bb *ibb, offset = intel_bb_offset(ibb); emit_vertex_2s(ibb, dst_x + width, dst_y + height); - emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); + + if (src != NULL) { + emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); + emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); + } emit_vertex_2s(ibb, dst_x, dst_y + height); - emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); + + if (src != NULL) { + emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); + emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); + } emit_vertex_2s(ibb, dst_x, dst_y); - emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); - emit_vertex_normalized(ibb, src_y, intel_buf_height(src)); + + if (src != NULL) { + emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); + emit_vertex_normalized(ibb, src_y, intel_buf_height(src)); + } return offset; } @@ -729,7 +743,7 @@ gen8_emit_sf(struct intel_bb *ibb) } static void -gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel) { +gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel, bool fast_clear) { const int max_threads = 63; intel_bb_out(ibb, GEN6_3DSTATE_WM | (2 - 2)); @@ -757,6 +771,10 @@ gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel) { 2 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); intel_bb_out(ibb, 0); /* scratch space stuff */ intel_bb_out(ibb, 0); /* scratch hi */ + + if (fast_clear) + intel_bb_out(ibb, GEN8_3DSTATE_FAST_CLEAR_ENABLE); + intel_bb_out(ibb, (max_threads - 1) << GEN8_3DSTATE_PS_MAX_THREADS_SHIFT | GEN6_3DSTATE_WM_16_DISPATCH_ENABLE); intel_bb_out(ibb, 6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT); @@ -890,13 +908,20 @@ void _gen9_render_copyfunc(struct intel_bb *ibb, uint32_t scissor_state; uint32_t vertex_buffer; uint32_t aux_pgtable_state; + bool fast_clear = src != NULL ? false : true; - igt_assert(src->bpp == dst->bpp); + if (src != NULL) + igt_assert(src->bpp == dst->bpp); + + if (!fast_clear) + igt_assert(src->bpp == dst->bpp); intel_bb_flush_render(ibb); intel_bb_add_intel_buf(ibb, dst, true); - intel_bb_add_intel_buf(ibb, src, false); + + if (!fast_clear) + intel_bb_add_intel_buf(ibb, src, false); intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT); @@ -949,11 +974,13 @@ void _gen9_render_copyfunc(struct intel_bb *ibb, intel_bb_out(ibb, 0); intel_bb_out(ibb, 0); + gen8_emit_ps(ibb, ps_kernel_off, fast_clear); + gen7_emit_clip(ibb); gen8_emit_sf(ibb); - gen8_emit_ps(ibb, ps_kernel_off); + gen8_emit_ps(ibb, ps_kernel_off, fast_clear); intel_bb_out(ibb, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS); intel_bb_out(ibb, ps_binding_table); @@ -1027,3 +1054,29 @@ void gen12_render_copyfunc(struct intel_bb *ibb, gen12_aux_pgtable_cleanup(ibb, &pgtable_info); } + +void gen12_render_clearfunc(struct intel_bb *ibb, + struct intel_buf *dst, + unsigned int dst_x, unsigned int dst_y, + unsigned int width, unsigned int height, + uint32_t r, uint32_t g, uint32_t b) +{ + struct aux_pgtable_info pgtable_info = { }; + + gen12_aux_pgtable_init(&pgtable_info, ibb, NULL, dst); + + /* BSpec 21136 */ + intel_bb_ptr_set(ibb, dst->cc.offset); + intel_bb_out(ibb, r); + intel_bb_out(ibb, b); + intel_bb_out(ibb, g); + intel_bb_out(ibb, 0xffffffff); + + _gen9_render_copyfunc(ibb, NULL, 0, 0, + width, height, dst, dst_x, dst_y, + pgtable_info.pgtable_buf, + gen12_render_copy, + sizeof(gen12_render_copy)); + + gen12_aux_pgtable_cleanup(ibb, &pgtable_info); +} diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index 53abecce..fac1ed4e 100644 --- a/tests/kms_ccs.c +++ b/tests/kms_ccs.c @@ -50,10 +50,12 @@ enum test_fb_flags { FB_MISALIGN_AUX_STRIDE = 1 << 2, FB_SMALL_AUX_STRIDE = 1 << 3, FB_ZERO_AUX_STRIDE = 1 << 4, + FB_CLEAR_COLOR = 1 << 5, }; typedef struct { int drm_fd; + int devid; igt_display_t display; igt_output_t *output; enum pipe pipe; @@ -62,6 +64,11 @@ typedef struct { igt_pipe_crc_t *pipe_crc; uint32_t format; uint64_t ccs_modifier; + struct igt_fb primary_fb; + igt_plane_t *primary; + igt_render_clearfunc_t fast_clear; + struct buf_ops *bops; + struct intel_bb *ibb; } data_t; static const struct { @@ -120,6 +127,16 @@ static void addfb_init(struct igt_fb *fb, struct drm_mode_fb_cmd2 *f) } } +static bool is_ccs_cc_modifier(uint64_t modifier) +{ + switch (modifier) { + case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: + return true; + default: + return false; + } +} + /* * The CCS planes of compressed framebuffers contain non-zero bytes if the * engine compressed effectively the framebuffer. The actual encoding of these @@ -290,6 +307,32 @@ static igt_plane_t *compatible_main_plane(data_t *data) return igt_output_get_plane_type(data->output, DRM_PLANE_TYPE_PRIMARY); } +static struct intel_buf *init_buf(data_t *data, const struct igt_fb *fb, const char *buf_name) +{ + struct intel_buf *buf; + uint32_t name, handle, tiling, stride, width, height, bpp, size; + + igt_assert_eq(fb->offsets[0], 0); + tiling = igt_fb_mod_to_tiling(fb->modifier); + stride = fb->strides[0]; + bpp = fb->plane_bpp[0]; + size = fb->size; + width = stride / (bpp / 8); + height = size / stride; + name = gem_flink(data->drm_fd, fb->gem_handle); + handle = gem_open(data->drm_fd, name); + buf = intel_buf_create_using_handle(data->bops, handle, width, height, bpp, 0, tiling, 0); + intel_buf_set_name(buf, buf_name); + intel_buf_set_ownership(buf, true); + + return buf; +} + +static void fini_buf(struct intel_buf *buf) +{ + intel_buf_destroy(buf); +} + static bool try_config(data_t *data, enum test_fb_flags fb_flags, igt_crc_t *crc) { @@ -349,6 +392,37 @@ static bool try_config(data_t *data, enum test_fb_flags fb_flags, if (data->flags & TEST_BAD_ROTATION_90) igt_plane_set_rotation(primary, IGT_ROTATION_90); + if (fb_flags & FB_CLEAR_COLOR) { + struct intel_buf *dst; + + /* require 32-bit bpp for a fast clear test */ + igt_skip_on(data->primary_fb.plane_bpp[0] != 32); + + data->ibb = intel_bb_create(data->drm_fd, 4096); + data->bops = buf_ops_create(data->drm_fd); + + dst = init_buf(data, &data->primary_fb, "fast clear dst"); + gem_set_domain(data->drm_fd, data->primary_fb.gem_handle, + I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT); + + /* + * We expect the kernel to limit the max fb + * size/stride to something that can still + * rendered with the blitter/render engine. + */ + data->fast_clear(data->ibb, dst, 0, 0, + data->primary_fb.width, + data->primary_fb.height, + colors[0].r*UINT32_MAX, + colors[0].g*UINT32_MAX, + colors[0].b*UINT32_MAX); + + fini_buf(dst); + intel_bb_reset(data->ibb, true); + + return true; + } + ret = igt_display_try_commit2(display, commit); if (data->flags & TEST_BAD_ROTATION_90) { igt_assert_eq(ret, -EINVAL); @@ -386,10 +460,18 @@ static int test_ccs(data_t *data) if (data->flags & TEST_CRC) { data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe, INTEL_PIPE_CRC_SOURCE_AUTO); - if (try_config(data, fb_flags | FB_COMPRESSED, &ref_crc) && - try_config(data, fb_flags, &crc)) { - igt_assert_crc_equal(&crc, &ref_crc); - valid_tests++; + if (is_ccs_cc_modifier(data->ccs_modifier)) { + if (try_config(data, fb_flags | FB_COMPRESSED, &ref_crc) && + try_config(data, fb_flags | FB_COMPRESSED | FB_CLEAR_COLOR, &crc)) { + igt_assert_crc_equal(&crc, &ref_crc); + valid_tests++; + } + } else { + if (try_config(data, fb_flags | FB_COMPRESSED, &ref_crc) && + try_config(data, fb_flags, &crc)) { + igt_assert_crc_equal(&crc, &ref_crc); + valid_tests++; + } } igt_pipe_crc_free(data->pipe_crc); @@ -471,11 +553,13 @@ igt_main_args("c", NULL, help_str, opt_handler, NULL) igt_fixture { data.drm_fd = drm_open_driver_master(DRIVER_INTEL); - igt_require(intel_gen(intel_get_drm_devid(data.drm_fd)) >= 9); + data.devid = intel_gen(intel_get_drm_devid(data.drm_fd)); + igt_require(data.devid >= 9); kmstest_set_vt_graphics_mode(); igt_require_pipe_crc(data.drm_fd); igt_display_require(&data.display, data.drm_fd); + data.fast_clear = igt_get_render_clearfunc(data.devid); } for_each_pipe_static(pipe) { -- 2.25.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test 2020-10-23 13:05 ` [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test Mika Kahola @ 2020-11-02 17:27 ` Imre Deak 2020-11-02 18:12 ` Imre Deak 2020-11-05 13:33 ` Kahola, Mika 0 siblings, 2 replies; 13+ messages in thread From: Imre Deak @ 2020-11-02 17:27 UTC (permalink / raw) To: Mika Kahola; +Cc: igt-dev On Fri, Oct 23, 2020 at 04:05:26PM +0300, Mika Kahola wrote: > The patch proposes a method to test CCS with clear color > capability. > > The test paints a solid color on primary fb and a small sprite fb. > These are cleared with fast clear feature. A crc is captured and > compared against the reference. > > v2: Modify _gen9_render_copyfunc to support fast clear (Matt) > Enable fast clear bit on 3D sequence (Matt) > Add helper function to figure out clear color modifier (Matt) > v3: Remove unrelated line additions/removes > v4: Fast clear with color (Imre) > v5: Write raw 32-bit color values to register (Imre) > Require 32-bit color format > v6: Rebase to use batchbuffer without libdrm dependency > v7: Enable clear color (Nanley) > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > --- > lib/gen8_render.h | 1 + > lib/gen9_render.h | 6 ++- > lib/intel_batchbuffer.c | 10 +++++ > lib/intel_batchbuffer.h | 6 +++ > lib/rendercopy.h | 4 ++ > lib/rendercopy_gen9.c | 79 ++++++++++++++++++++++++++++------ > tests/kms_ccs.c | 94 ++++++++++++++++++++++++++++++++++++++--- > 7 files changed, 181 insertions(+), 19 deletions(-) > > diff --git a/lib/gen8_render.h b/lib/gen8_render.h > index 31dc01bc..1b0f527e 100644 > --- a/lib/gen8_render.h > +++ b/lib/gen8_render.h > @@ -26,6 +26,7 @@ > > # define GEN8_VS_FLOATING_POINT_MODE_ALTERNATE (1 << 16) > > +#define GEN8_3DSTATE_FAST_CLEAR_ENABLE (1 << 8) > #define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP \ > GEN4_3D(3, 0, 0x21) > #define GEN8_3DSTATE_PS_BLEND GEN4_3D(3, 0, 0x4d) > diff --git a/lib/gen9_render.h b/lib/gen9_render.h > index 6274e902..b4cdf18a 100644 > --- a/lib/gen9_render.h > +++ b/lib/gen9_render.h > @@ -131,7 +131,11 @@ struct gen9_surface_state { > } ss10; > > struct { > - uint32_t aux_base_addr_hi; > + uint32_t aux_base_addr_hi:20; > + uint32_t procedual_texture:1; > + uint32_t clearvalue_addr_enable:1; > + uint32_t quilt_height:5; > + uint32_t quilt_width:5; > } ss11; These are in ss10. > > /* register can be used for either > diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c > index fc73495c..905f69ff 100644 > --- a/lib/intel_batchbuffer.c > +++ b/lib/intel_batchbuffer.c > @@ -1096,6 +1096,16 @@ igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid) > return copy; > } > > +igt_render_clearfunc_t igt_get_render_clearfunc(int devid) > +{ > + igt_render_clearfunc_t clear = NULL; > + > + if (IS_GEN12(devid)) > + clear = gen12_render_clearfunc; > + > + return clear; > +} > + > /** > * igt_get_media_fillfunc: > * @devid: pci device id > diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h > index ab1b0c28..4f0b33ee 100644 > --- a/lib/intel_batchbuffer.h > +++ b/lib/intel_batchbuffer.h > @@ -374,6 +374,12 @@ typedef void (*igt_vebox_copyfunc_t)(struct intel_bb *ibb, > > igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid); > > +typedef void (*igt_render_clearfunc_t)(struct intel_bb *ibb, > + struct intel_buf *dst, unsigned int dst_x, unsigned int dst_y, > + unsigned int width, unsigned int height, > + uint32_t r, uint32_t g, uint32_t b); The clear value needs to be in float format, so let's pass that in a float[4] array. > +igt_render_clearfunc_t igt_get_render_clearfunc(int devid); > + > /** > * igt_fillfunc_t: > * @i915: drm fd > diff --git a/lib/rendercopy.h b/lib/rendercopy.h > index 7d5f0802..394fc94e 100644 > --- a/lib/rendercopy.h > +++ b/lib/rendercopy.h > @@ -23,6 +23,10 @@ static inline void emit_vertex_normalized(struct intel_bb *ibb, > intel_bb_out(ibb, u.ui); > } > > +void gen12_render_clearfunc(struct intel_bb *ibb, > + struct intel_buf *dst, unsigned int dst_x, unsigned int dst_y, > + unsigned int width, unsigned int height, > + uint32_t r, uint32_t g, uint32_t b); > void gen12_render_copyfunc(struct intel_bb *ibb, > struct intel_buf *src, uint32_t src_x, uint32_t src_y, > uint32_t width, uint32_t height, > diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c > index ef6855c9..fb6f6ba3 100644 > --- a/lib/rendercopy_gen9.c > +++ b/lib/rendercopy_gen9.c > @@ -117,7 +117,7 @@ static const uint32_t gen12_render_copy[][4] = { > > /* Mostly copy+paste from gen6, except height, width, pitch moved */ > static uint32_t > -gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) { > +gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst, bool fast_clear) { No need for fast_clear, we need to program the color params whenever buf->cc.offset is set (and that's not only for fast clear). > struct gen9_surface_state *ss; > uint32_t write_domain, read_domain; > uint64_t address; > @@ -190,6 +190,9 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) { > buf->addr.offset); > ss->ss10.aux_base_addr = (address + buf->ccs[0].offset); > ss->ss11.aux_base_addr_hi = (address + buf->ccs[0].offset) >> 32; > + > + if (fast_clear) > + ss->ss11.clearvalue_addr_enable = 1; > } > > if (buf->cc.offset) { Let's move this whole cc.offset address programming under the I915_COMPRESSION_RENDER branch, where this is actually relevant. > @@ -217,8 +220,10 @@ gen8_bind_surfaces(struct intel_bb *ibb, > binding_table = intel_bb_ptr_align(ibb, 32); > binding_table_offset = intel_bb_ptr_add_return_prev_offset(ibb, 32); > > - binding_table[0] = gen8_bind_buf(ibb, dst, 1); > - binding_table[1] = gen8_bind_buf(ibb, src, 0); > + binding_table[0] = gen8_bind_buf(ibb, dst, 1, 1); > + > + if (src != NULL) > + binding_table[1] = gen8_bind_buf(ibb, src, 1, 0); > > return binding_table_offset; > } > @@ -274,16 +279,25 @@ gen7_fill_vertex_buffer_data(struct intel_bb *ibb, > offset = intel_bb_offset(ibb); > > emit_vertex_2s(ibb, dst_x + width, dst_y + height); > - emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); > - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > + > + if (src != NULL) { > + emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); > + emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > + } For the !src case you also need to emit the two source vertex elements to keep the VUE format we defined in gen6_emit_vertex_elements(). > > emit_vertex_2s(ibb, dst_x, dst_y + height); > - emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); > - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > + > + if (src != NULL) { > + emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); > + emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > + } > > emit_vertex_2s(ibb, dst_x, dst_y); > - emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); > - emit_vertex_normalized(ibb, src_y, intel_buf_height(src)); > + > + if (src != NULL) { > + emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); > + emit_vertex_normalized(ibb, src_y, intel_buf_height(src)); > + } > > return offset; > } > @@ -729,7 +743,7 @@ gen8_emit_sf(struct intel_bb *ibb) > } > > static void > -gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel) { > +gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel, bool fast_clear) { > const int max_threads = 63; > > intel_bb_out(ibb, GEN6_3DSTATE_WM | (2 - 2)); > @@ -757,6 +771,10 @@ gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel) { > 2 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); There is only 1 table entry in case of a fast clear, and sampler count should be also set to 0. > intel_bb_out(ibb, 0); /* scratch space stuff */ > intel_bb_out(ibb, 0); /* scratch hi */ > + > + if (fast_clear) > + intel_bb_out(ibb, GEN8_3DSTATE_FAST_CLEAR_ENABLE); This flag is set in the next dword. > + > intel_bb_out(ibb, (max_threads - 1) << GEN8_3DSTATE_PS_MAX_THREADS_SHIFT | > GEN6_3DSTATE_WM_16_DISPATCH_ENABLE); > intel_bb_out(ibb, 6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT); > > @@ -890,13 +908,20 @@ void _gen9_render_copyfunc(struct intel_bb *ibb, Would make sense to rename this to stg like gen9_render_op() as it can be either a copy or a fast clear now. > uint32_t scissor_state; > uint32_t vertex_buffer; > uint32_t aux_pgtable_state; > + bool fast_clear = src != NULL ? false : true; It's just bool fast_clear = src != NULL; > > - igt_assert(src->bpp == dst->bpp); > + if (src != NULL) > + igt_assert(src->bpp == dst->bpp); > + > + if (!fast_clear) > + igt_assert(src->bpp == dst->bpp); Redundant check. > > intel_bb_flush_render(ibb); > > intel_bb_add_intel_buf(ibb, dst, true); > - intel_bb_add_intel_buf(ibb, src, false); > + > + if (!fast_clear) > + intel_bb_add_intel_buf(ibb, src, false); > > intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT); > > @@ -949,11 +974,13 @@ void _gen9_render_copyfunc(struct intel_bb *ibb, > intel_bb_out(ibb, 0); > intel_bb_out(ibb, 0); > > + gen8_emit_ps(ibb, ps_kernel_off, fast_clear); > + > gen7_emit_clip(ibb); > > gen8_emit_sf(ibb); > > - gen8_emit_ps(ibb, ps_kernel_off); > + gen8_emit_ps(ibb, ps_kernel_off, fast_clear); > > intel_bb_out(ibb, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS); > intel_bb_out(ibb, ps_binding_table); > @@ -1027,3 +1054,29 @@ void gen12_render_copyfunc(struct intel_bb *ibb, > > gen12_aux_pgtable_cleanup(ibb, &pgtable_info); > } Before returning we also need PIPE_CONTROL(render_target_cache_flush, l3_fabric_flush and depth_stall) see BSpec/47112. > + > +void gen12_render_clearfunc(struct intel_bb *ibb, > + struct intel_buf *dst, > + unsigned int dst_x, unsigned int dst_y, > + unsigned int width, unsigned int height, > + uint32_t r, uint32_t g, uint32_t b) > +{ > + struct aux_pgtable_info pgtable_info = { }; > + > + gen12_aux_pgtable_init(&pgtable_info, ibb, NULL, dst); The above expects both src and dst to be set, so you need to add support for the dst only case there. > + > + /* BSpec 21136 */ > + intel_bb_ptr_set(ibb, dst->cc.offset); The above sets a pointer inside the ibb, but cc.offset is an offset in dst. Also these emitted values would be overwritten by the following batchbuffer initing in _gen9_render_copyfunc() and it's missing the reloc info. Let's pass the float[4] clear value to _gen9_render_copyfunc() and do an MI_STORE_DWORD_IMM+reloc emit for each of the clear value members after gen12_emit_aux_pgtable_state() in _gen9_render_copyfunc(). > + intel_bb_out(ibb, r); > + intel_bb_out(ibb, b); > + intel_bb_out(ibb, g); > + intel_bb_out(ibb, 0xffffffff); > + > + _gen9_render_copyfunc(ibb, NULL, 0, 0, > + width, height, dst, dst_x, dst_y, > + pgtable_info.pgtable_buf, > + gen12_render_copy, > + sizeof(gen12_render_copy)); > + > + gen12_aux_pgtable_cleanup(ibb, &pgtable_info); > +} > diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c > index 53abecce..fac1ed4e 100644 > --- a/tests/kms_ccs.c > +++ b/tests/kms_ccs.c > @@ -50,10 +50,12 @@ enum test_fb_flags { > FB_MISALIGN_AUX_STRIDE = 1 << 2, > FB_SMALL_AUX_STRIDE = 1 << 3, > FB_ZERO_AUX_STRIDE = 1 << 4, > + FB_CLEAR_COLOR = 1 << 5, No need for a new flag, we can pick the fast clear path based on the RC-CC modifier. > }; > > typedef struct { > int drm_fd; > + int devid; > igt_display_t display; > igt_output_t *output; > enum pipe pipe; > @@ -62,6 +64,11 @@ typedef struct { > igt_pipe_crc_t *pipe_crc; > uint32_t format; > uint64_t ccs_modifier; > + struct igt_fb primary_fb; > + igt_plane_t *primary; > + igt_render_clearfunc_t fast_clear; > + struct buf_ops *bops; > + struct intel_bb *ibb; Th above don't need to be cached here, we'll do a fast clear at a single spot, so can get all these values there locally. > } data_t; > > static const struct { > @@ -120,6 +127,16 @@ static void addfb_init(struct igt_fb *fb, struct drm_mode_fb_cmd2 *f) > } > } > > +static bool is_ccs_cc_modifier(uint64_t modifier) > +{ > + switch (modifier) { > + case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > + return true; > + default: > + return false; > + } > +} > + > /* > * The CCS planes of compressed framebuffers contain non-zero bytes if the > * engine compressed effectively the framebuffer. The actual encoding of these > @@ -290,6 +307,32 @@ static igt_plane_t *compatible_main_plane(data_t *data) > return igt_output_get_plane_type(data->output, DRM_PLANE_TYPE_PRIMARY); > } > > +static struct intel_buf *init_buf(data_t *data, const struct igt_fb *fb, const char *buf_name) > +{ > + struct intel_buf *buf; > + uint32_t name, handle, tiling, stride, width, height, bpp, size; > + > + igt_assert_eq(fb->offsets[0], 0); > + tiling = igt_fb_mod_to_tiling(fb->modifier); > + stride = fb->strides[0]; > + bpp = fb->plane_bpp[0]; > + size = fb->size; > + width = stride / (bpp / 8); > + height = size / stride; > + name = gem_flink(data->drm_fd, fb->gem_handle); > + handle = gem_open(data->drm_fd, name); > + buf = intel_buf_create_using_handle(data->bops, handle, width, height, bpp, 0, tiling, 0); This won't setup any of the compression state, so instead of init_buf() let's instead add a fast_clear_fb() func here and call a new exported struct intel_buf * igt_fb_create_intel_buf(int drm_fd, struct buf_ops *, const struct igt_fb *, const char *name); function from lib/igt_fb.c, which calls lib/igt_fb.c/crate_buf() internally. > + intel_buf_set_name(buf, buf_name); > + intel_buf_set_ownership(buf, true); > + > + return buf; > +} > + > +static void fini_buf(struct intel_buf *buf) > +{ > + intel_buf_destroy(buf); > +} > + > static bool try_config(data_t *data, enum test_fb_flags fb_flags, > igt_crc_t *crc) > { > @@ -349,6 +392,37 @@ static bool try_config(data_t *data, enum test_fb_flags fb_flags, > if (data->flags & TEST_BAD_ROTATION_90) > igt_plane_set_rotation(primary, IGT_ROTATION_90); > > + if (fb_flags & FB_CLEAR_COLOR) { > + struct intel_buf *dst; > + > + /* require 32-bit bpp for a fast clear test */ > + igt_skip_on(data->primary_fb.plane_bpp[0] != 32); This should be just a if (!ccs_cc_modifier && format != XRGB8888) return false; early return to avoid the overhead up to this point in the func. > + > + data->ibb = intel_bb_create(data->drm_fd, 4096); > + data->bops = buf_ops_create(data->drm_fd); > + > + dst = init_buf(data, &data->primary_fb, "fast clear dst"); > + gem_set_domain(data->drm_fd, data->primary_fb.gem_handle, > + I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT); > + > + /* > + * We expect the kernel to limit the max fb > + * size/stride to something that can still > + * rendered with the blitter/render engine. > + */ > + data->fast_clear(data->ibb, dst, 0, 0, > + data->primary_fb.width, > + data->primary_fb.height, > + colors[0].r*UINT32_MAX, > + colors[0].g*UINT32_MAX, > + colors[0].b*UINT32_MAX); > + > + fini_buf(dst); > + intel_bb_reset(data->ibb, true); All the above belongs to generate_fb() as an alternative path for the cairo fill there (in the !TEST_BAD_PIXEL_FORMAT branch for the RC-CC modifier case). > + > + return true; Stray return. > + } > + > ret = igt_display_try_commit2(display, commit); > if (data->flags & TEST_BAD_ROTATION_90) { > igt_assert_eq(ret, -EINVAL); > @@ -386,10 +460,18 @@ static int test_ccs(data_t *data) > if (data->flags & TEST_CRC) { > data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe, INTEL_PIPE_CRC_SOURCE_AUTO); > > - if (try_config(data, fb_flags | FB_COMPRESSED, &ref_crc) && > - try_config(data, fb_flags, &crc)) { > - igt_assert_crc_equal(&crc, &ref_crc); > - valid_tests++; > + if (is_ccs_cc_modifier(data->ccs_modifier)) { > + if (try_config(data, fb_flags | FB_COMPRESSED, &ref_crc) && > + try_config(data, fb_flags | FB_COMPRESSED | FB_CLEAR_COLOR, &crc)) { > + igt_assert_crc_equal(&crc, &ref_crc); > + valid_tests++; > + } > + } else { > + if (try_config(data, fb_flags | FB_COMPRESSED, &ref_crc) && > + try_config(data, fb_flags, &crc)) { > + igt_assert_crc_equal(&crc, &ref_crc); > + valid_tests++; > + } We can keep this function as-is, and just depend on the RC-CC modifier the pick the fast clear path in try_config(). Please also add a check_ccs_cc_plane() which will check if the fast_clear func() programmed the clear values properly and that the render engine generated the native surface format value 16 bytes above the dst.cc_offset area. The check should be something like uint32_t *cc_val = cc_map; igt_assert(color->r == cc_map[0] && color->g == cc_map[1] && color->b == cc_map[2]); native_color = (uint8_t)(color->r * 0xff) << 16 | (uint8_t)(color->g * 0xff) << 8 | (uint8_t)(color->b * 0xff); igt_assert(native_color == cc_map[4]); > } > > igt_pipe_crc_free(data->pipe_crc); > @@ -471,11 +553,13 @@ igt_main_args("c", NULL, help_str, opt_handler, NULL) > igt_fixture { > data.drm_fd = drm_open_driver_master(DRIVER_INTEL); > > - igt_require(intel_gen(intel_get_drm_devid(data.drm_fd)) >= 9); > + data.devid = intel_gen(intel_get_drm_devid(data.drm_fd)); > + igt_require(data.devid >= 9); > kmstest_set_vt_graphics_mode(); > igt_require_pipe_crc(data.drm_fd); > > igt_display_require(&data.display, data.drm_fd); > + data.fast_clear = igt_get_render_clearfunc(data.devid); No need to cache this in data, we can use it locally at the single spot it's needed. > } > > for_each_pipe_static(pipe) { > -- > 2.25.1 > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test 2020-11-02 17:27 ` Imre Deak @ 2020-11-02 18:12 ` Imre Deak 2020-11-03 8:15 ` Kahola, Mika 2020-11-03 13:55 ` Kahola, Mika 2020-11-05 13:33 ` Kahola, Mika 1 sibling, 2 replies; 13+ messages in thread From: Imre Deak @ 2020-11-02 18:12 UTC (permalink / raw) To: Mika Kahola; +Cc: igt-dev On Mon, Nov 02, 2020 at 07:27:05PM +0200, Imre Deak wrote: > [...] > On Fri, Oct 23, 2020 at 04:05:26PM +0300, Mika Kahola wrote: > > @@ -274,16 +279,25 @@ gen7_fill_vertex_buffer_data(struct intel_bb *ibb, > > offset = intel_bb_offset(ibb); > > > > emit_vertex_2s(ibb, dst_x + width, dst_y + height); > > - emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); > > - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > > + > > + if (src != NULL) { > > + emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); > > + emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); The x coords need to be scaled down by 64 pixels, the y coords by 16 lines. --Imre > > + } > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test 2020-11-02 18:12 ` Imre Deak @ 2020-11-03 8:15 ` Kahola, Mika 2020-11-03 13:55 ` Kahola, Mika 1 sibling, 0 replies; 13+ messages in thread From: Kahola, Mika @ 2020-11-03 8:15 UTC (permalink / raw) To: Deak, Imre; +Cc: igt-dev@lists.freedesktop.org > -----Original Message----- > From: Imre Deak <imre.deak@intel.com> > Sent: Monday, November 2, 2020 8:13 PM > To: Kahola, Mika <mika.kahola@intel.com> > Cc: igt-dev@lists.freedesktop.org > Subject: Re: [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test > > On Mon, Nov 02, 2020 at 07:27:05PM +0200, Imre Deak wrote: > > [...] > > On Fri, Oct 23, 2020 at 04:05:26PM +0300, Mika Kahola wrote: > > > @@ -274,16 +279,25 @@ gen7_fill_vertex_buffer_data(struct intel_bb > *ibb, > > > offset = intel_bb_offset(ibb); > > > > > > emit_vertex_2s(ibb, dst_x + width, dst_y + height); > > > - emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); > > > - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > > > + > > > + if (src != NULL) { > > > + emit_vertex_normalized(ibb, src_x + width, > intel_buf_width(src)); > > > + emit_vertex_normalized(ibb, src_y + height, > intel_buf_height(src)); > > The x coords need to be scaled down by 64 pixels, the y coords by 16 lines. Thanks for the review. I will address these two points. Cheers, Mika > > --Imre > > > > + } > > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test 2020-11-02 18:12 ` Imre Deak 2020-11-03 8:15 ` Kahola, Mika @ 2020-11-03 13:55 ` Kahola, Mika 2020-11-03 14:00 ` Imre Deak 1 sibling, 1 reply; 13+ messages in thread From: Kahola, Mika @ 2020-11-03 13:55 UTC (permalink / raw) To: Deak, Imre; +Cc: igt-dev@lists.freedesktop.org > -----Original Message----- > From: Imre Deak <imre.deak@intel.com> > Sent: Monday, November 2, 2020 8:13 PM > To: Kahola, Mika <mika.kahola@intel.com> > Cc: igt-dev@lists.freedesktop.org > Subject: Re: [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test > > On Mon, Nov 02, 2020 at 07:27:05PM +0200, Imre Deak wrote: > > [...] > > On Fri, Oct 23, 2020 at 04:05:26PM +0300, Mika Kahola wrote: > > > @@ -274,16 +279,25 @@ gen7_fill_vertex_buffer_data(struct intel_bb > *ibb, > > > offset = intel_bb_offset(ibb); > > > > > > emit_vertex_2s(ibb, dst_x + width, dst_y + height); > > > - emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); > > > - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > > > + > > > + if (src != NULL) { > > > + emit_vertex_normalized(ibb, src_x + width, > intel_buf_width(src)); > > > + emit_vertex_normalized(ibb, src_y + height, > intel_buf_height(src)); > > The x coords need to be scaled down by 64 pixels, the y coords by 16 lines. So you mean that dst coordinates in case of Clear Color should be scaled down, x by 64 pixels and y by 16 lines? > > --Imre > > > > + } > > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test 2020-11-03 13:55 ` Kahola, Mika @ 2020-11-03 14:00 ` Imre Deak 0 siblings, 0 replies; 13+ messages in thread From: Imre Deak @ 2020-11-03 14:00 UTC (permalink / raw) To: Kahola, Mika; +Cc: igt-dev@lists.freedesktop.org On Tue, Nov 03, 2020 at 03:55:19PM +0200, Kahola, Mika wrote: > > -----Original Message----- > > From: Imre Deak <imre.deak@intel.com> > > Sent: Monday, November 2, 2020 8:13 PM > > To: Kahola, Mika <mika.kahola@intel.com> > > Cc: igt-dev@lists.freedesktop.org > > Subject: Re: [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test > > > > On Mon, Nov 02, 2020 at 07:27:05PM +0200, Imre Deak wrote: > > > [...] > > > On Fri, Oct 23, 2020 at 04:05:26PM +0300, Mika Kahola wrote: > > > > @@ -274,16 +279,25 @@ gen7_fill_vertex_buffer_data(struct intel_bb > > *ibb, > > > > offset = intel_bb_offset(ibb); > > > > > > > > emit_vertex_2s(ibb, dst_x + width, dst_y + height); > > > > - emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); > > > > - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > > > > + > > > > + if (src != NULL) { > > > > + emit_vertex_normalized(ibb, src_x + width, > > intel_buf_width(src)); > > > > + emit_vertex_normalized(ibb, src_y + height, > > intel_buf_height(src)); > > > > The x coords need to be scaled down by 64 pixels, the y coords by 16 lines. > > So you mean that dst coordinates in case of Clear Color should be scaled down, x by 64 pixels and y by 16 lines? Yes, both x and width by 64 pixels and both y and height by 16 lines. > > > > > --Imre > > > > > > + } > > > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test 2020-11-02 17:27 ` Imre Deak 2020-11-02 18:12 ` Imre Deak @ 2020-11-05 13:33 ` Kahola, Mika 2020-11-05 14:26 ` Imre Deak 1 sibling, 1 reply; 13+ messages in thread From: Kahola, Mika @ 2020-11-05 13:33 UTC (permalink / raw) To: Deak, Imre; +Cc: igt-dev@lists.freedesktop.org > -----Original Message----- > From: Imre Deak <imre.deak@intel.com> > Sent: Monday, November 2, 2020 7:27 PM > To: Kahola, Mika <mika.kahola@intel.com> > Cc: igt-dev@lists.freedesktop.org > Subject: Re: [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test > > On Fri, Oct 23, 2020 at 04:05:26PM +0300, Mika Kahola wrote: > > The patch proposes a method to test CCS with clear color capability. > > > > The test paints a solid color on primary fb and a small sprite fb. > > These are cleared with fast clear feature. A crc is captured and > > compared against the reference. > > > > v2: Modify _gen9_render_copyfunc to support fast clear (Matt) > > Enable fast clear bit on 3D sequence (Matt) > > Add helper function to figure out clear color modifier (Matt) > > v3: Remove unrelated line additions/removes > > v4: Fast clear with color (Imre) > > v5: Write raw 32-bit color values to register (Imre) > > Require 32-bit color format > > v6: Rebase to use batchbuffer without libdrm dependency > > v7: Enable clear color (Nanley) > > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > > --- > > lib/gen8_render.h | 1 + > > lib/gen9_render.h | 6 ++- > > lib/intel_batchbuffer.c | 10 +++++ > > lib/intel_batchbuffer.h | 6 +++ > > lib/rendercopy.h | 4 ++ > > lib/rendercopy_gen9.c | 79 ++++++++++++++++++++++++++++------ > > tests/kms_ccs.c | 94 ++++++++++++++++++++++++++++++++++++++--- > > 7 files changed, 181 insertions(+), 19 deletions(-) > > > > diff --git a/lib/gen8_render.h b/lib/gen8_render.h index > > 31dc01bc..1b0f527e 100644 > > --- a/lib/gen8_render.h > > +++ b/lib/gen8_render.h > > @@ -26,6 +26,7 @@ > > > > # define GEN8_VS_FLOATING_POINT_MODE_ALTERNATE (1 << 16) > > > > +#define GEN8_3DSTATE_FAST_CLEAR_ENABLE (1 << 8) > > #define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP \ > > GEN4_3D(3, 0, 0x21) > > #define GEN8_3DSTATE_PS_BLEND GEN4_3D(3, 0, 0x4d) > > diff --git a/lib/gen9_render.h b/lib/gen9_render.h index > > 6274e902..b4cdf18a 100644 > > --- a/lib/gen9_render.h > > +++ b/lib/gen9_render.h > > @@ -131,7 +131,11 @@ struct gen9_surface_state { > > } ss10; > > > > struct { > > - uint32_t aux_base_addr_hi; > > + uint32_t aux_base_addr_hi:20; > > + uint32_t procedual_texture:1; > > + uint32_t clearvalue_addr_enable:1; > > + uint32_t quilt_height:5; > > + uint32_t quilt_width:5; > > } ss11; > > These are in ss10. > > > > > /* register can be used for either > > diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c index > > fc73495c..905f69ff 100644 > > --- a/lib/intel_batchbuffer.c > > +++ b/lib/intel_batchbuffer.c > > @@ -1096,6 +1096,16 @@ igt_vebox_copyfunc_t > igt_get_vebox_copyfunc(int devid) > > return copy; > > } > > > > +igt_render_clearfunc_t igt_get_render_clearfunc(int devid) { > > + igt_render_clearfunc_t clear = NULL; > > + > > + if (IS_GEN12(devid)) > > + clear = gen12_render_clearfunc; > > + > > + return clear; > > +} > > + > > /** > > * igt_get_media_fillfunc: > > * @devid: pci device id > > diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h index > > ab1b0c28..4f0b33ee 100644 > > --- a/lib/intel_batchbuffer.h > > +++ b/lib/intel_batchbuffer.h > > @@ -374,6 +374,12 @@ typedef void (*igt_vebox_copyfunc_t)(struct > > intel_bb *ibb, > > > > igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid); > > > > +typedef void (*igt_render_clearfunc_t)(struct intel_bb *ibb, > > + struct intel_buf *dst, unsigned int dst_x, > unsigned int dst_y, > > + unsigned int width, unsigned int height, > > + uint32_t r, uint32_t g, uint32_t b); > > The clear value needs to be in float format, so let's pass that in a float[4] > array. > > > +igt_render_clearfunc_t igt_get_render_clearfunc(int devid); > > + > > /** > > * igt_fillfunc_t: > > * @i915: drm fd > > diff --git a/lib/rendercopy.h b/lib/rendercopy.h index > > 7d5f0802..394fc94e 100644 > > --- a/lib/rendercopy.h > > +++ b/lib/rendercopy.h > > @@ -23,6 +23,10 @@ static inline void emit_vertex_normalized(struct > intel_bb *ibb, > > intel_bb_out(ibb, u.ui); > > } > > > > +void gen12_render_clearfunc(struct intel_bb *ibb, > > + struct intel_buf *dst, unsigned int dst_x, unsigned int > dst_y, > > + unsigned int width, unsigned int height, > > + uint32_t r, uint32_t g, uint32_t b); > > void gen12_render_copyfunc(struct intel_bb *ibb, > > struct intel_buf *src, uint32_t src_x, uint32_t src_y, > > uint32_t width, uint32_t height, diff --git > > a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index > > ef6855c9..fb6f6ba3 100644 > > --- a/lib/rendercopy_gen9.c > > +++ b/lib/rendercopy_gen9.c > > @@ -117,7 +117,7 @@ static const uint32_t gen12_render_copy[][4] = { > > > > /* Mostly copy+paste from gen6, except height, width, pitch moved */ > > static uint32_t -gen8_bind_buf(struct intel_bb *ibb, const struct > > intel_buf *buf, int is_dst) { > > +gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int > > +is_dst, bool fast_clear) { > > No need for fast_clear, we need to program the color params whenever > buf->cc.offset is set (and that's not only for fast clear). > > > struct gen9_surface_state *ss; > > uint32_t write_domain, read_domain; > > uint64_t address; > > @@ -190,6 +190,9 @@ gen8_bind_buf(struct intel_bb *ibb, const struct > intel_buf *buf, int is_dst) { > > buf->addr.offset); > > ss->ss10.aux_base_addr = (address + buf->ccs[0].offset); > > ss->ss11.aux_base_addr_hi = (address + buf->ccs[0].offset) > >> 32; > > + > > + if (fast_clear) > > + ss->ss11.clearvalue_addr_enable = 1; > > } > > > > if (buf->cc.offset) { > > Let's move this whole cc.offset address programming under the > I915_COMPRESSION_RENDER branch, where this is actually relevant. > > > @@ -217,8 +220,10 @@ gen8_bind_surfaces(struct intel_bb *ibb, > > binding_table = intel_bb_ptr_align(ibb, 32); > > binding_table_offset = intel_bb_ptr_add_return_prev_offset(ibb, > 32); > > > > - binding_table[0] = gen8_bind_buf(ibb, dst, 1); > > - binding_table[1] = gen8_bind_buf(ibb, src, 0); > > + binding_table[0] = gen8_bind_buf(ibb, dst, 1, 1); > > + > > + if (src != NULL) > > + binding_table[1] = gen8_bind_buf(ibb, src, 1, 0); > > > > return binding_table_offset; > > } > > @@ -274,16 +279,25 @@ gen7_fill_vertex_buffer_data(struct intel_bb > *ibb, > > offset = intel_bb_offset(ibb); > > > > emit_vertex_2s(ibb, dst_x + width, dst_y + height); > > - emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); > > - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > > + > > + if (src != NULL) { > > + emit_vertex_normalized(ibb, src_x + width, > intel_buf_width(src)); > > + emit_vertex_normalized(ibb, src_y + height, > intel_buf_height(src)); > > + } > > For the !src case you also need to emit the two source vertex elements to > keep the VUE format we defined in gen6_emit_vertex_elements(). In this case we don't have src, what should we define as source vertex element? Are those src_*, width/height and intel_buf_width/height() just zeros? Cheers, Mika > > > > > emit_vertex_2s(ibb, dst_x, dst_y + height); > > - emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); > > - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > > + > > + if (src != NULL) { > > + emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); > > + emit_vertex_normalized(ibb, src_y + height, > intel_buf_height(src)); > > + } > > > > emit_vertex_2s(ibb, dst_x, dst_y); > > - emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); > > - emit_vertex_normalized(ibb, src_y, intel_buf_height(src)); > > + > > + if (src != NULL) { > > + emit_vertex_normalized(ibb, src_x, intel_buf_width(src)); > > + emit_vertex_normalized(ibb, src_y, intel_buf_height(src)); > > + } > > > > return offset; > > } > > @@ -729,7 +743,7 @@ gen8_emit_sf(struct intel_bb *ibb) } > > > > static void > > -gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel) { > > +gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel, bool fast_clear) > > +{ > > const int max_threads = 63; > > > > intel_bb_out(ibb, GEN6_3DSTATE_WM | (2 - 2)); @@ -757,6 +771,10 > @@ > > gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel) { > > 2 << > GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); > > There is only 1 table entry in case of a fast clear, and sampler count should > be also set to 0. > > > intel_bb_out(ibb, 0); /* scratch space stuff */ > > intel_bb_out(ibb, 0); /* scratch hi */ > > + > > + if (fast_clear) > > + intel_bb_out(ibb, GEN8_3DSTATE_FAST_CLEAR_ENABLE); > > This flag is set in the next dword. > > > + > > intel_bb_out(ibb, (max_threads - 1) << > GEN8_3DSTATE_PS_MAX_THREADS_SHIFT | > > GEN6_3DSTATE_WM_16_DISPATCH_ENABLE); > > intel_bb_out(ibb, 6 << > GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT); > > > > @@ -890,13 +908,20 @@ void _gen9_render_copyfunc(struct intel_bb > *ibb, > > Would make sense to rename this to stg like gen9_render_op() as it can be > either a copy or a fast clear now. > > > uint32_t scissor_state; > > uint32_t vertex_buffer; > > uint32_t aux_pgtable_state; > > + bool fast_clear = src != NULL ? false : true; > > It's just > bool fast_clear = src != NULL; > > > > > - igt_assert(src->bpp == dst->bpp); > > + if (src != NULL) > > + igt_assert(src->bpp == dst->bpp); > > + > > + if (!fast_clear) > > + igt_assert(src->bpp == dst->bpp); > > Redundant check. > > > > > intel_bb_flush_render(ibb); > > > > intel_bb_add_intel_buf(ibb, dst, true); > > - intel_bb_add_intel_buf(ibb, src, false); > > + > > + if (!fast_clear) > > + intel_bb_add_intel_buf(ibb, src, false); > > > > intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT); > > > > @@ -949,11 +974,13 @@ void _gen9_render_copyfunc(struct intel_bb > *ibb, > > intel_bb_out(ibb, 0); > > intel_bb_out(ibb, 0); > > > > + gen8_emit_ps(ibb, ps_kernel_off, fast_clear); > > + > > gen7_emit_clip(ibb); > > > > gen8_emit_sf(ibb); > > > > - gen8_emit_ps(ibb, ps_kernel_off); > > + gen8_emit_ps(ibb, ps_kernel_off, fast_clear); > > > > intel_bb_out(ibb, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS); > > intel_bb_out(ibb, ps_binding_table); @@ -1027,3 +1054,29 @@ void > > gen12_render_copyfunc(struct intel_bb *ibb, > > > > gen12_aux_pgtable_cleanup(ibb, &pgtable_info); } > > Before returning we also need PIPE_CONTROL(render_target_cache_flush, > l3_fabric_flush and depth_stall) see BSpec/47112. > > > + > > +void gen12_render_clearfunc(struct intel_bb *ibb, > > + struct intel_buf *dst, > > + unsigned int dst_x, unsigned int dst_y, > > + unsigned int width, unsigned int height, > > + uint32_t r, uint32_t g, uint32_t b) { > > + struct aux_pgtable_info pgtable_info = { }; > > + > > + gen12_aux_pgtable_init(&pgtable_info, ibb, NULL, dst); > > The above expects both src and dst to be set, so you need to add support for > the dst only case there. > > > + > > + /* BSpec 21136 */ > > + intel_bb_ptr_set(ibb, dst->cc.offset); > > The above sets a pointer inside the ibb, but cc.offset is an offset in dst. Also > these emitted values would be overwritten by the following batchbuffer > initing in _gen9_render_copyfunc() and it's missing the reloc info. > > Let's pass the float[4] clear value to _gen9_render_copyfunc() and do an > MI_STORE_DWORD_IMM+reloc emit for each of the clear value members > after gen12_emit_aux_pgtable_state() in _gen9_render_copyfunc(). > > > + intel_bb_out(ibb, r); > > + intel_bb_out(ibb, b); > > + intel_bb_out(ibb, g); > > + intel_bb_out(ibb, 0xffffffff); > > + > > + _gen9_render_copyfunc(ibb, NULL, 0, 0, > > + width, height, dst, dst_x, dst_y, > > + pgtable_info.pgtable_buf, > > + gen12_render_copy, > > + sizeof(gen12_render_copy)); > > + > > + gen12_aux_pgtable_cleanup(ibb, &pgtable_info); } > > diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index > > 53abecce..fac1ed4e 100644 > > --- a/tests/kms_ccs.c > > +++ b/tests/kms_ccs.c > > @@ -50,10 +50,12 @@ enum test_fb_flags { > > FB_MISALIGN_AUX_STRIDE = 1 << 2, > > FB_SMALL_AUX_STRIDE = 1 << 3, > > FB_ZERO_AUX_STRIDE = 1 << 4, > > + FB_CLEAR_COLOR = 1 << 5, > > No need for a new flag, we can pick the fast clear path based on the RC-CC > modifier. > > > }; > > > > typedef struct { > > int drm_fd; > > + int devid; > > igt_display_t display; > > igt_output_t *output; > > enum pipe pipe; > > @@ -62,6 +64,11 @@ typedef struct { > > igt_pipe_crc_t *pipe_crc; > > uint32_t format; > > uint64_t ccs_modifier; > > + struct igt_fb primary_fb; > > + igt_plane_t *primary; > > + igt_render_clearfunc_t fast_clear; > > + struct buf_ops *bops; > > + struct intel_bb *ibb; > > Th above don't need to be cached here, we'll do a fast clear at a single spot, > so can get all these values there locally. > > > } data_t; > > > > static const struct { > > @@ -120,6 +127,16 @@ static void addfb_init(struct igt_fb *fb, struct > drm_mode_fb_cmd2 *f) > > } > > } > > > > +static bool is_ccs_cc_modifier(uint64_t modifier) { > > + switch (modifier) { > > + case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > + return true; > > + default: > > + return false; > > + } > > +} > > + > > /* > > * The CCS planes of compressed framebuffers contain non-zero bytes if > the > > * engine compressed effectively the framebuffer. The actual encoding > > of these @@ -290,6 +307,32 @@ static igt_plane_t > *compatible_main_plane(data_t *data) > > return igt_output_get_plane_type(data->output, > > DRM_PLANE_TYPE_PRIMARY); } > > > > +static struct intel_buf *init_buf(data_t *data, const struct igt_fb > > +*fb, const char *buf_name) { > > + struct intel_buf *buf; > > + uint32_t name, handle, tiling, stride, width, height, bpp, size; > > + > > + igt_assert_eq(fb->offsets[0], 0); > > + tiling = igt_fb_mod_to_tiling(fb->modifier); > > + stride = fb->strides[0]; > > + bpp = fb->plane_bpp[0]; > > + size = fb->size; > > + width = stride / (bpp / 8); > > + height = size / stride; > > + name = gem_flink(data->drm_fd, fb->gem_handle); > > + handle = gem_open(data->drm_fd, name); > > + buf = intel_buf_create_using_handle(data->bops, handle, width, > > +height, bpp, 0, tiling, 0); > > This won't setup any of the compression state, so instead of init_buf() let's > instead add a fast_clear_fb() func here and call a new exported > > struct intel_buf * > igt_fb_create_intel_buf(int drm_fd, struct buf_ops *, > const struct igt_fb *, const char *name); > > function from lib/igt_fb.c, which calls lib/igt_fb.c/crate_buf() internally. > > > > + intel_buf_set_name(buf, buf_name); > > + intel_buf_set_ownership(buf, true); > > + > > + return buf; > > +} > > + > > +static void fini_buf(struct intel_buf *buf) { > > + intel_buf_destroy(buf); > > +} > > + > > static bool try_config(data_t *data, enum test_fb_flags fb_flags, > > igt_crc_t *crc) > > { > > @@ -349,6 +392,37 @@ static bool try_config(data_t *data, enum > test_fb_flags fb_flags, > > if (data->flags & TEST_BAD_ROTATION_90) > > igt_plane_set_rotation(primary, IGT_ROTATION_90); > > > > + if (fb_flags & FB_CLEAR_COLOR) { > > + struct intel_buf *dst; > > + > > + /* require 32-bit bpp for a fast clear test */ > > + igt_skip_on(data->primary_fb.plane_bpp[0] != 32); > > This should be just a > > if (!ccs_cc_modifier && format != XRGB8888) > return false; > > early return to avoid the overhead up to this point in the func. > > > + > > + data->ibb = intel_bb_create(data->drm_fd, 4096); > > + data->bops = buf_ops_create(data->drm_fd); > > + > > + dst = init_buf(data, &data->primary_fb, "fast clear dst"); > > + gem_set_domain(data->drm_fd, data- > >primary_fb.gem_handle, > > + I915_GEM_DOMAIN_GTT, > I915_GEM_DOMAIN_GTT); > > + > > + /* > > + * We expect the kernel to limit the max fb > > + * size/stride to something that can still > > + * rendered with the blitter/render engine. > > + */ > > + data->fast_clear(data->ibb, dst, 0, 0, > > + data->primary_fb.width, > > + data->primary_fb.height, > > + colors[0].r*UINT32_MAX, > > + colors[0].g*UINT32_MAX, > > + colors[0].b*UINT32_MAX); > > + > > + fini_buf(dst); > > + intel_bb_reset(data->ibb, true); > > All the above belongs to generate_fb() as an alternative path for the cairo fill > there (in the !TEST_BAD_PIXEL_FORMAT branch for the RC-CC modifier case). > > > + > > + return true; > > Stray return. > > > + } > > + > > ret = igt_display_try_commit2(display, commit); > > if (data->flags & TEST_BAD_ROTATION_90) { > > igt_assert_eq(ret, -EINVAL); > > @@ -386,10 +460,18 @@ static int test_ccs(data_t *data) > > if (data->flags & TEST_CRC) { > > data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data- > >pipe, > > INTEL_PIPE_CRC_SOURCE_AUTO); > > > > - if (try_config(data, fb_flags | FB_COMPRESSED, &ref_crc) && > > - try_config(data, fb_flags, &crc)) { > > - igt_assert_crc_equal(&crc, &ref_crc); > > - valid_tests++; > > + if (is_ccs_cc_modifier(data->ccs_modifier)) { > > + if (try_config(data, fb_flags | FB_COMPRESSED, > &ref_crc) && > > + try_config(data, fb_flags | FB_COMPRESSED | > FB_CLEAR_COLOR, &crc)) { > > + igt_assert_crc_equal(&crc, &ref_crc); > > + valid_tests++; > > + } > > + } else { > > + if (try_config(data, fb_flags | FB_COMPRESSED, > &ref_crc) && > > + try_config(data, fb_flags, &crc)) { > > + igt_assert_crc_equal(&crc, &ref_crc); > > + valid_tests++; > > + } > > We can keep this function as-is, and just depend on the RC-CC modifier the > pick the fast clear path in try_config(). > > > Please also add a check_ccs_cc_plane() which will check if the fast_clear > func() programmed the clear values properly and that the render engine > generated the native surface format value 16 bytes above the dst.cc_offset > area. The check should be something like > > uint32_t *cc_val = cc_map; > > igt_assert(color->r == cc_map[0] && > color->g == cc_map[1] && > color->b == cc_map[2]); > > native_color = (uint8_t)(color->r * 0xff) << 16 | > (uint8_t)(color->g * 0xff) << 8 | > (uint8_t)(color->b * 0xff); > > igt_assert(native_color == cc_map[4]); > > > } > > > > igt_pipe_crc_free(data->pipe_crc); > > @@ -471,11 +553,13 @@ igt_main_args("c", NULL, help_str, opt_handler, > NULL) > > igt_fixture { > > data.drm_fd = drm_open_driver_master(DRIVER_INTEL); > > > > - igt_require(intel_gen(intel_get_drm_devid(data.drm_fd)) >= > 9); > > + data.devid = intel_gen(intel_get_drm_devid(data.drm_fd)); > > + igt_require(data.devid >= 9); > > kmstest_set_vt_graphics_mode(); > > igt_require_pipe_crc(data.drm_fd); > > > > igt_display_require(&data.display, data.drm_fd); > > + data.fast_clear = igt_get_render_clearfunc(data.devid); > > No need to cache this in data, we can use it locally at the single spot it's > needed. > > > } > > > > for_each_pipe_static(pipe) { > > -- > > 2.25.1 > > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test 2020-11-05 13:33 ` Kahola, Mika @ 2020-11-05 14:26 ` Imre Deak 2020-11-05 14:33 ` Kahola, Mika 0 siblings, 1 reply; 13+ messages in thread From: Imre Deak @ 2020-11-05 14:26 UTC (permalink / raw) To: Kahola, Mika; +Cc: igt-dev@lists.freedesktop.org On Thu, Nov 05, 2020 at 03:33:57PM +0200, Kahola, Mika wrote: > [....] > > > @@ -274,16 +279,25 @@ gen7_fill_vertex_buffer_data(struct intel_bb > > *ibb, > > > offset = intel_bb_offset(ibb); > > > > > > emit_vertex_2s(ibb, dst_x + width, dst_y + height); > > > - emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); > > > - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > > > + > > > + if (src != NULL) { > > > + emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); > > > + emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > > > + } > > > > For the !src case you also need to emit the two source vertex elements to > > keep the VUE format we defined in gen6_emit_vertex_elements(). > > In this case we don't have src, what should we define as source vertex > element? Are those src_*, width/height and intel_buf_width/height() > just zeros? Yes, just two 0s in float format, so two emit_vertex(0). The alternative would be to change the vertex layout, but I think it's simpler this way. --Imre _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test 2020-11-05 14:26 ` Imre Deak @ 2020-11-05 14:33 ` Kahola, Mika 0 siblings, 0 replies; 13+ messages in thread From: Kahola, Mika @ 2020-11-05 14:33 UTC (permalink / raw) To: Deak, Imre; +Cc: igt-dev@lists.freedesktop.org > -----Original Message----- > From: Imre Deak <imre.deak@intel.com> > Sent: Thursday, November 5, 2020 4:26 PM > To: Kahola, Mika <mika.kahola@intel.com> > Cc: igt-dev@lists.freedesktop.org > Subject: Re: [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test > > On Thu, Nov 05, 2020 at 03:33:57PM +0200, Kahola, Mika wrote: > > [....] > > > > @@ -274,16 +279,25 @@ gen7_fill_vertex_buffer_data(struct intel_bb > > > *ibb, > > > > offset = intel_bb_offset(ibb); > > > > > > > > emit_vertex_2s(ibb, dst_x + width, dst_y + height); > > > > - emit_vertex_normalized(ibb, src_x + width, intel_buf_width(src)); > > > > - emit_vertex_normalized(ibb, src_y + height, intel_buf_height(src)); > > > > + > > > > + if (src != NULL) { > > > > + emit_vertex_normalized(ibb, src_x + width, > intel_buf_width(src)); > > > > + emit_vertex_normalized(ibb, src_y + height, > intel_buf_height(src)); > > > > + } > > > > > > For the !src case you also need to emit the two source vertex > > > elements to keep the VUE format we defined in > gen6_emit_vertex_elements(). > > > > In this case we don't have src, what should we define as source vertex > > element? Are those src_*, width/height and intel_buf_width/height() > > just zeros? > > Yes, just two 0s in float format, so two emit_vertex(0). The alternative would > be to change the vertex layout, but I think it's simpler this way. Ok, thanks! I will do the first alternative. Cheers, Mika > > --Imre _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 13+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for tests/kms_ccs: CCS Clear Color test (rev8) 2020-10-23 13:05 [igt-dev] [PATCH i-g-t v7 0/2] tests/kms_ccs: CCS Clear Color test Mika Kahola 2020-10-23 13:05 ` [igt-dev] [PATCH i-g-t v7 1/2] tests/kms_ccs: Add debug information on format modifier Mika Kahola 2020-10-23 13:05 ` [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test Mika Kahola @ 2020-10-23 13:36 ` Patchwork 2020-10-23 16:22 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 3 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2020-10-23 13:36 UTC (permalink / raw) To: Mika Kahola; +Cc: igt-dev [-- Attachment #1.1: Type: text/plain, Size: 2664 bytes --] == Series Details == Series: tests/kms_ccs: CCS Clear Color test (rev8) URL : https://patchwork.freedesktop.org/series/76536/ State : success == Summary == CI Bug Log - changes from IGT_5823 -> IGTPW_5093 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/index.html Known issues ------------ Here are the changes found in IGTPW_5093 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1: - fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html #### Possible fixes #### * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt@core_hotunplug@unbind-rebind: - fi-icl-u2: [DMESG-WARN][5] ([i915#289]) -> [DMESG-WARN][6] ([i915#1982] / [i915#289]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289 Participating hosts (45 -> 39) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5823 -> IGTPW_5093 CI-20190529: 20190529 CI_DRM_9190: a3d535579dd93942862b867b4452ba11e4f6bbb1 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_5093: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/index.html IGT_5823: 7dd2fe99bd9dde00456cc5abf7e5ef0c8d7d6118 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/index.html [-- Attachment #1.2: Type: text/html, Size: 3508 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 13+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for tests/kms_ccs: CCS Clear Color test (rev8) 2020-10-23 13:05 [igt-dev] [PATCH i-g-t v7 0/2] tests/kms_ccs: CCS Clear Color test Mika Kahola ` (2 preceding siblings ...) 2020-10-23 13:36 ` [igt-dev] ✓ Fi.CI.BAT: success for tests/kms_ccs: CCS Clear Color test (rev8) Patchwork @ 2020-10-23 16:22 ` Patchwork 3 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2020-10-23 16:22 UTC (permalink / raw) To: Mika Kahola; +Cc: igt-dev [-- Attachment #1.1: Type: text/plain, Size: 16459 bytes --] == Series Details == Series: tests/kms_ccs: CCS Clear Color test (rev8) URL : https://patchwork.freedesktop.org/series/76536/ State : failure == Summary == CI Bug Log - changes from IGT_5823_full -> IGTPW_5093_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_5093_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_5093_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_5093_full: ### IGT changes ### #### Possible regressions #### * igt@api_intel_bb@render-ccs: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-iclb3/igt@api_intel_bb@render-ccs.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-iclb6/igt@api_intel_bb@render-ccs.html * igt@kms_plane_lowres@pipe-c-tiling-none: - shard-hsw: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-hsw2/igt@kms_plane_lowres@pipe-c-tiling-none.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-hsw5/igt@kms_plane_lowres@pipe-c-tiling-none.html #### Warnings #### * igt@core_hotunplug@hotrebind-lateclose: - shard-hsw: [WARN][5] ([i915#2283]) -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-hsw4/igt@core_hotunplug@hotrebind-lateclose.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-hsw7/igt@core_hotunplug@hotrebind-lateclose.html * igt@kms_content_protection@uevent: - shard-kbl: [FAIL][7] ([i915#2105]) -> [FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-kbl6/igt@kms_content_protection@uevent.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-kbl7/igt@kms_content_protection@uevent.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt@core_hotunplug@hotrebind}: - shard-hsw: NOTRUN -> [WARN][9] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-hsw6/igt@core_hotunplug@hotrebind.html Known issues ------------ Here are the changes found in IGTPW_5093_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-hsw: [PASS][10] -> [FAIL][11] ([i915#2389]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-hsw8/igt@gem_exec_reloc@basic-many-active@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-hsw6/igt@gem_exec_reloc@basic-many-active@rcs0.html * igt@gem_exec_reloc@basic-many-active@vecs0: - shard-glk: [PASS][12] -> [FAIL][13] ([i915#2389]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-glk6/igt@gem_exec_reloc@basic-many-active@vecs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-glk1/igt@gem_exec_reloc@basic-many-active@vecs0.html * igt@gem_exec_whisper@basic-queues-forked: - shard-glk: [PASS][14] -> [DMESG-WARN][15] ([i915#118] / [i915#95]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-glk4/igt@gem_exec_whisper@basic-queues-forked.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-glk6/igt@gem_exec_whisper@basic-queues-forked.html * igt@i915_pm_rpm@system-suspend: - shard-kbl: [PASS][16] -> [INCOMPLETE][17] ([i915#151] / [i915#155]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-kbl1/igt@i915_pm_rpm@system-suspend.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-kbl1/igt@i915_pm_rpm@system-suspend.html * igt@kms_big_fb@y-tiled-64bpp-rotate-0: - shard-iclb: [PASS][18] -> [DMESG-WARN][19] ([i915#1982]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-iclb7/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-iclb3/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html * igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding: - shard-kbl: [PASS][20] -> [FAIL][21] ([i915#54]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-kbl7/igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding.html - shard-apl: [PASS][22] -> [FAIL][23] ([i915#1635] / [i915#54]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-apl8/igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][24] -> [FAIL][25] ([i915#96]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-hsw5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled: - shard-apl: [PASS][26] -> [DMESG-WARN][27] ([i915#1635] / [i915#1982]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-apl4/igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-apl8/igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html * igt@kms_flip@2x-dpms-vs-vblank-race@ab-vga1-hdmi-a1: - shard-hsw: [PASS][28] -> [DMESG-WARN][29] ([i915#1982]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-hsw4/igt@kms_flip@2x-dpms-vs-vblank-race@ab-vga1-hdmi-a1.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-hsw1/igt@kms_flip@2x-dpms-vs-vblank-race@ab-vga1-hdmi-a1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: - shard-snb: [PASS][30] -> [FAIL][31] ([i915#2546]) +1 similar issue [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-snb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-snb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt: - shard-tglb: [PASS][32] -> [DMESG-WARN][33] ([i915#1982]) +3 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-tglb7/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-tglb7/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt.html * igt@kms_plane_lowres@pipe-b-tiling-y: - shard-kbl: [PASS][34] -> [DMESG-WARN][35] ([i915#165] / [i915#78]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-kbl7/igt@kms_plane_lowres@pipe-b-tiling-y.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-kbl2/igt@kms_plane_lowres@pipe-b-tiling-y.html * igt@kms_psr@psr2_cursor_render: - shard-iclb: [PASS][36] -> [SKIP][37] ([fdo#109441]) +1 similar issue [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-iclb2/igt@kms_psr@psr2_cursor_render.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-iclb8/igt@kms_psr@psr2_cursor_render.html * igt@perf@buffer-fill: - shard-kbl: [PASS][38] -> [SKIP][39] ([fdo#109271] / [i915#1354]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-kbl4/igt@perf@buffer-fill.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-kbl1/igt@perf@buffer-fill.html - shard-tglb: [PASS][40] -> [SKIP][41] ([i915#1354]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-tglb1/igt@perf@buffer-fill.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-tglb7/igt@perf@buffer-fill.html - shard-apl: [PASS][42] -> [SKIP][43] ([fdo#109271] / [i915#1354] / [i915#1635]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-apl6/igt@perf@buffer-fill.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-apl4/igt@perf@buffer-fill.html - shard-glk: [PASS][44] -> [SKIP][45] ([fdo#109271] / [i915#1354]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-glk4/igt@perf@buffer-fill.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-glk5/igt@perf@buffer-fill.html - shard-iclb: [PASS][46] -> [SKIP][47] ([i915#1354]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-iclb4/igt@perf@buffer-fill.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-iclb7/igt@perf@buffer-fill.html #### Possible fixes #### * igt@gem_exec_fence@long-history: - shard-kbl: [INCOMPLETE][48] ([CI#80]) -> [PASS][49] [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-kbl7/igt@gem_exec_fence@long-history.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-kbl2/igt@gem_exec_fence@long-history.html * igt@gem_exec_whisper@basic-contexts-all: - shard-glk: [DMESG-WARN][50] ([i915#118] / [i915#95]) -> [PASS][51] [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-glk9/igt@gem_exec_whisper@basic-contexts-all.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-glk1/igt@gem_exec_whisper@basic-contexts-all.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [FAIL][52] ([i915#454]) -> [PASS][53] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-iclb8/igt@i915_pm_dc@dc6-psr.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-iclb5/igt@i915_pm_dc@dc6-psr.html * {igt@kms_async_flips@async-flip-with-page-flip-events}: - shard-kbl: [FAIL][54] ([i915#2521]) -> [PASS][55] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-kbl4/igt@kms_async_flips@async-flip-with-page-flip-events.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-kbl2/igt@kms_async_flips@async-flip-with-page-flip-events.html - shard-tglb: [FAIL][56] ([i915#2521]) -> [PASS][57] [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-tglb1/igt@kms_async_flips@async-flip-with-page-flip-events.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-tglb8/igt@kms_async_flips@async-flip-with-page-flip-events.html * igt@kms_cursor_edge_walk@pipe-c-64x64-right-edge: - shard-glk: [DMESG-WARN][58] ([i915#1982]) -> [PASS][59] +1 similar issue [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-glk6/igt@kms_cursor_edge_walk@pipe-c-64x64-right-edge.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-glk7/igt@kms_cursor_edge_walk@pipe-c-64x64-right-edge.html * igt@kms_draw_crc@draw-method-rgb565-render-xtiled: - shard-apl: [DMESG-WARN][60] ([i915#1635] / [i915#1982]) -> [PASS][61] [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-apl2/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-apl6/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu: - shard-glk: [FAIL][62] ([i915#49]) -> [PASS][63] [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-glk9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-glk3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy: - shard-tglb: [DMESG-WARN][64] ([i915#1982]) -> [PASS][65] +4 similar issues [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html * igt@kms_psr@psr2_cursor_blt: - shard-iclb: [SKIP][66] ([fdo#109441]) -> [PASS][67] +2 similar issues [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-iclb3/igt@kms_psr@psr2_cursor_blt.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html #### Warnings #### * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-snb: [SKIP][68] ([fdo#109271]) -> [INCOMPLETE][69] ([i915#82]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-snb4/igt@i915_pm_dc@dc3co-vpb-simulation.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-snb4/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@kms_content_protection@lic: - shard-apl: [FAIL][70] ([fdo#110321] / [i915#1635]) -> [TIMEOUT][71] ([i915#1319] / [i915#1635]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-apl1/igt@kms_content_protection@lic.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-apl7/igt@kms_content_protection@lic.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][72] ([fdo#109349]) -> [DMESG-WARN][73] ([i915#1226]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5823/shard-iclb4/igt@kms_dp_dsc@basic-dsc-enable-edp.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1354]: https://gitlab.freedesktop.org/drm/intel/issues/1354 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105 [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283 [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389 [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96 Participating hosts (8 -> 8) ------------------------------ No changes in participating hosts Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5823 -> IGTPW_5093 CI-20190529: 20190529 CI_DRM_9190: a3d535579dd93942862b867b4452ba11e4f6bbb1 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_5093: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/index.html IGT_5823: 7dd2fe99bd9dde00456cc5abf7e5ef0c8d7d6118 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5093/index.html [-- Attachment #1.2: Type: text/html, Size: 19558 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2020-11-05 14:33 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-10-23 13:05 [igt-dev] [PATCH i-g-t v7 0/2] tests/kms_ccs: CCS Clear Color test Mika Kahola 2020-10-23 13:05 ` [igt-dev] [PATCH i-g-t v7 1/2] tests/kms_ccs: Add debug information on format modifier Mika Kahola 2020-10-23 13:05 ` [igt-dev] [PATCH i-g-t v7 2/2] tests/kms_ccs: CCS Clear Color test Mika Kahola 2020-11-02 17:27 ` Imre Deak 2020-11-02 18:12 ` Imre Deak 2020-11-03 8:15 ` Kahola, Mika 2020-11-03 13:55 ` Kahola, Mika 2020-11-03 14:00 ` Imre Deak 2020-11-05 13:33 ` Kahola, Mika 2020-11-05 14:26 ` Imre Deak 2020-11-05 14:33 ` Kahola, Mika 2020-10-23 13:36 ` [igt-dev] ✓ Fi.CI.BAT: success for tests/kms_ccs: CCS Clear Color test (rev8) Patchwork 2020-10-23 16:22 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
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