[igt-dev] [PATCH i-g-t 0/4] GEN12 Color Clear

[igt-dev] [PATCH i-g-t 0/4] GEN12 Color Clear

[Mika Kahola]

The patch series extends the IGT testing for Color Clear, which
is part of E2E compression feature for GEN12 platforms.

Color Clear offers additional compression capability by encoding
a solid color option in the compression tags. 

Mika Kahola (4):
  drm-uapi/drm_fourcc: Format modifier for GEN12 render engine with
    Color Clear
  lib/rendercopy_gen9: Add GEN12 color clear
  lib/igt_fb.c: Update tile sizes for GEN12 Color Clear
  tests/kms_ccs: Add GEN12 CCS Color Clear format modifiers

 include/drm-uapi/drm_fourcc.h |  1 +
 lib/gen9_render.h             |  7 +++++--
 lib/igt_fb.c                  | 33 +++++++++++++++++++++++++--------
 lib/intel_batchbuffer.h       |  3 +++
 lib/ioctl_wrappers.h          |  4 ++--
 lib/rendercopy_gen9.c         | 11 +++++++++++
 tests/kms_ccs.c               |  1 +
 7 files changed, 48 insertions(+), 12 deletions(-)

-- 
2.17.1

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[igt-dev] [PATCH i-g-t 1/4] drm-uapi/drm_fourcc: Format modifier for GEN12 render engine with Color Clear

[Mika Kahola]

Gen12 display can decompress surfaces compressed by render engine with Clear Color, add
a new modifier as the driver needs to know the surface was compressed by render engine.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 include/drm-uapi/drm_fourcc.h | 1 +
 lib/ioctl_wrappers.h          | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
index b93eb2d4..30af8dcf 100644
--- a/include/drm-uapi/drm_fourcc.h
+++ b/include/drm-uapi/drm_fourcc.h
@@ -410,6 +410,7 @@ extern "C" {
 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
 
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index f2412d78..a7172f37 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -201,8 +201,8 @@ struct local_drm_mode_fb_cmd2 {
 #define LOCAL_I915_FORMAT_MOD_Y_TILED_CCS	local_fourcc_mod_code(INTEL, 4)
 #define LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS	local_fourcc_mod_code(INTEL, 5)
 #define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
-
-#define LOCAL_DRM_IOCTL_MODE_ADDFB2	DRM_IOWR(0xB8, \
+#define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+#define LOCAL_DRM_IOCTL_MODE_ADDFB2	DRM_IOWR(0xB8,			\
 						 struct local_drm_mode_fb_cmd2)
 
 #define LOCAL_DRM_CAP_ADDFB2_MODIFIERS	0x10
-- 
2.17.1

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Re: [igt-dev] [PATCH i-g-t 1/4] drm-uapi/drm_fourcc: Format modifier for GEN12 render engine with Color Clear

[Sripada, Radhakrishna]

On Fri, 2019-11-29 at 15:47 +0200, Mika Kahola wrote:
> Gen12 display can decompress surfaces compressed by render engine
> with Clear Color, add
> a new modifier as the driver needs to know the surface was compressed
> by render engine.
> 
Reviewed-by: Radhakrishna Sripada<radhakrishna.sripada@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  include/drm-uapi/drm_fourcc.h | 1 +
>  lib/ioctl_wrappers.h          | 4 ++--
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-
> uapi/drm_fourcc.h
> index b93eb2d4..30af8dcf 100644
> --- a/include/drm-uapi/drm_fourcc.h
> +++ b/include/drm-uapi/drm_fourcc.h
> @@ -410,6 +410,7 @@ extern "C" {
>  #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
>  #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
>  #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL,
> 6)
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> fourcc_mod_code(INTEL, 8)
>  
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized
> macroblocks
> diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
> index f2412d78..a7172f37 100644
> --- a/lib/ioctl_wrappers.h
> +++ b/lib/ioctl_wrappers.h
> @@ -201,8 +201,8 @@ struct local_drm_mode_fb_cmd2 {
>  #define LOCAL_I915_FORMAT_MOD_Y_TILED_CCS	local_fourcc_mod_code(I
> NTEL, 4)
>  #define LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS	local_fourcc_mod_code(I
> NTEL, 5)
>  #define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
> fourcc_mod_code(INTEL, 6)
> -
> -#define LOCAL_DRM_IOCTL_MODE_ADDFB2	DRM_IOWR(0xB8, \
> +#define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> fourcc_mod_code(INTEL, 8)
> +#define LOCAL_DRM_IOCTL_MODE_ADDFB2	DRM_IOWR(0xB8,			
> \
>  						 struct
> local_drm_mode_fb_cmd2)
>  
>  #define LOCAL_DRM_CAP_ADDFB2_MODIFIERS	0x10
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[igt-dev] [PATCH i-g-t 2/4] lib/rendercopy_gen9: Add GEN12 color clear

[Mika Kahola]

GEN12 supports color clear feature on the 3rd plane. The patch
updates rendercopy function to and buffers to support clear color.

Surface state bitgroups 12 and 13 are updated to support clear value
or depth clear value.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 lib/gen9_render.h       |  7 +++++--
 lib/igt_fb.c            |  3 +++
 lib/intel_batchbuffer.h |  3 +++
 lib/rendercopy_gen9.c   | 11 +++++++++++
 4 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/lib/gen9_render.h b/lib/gen9_render.h
index 9ee5782b..ab99563a 100644
--- a/lib/gen9_render.h
+++ b/lib/gen9_render.h
@@ -118,12 +118,15 @@ struct gen9_surface_state {
 		uint32_t aux_base_addr_hi;
 	} ss11;
 
+	/* register can be used for either
+	 * clear value or depth clear value
+	 */
 	struct {
-		uint32_t hiz_depth_clear_value;
+		uint32_t clear_address;
 	} ss12;
 
 	struct {
-		uint32_t reserved;
+		uint32_t clear_address_hi;
 	} ss13;
 
 	struct {
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 1d1e0d22..53aa344a 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -1936,6 +1936,9 @@ static void init_buf(struct fb_blit_upload *blit,
 		buf->aux.offset = fb->offsets[1];
 		buf->aux.stride = fb->strides[1];
 	}
+
+	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+		buf->cc.offset = fb->offsets[2];
 }
 
 static void fini_buf(struct igt_buf *buf)
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index e5f6e6d0..fc28dd55 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -234,6 +234,9 @@ struct igt_buf {
 		uint32_t offset;
 		uint32_t stride;
 	} aux;
+	struct {
+		uint32_t offset;
+	} cc;
 	/*< private >*/
 	unsigned num_tiles;
 };
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 3189594f..8f75c185 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -271,6 +271,17 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf,
 		assert(ret == 0);
 	}
 
+	if (buf->cc.offset) {
+		ss->ss12.clear_address = buf->bo->offset64 + buf->cc.offset;
+		ss->ss13.clear_address_hi = (buf->bo->offset64 + buf->cc.offset) >> 32;
+
+		ret = drm_intel_bo_emit_reloc(batch->bo,
+					      intel_batchbuffer_subdata_offset(batch, &ss->ss12),
+					      buf->bo, buf->cc.offset,
+					      read_domain, write_domain);
+		assert(ret == 0);
+	}
+
 	return offset;
 }
 
-- 
2.17.1

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Re: [igt-dev] [PATCH i-g-t 2/4] lib/rendercopy_gen9: Add GEN12 color clear

[Sripada, Radhakrishna]

On Fri, 2019-11-29 at 15:47 +0200, Mika Kahola wrote:
> GEN12 supports color clear feature on the 3rd plane. The patch
> updates rendercopy function to and buffers to support clear color.
> 
> Surface state bitgroups 12 and 13 are updated to support clear value
> or depth clear value.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Radhakrishna Sripada<radhakrishna.sripada@intel.com>
> ---
>  lib/gen9_render.h       |  7 +++++--
>  lib/igt_fb.c            |  3 +++
>  lib/intel_batchbuffer.h |  3 +++
>  lib/rendercopy_gen9.c   | 11 +++++++++++
>  4 files changed, 22 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/gen9_render.h b/lib/gen9_render.h
> index 9ee5782b..ab99563a 100644
> --- a/lib/gen9_render.h
> +++ b/lib/gen9_render.h
> @@ -118,12 +118,15 @@ struct gen9_surface_state {
>  		uint32_t aux_base_addr_hi;
>  	} ss11;
>  
> +	/* register can be used for either
> +	 * clear value or depth clear value
> +	 */
>  	struct {
> -		uint32_t hiz_depth_clear_value;
> +		uint32_t clear_address;
>  	} ss12;
>  
>  	struct {
> -		uint32_t reserved;
> +		uint32_t clear_address_hi;
>  	} ss13;
>  
>  	struct {
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> index 1d1e0d22..53aa344a 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -1936,6 +1936,9 @@ static void init_buf(struct fb_blit_upload
> *blit,
>  		buf->aux.offset = fb->offsets[1];
>  		buf->aux.stride = fb->strides[1];
>  	}
> +
> +	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> +		buf->cc.offset = fb->offsets[2];
>  }
>  
>  static void fini_buf(struct igt_buf *buf)
> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
> index e5f6e6d0..fc28dd55 100644
> --- a/lib/intel_batchbuffer.h
> +++ b/lib/intel_batchbuffer.h
> @@ -234,6 +234,9 @@ struct igt_buf {
>  		uint32_t offset;
>  		uint32_t stride;
>  	} aux;
> +	struct {
> +		uint32_t offset;
> +	} cc;
>  	/*< private >*/
>  	unsigned num_tiles;
>  };
> diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
> index 3189594f..8f75c185 100644
> --- a/lib/rendercopy_gen9.c
> +++ b/lib/rendercopy_gen9.c
> @@ -271,6 +271,17 @@ gen8_bind_buf(struct intel_batchbuffer *batch,
> const struct igt_buf *buf,
>  		assert(ret == 0);
>  	}
>  
> +	if (buf->cc.offset) {
> +		ss->ss12.clear_address = buf->bo->offset64 + buf-
> >cc.offset;
> +		ss->ss13.clear_address_hi = (buf->bo->offset64 + buf-
> >cc.offset) >> 32;
> +
> +		ret = drm_intel_bo_emit_reloc(batch->bo,
> +					      intel_batchbuffer_subdata
> _offset(batch, &ss->ss12),
> +					      buf->bo, buf->cc.offset,
> +					      read_domain,
> write_domain);
> +		assert(ret == 0);
> +	}
> +
>  	return offset;
>  }
>  
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[igt-dev] [PATCH i-g-t 3/4] lib/igt_fb.c: Update tile sizes for GEN12 Color Clear

[Mika Kahola]

Update tile sizes for GEN12 Color Clear.

v2: Update number of planes to 3 in case of CCS format
    modifier (RK)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 lib/igt_fb.c | 30 ++++++++++++++++++++++--------
 1 file changed, 22 insertions(+), 8 deletions(-)

diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 53aa344a..6ce7cfea 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -402,6 +402,7 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
 	case LOCAL_I915_FORMAT_MOD_Y_TILED:
 	case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
 	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		igt_require_intel(fd);
 		if (intel_gen(intel_get_drm_devid(fd)) == 2) {
 			*width_ret = 128;
@@ -468,13 +469,15 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
 
 static bool is_gen12_ccs_modifier(uint64_t modifier)
 {
-	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
 }
 
 static bool is_ccs_modifier(uint64_t modifier)
 {
 
-	return is_gen12_ccs_modifier(modifier) ||
+	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
 		modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 		modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
@@ -489,6 +492,8 @@ static unsigned fb_plane_width(const struct igt_fb *fb, int plane)
 					    512 / (fb->plane_bpp[0] / 8)) * 64;
 		else
 			return DIV_ROUND_UP(fb->width, 1024) * 128;
+	} else if (is_gen12_ccs_modifier(fb->modifier) && plane == 2) {
+		return 64;
 	}
 
 	if (plane == 0)
@@ -501,7 +506,7 @@ static unsigned fb_plane_bpp(const struct igt_fb *fb, int plane)
 {
 	const struct format_desc_struct *format = lookup_drm_format(fb->drm_format);
 
-	if (is_ccs_modifier(fb->modifier) && plane == 1)
+	if (is_ccs_modifier(fb->modifier) && (plane == 1 || plane == 2))
 		return 8;
 	else
 		return format->plane_bpp[plane];
@@ -516,7 +521,8 @@ static unsigned fb_plane_height(const struct igt_fb *fb, int plane)
 			return DIV_ROUND_UP(fb->height, 128) * 4;
 		else
 			return DIV_ROUND_UP(fb->height, 512) * 32;
-	}
+	} else if (is_gen12_ccs_modifier(fb->modifier) && plane == 2)
+		return 1;
 
 	if (plane == 0)
 		return fb->height;
@@ -528,10 +534,14 @@ static int fb_num_planes(const struct igt_fb *fb)
 {
 	const struct format_desc_struct *format = lookup_drm_format(fb->drm_format);
 
-	if (is_ccs_modifier(fb->modifier))
-		return 2;
-	else
+	if (is_ccs_modifier(fb->modifier)) {
+		if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+			return 3;
+		else
+			return 2;
+	} else {
 		return format->num_planes;
+	}
 }
 
 void igt_init_fb(struct igt_fb *fb, int fd, int width, int height,
@@ -592,6 +602,9 @@ static uint32_t calc_plane_stride(struct igt_fb *fb, int plane)
 	} else if (is_gen12_ccs_modifier(fb->modifier) && plane == 1) {
 		/* A main surface using a CCS AUX surface must be 4x4 tiles aligned. */
 		return ALIGN(min_stride, 64);
+	} else if (is_gen12_ccs_modifier(fb->modifier) && plane == 2) {
+		/* clear color always fixed to 64 bytes */
+		return 64;
 	} else {
 		unsigned int tile_width, tile_height;
 
@@ -626,7 +639,7 @@ static uint64_t calc_plane_size(struct igt_fb *fb, int plane)
 		size = roundup_power_of_two(size);
 
 		return size;
-	} else if (is_gen12_ccs_modifier(fb->modifier) && plane == 1) {
+	} else if (is_gen12_ccs_modifier(fb->modifier) && (plane == 1 || plane == 2)) {
 		/* The AUX CCS surface must be page aligned */
 		return (uint64_t)fb->strides[plane] *
 			ALIGN(fb->plane_height[plane], 64);
@@ -719,6 +732,7 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
 	case LOCAL_I915_FORMAT_MOD_Y_TILED:
 	case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
 	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		return I915_TILING_Y;
 	case LOCAL_I915_FORMAT_MOD_Yf_TILED:
 	case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
-- 
2.17.1

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Re: [igt-dev] [PATCH i-g-t 3/4] lib/igt_fb.c: Update tile sizes for GEN12 Color Clear

[Sripada, Radhakrishna]

On Fri, 2019-11-29 at 15:47 +0200, Mika Kahola wrote:
> Update tile sizes for GEN12 Color Clear.
> 
> v2: Update number of planes to 3 in case of CCS format
>     modifier (RK)
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Radhakrishna Sripada<radhakrishna.sripada@intel.com>
> ---
>  lib/igt_fb.c | 30 ++++++++++++++++++++++--------
>  1 file changed, 22 insertions(+), 8 deletions(-)
> 
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> index 53aa344a..6ce7cfea 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -402,6 +402,7 @@ void igt_get_fb_tile_size(int fd, uint64_t
> modifier, int fb_bpp,
>  	case LOCAL_I915_FORMAT_MOD_Y_TILED:
>  	case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
>  	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  		igt_require_intel(fd);
>  		if (intel_gen(intel_get_drm_devid(fd)) == 2) {
>  			*width_ret = 128;
> @@ -468,13 +469,15 @@ void igt_get_fb_tile_size(int fd, uint64_t
> modifier, int fb_bpp,
>  
>  static bool is_gen12_ccs_modifier(uint64_t modifier)
>  {
> -	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
>  }
>  
>  static bool is_ccs_modifier(uint64_t modifier)
>  {
>  
> -	return is_gen12_ccs_modifier(modifier) ||
> +	return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> +		modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
>  		modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  		modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
>  }
> @@ -489,6 +492,8 @@ static unsigned fb_plane_width(const struct
> igt_fb *fb, int plane)
>  					    512 / (fb->plane_bpp[0] /
> 8)) * 64;
>  		else
>  			return DIV_ROUND_UP(fb->width, 1024) * 128;
> +	} else if (is_gen12_ccs_modifier(fb->modifier) && plane == 2) {
> +		return 64;
>  	}
>  
>  	if (plane == 0)
> @@ -501,7 +506,7 @@ static unsigned fb_plane_bpp(const struct igt_fb
> *fb, int plane)
>  {
>  	const struct format_desc_struct *format = lookup_drm_format(fb-
> >drm_format);
>  
> -	if (is_ccs_modifier(fb->modifier) && plane == 1)
> +	if (is_ccs_modifier(fb->modifier) && (plane == 1 || plane ==
> 2))
>  		return 8;
>  	else
>  		return format->plane_bpp[plane];
> @@ -516,7 +521,8 @@ static unsigned fb_plane_height(const struct
> igt_fb *fb, int plane)
>  			return DIV_ROUND_UP(fb->height, 128) * 4;
>  		else
>  			return DIV_ROUND_UP(fb->height, 512) * 32;
> -	}
> +	} else if (is_gen12_ccs_modifier(fb->modifier) && plane == 2)
> +		return 1;
>  
>  	if (plane == 0)
>  		return fb->height;
> @@ -528,10 +534,14 @@ static int fb_num_planes(const struct igt_fb
> *fb)
>  {
>  	const struct format_desc_struct *format = lookup_drm_format(fb-
> >drm_format);
>  
> -	if (is_ccs_modifier(fb->modifier))
> -		return 2;
> -	else
> +	if (is_ccs_modifier(fb->modifier)) {
> +		if (fb->modifier ==
> I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
> +			return 3;
> +		else
> +			return 2;
> +	} else {
>  		return format->num_planes;
> +	}
>  }
>  
>  void igt_init_fb(struct igt_fb *fb, int fd, int width, int height,
> @@ -592,6 +602,9 @@ static uint32_t calc_plane_stride(struct igt_fb
> *fb, int plane)
>  	} else if (is_gen12_ccs_modifier(fb->modifier) && plane == 1) {
>  		/* A main surface using a CCS AUX surface must be 4x4
> tiles aligned. */
>  		return ALIGN(min_stride, 64);
> +	} else if (is_gen12_ccs_modifier(fb->modifier) && plane == 2) {
> +		/* clear color always fixed to 64 bytes */
> +		return 64;
>  	} else {
>  		unsigned int tile_width, tile_height;
>  
> @@ -626,7 +639,7 @@ static uint64_t calc_plane_size(struct igt_fb
> *fb, int plane)
>  		size = roundup_power_of_two(size);
>  
>  		return size;
> -	} else if (is_gen12_ccs_modifier(fb->modifier) && plane == 1) {
> +	} else if (is_gen12_ccs_modifier(fb->modifier) && (plane == 1
> || plane == 2)) {
>  		/* The AUX CCS surface must be page aligned */
>  		return (uint64_t)fb->strides[plane] *
>  			ALIGN(fb->plane_height[plane], 64);
> @@ -719,6 +732,7 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
>  	case LOCAL_I915_FORMAT_MOD_Y_TILED:
>  	case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
>  	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> +	case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  		return I915_TILING_Y;
>  	case LOCAL_I915_FORMAT_MOD_Yf_TILED:
>  	case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
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[igt-dev] [PATCH i-g-t 4/4] tests/kms_ccs: Add GEN12 CCS Color Clear format modifiers

[Mika Kahola]

Add GEN12 CCS format modifiers for Color Clear feature.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 tests/kms_ccs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index 9788e602..d5178824 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -74,6 +74,7 @@ static const uint64_t ccs_modifiers[] = {
 	LOCAL_I915_FORMAT_MOD_Y_TILED_CCS,
 	LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS,
 	LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+	LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
 };
 
 /*
-- 
2.17.1

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Re: [igt-dev] [PATCH i-g-t 4/4] tests/kms_ccs: Add GEN12 CCS Color Clear format modifiers

[Sripada, Radhakrishna]

On Fri, 2019-11-29 at 15:47 +0200, Mika Kahola wrote:
> Add GEN12 CCS format modifiers for Color Clear feature.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Radhakrishna Sripada<radhakrishna.sripada@intel.com>
> ---
>  tests/kms_ccs.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
> index 9788e602..d5178824 100644
> --- a/tests/kms_ccs.c
> +++ b/tests/kms_ccs.c
> @@ -74,6 +74,7 @@ static const uint64_t ccs_modifiers[] = {
>  	LOCAL_I915_FORMAT_MOD_Y_TILED_CCS,
>  	LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS,
>  	LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> +	LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
>  };
>  
>  /*
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[igt-dev] ✗ GitLab.Pipeline: warning for GEN12 Color Clear

[Patchwork]

== Series Details ==

Series: GEN12 Color Clear
URL   : https://patchwork.freedesktop.org/series/70212/
State : warning

== Summary ==

Did not get list of undocumented tests for this run, something is wrong!

Other than that, pipeline status: FAILED.

see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/84049 for the overview.

build-containers:build-debian-armhf has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/1039580):
  ^[[0KRunning with gitlab-runner 12.4.0 (1564076b)
  ^[[0;m^[[0K  on fdo-gitlab-gce-runner3 81280d8f
  ^[[0;msection_start:1575036093:prepare_executor
  ^[[0K^[[0KUsing Docker executor with image registry.freedesktop.org/wayland/ci-templates/buildah ...
  ^[[0;m^[[0KAuthenticating with credentials from job payload (GitLab Registry)
  ^[[0;m^[[0KPulling docker image registry.freedesktop.org/wayland/ci-templates/buildah ...
  ^[[0;m^[[0KUsing docker image sha256:594aa868d31ee3304dee8cae8a3433c89a6fcfcf6c7d420c04cce22f60147176 for registry.freedesktop.org/wayland/ci-templates/buildah ...
  ^[[0;msection_end:1575036130:prepare_executor
  ^[[0Ksection_start:1575036130:prepare_script
  ^[[0Ksection_end:1575036139:prepare_script
  ^[[0Ksection_start:1575036139:upload_artifacts_on_failure
  ^[[0Ksection_end:1575036140:upload_artifacts_on_failure
  ^[[0K^[[31;1mERROR: Job failed (system failure): Error response from daemon: No such container: 219745d161adadd8a1f55828a2506f17013a45d571339e83c6583e988b529e54 (executor_docker.go:740:8s)
  ^[[0;m

== Logs ==

For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/84049
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[igt-dev] ✗ Fi.CI.BAT: failure for GEN12 Color Clear

[Patchwork]

== Series Details ==

Series: GEN12 Color Clear
URL   : https://patchwork.freedesktop.org/series/70212/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7442 -> IGTPW_3786
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_3786 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_3786, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3786/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3786:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-kbl-r:           [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7442/fi-kbl-r/igt@gem_exec_suspend@basic-s0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3786/fi-kbl-r/igt@gem_exec_suspend@basic-s0.html

  
Known issues
------------

  Here are the changes found in IGTPW_3786 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-kbl-7500u:       [PASS][3] -> [DMESG-WARN][4] ([fdo#107139])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7442/fi-kbl-7500u/igt@gem_exec_suspend@basic-s4-devices.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3786/fi-kbl-7500u/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@i915_module_load@reload-no-display:
    - fi-skl-lmem:        [PASS][5] -> [DMESG-WARN][6] ([fdo#112261])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7442/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3786/fi-skl-lmem/igt@i915_module_load@reload-no-display.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          [PASS][7] -> [FAIL][8] ([fdo#103167])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7442/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3786/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@gem_ctx_create@basic-files:
    - {fi-tgl-u}:         [INCOMPLETE][9] ([fdo#111735]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7442/fi-tgl-u/igt@gem_ctx_create@basic-files.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3786/fi-tgl-u/igt@gem_ctx_create@basic-files.html

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-skl-6770hq:      [DMESG-WARN][11] ([fdo#105541]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7442/fi-skl-6770hq/igt@i915_module_load@reload-with-fault-injection.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3786/fi-skl-6770hq/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-peppy:       [DMESG-FAIL][13] ([fdo#112147]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7442/fi-hsw-peppy/igt@i915_selftest@live_blt.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3786/fi-hsw-peppy/igt@i915_selftest@live_blt.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-cfl-8700k:       [INCOMPLETE][15] ([fdo#111700]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7442/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3786/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html

  * igt@i915_selftest@live_sanitycheck:
    - {fi-kbl-7560u}:     [DMESG-WARN][17] ([fdo#112260]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7442/fi-kbl-7560u/igt@i915_selftest@live_sanitycheck.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3786/fi-kbl-7560u/igt@i915_selftest@live_sanitycheck.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][19] ([fdo#111045] / [fdo#111096]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7442/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3786/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Warnings ####

  * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
    - fi-kbl-x1275:       [DMESG-WARN][21] ([fdo#103558] / [fdo#105602]) -> [DMESG-WARN][22] ([fdo#103558] / [fdo#105602] / [fdo#105763]) +3 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7442/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3786/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-modeset:
    - fi-kbl-x1275:       [DMESG-WARN][23] ([fdo#103558] / [fdo#105602] / [fdo#105763]) -> [DMESG-WARN][24] ([fdo#103558] / [fdo#105602]) +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7442/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3786/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111700]: https://bugs.freedesktop.org/show_bug.cgi?id=111700
  [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
  [fdo#112147]: https://bugs.freedesktop.org/show_bug.cgi?id=112147
  [fdo#112260]: https://bugs.freedesktop.org/show_bug.cgi?id=112260
  [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261


Participating hosts (52 -> 45)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-ivb-3770 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5316 -> IGTPW_3786

  CI-20190529: 20190529
  CI_DRM_7442: 00ea566be6d64f834a83233cca6491fafc0f6075 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3786: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3786/index.html
  IGT_5316: f38b398103fea0423b7bf133bbe5868fde99623c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3786/index.html
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[igt-dev] ✗ Fi.CI.BAT: failure for GEN12 Color Clear (rev2)

[Patchwork]

== Series Details ==

Series: GEN12 Color Clear (rev2)
URL   : https://patchwork.freedesktop.org/series/70212/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7459 -> IGTPW_3792
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_3792 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_3792, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3792/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3792:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live_evict:
    - fi-bwr-2160:        [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7459/fi-bwr-2160/igt@i915_selftest@live_evict.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3792/fi-bwr-2160/igt@i915_selftest@live_evict.html

  
Known issues
------------

  Here are the changes found in IGTPW_3792 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [PASS][3] -> [FAIL][4] ([i915#178])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7459/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3792/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
    - fi-skl-lmem:        [PASS][5] -> [DMESG-WARN][6] ([i915#592])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7459/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3792/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html

  
#### Warnings ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-kbl-x1275:       [DMESG-WARN][7] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][8] ([i915#62] / [i915#92]) +4 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7459/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3792/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-kbl-x1275:       [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7459/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3792/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  
  [i915#178]: https://gitlab.freedesktop.org/drm/intel/issues/178
  [i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (52 -> 46)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5320 -> IGTPW_3792

  CI-20190529: 20190529
  CI_DRM_7459: 8c8fc21a7dbe3dd0cfbd6f255b436074b930ddee @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3792: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3792/index.html
  IGT_5320: 06833ffeaf7621c3fef097166539bbe999a33e9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3792/index.html
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Re: [igt-dev] [PATCH i-g-t 0/4] GEN12 Color Clear

[Kahola, Mika]

The series has been pushed upstream.

Thanks for the review!

On Fri, 2019-11-29 at 15:47 +0200, Mika Kahola wrote:
> The patch series extends the IGT testing for Color Clear, which
> is part of E2E compression feature for GEN12 platforms.
> 
> Color Clear offers additional compression capability by encoding
> a solid color option in the compression tags. 
> 
> Mika Kahola (4):
>   drm-uapi/drm_fourcc: Format modifier for GEN12 render engine with
>     Color Clear
>   lib/rendercopy_gen9: Add GEN12 color clear
>   lib/igt_fb.c: Update tile sizes for GEN12 Color Clear
>   tests/kms_ccs: Add GEN12 CCS Color Clear format modifiers
> 
>  include/drm-uapi/drm_fourcc.h |  1 +
>  lib/gen9_render.h             |  7 +++++--
>  lib/igt_fb.c                  | 33 +++++++++++++++++++++++++--------
>  lib/intel_batchbuffer.h       |  3 +++
>  lib/ioctl_wrappers.h          |  4 ++--
>  lib/rendercopy_gen9.c         | 11 +++++++++++
>  tests/kms_ccs.c               |  1 +
>  7 files changed, 48 insertions(+), 12 deletions(-)
> 
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