From: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: igt-dev@lists.freedesktop.org
Subject: Re: [igt-dev] [PATCH i-g-t 3/8] tools/intel_watermark: Deal with TGL planes
Date: Fri, 14 May 2021 12:47:56 +0300 [thread overview]
Message-ID: <20210514094756.GC8606@intel.com> (raw)
In-Reply-To: <20210414022754.31710-4-ville.syrjala@linux.intel.com>
On Wed, Apr 14, 2021 at 05:27:49AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> TGL has the same amount of planes as ICL. Make intel_watermark
> aware of that fact.
>
> v2: Use intel_gen()
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@gmail.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> tools/intel_watermark.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index 39aaf9fbe055..4a5764b59677 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -133,9 +133,11 @@ static char endis_ast(bool enabled)
>
> static int skl_num_planes(uint32_t d, int pipe)
> {
> - if (IS_GEN11(d))
> + int gen = intel_gen(d);
> +
> + if (gen >= 11)
> return 8;
> - else if (IS_GEN10(d) || IS_GEMINILAKE(d))
> + else if (gen == 10 || IS_GEMINILAKE(d))
> return 5;
> else if (IS_BROXTON(d))
> return pipe == 2 ? 4 : 5;
> @@ -145,9 +147,11 @@ static int skl_num_planes(uint32_t d, int pipe)
>
> static int skl_max_planes(uint32_t d)
> {
> - if (IS_GEN11(d))
> + int gen = intel_gen(d);
> +
> + if (gen >= 11)
> return 8;
> - else if (IS_GEN10(d) || IS_GEMINILAKE(d) || IS_BROXTON(d))
> + else if (gen == 10 || IS_GEMINILAKE(d) || IS_BROXTON(d))
> return 5;
> else
> return 4;
> --
> 2.26.3
>
> _______________________________________________
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> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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next prev parent reply other threads:[~2021-05-14 9:44 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-14 2:27 [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms Ville Syrjala
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 1/8] tools/intel_watermark: Parse WM_DBG to help diagnose watermark issues Ville Syrjala
2021-05-14 9:31 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 2/8] tools/intel_watermark: Use WM_SR_CNT to observe SR residency Ville Syrjala
2021-05-14 9:36 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 3/8] tools/intel_watermark: Deal with TGL planes Ville Syrjala
2021-05-14 9:47 ` Lisovskiy, Stanislav [this message]
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 4/8] tools/intel_watermark: Reduce the number of planes for rkl/adls/adlp Ville Syrjala
2021-05-14 9:53 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 5/8] tools/intel_watermark: TGL+ can have 4 pipes Ville Syrjala
2021-05-14 9:53 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 6/8] tools/intel_watermark: Make reg dump section less wide Ville Syrjala
2021-05-14 9:50 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 7/8] tools/intel_watermark: Handle ADL-P dedicated SAGV watermarks Ville Syrjala
2021-05-14 9:51 ` Lisovskiy, Stanislav
2021-04-14 2:27 ` [igt-dev] [PATCH i-g-t 8/8] tools/intel_watermark: Widen register bitfields Ville Syrjala
2021-05-14 9:51 ` Lisovskiy, Stanislav
2021-04-14 3:04 ` [igt-dev] ✓ Fi.CI.BAT: success for tools/intel_watermark: Support new platofrms Patchwork
2021-04-14 4:01 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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