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From: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: igt-dev@lists.freedesktop.org
Subject: Re: [igt-dev] [PATCH i-g-t 4/8] tools/intel_watermark: Reduce the number of planes for rkl/adls/adlp
Date: Fri, 14 May 2021 12:53:03 +0300	[thread overview]
Message-ID: <20210514095303.GD8652@intel.com> (raw)
In-Reply-To: <20210414022754.31710-5-ville.syrjala@linux.intel.com>

On Wed, Apr 14, 2021 at 05:27:50AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Modern platforms have just 5 universal planes + cursor per pipe..

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@gmail.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  tools/intel_watermark.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index 4a5764b59677..ff373fdb0c6d 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -135,7 +135,9 @@ static int skl_num_planes(uint32_t d, int pipe)
>  {
>  	int gen = intel_gen(d);
>  
> -	if (gen >= 11)
> +	if (gen >= 13 || IS_ALDERLAKE_S(d) || IS_ROCKETLAKE(d))
> +		return 6;
> +	else if (gen >= 11)
>  		return 8;
>  	else if (gen == 10 || IS_GEMINILAKE(d))
>  		return 5;
> @@ -149,7 +151,9 @@ static int skl_max_planes(uint32_t d)
>  {
>  	int gen = intel_gen(d);
>  
> -	if (gen >= 11)
> +	if (gen >= 13 || IS_ALDERLAKE_S(d) || IS_ROCKETLAKE(d))
> +		return 6;
> +	else if (gen >= 11)
>  		return 8;
>  	else if (gen == 10 || IS_GEMINILAKE(d) || IS_BROXTON(d))
>  		return 5;
> -- 
> 2.26.3
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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  reply	other threads:[~2021-05-14  9:49 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-14  2:27 [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms Ville Syrjala
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 1/8] tools/intel_watermark: Parse WM_DBG to help diagnose watermark issues Ville Syrjala
2021-05-14  9:31   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 2/8] tools/intel_watermark: Use WM_SR_CNT to observe SR residency Ville Syrjala
2021-05-14  9:36   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 3/8] tools/intel_watermark: Deal with TGL planes Ville Syrjala
2021-05-14  9:47   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 4/8] tools/intel_watermark: Reduce the number of planes for rkl/adls/adlp Ville Syrjala
2021-05-14  9:53   ` Lisovskiy, Stanislav [this message]
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 5/8] tools/intel_watermark: TGL+ can have 4 pipes Ville Syrjala
2021-05-14  9:53   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 6/8] tools/intel_watermark: Make reg dump section less wide Ville Syrjala
2021-05-14  9:50   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 7/8] tools/intel_watermark: Handle ADL-P dedicated SAGV watermarks Ville Syrjala
2021-05-14  9:51   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 8/8] tools/intel_watermark: Widen register bitfields Ville Syrjala
2021-05-14  9:51   ` Lisovskiy, Stanislav
2021-04-14  3:04 ` [igt-dev] ✓ Fi.CI.BAT: success for tools/intel_watermark: Support new platofrms Patchwork
2021-04-14  4:01 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork

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